rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module PE_20 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_d : { bits : UInt<32>}, out_a : { bits : UInt<32>}, out_b : { bits : UInt<32>}, out_c : { bits : UInt<32>}, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<4>, out_id : UInt<4>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_4 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : { bits : UInt<32>}, clock reg c2 : { bits : UInt<32>}, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a.bits, io.in_a.bits reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node io_out_c_self_rec_rawIn_sign = bits(c1.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn = bits(c1.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn = bits(c1.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn = eq(io_out_c_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn = eq(io_out_c_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T = bits(io_out_c_self_rec_rawIn_fractIn, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_1 = bits(io_out_c_self_rec_rawIn_fractIn, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_2 = bits(io_out_c_self_rec_rawIn_fractIn, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_3 = bits(io_out_c_self_rec_rawIn_fractIn, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_4 = bits(io_out_c_self_rec_rawIn_fractIn, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_5 = bits(io_out_c_self_rec_rawIn_fractIn, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_6 = bits(io_out_c_self_rec_rawIn_fractIn, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_7 = bits(io_out_c_self_rec_rawIn_fractIn, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_8 = bits(io_out_c_self_rec_rawIn_fractIn, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_9 = bits(io_out_c_self_rec_rawIn_fractIn, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_10 = bits(io_out_c_self_rec_rawIn_fractIn, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_11 = bits(io_out_c_self_rec_rawIn_fractIn, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_12 = bits(io_out_c_self_rec_rawIn_fractIn, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_13 = bits(io_out_c_self_rec_rawIn_fractIn, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_14 = bits(io_out_c_self_rec_rawIn_fractIn, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_15 = bits(io_out_c_self_rec_rawIn_fractIn, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_16 = bits(io_out_c_self_rec_rawIn_fractIn, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_17 = bits(io_out_c_self_rec_rawIn_fractIn, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_18 = bits(io_out_c_self_rec_rawIn_fractIn, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_19 = bits(io_out_c_self_rec_rawIn_fractIn, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_20 = bits(io_out_c_self_rec_rawIn_fractIn, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_21 = bits(io_out_c_self_rec_rawIn_fractIn, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_22 = bits(io_out_c_self_rec_rawIn_fractIn, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_23 = mux(_io_out_c_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_24 = mux(_io_out_c_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_23) node _io_out_c_self_rec_rawIn_normDist_T_25 = mux(_io_out_c_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_24) node _io_out_c_self_rec_rawIn_normDist_T_26 = mux(_io_out_c_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_25) node _io_out_c_self_rec_rawIn_normDist_T_27 = mux(_io_out_c_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_26) node _io_out_c_self_rec_rawIn_normDist_T_28 = mux(_io_out_c_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_27) node _io_out_c_self_rec_rawIn_normDist_T_29 = mux(_io_out_c_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_28) node _io_out_c_self_rec_rawIn_normDist_T_30 = mux(_io_out_c_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_29) node _io_out_c_self_rec_rawIn_normDist_T_31 = mux(_io_out_c_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_30) node _io_out_c_self_rec_rawIn_normDist_T_32 = mux(_io_out_c_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_31) node _io_out_c_self_rec_rawIn_normDist_T_33 = mux(_io_out_c_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_32) node _io_out_c_self_rec_rawIn_normDist_T_34 = mux(_io_out_c_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_33) node _io_out_c_self_rec_rawIn_normDist_T_35 = mux(_io_out_c_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_34) node _io_out_c_self_rec_rawIn_normDist_T_36 = mux(_io_out_c_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_35) node _io_out_c_self_rec_rawIn_normDist_T_37 = mux(_io_out_c_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_36) node _io_out_c_self_rec_rawIn_normDist_T_38 = mux(_io_out_c_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_37) node _io_out_c_self_rec_rawIn_normDist_T_39 = mux(_io_out_c_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_38) node _io_out_c_self_rec_rawIn_normDist_T_40 = mux(_io_out_c_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_39) node _io_out_c_self_rec_rawIn_normDist_T_41 = mux(_io_out_c_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_40) node _io_out_c_self_rec_rawIn_normDist_T_42 = mux(_io_out_c_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_41) node _io_out_c_self_rec_rawIn_normDist_T_43 = mux(_io_out_c_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_42) node io_out_c_self_rec_rawIn_normDist = mux(_io_out_c_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_43) node _io_out_c_self_rec_rawIn_subnormFract_T = dshl(io_out_c_self_rec_rawIn_fractIn, io_out_c_self_rec_rawIn_normDist) node _io_out_c_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_self_rec_rawIn_subnormFract = shl(_io_out_c_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T = xor(io_out_c_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, _io_out_c_self_rec_rawIn_adjustedExp_T, io_out_c_self_rec_rawIn_expIn) node _io_out_c_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_1, _io_out_c_self_rec_rawIn_adjustedExp_T_3) node io_out_c_self_rec_rawIn_adjustedExp = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_self_rec_rawIn_isZero = and(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_isZeroFractIn) node _io_out_c_self_rec_rawIn_isSpecial_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 7) node io_out_c_self_rec_rawIn_isSpecial = eq(_io_out_c_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T = eq(io_out_c_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_1 = and(io_out_c_self_rec_rawIn_isSpecial, _io_out_c_self_rec_rawIn_out_isNaN_T) connect io_out_c_self_rec_rawIn.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_1 node _io_out_c_self_rec_rawIn_out_isInf_T = and(io_out_c_self_rec_rawIn_isSpecial, io_out_c_self_rec_rawIn_isZeroFractIn) connect io_out_c_self_rec_rawIn.isInf, _io_out_c_self_rec_rawIn_out_isInf_T connect io_out_c_self_rec_rawIn.isZero, io_out_c_self_rec_rawIn_isZero connect io_out_c_self_rec_rawIn.sign, io_out_c_self_rec_rawIn_sign node _io_out_c_self_rec_rawIn_out_sExp_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T) connect io_out_c_self_rec_rawIn.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_1 node _io_out_c_self_rec_rawIn_out_sig_T = eq(io_out_c_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T) node _io_out_c_self_rec_rawIn_out_sig_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_subnormFract, io_out_c_self_rec_rawIn_fractIn) node _io_out_c_self_rec_rawIn_out_sig_T_3 = cat(_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2) connect io_out_c_self_rec_rawIn.sig, _io_out_c_self_rec_rawIn_out_sig_T_3 node _io_out_c_self_rec_T = bits(io_out_c_self_rec_rawIn.sExp, 8, 6) node _io_out_c_self_rec_T_1 = mux(io_out_c_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_self_rec_T) node _io_out_c_self_rec_T_2 = mux(io_out_c_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_3 = or(_io_out_c_self_rec_T_1, _io_out_c_self_rec_T_2) node _io_out_c_self_rec_T_4 = cat(io_out_c_self_rec_rawIn.sign, _io_out_c_self_rec_T_3) node _io_out_c_self_rec_T_5 = bits(io_out_c_self_rec_rawIn.sExp, 5, 0) node _io_out_c_self_rec_T_6 = cat(_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5) node _io_out_c_self_rec_T_7 = bits(io_out_c_self_rec_rawIn.sig, 22, 0) node io_out_c_self_rec = cat(_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7) wire io_out_c_shift_exp : UInt<8> node _io_out_c_shift_exp_T = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_1 = tail(_io_out_c_shift_exp_T, 1) connect io_out_c_shift_exp, _io_out_c_shift_exp_T_1 node io_out_c_shift_fn_hi = cat(UInt<1>(0h0), io_out_c_shift_exp) node io_out_c_shift_fn = cat(io_out_c_shift_fn_hi, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign = bits(io_out_c_shift_fn, 31, 31) node io_out_c_shift_rec_rawIn_expIn = bits(io_out_c_shift_fn, 30, 23) node io_out_c_shift_rec_rawIn_fractIn = bits(io_out_c_shift_fn, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn = eq(io_out_c_shift_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn = eq(io_out_c_shift_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T = bits(io_out_c_shift_rec_rawIn_fractIn, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_1 = bits(io_out_c_shift_rec_rawIn_fractIn, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_2 = bits(io_out_c_shift_rec_rawIn_fractIn, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_3 = bits(io_out_c_shift_rec_rawIn_fractIn, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_4 = bits(io_out_c_shift_rec_rawIn_fractIn, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_5 = bits(io_out_c_shift_rec_rawIn_fractIn, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_6 = bits(io_out_c_shift_rec_rawIn_fractIn, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_7 = bits(io_out_c_shift_rec_rawIn_fractIn, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_8 = bits(io_out_c_shift_rec_rawIn_fractIn, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_9 = bits(io_out_c_shift_rec_rawIn_fractIn, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_10 = bits(io_out_c_shift_rec_rawIn_fractIn, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_11 = bits(io_out_c_shift_rec_rawIn_fractIn, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_12 = bits(io_out_c_shift_rec_rawIn_fractIn, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_13 = bits(io_out_c_shift_rec_rawIn_fractIn, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_14 = bits(io_out_c_shift_rec_rawIn_fractIn, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_15 = bits(io_out_c_shift_rec_rawIn_fractIn, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_16 = bits(io_out_c_shift_rec_rawIn_fractIn, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_17 = bits(io_out_c_shift_rec_rawIn_fractIn, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_18 = bits(io_out_c_shift_rec_rawIn_fractIn, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_19 = bits(io_out_c_shift_rec_rawIn_fractIn, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_20 = bits(io_out_c_shift_rec_rawIn_fractIn, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_21 = bits(io_out_c_shift_rec_rawIn_fractIn, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_22 = bits(io_out_c_shift_rec_rawIn_fractIn, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_23 = mux(_io_out_c_shift_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_24 = mux(_io_out_c_shift_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_23) node _io_out_c_shift_rec_rawIn_normDist_T_25 = mux(_io_out_c_shift_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_24) node _io_out_c_shift_rec_rawIn_normDist_T_26 = mux(_io_out_c_shift_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_25) node _io_out_c_shift_rec_rawIn_normDist_T_27 = mux(_io_out_c_shift_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_26) node _io_out_c_shift_rec_rawIn_normDist_T_28 = mux(_io_out_c_shift_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_27) node _io_out_c_shift_rec_rawIn_normDist_T_29 = mux(_io_out_c_shift_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_28) node _io_out_c_shift_rec_rawIn_normDist_T_30 = mux(_io_out_c_shift_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_29) node _io_out_c_shift_rec_rawIn_normDist_T_31 = mux(_io_out_c_shift_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_30) node _io_out_c_shift_rec_rawIn_normDist_T_32 = mux(_io_out_c_shift_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_31) node _io_out_c_shift_rec_rawIn_normDist_T_33 = mux(_io_out_c_shift_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_32) node _io_out_c_shift_rec_rawIn_normDist_T_34 = mux(_io_out_c_shift_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_33) node _io_out_c_shift_rec_rawIn_normDist_T_35 = mux(_io_out_c_shift_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_34) node _io_out_c_shift_rec_rawIn_normDist_T_36 = mux(_io_out_c_shift_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_35) node _io_out_c_shift_rec_rawIn_normDist_T_37 = mux(_io_out_c_shift_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_36) node _io_out_c_shift_rec_rawIn_normDist_T_38 = mux(_io_out_c_shift_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_37) node _io_out_c_shift_rec_rawIn_normDist_T_39 = mux(_io_out_c_shift_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_38) node _io_out_c_shift_rec_rawIn_normDist_T_40 = mux(_io_out_c_shift_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_39) node _io_out_c_shift_rec_rawIn_normDist_T_41 = mux(_io_out_c_shift_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_40) node _io_out_c_shift_rec_rawIn_normDist_T_42 = mux(_io_out_c_shift_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_41) node _io_out_c_shift_rec_rawIn_normDist_T_43 = mux(_io_out_c_shift_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_42) node io_out_c_shift_rec_rawIn_normDist = mux(_io_out_c_shift_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_43) node _io_out_c_shift_rec_rawIn_subnormFract_T = dshl(io_out_c_shift_rec_rawIn_fractIn, io_out_c_shift_rec_rawIn_normDist) node _io_out_c_shift_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T = xor(io_out_c_shift_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, _io_out_c_shift_rec_rawIn_adjustedExp_T, io_out_c_shift_rec_rawIn_expIn) node _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_2) node _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_3) node io_out_c_shift_rec_rawIn_adjustedExp = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_shift_rec_rawIn_isZero = and(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_isZeroFractIn) node _io_out_c_shift_rec_rawIn_isSpecial_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial = eq(_io_out_c_shift_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T = eq(io_out_c_shift_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial, _io_out_c_shift_rec_rawIn_out_isNaN_T) connect io_out_c_shift_rec_rawIn.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_1 node _io_out_c_shift_rec_rawIn_out_isInf_T = and(io_out_c_shift_rec_rawIn_isSpecial, io_out_c_shift_rec_rawIn_isZeroFractIn) connect io_out_c_shift_rec_rawIn.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T connect io_out_c_shift_rec_rawIn.isZero, io_out_c_shift_rec_rawIn_isZero connect io_out_c_shift_rec_rawIn.sign, io_out_c_shift_rec_rawIn_sign node _io_out_c_shift_rec_rawIn_out_sExp_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T) connect io_out_c_shift_rec_rawIn.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_1 node _io_out_c_shift_rec_rawIn_out_sig_T = eq(io_out_c_shift_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T) node _io_out_c_shift_rec_rawIn_out_sig_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_subnormFract, io_out_c_shift_rec_rawIn_fractIn) node _io_out_c_shift_rec_rawIn_out_sig_T_3 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2) connect io_out_c_shift_rec_rawIn.sig, _io_out_c_shift_rec_rawIn_out_sig_T_3 node _io_out_c_shift_rec_T = bits(io_out_c_shift_rec_rawIn.sExp, 8, 6) node _io_out_c_shift_rec_T_1 = mux(io_out_c_shift_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T) node _io_out_c_shift_rec_T_2 = mux(io_out_c_shift_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_3 = or(_io_out_c_shift_rec_T_1, _io_out_c_shift_rec_T_2) node _io_out_c_shift_rec_T_4 = cat(io_out_c_shift_rec_rawIn.sign, _io_out_c_shift_rec_T_3) node _io_out_c_shift_rec_T_5 = bits(io_out_c_shift_rec_rawIn.sExp, 5, 0) node _io_out_c_shift_rec_T_6 = cat(_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5) node _io_out_c_shift_rec_T_7 = bits(io_out_c_shift_rec_rawIn.sig, 22, 0) node io_out_c_shift_rec = cat(_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7) node _io_out_c_T = neq(io_out_c_shift_exp, UInt<1>(0h0)) node _io_out_c_T_1 = asUInt(reset) node _io_out_c_T_2 = eq(_io_out_c_T_1, UInt<1>(0h0)) when _io_out_c_T_2 : node _io_out_c_T_3 = eq(_io_out_c_T, UInt<1>(0h0)) when _io_out_c_T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf assert(clock, _io_out_c_T, UInt<1>(0h1), "") : io_out_c_assert inst io_out_c_muladder of MulRecFN_32 connect io_out_c_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder.io.a, io_out_c_self_rec connect io_out_c_muladder.io.b, io_out_c_shift_rec wire io_out_c_result : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp = bits(io_out_c_muladder.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T = bits(io_out_c_result_bits_rawIn_exp, 8, 6) node io_out_c_result_bits_rawIn_isZero = eq(_io_out_c_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T = bits(io_out_c_result_bits_rawIn_exp, 8, 7) node io_out_c_result_bits_rawIn_isSpecial = eq(_io_out_c_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_1 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isNaN_T) connect io_out_c_result_bits_rawIn.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_1 node _io_out_c_result_bits_rawIn_out_isInf_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_1 = eq(_io_out_c_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_2 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isInf_T_1) connect io_out_c_result_bits_rawIn.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_2 connect io_out_c_result_bits_rawIn.isZero, io_out_c_result_bits_rawIn_isZero node _io_out_c_result_bits_rawIn_out_sign_T = bits(io_out_c_muladder.io.out, 32, 32) connect io_out_c_result_bits_rawIn.sign, _io_out_c_result_bits_rawIn_out_sign_T node _io_out_c_result_bits_rawIn_out_sExp_T = cvt(io_out_c_result_bits_rawIn_exp) connect io_out_c_result_bits_rawIn.sExp, _io_out_c_result_bits_rawIn_out_sExp_T node _io_out_c_result_bits_rawIn_out_sig_T = eq(io_out_c_result_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T) node _io_out_c_result_bits_rawIn_out_sig_T_2 = bits(io_out_c_muladder.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_3 = cat(_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2) connect io_out_c_result_bits_rawIn.sig, _io_out_c_result_bits_rawIn_out_sig_T_3 node io_out_c_result_bits_isSubnormal = lt(io_out_c_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T = bits(io_out_c_result_bits_rawIn.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T) node io_out_c_result_bits_denormShiftDist = tail(_io_out_c_result_bits_denormShiftDist_T_1, 1) node _io_out_c_result_bits_denormFract_T = shr(io_out_c_result_bits_rawIn.sig, 1) node _io_out_c_result_bits_denormFract_T_1 = dshr(_io_out_c_result_bits_denormFract_T, io_out_c_result_bits_denormShiftDist) node io_out_c_result_bits_denormFract = bits(_io_out_c_result_bits_denormFract_T_1, 22, 0) node _io_out_c_result_bits_expOut_T = bits(io_out_c_result_bits_rawIn.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_1 = sub(_io_out_c_result_bits_expOut_T, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_2 = tail(_io_out_c_result_bits_expOut_T_1, 1) node _io_out_c_result_bits_expOut_T_3 = mux(io_out_c_result_bits_isSubnormal, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_2) node _io_out_c_result_bits_expOut_T_4 = or(io_out_c_result_bits_rawIn.isNaN, io_out_c_result_bits_rawIn.isInf) node _io_out_c_result_bits_expOut_T_5 = mux(_io_out_c_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut = or(_io_out_c_result_bits_expOut_T_3, _io_out_c_result_bits_expOut_T_5) node _io_out_c_result_bits_fractOut_T = bits(io_out_c_result_bits_rawIn.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_1 = mux(io_out_c_result_bits_rawIn.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T) node io_out_c_result_bits_fractOut = mux(io_out_c_result_bits_isSubnormal, io_out_c_result_bits_denormFract, _io_out_c_result_bits_fractOut_T_1) node io_out_c_result_bits_hi = cat(io_out_c_result_bits_rawIn.sign, io_out_c_result_bits_expOut) node _io_out_c_result_bits_T = cat(io_out_c_result_bits_hi, io_out_c_result_bits_fractOut) connect io_out_c_result.bits, _io_out_c_result_bits_T node io_out_c_self_rec_rawIn_sign_1 = bits(io_out_c_result.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_1 = bits(io_out_c_result.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_1 = bits(io_out_c_result.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_self_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_44 = bits(io_out_c_self_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_45 = bits(io_out_c_self_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_46 = bits(io_out_c_self_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_47 = bits(io_out_c_self_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_48 = bits(io_out_c_self_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_49 = bits(io_out_c_self_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_50 = bits(io_out_c_self_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_51 = bits(io_out_c_self_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_52 = bits(io_out_c_self_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_53 = bits(io_out_c_self_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_54 = bits(io_out_c_self_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_55 = bits(io_out_c_self_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_56 = bits(io_out_c_self_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_57 = bits(io_out_c_self_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_58 = bits(io_out_c_self_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_59 = bits(io_out_c_self_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_60 = bits(io_out_c_self_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_61 = bits(io_out_c_self_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_62 = bits(io_out_c_self_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_63 = bits(io_out_c_self_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_64 = bits(io_out_c_self_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_65 = bits(io_out_c_self_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_66 = bits(io_out_c_self_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_67 = mux(_io_out_c_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_68 = mux(_io_out_c_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_67) node _io_out_c_self_rec_rawIn_normDist_T_69 = mux(_io_out_c_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_68) node _io_out_c_self_rec_rawIn_normDist_T_70 = mux(_io_out_c_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_69) node _io_out_c_self_rec_rawIn_normDist_T_71 = mux(_io_out_c_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_70) node _io_out_c_self_rec_rawIn_normDist_T_72 = mux(_io_out_c_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_71) node _io_out_c_self_rec_rawIn_normDist_T_73 = mux(_io_out_c_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_72) node _io_out_c_self_rec_rawIn_normDist_T_74 = mux(_io_out_c_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_73) node _io_out_c_self_rec_rawIn_normDist_T_75 = mux(_io_out_c_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_74) node _io_out_c_self_rec_rawIn_normDist_T_76 = mux(_io_out_c_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_75) node _io_out_c_self_rec_rawIn_normDist_T_77 = mux(_io_out_c_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_76) node _io_out_c_self_rec_rawIn_normDist_T_78 = mux(_io_out_c_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_77) node _io_out_c_self_rec_rawIn_normDist_T_79 = mux(_io_out_c_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_78) node _io_out_c_self_rec_rawIn_normDist_T_80 = mux(_io_out_c_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_79) node _io_out_c_self_rec_rawIn_normDist_T_81 = mux(_io_out_c_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_80) node _io_out_c_self_rec_rawIn_normDist_T_82 = mux(_io_out_c_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_81) node _io_out_c_self_rec_rawIn_normDist_T_83 = mux(_io_out_c_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_82) node _io_out_c_self_rec_rawIn_normDist_T_84 = mux(_io_out_c_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_83) node _io_out_c_self_rec_rawIn_normDist_T_85 = mux(_io_out_c_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_84) node _io_out_c_self_rec_rawIn_normDist_T_86 = mux(_io_out_c_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_85) node _io_out_c_self_rec_rawIn_normDist_T_87 = mux(_io_out_c_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_86) node io_out_c_self_rec_rawIn_normDist_1 = mux(_io_out_c_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_87) node _io_out_c_self_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_self_rec_rawIn_fractIn_1, io_out_c_self_rec_rawIn_normDist_1) node _io_out_c_self_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_1 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, _io_out_c_self_rec_rawIn_adjustedExp_T_5, io_out_c_self_rec_rawIn_expIn_1) node _io_out_c_self_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_7) node _io_out_c_self_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_6, _io_out_c_self_rec_rawIn_adjustedExp_T_8) node io_out_c_self_rec_rawIn_adjustedExp_1 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_self_rec_rawIn_isZero_1 = and(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) node _io_out_c_self_rec_rawIn_isSpecial_T_1 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_1 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_1, _io_out_c_self_rec_rawIn_out_isNaN_T_2) connect io_out_c_self_rec_rawIn_1.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_3 node _io_out_c_self_rec_rawIn_out_isInf_T_1 = and(io_out_c_self_rec_rawIn_isSpecial_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) connect io_out_c_self_rec_rawIn_1.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_1 connect io_out_c_self_rec_rawIn_1.isZero, io_out_c_self_rec_rawIn_isZero_1 connect io_out_c_self_rec_rawIn_1.sign, io_out_c_self_rec_rawIn_sign_1 node _io_out_c_self_rec_rawIn_out_sExp_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_2) connect io_out_c_self_rec_rawIn_1.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_3 node _io_out_c_self_rec_rawIn_out_sig_T_4 = eq(io_out_c_self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_4) node _io_out_c_self_rec_rawIn_out_sig_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_subnormFract_1, io_out_c_self_rec_rawIn_fractIn_1) node _io_out_c_self_rec_rawIn_out_sig_T_7 = cat(_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6) connect io_out_c_self_rec_rawIn_1.sig, _io_out_c_self_rec_rawIn_out_sig_T_7 node _io_out_c_self_rec_T_8 = bits(io_out_c_self_rec_rawIn_1.sExp, 8, 6) node _io_out_c_self_rec_T_9 = mux(io_out_c_self_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_8) node _io_out_c_self_rec_T_10 = mux(io_out_c_self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_11 = or(_io_out_c_self_rec_T_9, _io_out_c_self_rec_T_10) node _io_out_c_self_rec_T_12 = cat(io_out_c_self_rec_rawIn_1.sign, _io_out_c_self_rec_T_11) node _io_out_c_self_rec_T_13 = bits(io_out_c_self_rec_rawIn_1.sExp, 5, 0) node _io_out_c_self_rec_T_14 = cat(_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13) node _io_out_c_self_rec_T_15 = bits(io_out_c_self_rec_rawIn_1.sig, 22, 0) node io_out_c_self_rec_1 = cat(_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15) inst io_out_c_resizer of RecFNToRecFN_170 connect io_out_c_resizer.io.in, io_out_c_self_rec_1 connect io_out_c_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_1 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_1 = bits(io_out_c_resizer.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 6) node io_out_c_result_bits_rawIn_isZero_1 = eq(_io_out_c_result_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_1 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_2 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_3 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isNaN_T_2) connect io_out_c_result_bits_rawIn_1.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_3 node _io_out_c_result_bits_rawIn_out_isInf_T_3 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_4 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isInf_T_4) connect io_out_c_result_bits_rawIn_1.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_5 connect io_out_c_result_bits_rawIn_1.isZero, io_out_c_result_bits_rawIn_isZero_1 node _io_out_c_result_bits_rawIn_out_sign_T_1 = bits(io_out_c_resizer.io.out, 32, 32) connect io_out_c_result_bits_rawIn_1.sign, _io_out_c_result_bits_rawIn_out_sign_T_1 node _io_out_c_result_bits_rawIn_out_sExp_T_1 = cvt(io_out_c_result_bits_rawIn_exp_1) connect io_out_c_result_bits_rawIn_1.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_1 node _io_out_c_result_bits_rawIn_out_sig_T_4 = eq(io_out_c_result_bits_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_4) node _io_out_c_result_bits_rawIn_out_sig_T_6 = bits(io_out_c_resizer.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_7 = cat(_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6) connect io_out_c_result_bits_rawIn_1.sig, _io_out_c_result_bits_rawIn_out_sig_T_7 node io_out_c_result_bits_isSubnormal_1 = lt(io_out_c_result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_2 = bits(io_out_c_result_bits_rawIn_1.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_2) node io_out_c_result_bits_denormShiftDist_1 = tail(_io_out_c_result_bits_denormShiftDist_T_3, 1) node _io_out_c_result_bits_denormFract_T_2 = shr(io_out_c_result_bits_rawIn_1.sig, 1) node _io_out_c_result_bits_denormFract_T_3 = dshr(_io_out_c_result_bits_denormFract_T_2, io_out_c_result_bits_denormShiftDist_1) node io_out_c_result_bits_denormFract_1 = bits(_io_out_c_result_bits_denormFract_T_3, 22, 0) node _io_out_c_result_bits_expOut_T_6 = bits(io_out_c_result_bits_rawIn_1.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_7 = sub(_io_out_c_result_bits_expOut_T_6, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_8 = tail(_io_out_c_result_bits_expOut_T_7, 1) node _io_out_c_result_bits_expOut_T_9 = mux(io_out_c_result_bits_isSubnormal_1, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_8) node _io_out_c_result_bits_expOut_T_10 = or(io_out_c_result_bits_rawIn_1.isNaN, io_out_c_result_bits_rawIn_1.isInf) node _io_out_c_result_bits_expOut_T_11 = mux(_io_out_c_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_1 = or(_io_out_c_result_bits_expOut_T_9, _io_out_c_result_bits_expOut_T_11) node _io_out_c_result_bits_fractOut_T_2 = bits(io_out_c_result_bits_rawIn_1.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_3 = mux(io_out_c_result_bits_rawIn_1.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_2) node io_out_c_result_bits_fractOut_1 = mux(io_out_c_result_bits_isSubnormal_1, io_out_c_result_bits_denormFract_1, _io_out_c_result_bits_fractOut_T_3) node io_out_c_result_bits_hi_1 = cat(io_out_c_result_bits_rawIn_1.sign, io_out_c_result_bits_expOut_1) node _io_out_c_result_bits_T_1 = cat(io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1) connect io_out_c_result_1.bits, _io_out_c_result_bits_T_1 connect io.out_c, io_out_c_result_1 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_1 : UInt<32> connect _mac_unit_io_in_b_WIRE_1, io.in_b.bits node _mac_unit_io_in_b_T = bits(_mac_unit_io_in_b_WIRE_1, 31, 0) connect _mac_unit_io_in_b_WIRE.bits, _mac_unit_io_in_b_T connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE.bits connect mac_unit.io.in_c.bits, c2.bits connect c2, mac_unit.io.out_d node c1_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c1_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c1_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c1_self_rec_rawIn_isZeroExpIn = eq(c1_self_rec_rawIn_expIn, UInt<1>(0h0)) node c1_self_rec_rawIn_isZeroFractIn = eq(c1_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_normDist_T = bits(c1_self_rec_rawIn_fractIn, 0, 0) node _c1_self_rec_rawIn_normDist_T_1 = bits(c1_self_rec_rawIn_fractIn, 1, 1) node _c1_self_rec_rawIn_normDist_T_2 = bits(c1_self_rec_rawIn_fractIn, 2, 2) node _c1_self_rec_rawIn_normDist_T_3 = bits(c1_self_rec_rawIn_fractIn, 3, 3) node _c1_self_rec_rawIn_normDist_T_4 = bits(c1_self_rec_rawIn_fractIn, 4, 4) node _c1_self_rec_rawIn_normDist_T_5 = bits(c1_self_rec_rawIn_fractIn, 5, 5) node _c1_self_rec_rawIn_normDist_T_6 = bits(c1_self_rec_rawIn_fractIn, 6, 6) node _c1_self_rec_rawIn_normDist_T_7 = bits(c1_self_rec_rawIn_fractIn, 7, 7) node _c1_self_rec_rawIn_normDist_T_8 = bits(c1_self_rec_rawIn_fractIn, 8, 8) node _c1_self_rec_rawIn_normDist_T_9 = bits(c1_self_rec_rawIn_fractIn, 9, 9) node _c1_self_rec_rawIn_normDist_T_10 = bits(c1_self_rec_rawIn_fractIn, 10, 10) node _c1_self_rec_rawIn_normDist_T_11 = bits(c1_self_rec_rawIn_fractIn, 11, 11) node _c1_self_rec_rawIn_normDist_T_12 = bits(c1_self_rec_rawIn_fractIn, 12, 12) node _c1_self_rec_rawIn_normDist_T_13 = bits(c1_self_rec_rawIn_fractIn, 13, 13) node _c1_self_rec_rawIn_normDist_T_14 = bits(c1_self_rec_rawIn_fractIn, 14, 14) node _c1_self_rec_rawIn_normDist_T_15 = bits(c1_self_rec_rawIn_fractIn, 15, 15) node _c1_self_rec_rawIn_normDist_T_16 = bits(c1_self_rec_rawIn_fractIn, 16, 16) node _c1_self_rec_rawIn_normDist_T_17 = bits(c1_self_rec_rawIn_fractIn, 17, 17) node _c1_self_rec_rawIn_normDist_T_18 = bits(c1_self_rec_rawIn_fractIn, 18, 18) node _c1_self_rec_rawIn_normDist_T_19 = bits(c1_self_rec_rawIn_fractIn, 19, 19) node _c1_self_rec_rawIn_normDist_T_20 = bits(c1_self_rec_rawIn_fractIn, 20, 20) node _c1_self_rec_rawIn_normDist_T_21 = bits(c1_self_rec_rawIn_fractIn, 21, 21) node _c1_self_rec_rawIn_normDist_T_22 = bits(c1_self_rec_rawIn_fractIn, 22, 22) node _c1_self_rec_rawIn_normDist_T_23 = mux(_c1_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c1_self_rec_rawIn_normDist_T_24 = mux(_c1_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c1_self_rec_rawIn_normDist_T_23) node _c1_self_rec_rawIn_normDist_T_25 = mux(_c1_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c1_self_rec_rawIn_normDist_T_24) node _c1_self_rec_rawIn_normDist_T_26 = mux(_c1_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c1_self_rec_rawIn_normDist_T_25) node _c1_self_rec_rawIn_normDist_T_27 = mux(_c1_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c1_self_rec_rawIn_normDist_T_26) node _c1_self_rec_rawIn_normDist_T_28 = mux(_c1_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c1_self_rec_rawIn_normDist_T_27) node _c1_self_rec_rawIn_normDist_T_29 = mux(_c1_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c1_self_rec_rawIn_normDist_T_28) node _c1_self_rec_rawIn_normDist_T_30 = mux(_c1_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c1_self_rec_rawIn_normDist_T_29) node _c1_self_rec_rawIn_normDist_T_31 = mux(_c1_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c1_self_rec_rawIn_normDist_T_30) node _c1_self_rec_rawIn_normDist_T_32 = mux(_c1_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c1_self_rec_rawIn_normDist_T_31) node _c1_self_rec_rawIn_normDist_T_33 = mux(_c1_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c1_self_rec_rawIn_normDist_T_32) node _c1_self_rec_rawIn_normDist_T_34 = mux(_c1_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c1_self_rec_rawIn_normDist_T_33) node _c1_self_rec_rawIn_normDist_T_35 = mux(_c1_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c1_self_rec_rawIn_normDist_T_34) node _c1_self_rec_rawIn_normDist_T_36 = mux(_c1_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c1_self_rec_rawIn_normDist_T_35) node _c1_self_rec_rawIn_normDist_T_37 = mux(_c1_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c1_self_rec_rawIn_normDist_T_36) node _c1_self_rec_rawIn_normDist_T_38 = mux(_c1_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c1_self_rec_rawIn_normDist_T_37) node _c1_self_rec_rawIn_normDist_T_39 = mux(_c1_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c1_self_rec_rawIn_normDist_T_38) node _c1_self_rec_rawIn_normDist_T_40 = mux(_c1_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c1_self_rec_rawIn_normDist_T_39) node _c1_self_rec_rawIn_normDist_T_41 = mux(_c1_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c1_self_rec_rawIn_normDist_T_40) node _c1_self_rec_rawIn_normDist_T_42 = mux(_c1_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c1_self_rec_rawIn_normDist_T_41) node _c1_self_rec_rawIn_normDist_T_43 = mux(_c1_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c1_self_rec_rawIn_normDist_T_42) node c1_self_rec_rawIn_normDist = mux(_c1_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c1_self_rec_rawIn_normDist_T_43) node _c1_self_rec_rawIn_subnormFract_T = dshl(c1_self_rec_rawIn_fractIn, c1_self_rec_rawIn_normDist) node _c1_self_rec_rawIn_subnormFract_T_1 = bits(_c1_self_rec_rawIn_subnormFract_T, 21, 0) node c1_self_rec_rawIn_subnormFract = shl(_c1_self_rec_rawIn_subnormFract_T_1, 1) node _c1_self_rec_rawIn_adjustedExp_T = xor(c1_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c1_self_rec_rawIn_adjustedExp_T_1 = mux(c1_self_rec_rawIn_isZeroExpIn, _c1_self_rec_rawIn_adjustedExp_T, c1_self_rec_rawIn_expIn) node _c1_self_rec_rawIn_adjustedExp_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c1_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c1_self_rec_rawIn_adjustedExp_T_2) node _c1_self_rec_rawIn_adjustedExp_T_4 = add(_c1_self_rec_rawIn_adjustedExp_T_1, _c1_self_rec_rawIn_adjustedExp_T_3) node c1_self_rec_rawIn_adjustedExp = tail(_c1_self_rec_rawIn_adjustedExp_T_4, 1) node c1_self_rec_rawIn_isZero = and(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_isZeroFractIn) node _c1_self_rec_rawIn_isSpecial_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 7) node c1_self_rec_rawIn_isSpecial = eq(_c1_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_self_rec_rawIn_out_isNaN_T = eq(c1_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_isNaN_T_1 = and(c1_self_rec_rawIn_isSpecial, _c1_self_rec_rawIn_out_isNaN_T) connect c1_self_rec_rawIn.isNaN, _c1_self_rec_rawIn_out_isNaN_T_1 node _c1_self_rec_rawIn_out_isInf_T = and(c1_self_rec_rawIn_isSpecial, c1_self_rec_rawIn_isZeroFractIn) connect c1_self_rec_rawIn.isInf, _c1_self_rec_rawIn_out_isInf_T connect c1_self_rec_rawIn.isZero, c1_self_rec_rawIn_isZero connect c1_self_rec_rawIn.sign, c1_self_rec_rawIn_sign node _c1_self_rec_rawIn_out_sExp_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 0) node _c1_self_rec_rawIn_out_sExp_T_1 = cvt(_c1_self_rec_rawIn_out_sExp_T) connect c1_self_rec_rawIn.sExp, _c1_self_rec_rawIn_out_sExp_T_1 node _c1_self_rec_rawIn_out_sig_T = eq(c1_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_self_rec_rawIn_out_sig_T) node _c1_self_rec_rawIn_out_sig_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_subnormFract, c1_self_rec_rawIn_fractIn) node _c1_self_rec_rawIn_out_sig_T_3 = cat(_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2) connect c1_self_rec_rawIn.sig, _c1_self_rec_rawIn_out_sig_T_3 node _c1_self_rec_T = bits(c1_self_rec_rawIn.sExp, 8, 6) node _c1_self_rec_T_1 = mux(c1_self_rec_rawIn.isZero, UInt<3>(0h0), _c1_self_rec_T) node _c1_self_rec_T_2 = mux(c1_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c1_self_rec_T_3 = or(_c1_self_rec_T_1, _c1_self_rec_T_2) node _c1_self_rec_T_4 = cat(c1_self_rec_rawIn.sign, _c1_self_rec_T_3) node _c1_self_rec_T_5 = bits(c1_self_rec_rawIn.sExp, 5, 0) node _c1_self_rec_T_6 = cat(_c1_self_rec_T_4, _c1_self_rec_T_5) node _c1_self_rec_T_7 = bits(c1_self_rec_rawIn.sig, 22, 0) node c1_self_rec = cat(_c1_self_rec_T_6, _c1_self_rec_T_7) inst c1_resizer of RecFNToRecFN_171 connect c1_resizer.io.in, c1_self_rec connect c1_resizer.io.roundingMode, UInt<3>(0h0) connect c1_resizer.io.detectTininess, UInt<1>(0h1) wire c1_result : { bits : UInt<32>} node c1_result_bits_rawIn_exp = bits(c1_resizer.io.out, 31, 23) node _c1_result_bits_rawIn_isZero_T = bits(c1_result_bits_rawIn_exp, 8, 6) node c1_result_bits_rawIn_isZero = eq(_c1_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_isSpecial_T = bits(c1_result_bits_rawIn_exp, 8, 7) node c1_result_bits_rawIn_isSpecial = eq(_c1_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_result_bits_rawIn_out_isNaN_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isNaN_T_1 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isNaN_T) connect c1_result_bits_rawIn.isNaN, _c1_result_bits_rawIn_out_isNaN_T_1 node _c1_result_bits_rawIn_out_isInf_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isInf_T_1 = eq(_c1_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_isInf_T_2 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isInf_T_1) connect c1_result_bits_rawIn.isInf, _c1_result_bits_rawIn_out_isInf_T_2 connect c1_result_bits_rawIn.isZero, c1_result_bits_rawIn_isZero node _c1_result_bits_rawIn_out_sign_T = bits(c1_resizer.io.out, 32, 32) connect c1_result_bits_rawIn.sign, _c1_result_bits_rawIn_out_sign_T node _c1_result_bits_rawIn_out_sExp_T = cvt(c1_result_bits_rawIn_exp) connect c1_result_bits_rawIn.sExp, _c1_result_bits_rawIn_out_sExp_T node _c1_result_bits_rawIn_out_sig_T = eq(c1_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_result_bits_rawIn_out_sig_T) node _c1_result_bits_rawIn_out_sig_T_2 = bits(c1_resizer.io.out, 22, 0) node _c1_result_bits_rawIn_out_sig_T_3 = cat(_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2) connect c1_result_bits_rawIn.sig, _c1_result_bits_rawIn_out_sig_T_3 node c1_result_bits_isSubnormal = lt(c1_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c1_result_bits_denormShiftDist_T = bits(c1_result_bits_rawIn.sExp, 4, 0) node _c1_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c1_result_bits_denormShiftDist_T) node c1_result_bits_denormShiftDist = tail(_c1_result_bits_denormShiftDist_T_1, 1) node _c1_result_bits_denormFract_T = shr(c1_result_bits_rawIn.sig, 1) node _c1_result_bits_denormFract_T_1 = dshr(_c1_result_bits_denormFract_T, c1_result_bits_denormShiftDist) node c1_result_bits_denormFract = bits(_c1_result_bits_denormFract_T_1, 22, 0) node _c1_result_bits_expOut_T = bits(c1_result_bits_rawIn.sExp, 7, 0) node _c1_result_bits_expOut_T_1 = sub(_c1_result_bits_expOut_T, UInt<8>(0h81)) node _c1_result_bits_expOut_T_2 = tail(_c1_result_bits_expOut_T_1, 1) node _c1_result_bits_expOut_T_3 = mux(c1_result_bits_isSubnormal, UInt<1>(0h0), _c1_result_bits_expOut_T_2) node _c1_result_bits_expOut_T_4 = or(c1_result_bits_rawIn.isNaN, c1_result_bits_rawIn.isInf) node _c1_result_bits_expOut_T_5 = mux(_c1_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c1_result_bits_expOut = or(_c1_result_bits_expOut_T_3, _c1_result_bits_expOut_T_5) node _c1_result_bits_fractOut_T = bits(c1_result_bits_rawIn.sig, 22, 0) node _c1_result_bits_fractOut_T_1 = mux(c1_result_bits_rawIn.isInf, UInt<1>(0h0), _c1_result_bits_fractOut_T) node c1_result_bits_fractOut = mux(c1_result_bits_isSubnormal, c1_result_bits_denormFract, _c1_result_bits_fractOut_T_1) node c1_result_bits_hi = cat(c1_result_bits_rawIn.sign, c1_result_bits_expOut) node _c1_result_bits_T = cat(c1_result_bits_hi, c1_result_bits_fractOut) connect c1_result.bits, _c1_result_bits_T connect c1, c1_result else : node io_out_c_self_rec_rawIn_sign_2 = bits(c2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_2 = bits(c2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_2 = bits(c2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_2 = eq(io_out_c_self_rec_rawIn_expIn_2, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_2 = eq(io_out_c_self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_88 = bits(io_out_c_self_rec_rawIn_fractIn_2, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_89 = bits(io_out_c_self_rec_rawIn_fractIn_2, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_90 = bits(io_out_c_self_rec_rawIn_fractIn_2, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_91 = bits(io_out_c_self_rec_rawIn_fractIn_2, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_92 = bits(io_out_c_self_rec_rawIn_fractIn_2, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_93 = bits(io_out_c_self_rec_rawIn_fractIn_2, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_94 = bits(io_out_c_self_rec_rawIn_fractIn_2, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_95 = bits(io_out_c_self_rec_rawIn_fractIn_2, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_96 = bits(io_out_c_self_rec_rawIn_fractIn_2, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_97 = bits(io_out_c_self_rec_rawIn_fractIn_2, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_98 = bits(io_out_c_self_rec_rawIn_fractIn_2, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_99 = bits(io_out_c_self_rec_rawIn_fractIn_2, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_100 = bits(io_out_c_self_rec_rawIn_fractIn_2, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_101 = bits(io_out_c_self_rec_rawIn_fractIn_2, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_102 = bits(io_out_c_self_rec_rawIn_fractIn_2, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_103 = bits(io_out_c_self_rec_rawIn_fractIn_2, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_104 = bits(io_out_c_self_rec_rawIn_fractIn_2, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_105 = bits(io_out_c_self_rec_rawIn_fractIn_2, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_106 = bits(io_out_c_self_rec_rawIn_fractIn_2, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_107 = bits(io_out_c_self_rec_rawIn_fractIn_2, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_108 = bits(io_out_c_self_rec_rawIn_fractIn_2, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_109 = bits(io_out_c_self_rec_rawIn_fractIn_2, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_110 = bits(io_out_c_self_rec_rawIn_fractIn_2, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_111 = mux(_io_out_c_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_112 = mux(_io_out_c_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_111) node _io_out_c_self_rec_rawIn_normDist_T_113 = mux(_io_out_c_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_112) node _io_out_c_self_rec_rawIn_normDist_T_114 = mux(_io_out_c_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_113) node _io_out_c_self_rec_rawIn_normDist_T_115 = mux(_io_out_c_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_114) node _io_out_c_self_rec_rawIn_normDist_T_116 = mux(_io_out_c_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_115) node _io_out_c_self_rec_rawIn_normDist_T_117 = mux(_io_out_c_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_116) node _io_out_c_self_rec_rawIn_normDist_T_118 = mux(_io_out_c_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_117) node _io_out_c_self_rec_rawIn_normDist_T_119 = mux(_io_out_c_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_118) node _io_out_c_self_rec_rawIn_normDist_T_120 = mux(_io_out_c_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_119) node _io_out_c_self_rec_rawIn_normDist_T_121 = mux(_io_out_c_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_120) node _io_out_c_self_rec_rawIn_normDist_T_122 = mux(_io_out_c_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_121) node _io_out_c_self_rec_rawIn_normDist_T_123 = mux(_io_out_c_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_122) node _io_out_c_self_rec_rawIn_normDist_T_124 = mux(_io_out_c_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_123) node _io_out_c_self_rec_rawIn_normDist_T_125 = mux(_io_out_c_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_124) node _io_out_c_self_rec_rawIn_normDist_T_126 = mux(_io_out_c_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_125) node _io_out_c_self_rec_rawIn_normDist_T_127 = mux(_io_out_c_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_126) node _io_out_c_self_rec_rawIn_normDist_T_128 = mux(_io_out_c_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_127) node _io_out_c_self_rec_rawIn_normDist_T_129 = mux(_io_out_c_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_128) node _io_out_c_self_rec_rawIn_normDist_T_130 = mux(_io_out_c_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_129) node _io_out_c_self_rec_rawIn_normDist_T_131 = mux(_io_out_c_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_130) node io_out_c_self_rec_rawIn_normDist_2 = mux(_io_out_c_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_131) node _io_out_c_self_rec_rawIn_subnormFract_T_4 = dshl(io_out_c_self_rec_rawIn_fractIn_2, io_out_c_self_rec_rawIn_normDist_2) node _io_out_c_self_rec_rawIn_subnormFract_T_5 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_4, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_2 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_5, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_10 = xor(io_out_c_self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_11 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, _io_out_c_self_rec_rawIn_adjustedExp_T_10, io_out_c_self_rec_rawIn_expIn_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_12 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_12) node _io_out_c_self_rec_rawIn_adjustedExp_T_14 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_11, _io_out_c_self_rec_rawIn_adjustedExp_T_13) node io_out_c_self_rec_rawIn_adjustedExp_2 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_14, 1) node io_out_c_self_rec_rawIn_isZero_2 = and(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) node _io_out_c_self_rec_rawIn_isSpecial_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_2 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_4 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_5 = and(io_out_c_self_rec_rawIn_isSpecial_2, _io_out_c_self_rec_rawIn_out_isNaN_T_4) connect io_out_c_self_rec_rawIn_2.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_5 node _io_out_c_self_rec_rawIn_out_isInf_T_2 = and(io_out_c_self_rec_rawIn_isSpecial_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) connect io_out_c_self_rec_rawIn_2.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_2 connect io_out_c_self_rec_rawIn_2.isZero, io_out_c_self_rec_rawIn_isZero_2 connect io_out_c_self_rec_rawIn_2.sign, io_out_c_self_rec_rawIn_sign_2 node _io_out_c_self_rec_rawIn_out_sExp_T_4 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_5 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_4) connect io_out_c_self_rec_rawIn_2.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_5 node _io_out_c_self_rec_rawIn_out_sig_T_8 = eq(io_out_c_self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_8) node _io_out_c_self_rec_rawIn_out_sig_T_10 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_subnormFract_2, io_out_c_self_rec_rawIn_fractIn_2) node _io_out_c_self_rec_rawIn_out_sig_T_11 = cat(_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10) connect io_out_c_self_rec_rawIn_2.sig, _io_out_c_self_rec_rawIn_out_sig_T_11 node _io_out_c_self_rec_T_16 = bits(io_out_c_self_rec_rawIn_2.sExp, 8, 6) node _io_out_c_self_rec_T_17 = mux(io_out_c_self_rec_rawIn_2.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_16) node _io_out_c_self_rec_T_18 = mux(io_out_c_self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_19 = or(_io_out_c_self_rec_T_17, _io_out_c_self_rec_T_18) node _io_out_c_self_rec_T_20 = cat(io_out_c_self_rec_rawIn_2.sign, _io_out_c_self_rec_T_19) node _io_out_c_self_rec_T_21 = bits(io_out_c_self_rec_rawIn_2.sExp, 5, 0) node _io_out_c_self_rec_T_22 = cat(_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21) node _io_out_c_self_rec_T_23 = bits(io_out_c_self_rec_rawIn_2.sig, 22, 0) node io_out_c_self_rec_2 = cat(_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23) wire io_out_c_shift_exp_1 : UInt<8> node _io_out_c_shift_exp_T_2 = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_3 = tail(_io_out_c_shift_exp_T_2, 1) connect io_out_c_shift_exp_1, _io_out_c_shift_exp_T_3 node io_out_c_shift_fn_hi_1 = cat(UInt<1>(0h0), io_out_c_shift_exp_1) node io_out_c_shift_fn_1 = cat(io_out_c_shift_fn_hi_1, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign_1 = bits(io_out_c_shift_fn_1, 31, 31) node io_out_c_shift_rec_rawIn_expIn_1 = bits(io_out_c_shift_fn_1, 30, 23) node io_out_c_shift_rec_rawIn_fractIn_1 = bits(io_out_c_shift_fn_1, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_shift_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_shift_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T_44 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_45 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_46 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_47 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_48 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_49 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_50 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_51 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_52 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_53 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_54 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_55 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_56 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_57 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_58 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_59 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_60 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_61 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_62 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_63 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_64 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_65 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_66 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_67 = mux(_io_out_c_shift_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_68 = mux(_io_out_c_shift_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_67) node _io_out_c_shift_rec_rawIn_normDist_T_69 = mux(_io_out_c_shift_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_68) node _io_out_c_shift_rec_rawIn_normDist_T_70 = mux(_io_out_c_shift_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_69) node _io_out_c_shift_rec_rawIn_normDist_T_71 = mux(_io_out_c_shift_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_70) node _io_out_c_shift_rec_rawIn_normDist_T_72 = mux(_io_out_c_shift_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_71) node _io_out_c_shift_rec_rawIn_normDist_T_73 = mux(_io_out_c_shift_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_72) node _io_out_c_shift_rec_rawIn_normDist_T_74 = mux(_io_out_c_shift_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_73) node _io_out_c_shift_rec_rawIn_normDist_T_75 = mux(_io_out_c_shift_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_74) node _io_out_c_shift_rec_rawIn_normDist_T_76 = mux(_io_out_c_shift_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_75) node _io_out_c_shift_rec_rawIn_normDist_T_77 = mux(_io_out_c_shift_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_76) node _io_out_c_shift_rec_rawIn_normDist_T_78 = mux(_io_out_c_shift_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_77) node _io_out_c_shift_rec_rawIn_normDist_T_79 = mux(_io_out_c_shift_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_78) node _io_out_c_shift_rec_rawIn_normDist_T_80 = mux(_io_out_c_shift_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_79) node _io_out_c_shift_rec_rawIn_normDist_T_81 = mux(_io_out_c_shift_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_80) node _io_out_c_shift_rec_rawIn_normDist_T_82 = mux(_io_out_c_shift_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_81) node _io_out_c_shift_rec_rawIn_normDist_T_83 = mux(_io_out_c_shift_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_82) node _io_out_c_shift_rec_rawIn_normDist_T_84 = mux(_io_out_c_shift_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_83) node _io_out_c_shift_rec_rawIn_normDist_T_85 = mux(_io_out_c_shift_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_84) node _io_out_c_shift_rec_rawIn_normDist_T_86 = mux(_io_out_c_shift_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_85) node _io_out_c_shift_rec_rawIn_normDist_T_87 = mux(_io_out_c_shift_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_86) node io_out_c_shift_rec_rawIn_normDist_1 = mux(_io_out_c_shift_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_87) node _io_out_c_shift_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_shift_rec_rawIn_fractIn_1, io_out_c_shift_rec_rawIn_normDist_1) node _io_out_c_shift_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract_1 = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_shift_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_5, io_out_c_shift_rec_rawIn_expIn_1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_7) node _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_6, _io_out_c_shift_rec_rawIn_adjustedExp_T_8) node io_out_c_shift_rec_rawIn_adjustedExp_1 = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_shift_rec_rawIn_isZero_1 = and(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) node _io_out_c_shift_rec_rawIn_isSpecial_T_1 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial_1 = eq(_io_out_c_shift_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_shift_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = and(io_out_c_shift_rec_rawIn_isSpecial_1, _io_out_c_shift_rec_rawIn_out_isNaN_T_2) connect io_out_c_shift_rec_rawIn_1.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_3 node _io_out_c_shift_rec_rawIn_out_isInf_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) connect io_out_c_shift_rec_rawIn_1.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T_1 connect io_out_c_shift_rec_rawIn_1.isZero, io_out_c_shift_rec_rawIn_isZero_1 connect io_out_c_shift_rec_rawIn_1.sign, io_out_c_shift_rec_rawIn_sign_1 node _io_out_c_shift_rec_rawIn_out_sExp_T_2 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T_2) connect io_out_c_shift_rec_rawIn_1.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_3 node _io_out_c_shift_rec_rawIn_out_sig_T_4 = eq(io_out_c_shift_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T_4) node _io_out_c_shift_rec_rawIn_out_sig_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_subnormFract_1, io_out_c_shift_rec_rawIn_fractIn_1) node _io_out_c_shift_rec_rawIn_out_sig_T_7 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6) connect io_out_c_shift_rec_rawIn_1.sig, _io_out_c_shift_rec_rawIn_out_sig_T_7 node _io_out_c_shift_rec_T_8 = bits(io_out_c_shift_rec_rawIn_1.sExp, 8, 6) node _io_out_c_shift_rec_T_9 = mux(io_out_c_shift_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T_8) node _io_out_c_shift_rec_T_10 = mux(io_out_c_shift_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_11 = or(_io_out_c_shift_rec_T_9, _io_out_c_shift_rec_T_10) node _io_out_c_shift_rec_T_12 = cat(io_out_c_shift_rec_rawIn_1.sign, _io_out_c_shift_rec_T_11) node _io_out_c_shift_rec_T_13 = bits(io_out_c_shift_rec_rawIn_1.sExp, 5, 0) node _io_out_c_shift_rec_T_14 = cat(_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13) node _io_out_c_shift_rec_T_15 = bits(io_out_c_shift_rec_rawIn_1.sig, 22, 0) node io_out_c_shift_rec_1 = cat(_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15) node _io_out_c_T_4 = neq(io_out_c_shift_exp_1, UInt<1>(0h0)) node _io_out_c_T_5 = asUInt(reset) node _io_out_c_T_6 = eq(_io_out_c_T_5, UInt<1>(0h0)) when _io_out_c_T_6 : node _io_out_c_T_7 = eq(_io_out_c_T_4, UInt<1>(0h0)) when _io_out_c_T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf_1 assert(clock, _io_out_c_T_4, UInt<1>(0h1), "") : io_out_c_assert_1 inst io_out_c_muladder_1 of MulRecFN_33 connect io_out_c_muladder_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder_1.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder_1.io.a, io_out_c_self_rec_2 connect io_out_c_muladder_1.io.b, io_out_c_shift_rec_1 wire io_out_c_result_2 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_2 = bits(io_out_c_muladder_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 6) node io_out_c_result_bits_rawIn_isZero_2 = eq(_io_out_c_result_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_2 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_4 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isNaN_T_4) connect io_out_c_result_bits_rawIn_2.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_5 node _io_out_c_result_bits_rawIn_out_isInf_T_6 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_7 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_8 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isInf_T_7) connect io_out_c_result_bits_rawIn_2.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_8 connect io_out_c_result_bits_rawIn_2.isZero, io_out_c_result_bits_rawIn_isZero_2 node _io_out_c_result_bits_rawIn_out_sign_T_2 = bits(io_out_c_muladder_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_2.sign, _io_out_c_result_bits_rawIn_out_sign_T_2 node _io_out_c_result_bits_rawIn_out_sExp_T_2 = cvt(io_out_c_result_bits_rawIn_exp_2) connect io_out_c_result_bits_rawIn_2.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_2 node _io_out_c_result_bits_rawIn_out_sig_T_8 = eq(io_out_c_result_bits_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_8) node _io_out_c_result_bits_rawIn_out_sig_T_10 = bits(io_out_c_muladder_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_11 = cat(_io_out_c_result_bits_rawIn_out_sig_T_9, _io_out_c_result_bits_rawIn_out_sig_T_10) connect io_out_c_result_bits_rawIn_2.sig, _io_out_c_result_bits_rawIn_out_sig_T_11 node io_out_c_result_bits_isSubnormal_2 = lt(io_out_c_result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_4 = bits(io_out_c_result_bits_rawIn_2.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_4) node io_out_c_result_bits_denormShiftDist_2 = tail(_io_out_c_result_bits_denormShiftDist_T_5, 1) node _io_out_c_result_bits_denormFract_T_4 = shr(io_out_c_result_bits_rawIn_2.sig, 1) node _io_out_c_result_bits_denormFract_T_5 = dshr(_io_out_c_result_bits_denormFract_T_4, io_out_c_result_bits_denormShiftDist_2) node io_out_c_result_bits_denormFract_2 = bits(_io_out_c_result_bits_denormFract_T_5, 22, 0) node _io_out_c_result_bits_expOut_T_12 = bits(io_out_c_result_bits_rawIn_2.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_13 = sub(_io_out_c_result_bits_expOut_T_12, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_14 = tail(_io_out_c_result_bits_expOut_T_13, 1) node _io_out_c_result_bits_expOut_T_15 = mux(io_out_c_result_bits_isSubnormal_2, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_14) node _io_out_c_result_bits_expOut_T_16 = or(io_out_c_result_bits_rawIn_2.isNaN, io_out_c_result_bits_rawIn_2.isInf) node _io_out_c_result_bits_expOut_T_17 = mux(_io_out_c_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_2 = or(_io_out_c_result_bits_expOut_T_15, _io_out_c_result_bits_expOut_T_17) node _io_out_c_result_bits_fractOut_T_4 = bits(io_out_c_result_bits_rawIn_2.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_5 = mux(io_out_c_result_bits_rawIn_2.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_4) node io_out_c_result_bits_fractOut_2 = mux(io_out_c_result_bits_isSubnormal_2, io_out_c_result_bits_denormFract_2, _io_out_c_result_bits_fractOut_T_5) node io_out_c_result_bits_hi_2 = cat(io_out_c_result_bits_rawIn_2.sign, io_out_c_result_bits_expOut_2) node _io_out_c_result_bits_T_2 = cat(io_out_c_result_bits_hi_2, io_out_c_result_bits_fractOut_2) connect io_out_c_result_2.bits, _io_out_c_result_bits_T_2 node io_out_c_self_rec_rawIn_sign_3 = bits(io_out_c_result_2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_3 = bits(io_out_c_result_2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_3 = bits(io_out_c_result_2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_3 = eq(io_out_c_self_rec_rawIn_expIn_3, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_3 = eq(io_out_c_self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_132 = bits(io_out_c_self_rec_rawIn_fractIn_3, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_133 = bits(io_out_c_self_rec_rawIn_fractIn_3, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_134 = bits(io_out_c_self_rec_rawIn_fractIn_3, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_135 = bits(io_out_c_self_rec_rawIn_fractIn_3, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_136 = bits(io_out_c_self_rec_rawIn_fractIn_3, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_137 = bits(io_out_c_self_rec_rawIn_fractIn_3, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_138 = bits(io_out_c_self_rec_rawIn_fractIn_3, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_139 = bits(io_out_c_self_rec_rawIn_fractIn_3, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_140 = bits(io_out_c_self_rec_rawIn_fractIn_3, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_141 = bits(io_out_c_self_rec_rawIn_fractIn_3, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_142 = bits(io_out_c_self_rec_rawIn_fractIn_3, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_143 = bits(io_out_c_self_rec_rawIn_fractIn_3, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_144 = bits(io_out_c_self_rec_rawIn_fractIn_3, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_145 = bits(io_out_c_self_rec_rawIn_fractIn_3, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_146 = bits(io_out_c_self_rec_rawIn_fractIn_3, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_147 = bits(io_out_c_self_rec_rawIn_fractIn_3, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_148 = bits(io_out_c_self_rec_rawIn_fractIn_3, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_149 = bits(io_out_c_self_rec_rawIn_fractIn_3, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_150 = bits(io_out_c_self_rec_rawIn_fractIn_3, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_151 = bits(io_out_c_self_rec_rawIn_fractIn_3, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_152 = bits(io_out_c_self_rec_rawIn_fractIn_3, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_153 = bits(io_out_c_self_rec_rawIn_fractIn_3, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_154 = bits(io_out_c_self_rec_rawIn_fractIn_3, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_155 = mux(_io_out_c_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_156 = mux(_io_out_c_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_155) node _io_out_c_self_rec_rawIn_normDist_T_157 = mux(_io_out_c_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_156) node _io_out_c_self_rec_rawIn_normDist_T_158 = mux(_io_out_c_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_157) node _io_out_c_self_rec_rawIn_normDist_T_159 = mux(_io_out_c_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_158) node _io_out_c_self_rec_rawIn_normDist_T_160 = mux(_io_out_c_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_159) node _io_out_c_self_rec_rawIn_normDist_T_161 = mux(_io_out_c_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_160) node _io_out_c_self_rec_rawIn_normDist_T_162 = mux(_io_out_c_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_161) node _io_out_c_self_rec_rawIn_normDist_T_163 = mux(_io_out_c_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_162) node _io_out_c_self_rec_rawIn_normDist_T_164 = mux(_io_out_c_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_163) node _io_out_c_self_rec_rawIn_normDist_T_165 = mux(_io_out_c_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_164) node _io_out_c_self_rec_rawIn_normDist_T_166 = mux(_io_out_c_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_165) node _io_out_c_self_rec_rawIn_normDist_T_167 = mux(_io_out_c_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_166) node _io_out_c_self_rec_rawIn_normDist_T_168 = mux(_io_out_c_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_167) node _io_out_c_self_rec_rawIn_normDist_T_169 = mux(_io_out_c_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_168) node _io_out_c_self_rec_rawIn_normDist_T_170 = mux(_io_out_c_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_169) node _io_out_c_self_rec_rawIn_normDist_T_171 = mux(_io_out_c_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_170) node _io_out_c_self_rec_rawIn_normDist_T_172 = mux(_io_out_c_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_171) node _io_out_c_self_rec_rawIn_normDist_T_173 = mux(_io_out_c_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_172) node _io_out_c_self_rec_rawIn_normDist_T_174 = mux(_io_out_c_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_173) node _io_out_c_self_rec_rawIn_normDist_T_175 = mux(_io_out_c_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_174) node io_out_c_self_rec_rawIn_normDist_3 = mux(_io_out_c_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_175) node _io_out_c_self_rec_rawIn_subnormFract_T_6 = dshl(io_out_c_self_rec_rawIn_fractIn_3, io_out_c_self_rec_rawIn_normDist_3) node _io_out_c_self_rec_rawIn_subnormFract_T_7 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_6, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_3 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_7, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_15 = xor(io_out_c_self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_16 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, _io_out_c_self_rec_rawIn_adjustedExp_T_15, io_out_c_self_rec_rawIn_expIn_3) node _io_out_c_self_rec_rawIn_adjustedExp_T_17 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_17) node _io_out_c_self_rec_rawIn_adjustedExp_T_19 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_16, _io_out_c_self_rec_rawIn_adjustedExp_T_18) node io_out_c_self_rec_rawIn_adjustedExp_3 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_19, 1) node io_out_c_self_rec_rawIn_isZero_3 = and(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) node _io_out_c_self_rec_rawIn_isSpecial_T_3 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_3 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_6 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_7 = and(io_out_c_self_rec_rawIn_isSpecial_3, _io_out_c_self_rec_rawIn_out_isNaN_T_6) connect io_out_c_self_rec_rawIn_3.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_7 node _io_out_c_self_rec_rawIn_out_isInf_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) connect io_out_c_self_rec_rawIn_3.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_3 connect io_out_c_self_rec_rawIn_3.isZero, io_out_c_self_rec_rawIn_isZero_3 connect io_out_c_self_rec_rawIn_3.sign, io_out_c_self_rec_rawIn_sign_3 node _io_out_c_self_rec_rawIn_out_sExp_T_6 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_7 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_6) connect io_out_c_self_rec_rawIn_3.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_7 node _io_out_c_self_rec_rawIn_out_sig_T_12 = eq(io_out_c_self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_12) node _io_out_c_self_rec_rawIn_out_sig_T_14 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_subnormFract_3, io_out_c_self_rec_rawIn_fractIn_3) node _io_out_c_self_rec_rawIn_out_sig_T_15 = cat(_io_out_c_self_rec_rawIn_out_sig_T_13, _io_out_c_self_rec_rawIn_out_sig_T_14) connect io_out_c_self_rec_rawIn_3.sig, _io_out_c_self_rec_rawIn_out_sig_T_15 node _io_out_c_self_rec_T_24 = bits(io_out_c_self_rec_rawIn_3.sExp, 8, 6) node _io_out_c_self_rec_T_25 = mux(io_out_c_self_rec_rawIn_3.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_24) node _io_out_c_self_rec_T_26 = mux(io_out_c_self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_27 = or(_io_out_c_self_rec_T_25, _io_out_c_self_rec_T_26) node _io_out_c_self_rec_T_28 = cat(io_out_c_self_rec_rawIn_3.sign, _io_out_c_self_rec_T_27) node _io_out_c_self_rec_T_29 = bits(io_out_c_self_rec_rawIn_3.sExp, 5, 0) node _io_out_c_self_rec_T_30 = cat(_io_out_c_self_rec_T_28, _io_out_c_self_rec_T_29) node _io_out_c_self_rec_T_31 = bits(io_out_c_self_rec_rawIn_3.sig, 22, 0) node io_out_c_self_rec_3 = cat(_io_out_c_self_rec_T_30, _io_out_c_self_rec_T_31) inst io_out_c_resizer_1 of RecFNToRecFN_172 connect io_out_c_resizer_1.io.in, io_out_c_self_rec_3 connect io_out_c_resizer_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer_1.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_3 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_3 = bits(io_out_c_resizer_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 6) node io_out_c_result_bits_rawIn_isZero_3 = eq(_io_out_c_result_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_3 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_6 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_7 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isNaN_T_6) connect io_out_c_result_bits_rawIn_3.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_7 node _io_out_c_result_bits_rawIn_out_isInf_T_9 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_10 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_11 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isInf_T_10) connect io_out_c_result_bits_rawIn_3.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_11 connect io_out_c_result_bits_rawIn_3.isZero, io_out_c_result_bits_rawIn_isZero_3 node _io_out_c_result_bits_rawIn_out_sign_T_3 = bits(io_out_c_resizer_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_3.sign, _io_out_c_result_bits_rawIn_out_sign_T_3 node _io_out_c_result_bits_rawIn_out_sExp_T_3 = cvt(io_out_c_result_bits_rawIn_exp_3) connect io_out_c_result_bits_rawIn_3.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_3 node _io_out_c_result_bits_rawIn_out_sig_T_12 = eq(io_out_c_result_bits_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_12) node _io_out_c_result_bits_rawIn_out_sig_T_14 = bits(io_out_c_resizer_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_15 = cat(_io_out_c_result_bits_rawIn_out_sig_T_13, _io_out_c_result_bits_rawIn_out_sig_T_14) connect io_out_c_result_bits_rawIn_3.sig, _io_out_c_result_bits_rawIn_out_sig_T_15 node io_out_c_result_bits_isSubnormal_3 = lt(io_out_c_result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_6 = bits(io_out_c_result_bits_rawIn_3.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_6) node io_out_c_result_bits_denormShiftDist_3 = tail(_io_out_c_result_bits_denormShiftDist_T_7, 1) node _io_out_c_result_bits_denormFract_T_6 = shr(io_out_c_result_bits_rawIn_3.sig, 1) node _io_out_c_result_bits_denormFract_T_7 = dshr(_io_out_c_result_bits_denormFract_T_6, io_out_c_result_bits_denormShiftDist_3) node io_out_c_result_bits_denormFract_3 = bits(_io_out_c_result_bits_denormFract_T_7, 22, 0) node _io_out_c_result_bits_expOut_T_18 = bits(io_out_c_result_bits_rawIn_3.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_19 = sub(_io_out_c_result_bits_expOut_T_18, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_20 = tail(_io_out_c_result_bits_expOut_T_19, 1) node _io_out_c_result_bits_expOut_T_21 = mux(io_out_c_result_bits_isSubnormal_3, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_20) node _io_out_c_result_bits_expOut_T_22 = or(io_out_c_result_bits_rawIn_3.isNaN, io_out_c_result_bits_rawIn_3.isInf) node _io_out_c_result_bits_expOut_T_23 = mux(_io_out_c_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_3 = or(_io_out_c_result_bits_expOut_T_21, _io_out_c_result_bits_expOut_T_23) node _io_out_c_result_bits_fractOut_T_6 = bits(io_out_c_result_bits_rawIn_3.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_7 = mux(io_out_c_result_bits_rawIn_3.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_6) node io_out_c_result_bits_fractOut_3 = mux(io_out_c_result_bits_isSubnormal_3, io_out_c_result_bits_denormFract_3, _io_out_c_result_bits_fractOut_T_7) node io_out_c_result_bits_hi_3 = cat(io_out_c_result_bits_rawIn_3.sign, io_out_c_result_bits_expOut_3) node _io_out_c_result_bits_T_3 = cat(io_out_c_result_bits_hi_3, io_out_c_result_bits_fractOut_3) connect io_out_c_result_3.bits, _io_out_c_result_bits_T_3 connect io.out_c, io_out_c_result_3 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_2 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_3 : UInt<32> connect _mac_unit_io_in_b_WIRE_3, io.in_b.bits node _mac_unit_io_in_b_T_1 = bits(_mac_unit_io_in_b_WIRE_3, 31, 0) connect _mac_unit_io_in_b_WIRE_2.bits, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_2.bits connect mac_unit.io.in_c.bits, c1.bits connect c1, mac_unit.io.out_d node c2_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c2_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c2_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c2_self_rec_rawIn_isZeroExpIn = eq(c2_self_rec_rawIn_expIn, UInt<1>(0h0)) node c2_self_rec_rawIn_isZeroFractIn = eq(c2_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_normDist_T = bits(c2_self_rec_rawIn_fractIn, 0, 0) node _c2_self_rec_rawIn_normDist_T_1 = bits(c2_self_rec_rawIn_fractIn, 1, 1) node _c2_self_rec_rawIn_normDist_T_2 = bits(c2_self_rec_rawIn_fractIn, 2, 2) node _c2_self_rec_rawIn_normDist_T_3 = bits(c2_self_rec_rawIn_fractIn, 3, 3) node _c2_self_rec_rawIn_normDist_T_4 = bits(c2_self_rec_rawIn_fractIn, 4, 4) node _c2_self_rec_rawIn_normDist_T_5 = bits(c2_self_rec_rawIn_fractIn, 5, 5) node _c2_self_rec_rawIn_normDist_T_6 = bits(c2_self_rec_rawIn_fractIn, 6, 6) node _c2_self_rec_rawIn_normDist_T_7 = bits(c2_self_rec_rawIn_fractIn, 7, 7) node _c2_self_rec_rawIn_normDist_T_8 = bits(c2_self_rec_rawIn_fractIn, 8, 8) node _c2_self_rec_rawIn_normDist_T_9 = bits(c2_self_rec_rawIn_fractIn, 9, 9) node _c2_self_rec_rawIn_normDist_T_10 = bits(c2_self_rec_rawIn_fractIn, 10, 10) node _c2_self_rec_rawIn_normDist_T_11 = bits(c2_self_rec_rawIn_fractIn, 11, 11) node _c2_self_rec_rawIn_normDist_T_12 = bits(c2_self_rec_rawIn_fractIn, 12, 12) node _c2_self_rec_rawIn_normDist_T_13 = bits(c2_self_rec_rawIn_fractIn, 13, 13) node _c2_self_rec_rawIn_normDist_T_14 = bits(c2_self_rec_rawIn_fractIn, 14, 14) node _c2_self_rec_rawIn_normDist_T_15 = bits(c2_self_rec_rawIn_fractIn, 15, 15) node _c2_self_rec_rawIn_normDist_T_16 = bits(c2_self_rec_rawIn_fractIn, 16, 16) node _c2_self_rec_rawIn_normDist_T_17 = bits(c2_self_rec_rawIn_fractIn, 17, 17) node _c2_self_rec_rawIn_normDist_T_18 = bits(c2_self_rec_rawIn_fractIn, 18, 18) node _c2_self_rec_rawIn_normDist_T_19 = bits(c2_self_rec_rawIn_fractIn, 19, 19) node _c2_self_rec_rawIn_normDist_T_20 = bits(c2_self_rec_rawIn_fractIn, 20, 20) node _c2_self_rec_rawIn_normDist_T_21 = bits(c2_self_rec_rawIn_fractIn, 21, 21) node _c2_self_rec_rawIn_normDist_T_22 = bits(c2_self_rec_rawIn_fractIn, 22, 22) node _c2_self_rec_rawIn_normDist_T_23 = mux(_c2_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c2_self_rec_rawIn_normDist_T_24 = mux(_c2_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c2_self_rec_rawIn_normDist_T_23) node _c2_self_rec_rawIn_normDist_T_25 = mux(_c2_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c2_self_rec_rawIn_normDist_T_24) node _c2_self_rec_rawIn_normDist_T_26 = mux(_c2_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c2_self_rec_rawIn_normDist_T_25) node _c2_self_rec_rawIn_normDist_T_27 = mux(_c2_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c2_self_rec_rawIn_normDist_T_26) node _c2_self_rec_rawIn_normDist_T_28 = mux(_c2_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c2_self_rec_rawIn_normDist_T_27) node _c2_self_rec_rawIn_normDist_T_29 = mux(_c2_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c2_self_rec_rawIn_normDist_T_28) node _c2_self_rec_rawIn_normDist_T_30 = mux(_c2_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c2_self_rec_rawIn_normDist_T_29) node _c2_self_rec_rawIn_normDist_T_31 = mux(_c2_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c2_self_rec_rawIn_normDist_T_30) node _c2_self_rec_rawIn_normDist_T_32 = mux(_c2_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c2_self_rec_rawIn_normDist_T_31) node _c2_self_rec_rawIn_normDist_T_33 = mux(_c2_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c2_self_rec_rawIn_normDist_T_32) node _c2_self_rec_rawIn_normDist_T_34 = mux(_c2_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c2_self_rec_rawIn_normDist_T_33) node _c2_self_rec_rawIn_normDist_T_35 = mux(_c2_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c2_self_rec_rawIn_normDist_T_34) node _c2_self_rec_rawIn_normDist_T_36 = mux(_c2_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c2_self_rec_rawIn_normDist_T_35) node _c2_self_rec_rawIn_normDist_T_37 = mux(_c2_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c2_self_rec_rawIn_normDist_T_36) node _c2_self_rec_rawIn_normDist_T_38 = mux(_c2_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c2_self_rec_rawIn_normDist_T_37) node _c2_self_rec_rawIn_normDist_T_39 = mux(_c2_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c2_self_rec_rawIn_normDist_T_38) node _c2_self_rec_rawIn_normDist_T_40 = mux(_c2_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c2_self_rec_rawIn_normDist_T_39) node _c2_self_rec_rawIn_normDist_T_41 = mux(_c2_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c2_self_rec_rawIn_normDist_T_40) node _c2_self_rec_rawIn_normDist_T_42 = mux(_c2_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c2_self_rec_rawIn_normDist_T_41) node _c2_self_rec_rawIn_normDist_T_43 = mux(_c2_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c2_self_rec_rawIn_normDist_T_42) node c2_self_rec_rawIn_normDist = mux(_c2_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c2_self_rec_rawIn_normDist_T_43) node _c2_self_rec_rawIn_subnormFract_T = dshl(c2_self_rec_rawIn_fractIn, c2_self_rec_rawIn_normDist) node _c2_self_rec_rawIn_subnormFract_T_1 = bits(_c2_self_rec_rawIn_subnormFract_T, 21, 0) node c2_self_rec_rawIn_subnormFract = shl(_c2_self_rec_rawIn_subnormFract_T_1, 1) node _c2_self_rec_rawIn_adjustedExp_T = xor(c2_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c2_self_rec_rawIn_adjustedExp_T_1 = mux(c2_self_rec_rawIn_isZeroExpIn, _c2_self_rec_rawIn_adjustedExp_T, c2_self_rec_rawIn_expIn) node _c2_self_rec_rawIn_adjustedExp_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c2_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c2_self_rec_rawIn_adjustedExp_T_2) node _c2_self_rec_rawIn_adjustedExp_T_4 = add(_c2_self_rec_rawIn_adjustedExp_T_1, _c2_self_rec_rawIn_adjustedExp_T_3) node c2_self_rec_rawIn_adjustedExp = tail(_c2_self_rec_rawIn_adjustedExp_T_4, 1) node c2_self_rec_rawIn_isZero = and(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_isZeroFractIn) node _c2_self_rec_rawIn_isSpecial_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 7) node c2_self_rec_rawIn_isSpecial = eq(_c2_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_self_rec_rawIn_out_isNaN_T = eq(c2_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_isNaN_T_1 = and(c2_self_rec_rawIn_isSpecial, _c2_self_rec_rawIn_out_isNaN_T) connect c2_self_rec_rawIn.isNaN, _c2_self_rec_rawIn_out_isNaN_T_1 node _c2_self_rec_rawIn_out_isInf_T = and(c2_self_rec_rawIn_isSpecial, c2_self_rec_rawIn_isZeroFractIn) connect c2_self_rec_rawIn.isInf, _c2_self_rec_rawIn_out_isInf_T connect c2_self_rec_rawIn.isZero, c2_self_rec_rawIn_isZero connect c2_self_rec_rawIn.sign, c2_self_rec_rawIn_sign node _c2_self_rec_rawIn_out_sExp_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 0) node _c2_self_rec_rawIn_out_sExp_T_1 = cvt(_c2_self_rec_rawIn_out_sExp_T) connect c2_self_rec_rawIn.sExp, _c2_self_rec_rawIn_out_sExp_T_1 node _c2_self_rec_rawIn_out_sig_T = eq(c2_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_self_rec_rawIn_out_sig_T) node _c2_self_rec_rawIn_out_sig_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_subnormFract, c2_self_rec_rawIn_fractIn) node _c2_self_rec_rawIn_out_sig_T_3 = cat(_c2_self_rec_rawIn_out_sig_T_1, _c2_self_rec_rawIn_out_sig_T_2) connect c2_self_rec_rawIn.sig, _c2_self_rec_rawIn_out_sig_T_3 node _c2_self_rec_T = bits(c2_self_rec_rawIn.sExp, 8, 6) node _c2_self_rec_T_1 = mux(c2_self_rec_rawIn.isZero, UInt<3>(0h0), _c2_self_rec_T) node _c2_self_rec_T_2 = mux(c2_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c2_self_rec_T_3 = or(_c2_self_rec_T_1, _c2_self_rec_T_2) node _c2_self_rec_T_4 = cat(c2_self_rec_rawIn.sign, _c2_self_rec_T_3) node _c2_self_rec_T_5 = bits(c2_self_rec_rawIn.sExp, 5, 0) node _c2_self_rec_T_6 = cat(_c2_self_rec_T_4, _c2_self_rec_T_5) node _c2_self_rec_T_7 = bits(c2_self_rec_rawIn.sig, 22, 0) node c2_self_rec = cat(_c2_self_rec_T_6, _c2_self_rec_T_7) inst c2_resizer of RecFNToRecFN_173 connect c2_resizer.io.in, c2_self_rec connect c2_resizer.io.roundingMode, UInt<3>(0h0) connect c2_resizer.io.detectTininess, UInt<1>(0h1) wire c2_result : { bits : UInt<32>} node c2_result_bits_rawIn_exp = bits(c2_resizer.io.out, 31, 23) node _c2_result_bits_rawIn_isZero_T = bits(c2_result_bits_rawIn_exp, 8, 6) node c2_result_bits_rawIn_isZero = eq(_c2_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_isSpecial_T = bits(c2_result_bits_rawIn_exp, 8, 7) node c2_result_bits_rawIn_isSpecial = eq(_c2_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_result_bits_rawIn_out_isNaN_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isNaN_T_1 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isNaN_T) connect c2_result_bits_rawIn.isNaN, _c2_result_bits_rawIn_out_isNaN_T_1 node _c2_result_bits_rawIn_out_isInf_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isInf_T_1 = eq(_c2_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_isInf_T_2 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isInf_T_1) connect c2_result_bits_rawIn.isInf, _c2_result_bits_rawIn_out_isInf_T_2 connect c2_result_bits_rawIn.isZero, c2_result_bits_rawIn_isZero node _c2_result_bits_rawIn_out_sign_T = bits(c2_resizer.io.out, 32, 32) connect c2_result_bits_rawIn.sign, _c2_result_bits_rawIn_out_sign_T node _c2_result_bits_rawIn_out_sExp_T = cvt(c2_result_bits_rawIn_exp) connect c2_result_bits_rawIn.sExp, _c2_result_bits_rawIn_out_sExp_T node _c2_result_bits_rawIn_out_sig_T = eq(c2_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_result_bits_rawIn_out_sig_T) node _c2_result_bits_rawIn_out_sig_T_2 = bits(c2_resizer.io.out, 22, 0) node _c2_result_bits_rawIn_out_sig_T_3 = cat(_c2_result_bits_rawIn_out_sig_T_1, _c2_result_bits_rawIn_out_sig_T_2) connect c2_result_bits_rawIn.sig, _c2_result_bits_rawIn_out_sig_T_3 node c2_result_bits_isSubnormal = lt(c2_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c2_result_bits_denormShiftDist_T = bits(c2_result_bits_rawIn.sExp, 4, 0) node _c2_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c2_result_bits_denormShiftDist_T) node c2_result_bits_denormShiftDist = tail(_c2_result_bits_denormShiftDist_T_1, 1) node _c2_result_bits_denormFract_T = shr(c2_result_bits_rawIn.sig, 1) node _c2_result_bits_denormFract_T_1 = dshr(_c2_result_bits_denormFract_T, c2_result_bits_denormShiftDist) node c2_result_bits_denormFract = bits(_c2_result_bits_denormFract_T_1, 22, 0) node _c2_result_bits_expOut_T = bits(c2_result_bits_rawIn.sExp, 7, 0) node _c2_result_bits_expOut_T_1 = sub(_c2_result_bits_expOut_T, UInt<8>(0h81)) node _c2_result_bits_expOut_T_2 = tail(_c2_result_bits_expOut_T_1, 1) node _c2_result_bits_expOut_T_3 = mux(c2_result_bits_isSubnormal, UInt<1>(0h0), _c2_result_bits_expOut_T_2) node _c2_result_bits_expOut_T_4 = or(c2_result_bits_rawIn.isNaN, c2_result_bits_rawIn.isInf) node _c2_result_bits_expOut_T_5 = mux(_c2_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c2_result_bits_expOut = or(_c2_result_bits_expOut_T_3, _c2_result_bits_expOut_T_5) node _c2_result_bits_fractOut_T = bits(c2_result_bits_rawIn.sig, 22, 0) node _c2_result_bits_fractOut_T_1 = mux(c2_result_bits_rawIn.isInf, UInt<1>(0h0), _c2_result_bits_fractOut_T) node c2_result_bits_fractOut = mux(c2_result_bits_isSubnormal, c2_result_bits_denormFract, _c2_result_bits_fractOut_T_1) node c2_result_bits_hi = cat(c2_result_bits_rawIn.sign, c2_result_bits_expOut) node _c2_result_bits_T = cat(c2_result_bits_hi, c2_result_bits_fractOut) connect c2_result.bits, _c2_result_bits_T connect c2, c2_result else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_4 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_5 : UInt<32> connect _mac_unit_io_in_b_WIRE_5, c2.bits node _mac_unit_io_in_b_T_2 = bits(_mac_unit_io_in_b_WIRE_5, 31, 0) connect _mac_unit_io_in_b_WIRE_4.bits, _mac_unit_io_in_b_T_2 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_4.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_6 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_7 : UInt<32> connect _mac_unit_io_in_b_WIRE_7, c1.bits node _mac_unit_io_in_b_T_3 = bits(_mac_unit_io_in_b_WIRE_7, 31, 0) connect _mac_unit_io_in_b_WIRE_6.bits, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_6.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c.bits invalidate io.out_b.bits wire _mac_unit_io_in_b_WIRE_8 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_9 : UInt<32> connect _mac_unit_io_in_b_WIRE_9, io.in_b.bits node _mac_unit_io_in_b_T_4 = bits(_mac_unit_io_in_b_WIRE_9, 31, 0) connect _mac_unit_io_in_b_WIRE_8.bits, _mac_unit_io_in_b_T_4 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_8.bits connect mac_unit.io.in_c.bits, c2.bits node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b.bits invalidate mac_unit.io.in_c.bits	module PE_20( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [31:0] io_in_a_bits, // @[PE.scala:35:14] input [31:0] io_in_b_bits, // @[PE.scala:35:14] input [31:0] io_in_d_bits, // @[PE.scala:35:14] output [31:0] io_out_a_bits, // @[PE.scala:35:14] output [31:0] io_out_b_bits, // @[PE.scala:35:14] output [31:0] io_out_c_bits, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [3:0] io_in_id, // @[PE.scala:35:14] output [3:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30] wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30] wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7] wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15] wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7] wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37] wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37] wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7] wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7] reg [31:0] c1_bits; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38] reg [31:0] c2_bits; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] \| _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29] wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34] wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34] wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] \| _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T = \|io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15] wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}] wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26] wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN \| io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 \| _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] \| _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN \| io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 \| _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37] assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37] wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] \| _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26] wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN \| c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 \| _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] \| _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29] wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] \| _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T_4 = \|io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15] wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<14>(0h2000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<13>(0h1000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<18>(0h2f000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<13>(0h1000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<27>(0h4000000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_155, _T_160) node _T_192 = or(_T_191, _T_165) node _T_193 = or(_T_192, _T_170) node _T_194 = or(_T_193, _T_175) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_185) node _T_197 = or(_T_196, _T_190) node _T_198 = and(_T_150, _T_197) node _T_199 = or(UInt<1>(0h0), _T_198) node _T_200 = and(_T_149, _T_199) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_200, UInt<1>(0h1), "") : assert_2 node _T_204 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_8) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<1>(0h1)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_9) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<2>(0h2)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_10) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<2>(0h3)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_11) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_231 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_204 connect _WIRE[1], _T_210 connect _WIRE[2], _T_216 connect _WIRE[3], _T_222 connect _WIRE[4], _T_228 connect _WIRE[5], _T_229 connect _WIRE[6], _T_230 connect _WIRE[7], _T_231 connect _WIRE[8], _T_232 node _T_233 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_234 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_235 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_238 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[5], _T_233, UInt<1>(0h0)) node _T_240 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_242 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_243 = or(_T_234, _T_235) node _T_244 = or(_T_243, _T_236) node _T_245 = or(_T_244, _T_237) node _T_246 = or(_T_245, _T_238) node _T_247 = or(_T_246, _T_239) node _T_248 = or(_T_247, _T_240) node _T_249 = or(_T_248, _T_241) node _T_250 = or(_T_249, _T_242) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_250 node _T_251 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_252 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_253 = and(_T_251, _T_252) node _T_254 = or(UInt<1>(0h0), _T_253) node _T_255 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<14>(0h2000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<17>(0h10000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_271 = cvt(_T_270) node _T_272 = and(_T_271, asSInt(UInt<18>(0h2f000))) node _T_273 = asSInt(_T_272) node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) node _T_275 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_276 = cvt(_T_275) node _T_277 = and(_T_276, asSInt(UInt<17>(0h10000))) node _T_278 = asSInt(_T_277) node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) node _T_280 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<13>(0h1000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<27>(0h4000000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<13>(0h1000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_259, _T_264) node _T_296 = or(_T_295, _T_269) node _T_297 = or(_T_296, _T_274) node _T_298 = or(_T_297, _T_279) node _T_299 = or(_T_298, _T_284) node _T_300 = or(_T_299, _T_289) node _T_301 = or(_T_300, _T_294) node _T_302 = and(_T_254, _T_301) node _T_303 = or(UInt<1>(0h0), _T_302) node _T_304 = and(_WIRE_1, _T_303) node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_T_304, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_304, UInt<1>(0h1), "") : assert_3 node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(source_ok, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_311 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_311, UInt<1>(0h1), "") : assert_5 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_318 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_318, UInt<1>(0h1), "") : assert_7 node _T_322 = not(io.in.a.bits.mask) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(_T_323, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_323, UInt<1>(0h1), "") : assert_8 node _T_327 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_327, UInt<1>(0h1), "") : assert_9 node _T_331 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_331 : node _T_332 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_333 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_12) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<1>(0h1)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_13) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_348 = shr(io.in.a.bits.source, 2) node _T_349 = eq(_T_348, UInt<2>(0h2)) node _T_350 = leq(UInt<1>(0h0), uncommonBits_14) node _T_351 = and(_T_349, _T_350) node _T_352 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_353 = and(_T_351, _T_352) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_354 = shr(io.in.a.bits.source, 2) node _T_355 = eq(_T_354, UInt<2>(0h3)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_15) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_362 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_363 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_364 = or(_T_335, _T_341) node _T_365 = or(_T_364, _T_347) node _T_366 = or(_T_365, _T_353) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = and(_T_334, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<27>(0h4000000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<13>(0h1000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = or(_T_379, _T_384) node _T_416 = or(_T_415, _T_389) node _T_417 = or(_T_416, _T_394) node _T_418 = or(_T_417, _T_399) node _T_419 = or(_T_418, _T_404) node _T_420 = or(_T_419, _T_409) node _T_421 = or(_T_420, _T_414) node _T_422 = and(_T_374, _T_421) node _T_423 = or(UInt<1>(0h0), _T_422) node _T_424 = and(_T_373, _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_424, UInt<1>(0h1), "") : assert_10 node _T_428 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<1>(0h0)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_16) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_435 = shr(io.in.a.bits.source, 2) node _T_436 = eq(_T_435, UInt<1>(0h1)) node _T_437 = leq(UInt<1>(0h0), uncommonBits_17) node _T_438 = and(_T_436, _T_437) node _T_439 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_440 = and(_T_438, _T_439) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_441 = shr(io.in.a.bits.source, 2) node _T_442 = eq(_T_441, UInt<2>(0h2)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_18) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_446 = and(_T_444, _T_445) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_447 = shr(io.in.a.bits.source, 2) node _T_448 = eq(_T_447, UInt<2>(0h3)) node _T_449 = leq(UInt<1>(0h0), uncommonBits_19) node _T_450 = and(_T_448, _T_449) node _T_451 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_452 = and(_T_450, _T_451) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_456 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_428 connect _WIRE_2[1], _T_434 connect _WIRE_2[2], _T_440 connect _WIRE_2[3], _T_446 connect _WIRE_2[4], _T_452 connect _WIRE_2[5], _T_453 connect _WIRE_2[6], _T_454 connect _WIRE_2[7], _T_455 connect _WIRE_2[8], _T_456 node _T_457 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_458 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE_2[5], _T_457, UInt<1>(0h0)) node _T_464 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = or(_T_458, _T_459) node _T_468 = or(_T_467, _T_460) node _T_469 = or(_T_468, _T_461) node _T_470 = or(_T_469, _T_462) node _T_471 = or(_T_470, _T_463) node _T_472 = or(_T_471, _T_464) node _T_473 = or(_T_472, _T_465) node _T_474 = or(_T_473, _T_466) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_474 node _T_475 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_476 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_477 = and(_T_475, _T_476) node _T_478 = or(UInt<1>(0h0), _T_477) node _T_479 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<14>(0h2000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<13>(0h1000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<17>(0h10000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<18>(0h2f000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_500 = cvt(_T_499) node _T_501 = and(_T_500, asSInt(UInt<17>(0h10000))) node _T_502 = asSInt(_T_501) node _T_503 = eq(_T_502, asSInt(UInt<1>(0h0))) node _T_504 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<13>(0h1000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<27>(0h4000000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = or(_T_483, _T_488) node _T_520 = or(_T_519, _T_493) node _T_521 = or(_T_520, _T_498) node _T_522 = or(_T_521, _T_503) node _T_523 = or(_T_522, _T_508) node _T_524 = or(_T_523, _T_513) node _T_525 = or(_T_524, _T_518) node _T_526 = and(_T_478, _T_525) node _T_527 = or(UInt<1>(0h0), _T_526) node _T_528 = and(_WIRE_3, _T_527) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_528, UInt<1>(0h1), "") : assert_11 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(source_ok, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_535 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_535, UInt<1>(0h1), "") : assert_13 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(is_aligned, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_542 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_542, UInt<1>(0h1), "") : assert_15 node _T_546 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_546, UInt<1>(0h1), "") : assert_16 node _T_550 = not(io.in.a.bits.mask) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_551, UInt<1>(0h1), "") : assert_17 node _T_555 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_555, UInt<1>(0h1), "") : assert_18 node _T_559 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_559 : node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<1>(0h0)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_20) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_570 = shr(io.in.a.bits.source, 2) node _T_571 = eq(_T_570, UInt<1>(0h1)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_21) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<2>(0h2)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_22) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<2>(0h3)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_23) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_591 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_592 = or(_T_563, _T_569) node _T_593 = or(_T_592, _T_575) node _T_594 = or(_T_593, _T_581) node _T_595 = or(_T_594, _T_587) node _T_596 = or(_T_595, _T_588) node _T_597 = or(_T_596, _T_589) node _T_598 = or(_T_597, _T_590) node _T_599 = or(_T_598, _T_591) node _T_600 = and(_T_562, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_601, UInt<1>(0h1), "") : assert_19 node _T_605 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_606 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_607 = and(_T_605, _T_606) node _T_608 = or(UInt<1>(0h0), _T_607) node _T_609 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<13>(0h1000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = and(_T_608, _T_613) node _T_615 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_616 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_617 = and(_T_615, _T_616) node _T_618 = or(UInt<1>(0h0), _T_617) node _T_619 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<14>(0h2000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<18>(0h2f000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<17>(0h10000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<13>(0h1000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_645 = cvt(_T_644) node _T_646 = and(_T_645, asSInt(UInt<27>(0h4000000))) node _T_647 = asSInt(_T_646) node _T_648 = eq(_T_647, asSInt(UInt<1>(0h0))) node _T_649 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_650 = cvt(_T_649) node _T_651 = and(_T_650, asSInt(UInt<13>(0h1000))) node _T_652 = asSInt(_T_651) node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0))) node _T_654 = or(_T_623, _T_628) node _T_655 = or(_T_654, _T_633) node _T_656 = or(_T_655, _T_638) node _T_657 = or(_T_656, _T_643) node _T_658 = or(_T_657, _T_648) node _T_659 = or(_T_658, _T_653) node _T_660 = and(_T_618, _T_659) node _T_661 = or(UInt<1>(0h0), _T_614) node _T_662 = or(_T_661, _T_660) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_662, UInt<1>(0h1), "") : assert_20 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(source_ok, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_672, UInt<1>(0h1), "") : assert_23 node _T_676 = eq(io.in.a.bits.mask, mask) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_676, UInt<1>(0h1), "") : assert_24 node _T_680 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_680, UInt<1>(0h1), "") : assert_25 node _T_684 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_24) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_25) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_26) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_27) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_728 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_729 = and(_T_727, _T_728) node _T_730 = or(UInt<1>(0h0), _T_729) node _T_731 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = and(_T_730, _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<18>(0h2f000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<13>(0h1000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<27>(0h4000000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = or(_T_745, _T_750) node _T_772 = or(_T_771, _T_755) node _T_773 = or(_T_772, _T_760) node _T_774 = or(_T_773, _T_765) node _T_775 = or(_T_774, _T_770) node _T_776 = and(_T_740, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_736) node _T_785 = or(_T_784, _T_776) node _T_786 = or(_T_785, _T_783) node _T_787 = and(_T_726, _T_786) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_787, UInt<1>(0h1), "") : assert_26 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(source_ok, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(is_aligned, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_797 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(_T_797, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_797, UInt<1>(0h1), "") : assert_29 node _T_801 = eq(io.in.a.bits.mask, mask) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_801, UInt<1>(0h1), "") : assert_30 node _T_805 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_805 : node _T_806 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_807 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_808 = and(_T_806, _T_807) node _T_809 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_810 = shr(io.in.a.bits.source, 2) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = leq(UInt<1>(0h0), uncommonBits_28) node _T_813 = and(_T_811, _T_812) node _T_814 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_815 = and(_T_813, _T_814) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_816 = shr(io.in.a.bits.source, 2) node _T_817 = eq(_T_816, UInt<1>(0h1)) node _T_818 = leq(UInt<1>(0h0), uncommonBits_29) node _T_819 = and(_T_817, _T_818) node _T_820 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_821 = and(_T_819, _T_820) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_822 = shr(io.in.a.bits.source, 2) node _T_823 = eq(_T_822, UInt<2>(0h2)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_30) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_828 = shr(io.in.a.bits.source, 2) node _T_829 = eq(_T_828, UInt<2>(0h3)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_31) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_833 = and(_T_831, _T_832) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_837 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_838 = or(_T_809, _T_815) node _T_839 = or(_T_838, _T_821) node _T_840 = or(_T_839, _T_827) node _T_841 = or(_T_840, _T_833) node _T_842 = or(_T_841, _T_834) node _T_843 = or(_T_842, _T_835) node _T_844 = or(_T_843, _T_836) node _T_845 = or(_T_844, _T_837) node _T_846 = and(_T_808, _T_845) node _T_847 = or(UInt<1>(0h0), _T_846) node _T_848 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_849 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_850 = and(_T_848, _T_849) node _T_851 = or(UInt<1>(0h0), _T_850) node _T_852 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_853 = cvt(_T_852) node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000))) node _T_855 = asSInt(_T_854) node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0))) node _T_857 = and(_T_851, _T_856) node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_859 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_860 = and(_T_858, _T_859) node _T_861 = or(UInt<1>(0h0), _T_860) node _T_862 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<14>(0h2000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<18>(0h2f000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_873 = cvt(_T_872) node _T_874 = and(_T_873, asSInt(UInt<17>(0h10000))) node _T_875 = asSInt(_T_874) node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0))) node _T_877 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<13>(0h1000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<27>(0h4000000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<13>(0h1000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = or(_T_866, _T_871) node _T_893 = or(_T_892, _T_876) node _T_894 = or(_T_893, _T_881) node _T_895 = or(_T_894, _T_886) node _T_896 = or(_T_895, _T_891) node _T_897 = and(_T_861, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<17>(0h10000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = and(_T_898, _T_903) node _T_905 = or(UInt<1>(0h0), _T_857) node _T_906 = or(_T_905, _T_897) node _T_907 = or(_T_906, _T_904) node _T_908 = and(_T_847, _T_907) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_908, UInt<1>(0h1), "") : assert_31 node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(source_ok, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(is_aligned, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_918 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_918, UInt<1>(0h1), "") : assert_34 node _T_922 = not(mask) node _T_923 = and(io.in.a.bits.mask, _T_922) node _T_924 = eq(_T_923, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_924, UInt<1>(0h1), "") : assert_35 node _T_928 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_928 : node _T_929 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_930 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_931 = and(_T_929, _T_930) node _T_932 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_933 = shr(io.in.a.bits.source, 2) node _T_934 = eq(_T_933, UInt<1>(0h0)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_32) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_938 = and(_T_936, _T_937) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_939 = shr(io.in.a.bits.source, 2) node _T_940 = eq(_T_939, UInt<1>(0h1)) node _T_941 = leq(UInt<1>(0h0), uncommonBits_33) node _T_942 = and(_T_940, _T_941) node _T_943 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_944 = and(_T_942, _T_943) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_945 = shr(io.in.a.bits.source, 2) node _T_946 = eq(_T_945, UInt<2>(0h2)) node _T_947 = leq(UInt<1>(0h0), uncommonBits_34) node _T_948 = and(_T_946, _T_947) node _T_949 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<2>(0h3)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_35) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_961 = or(_T_932, _T_938) node _T_962 = or(_T_961, _T_944) node _T_963 = or(_T_962, _T_950) node _T_964 = or(_T_963, _T_956) node _T_965 = or(_T_964, _T_957) node _T_966 = or(_T_965, _T_958) node _T_967 = or(_T_966, _T_959) node _T_968 = or(_T_967, _T_960) node _T_969 = and(_T_931, _T_968) node _T_970 = or(UInt<1>(0h0), _T_969) node _T_971 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_972 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_973 = and(_T_971, _T_972) node _T_974 = or(UInt<1>(0h0), _T_973) node _T_975 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_976 = cvt(_T_975) node _T_977 = and(_T_976, asSInt(UInt<14>(0h2000))) node _T_978 = asSInt(_T_977) node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0))) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_986 = cvt(_T_985) node _T_987 = and(_T_986, asSInt(UInt<18>(0h2f000))) node _T_988 = asSInt(_T_987) node _T_989 = eq(_T_988, asSInt(UInt<1>(0h0))) node _T_990 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_991 = cvt(_T_990) node _T_992 = and(_T_991, asSInt(UInt<17>(0h10000))) node _T_993 = asSInt(_T_992) node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0))) node _T_995 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_996 = cvt(_T_995) node _T_997 = and(_T_996, asSInt(UInt<13>(0h1000))) node _T_998 = asSInt(_T_997) node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0))) node _T_1000 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<27>(0h4000000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<13>(0h1000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_979, _T_984) node _T_1011 = or(_T_1010, _T_989) node _T_1012 = or(_T_1011, _T_994) node _T_1013 = or(_T_1012, _T_999) node _T_1014 = or(_T_1013, _T_1004) node _T_1015 = or(_T_1014, _T_1009) node _T_1016 = and(_T_974, _T_1015) node _T_1017 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1018 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<17>(0h10000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = and(_T_1017, _T_1022) node _T_1024 = or(UInt<1>(0h0), _T_1016) node _T_1025 = or(_T_1024, _T_1023) node _T_1026 = and(_T_970, _T_1025) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_36 node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(is_aligned, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1036 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_39 node _T_1040 = eq(io.in.a.bits.mask, mask) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_40 node _T_1044 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1044 : node _T_1045 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1046 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1049 = shr(io.in.a.bits.source, 2) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1055 = shr(io.in.a.bits.source, 2) node _T_1056 = eq(_T_1055, UInt<1>(0h1)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1061 = shr(io.in.a.bits.source, 2) node _T_1062 = eq(_T_1061, UInt<2>(0h2)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1066 = and(_T_1064, _T_1065) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1067 = shr(io.in.a.bits.source, 2) node _T_1068 = eq(_T_1067, UInt<2>(0h3)) node _T_1069 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1077 = or(_T_1048, _T_1054) node _T_1078 = or(_T_1077, _T_1060) node _T_1079 = or(_T_1078, _T_1066) node _T_1080 = or(_T_1079, _T_1072) node _T_1081 = or(_T_1080, _T_1073) node _T_1082 = or(_T_1081, _T_1074) node _T_1083 = or(_T_1082, _T_1075) node _T_1084 = or(_T_1083, _T_1076) node _T_1085 = and(_T_1047, _T_1084) node _T_1086 = or(UInt<1>(0h0), _T_1085) node _T_1087 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1088 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = or(UInt<1>(0h0), _T_1089) node _T_1091 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1092 = cvt(_T_1091) node _T_1093 = and(_T_1092, asSInt(UInt<14>(0h2000))) node _T_1094 = asSInt(_T_1093) node _T_1095 = eq(_T_1094, asSInt(UInt<1>(0h0))) node _T_1096 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1097 = cvt(_T_1096) node _T_1098 = and(_T_1097, asSInt(UInt<13>(0h1000))) node _T_1099 = asSInt(_T_1098) node _T_1100 = eq(_T_1099, asSInt(UInt<1>(0h0))) node _T_1101 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<18>(0h2f000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<17>(0h10000))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1112 = cvt(_T_1111) node _T_1113 = and(_T_1112, asSInt(UInt<13>(0h1000))) node _T_1114 = asSInt(_T_1113) node _T_1115 = eq(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1117 = cvt(_T_1116) node _T_1118 = and(_T_1117, asSInt(UInt<27>(0h4000000))) node _T_1119 = asSInt(_T_1118) node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0))) node _T_1121 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<13>(0h1000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = or(_T_1095, _T_1100) node _T_1127 = or(_T_1126, _T_1105) node _T_1128 = or(_T_1127, _T_1110) node _T_1129 = or(_T_1128, _T_1115) node _T_1130 = or(_T_1129, _T_1120) node _T_1131 = or(_T_1130, _T_1125) node _T_1132 = and(_T_1090, _T_1131) node _T_1133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = and(_T_1133, _T_1138) node _T_1140 = or(UInt<1>(0h0), _T_1132) node _T_1141 = or(_T_1140, _T_1139) node _T_1142 = and(_T_1086, _T_1141) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_41 node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(source_ok, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(is_aligned, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1152 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_44 node _T_1156 = eq(io.in.a.bits.mask, mask) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_45 node _T_1160 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1160 : node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1162 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<1>(0h1)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1177 = shr(io.in.a.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h2)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1183 = shr(io.in.a.bits.source, 2) node _T_1184 = eq(_T_1183, UInt<2>(0h3)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1193 = or(_T_1164, _T_1170) node _T_1194 = or(_T_1193, _T_1176) node _T_1195 = or(_T_1194, _T_1182) node _T_1196 = or(_T_1195, _T_1188) node _T_1197 = or(_T_1196, _T_1189) node _T_1198 = or(_T_1197, _T_1190) node _T_1199 = or(_T_1198, _T_1191) node _T_1200 = or(_T_1199, _T_1192) node _T_1201 = and(_T_1163, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1201) node _T_1203 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1204 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = or(UInt<1>(0h0), _T_1205) node _T_1207 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1208 = cvt(_T_1207) node _T_1209 = and(_T_1208, asSInt(UInt<13>(0h1000))) node _T_1210 = asSInt(_T_1209) node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = and(_T_1206, _T_1211) node _T_1213 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1214 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<14>(0h2000))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1220 = cvt(_T_1219) node _T_1221 = and(_T_1220, asSInt(UInt<17>(0h10000))) node _T_1222 = asSInt(_T_1221) node _T_1223 = eq(_T_1222, asSInt(UInt<1>(0h0))) node _T_1224 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1225 = cvt(_T_1224) node _T_1226 = and(_T_1225, asSInt(UInt<18>(0h2f000))) node _T_1227 = asSInt(_T_1226) node _T_1228 = eq(_T_1227, asSInt(UInt<1>(0h0))) node _T_1229 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1230 = cvt(_T_1229) node _T_1231 = and(_T_1230, asSInt(UInt<17>(0h10000))) node _T_1232 = asSInt(_T_1231) node _T_1233 = eq(_T_1232, asSInt(UInt<1>(0h0))) node _T_1234 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1235 = cvt(_T_1234) node _T_1236 = and(_T_1235, asSInt(UInt<13>(0h1000))) node _T_1237 = asSInt(_T_1236) node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0))) node _T_1239 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1240 = cvt(_T_1239) node _T_1241 = and(_T_1240, asSInt(UInt<27>(0h4000000))) node _T_1242 = asSInt(_T_1241) node _T_1243 = eq(_T_1242, asSInt(UInt<1>(0h0))) node _T_1244 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1245 = cvt(_T_1244) node _T_1246 = and(_T_1245, asSInt(UInt<13>(0h1000))) node _T_1247 = asSInt(_T_1246) node _T_1248 = eq(_T_1247, asSInt(UInt<1>(0h0))) node _T_1249 = or(_T_1218, _T_1223) node _T_1250 = or(_T_1249, _T_1228) node _T_1251 = or(_T_1250, _T_1233) node _T_1252 = or(_T_1251, _T_1238) node _T_1253 = or(_T_1252, _T_1243) node _T_1254 = or(_T_1253, _T_1248) node _T_1255 = and(_T_1213, _T_1254) node _T_1256 = or(UInt<1>(0h0), _T_1212) node _T_1257 = or(_T_1256, _T_1255) node _T_1258 = and(_T_1202, _T_1257) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_46 node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(source_ok, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(is_aligned, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1268 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_49 node _T_1272 = eq(io.in.a.bits.mask, mask) node _T_1273 = asUInt(reset) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) when _T_1274 : node _T_1275 = eq(_T_1272, UInt<1>(0h0)) when _T_1275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1272, UInt<1>(0h1), "") : assert_50 node _T_1276 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1280 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1284 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1284 : node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(source_ok_1, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1288 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_54 node _T_1292 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_55 node _T_1296 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_56 node _T_1300 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_57 node _T_1304 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1304 : node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(source_ok_1, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(sink_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1311 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_60 node _T_1315 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_61 node _T_1319 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_62 node _T_1323 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_63 node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1328 = or(UInt<1>(0h1), _T_1327) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_64 node _T_1332 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1332 : node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(source_ok_1, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(sink_ok, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1339 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_67 node _T_1343 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_68 node _T_1347 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_69 node _T_1351 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1352 = or(_T_1351, io.in.d.bits.corrupt) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_70 node _T_1356 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1357 = or(UInt<1>(0h1), _T_1356) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_71 node _T_1361 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1361 : node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(source_ok_1, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1365 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_73 node _T_1369 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_74 node _T_1373 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1374 = or(UInt<1>(0h1), _T_1373) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_75 node _T_1378 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1378 : node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(source_ok_1, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1382 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1383 = asUInt(reset) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) when _T_1384 : node _T_1385 = eq(_T_1382, UInt<1>(0h0)) when _T_1385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1382, UInt<1>(0h1), "") : assert_77 node _T_1386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1387 = or(_T_1386, io.in.d.bits.corrupt) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_78 node _T_1391 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1392 = or(UInt<1>(0h1), _T_1391) node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(_T_1392, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1392, UInt<1>(0h1), "") : assert_79 node _T_1396 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1396 : node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(source_ok_1, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1400 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_81 node _T_1404 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_82 node _T_1408 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1409 = or(UInt<1>(0h1), _T_1408) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1413 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(_T_1413, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1413, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1417 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(_T_1417, UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1417, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1421 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1425 = eq(a_first, UInt<1>(0h0)) node _T_1426 = and(io.in.a.valid, _T_1425) when _T_1426 : node _T_1427 = eq(io.in.a.bits.opcode, opcode) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_87 node _T_1431 = eq(io.in.a.bits.param, param) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_88 node _T_1435 = eq(io.in.a.bits.size, size) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_89 node _T_1439 = eq(io.in.a.bits.source, source) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_90 node _T_1443 = eq(io.in.a.bits.address, address) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_91 node _T_1447 = and(io.in.a.ready, io.in.a.valid) node _T_1448 = and(_T_1447, a_first) when _T_1448 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1449 = eq(d_first, UInt<1>(0h0)) node _T_1450 = and(io.in.d.valid, _T_1449) when _T_1450 : node _T_1451 = eq(io.in.d.bits.opcode, opcode_1) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_92 node _T_1455 = eq(io.in.d.bits.param, param_1) node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(_T_1455, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1455, UInt<1>(0h1), "") : assert_93 node _T_1459 = eq(io.in.d.bits.size, size_1) node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(_T_1459, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1459, UInt<1>(0h1), "") : assert_94 node _T_1463 = eq(io.in.d.bits.source, source_1) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_95 node _T_1467 = eq(io.in.d.bits.sink, sink) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_96 node _T_1471 = eq(io.in.d.bits.denied, denied) node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(_T_1471, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1471, UInt<1>(0h1), "") : assert_97 node _T_1475 = and(io.in.d.ready, io.in.d.valid) node _T_1476 = and(_T_1475, d_first) when _T_1476 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1477 = and(io.in.a.valid, a_first_1) node _T_1478 = and(_T_1477, UInt<1>(0h1)) when _T_1478 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1479 = and(io.in.a.ready, io.in.a.valid) node _T_1480 = and(_T_1479, a_first_1) node _T_1481 = and(_T_1480, UInt<1>(0h1)) when _T_1481 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1482 = dshr(inflight, io.in.a.bits.source) node _T_1483 = bits(_T_1482, 0, 0) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1488 = and(io.in.d.valid, d_first_1) node _T_1489 = and(_T_1488, UInt<1>(0h1)) node _T_1490 = eq(d_release_ack, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1492 = and(io.in.d.ready, io.in.d.valid) node _T_1493 = and(_T_1492, d_first_1) node _T_1494 = and(_T_1493, UInt<1>(0h1)) node _T_1495 = eq(d_release_ack, UInt<1>(0h0)) node _T_1496 = and(_T_1494, _T_1495) when _T_1496 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1497 = and(io.in.d.valid, d_first_1) node _T_1498 = and(_T_1497, UInt<1>(0h1)) node _T_1499 = eq(d_release_ack, UInt<1>(0h0)) node _T_1500 = and(_T_1498, _T_1499) when _T_1500 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1501 = dshr(inflight, io.in.d.bits.source) node _T_1502 = bits(_T_1501, 0, 0) node _T_1503 = or(_T_1502, same_cycle_resp) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1507 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1508 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1509 = or(_T_1507, _T_1508) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_100 node _T_1513 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(_T_1513, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1513, UInt<1>(0h1), "") : assert_101 else : node _T_1517 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1518 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_102 node _T_1523 = eq(io.in.d.bits.size, a_size_lookup) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_103 node _T_1527 = and(io.in.d.valid, d_first_1) node _T_1528 = and(_T_1527, a_first_1) node _T_1529 = and(_T_1528, io.in.a.valid) node _T_1530 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1531 = and(_T_1529, _T_1530) node _T_1532 = eq(d_release_ack, UInt<1>(0h0)) node _T_1533 = and(_T_1531, _T_1532) when _T_1533 : node _T_1534 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1535 = or(_T_1534, io.in.a.ready) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_104 node _T_1539 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1540 = orr(a_set_wo_ready) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) node _T_1542 = or(_T_1539, _T_1541) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1546 = orr(inflight) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) node _T_1548 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1549 = or(_T_1547, _T_1548) node _T_1550 = lt(watchdog, plusarg_reader.out) node _T_1551 = or(_T_1549, _T_1550) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1555 = and(io.in.a.ready, io.in.a.valid) node _T_1556 = and(io.in.d.ready, io.in.d.valid) node _T_1557 = or(_T_1555, _T_1556) when _T_1557 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1558 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1559 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1560 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = and(_T_1558, _T_1561) when _T_1562 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1563 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1564 = and(_T_1563, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1565 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1566 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = and(_T_1564, _T_1567) when _T_1568 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1569 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1570 = bits(_T_1569, 0, 0) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1575 = and(io.in.d.valid, d_first_2) node _T_1576 = and(_T_1575, UInt<1>(0h1)) node _T_1577 = and(_T_1576, d_release_ack_1) when _T_1577 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1578 = and(io.in.d.ready, io.in.d.valid) node _T_1579 = and(_T_1578, d_first_2) node _T_1580 = and(_T_1579, UInt<1>(0h1)) node _T_1581 = and(_T_1580, d_release_ack_1) when _T_1581 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1582 = and(io.in.d.valid, d_first_2) node _T_1583 = and(_T_1582, UInt<1>(0h1)) node _T_1584 = and(_T_1583, d_release_ack_1) when _T_1584 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1585 = dshr(inflight_1, io.in.d.bits.source) node _T_1586 = bits(_T_1585, 0, 0) node _T_1587 = or(_T_1586, same_cycle_resp_1) node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(_T_1587, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1587, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1591 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_109 else : node _T_1595 = eq(io.in.d.bits.size, c_size_lookup) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_110 node _T_1599 = and(io.in.d.valid, d_first_2) node _T_1600 = and(_T_1599, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1601 = and(_T_1600, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1602 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1603 = and(_T_1601, _T_1602) node _T_1604 = and(_T_1603, d_release_ack_1) node _T_1605 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1606 = and(_T_1604, _T_1605) when _T_1606 : node _T_1607 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1608 = or(_T_1607, _WIRE_27.ready) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_111 node _T_1612 = orr(c_set_wo_ready) when _T_1612 : node _T_1613 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(_T_1613, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1613, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1617 = orr(inflight_1) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) node _T_1619 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1620 = or(_T_1618, _T_1619) node _T_1621 = lt(watchdog_1, plusarg_reader_1.out) node _T_1622 = or(_T_1620, _T_1621) node _T_1623 = asUInt(reset) node _T_1624 = eq(_T_1623, UInt<1>(0h0)) when _T_1624 : node _T_1625 = eq(_T_1622, UInt<1>(0h0)) when _T_1625 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1622, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1626 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1627 = and(io.in.d.ready, io.in.d.valid) node _T_1628 = or(_T_1626, _T_1627) when _T_1628 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1555 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1555; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1555; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1628 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1628; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1628; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1628; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1481 = _T_1555 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1481 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1481 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1481 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1481 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1481 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1527 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1527 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1496 = _T_1628 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1496 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1496 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1496 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1599 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1599 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1581 = _T_1628 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1581 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1581 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1581 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_24 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_24(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_205 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_205( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_66 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_66( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_8 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<25> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_46_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_39_2, rrd_cs_decoder_decoded_andMatrixOutputs_27_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_52_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_25_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_1_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_56_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_63_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_19) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_23_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_22_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_37_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_51_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_6_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_54_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_27) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_61_2, rrd_cs_decoder_decoded_andMatrixOutputs_48_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_7_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_30) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_53_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_32) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_35 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_34) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_14, _rrd_cs_decoder_decoded_orMatrixOutputs_T_12) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_18) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_24, _rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_29, _rrd_cs_decoder_decoded_orMatrixOutputs_T_28) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_31) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_35) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_14, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 24, 24) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 24, 21) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 20, 20) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 17, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid	module RegisterReadDecode_8( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [15:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [15:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [15:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [15:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [4:0] rrd_cs_decoder_4; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [24:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [24:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = rrd_cs_decoder_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62; // @[pla.scala:90:45, :98:70] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = rrd_cs_decoder_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_46_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_39_2, rrd_cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_52_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_25_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_56_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_23_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [9:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_6_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_61_2, rrd_cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_35 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_34; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_14, _rrd_cs_decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_24, _rrd_cs_decoder_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_29, _rrd_cs_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_31}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, 3'h0}; // @[pla.scala:102:36] wire [12:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:102:36] wire [24:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_14, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_21; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = rrd_cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [3:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[24:21]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[20]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] assign rrd_cs_decoder_4 = rrd_cs_decoder_decoded[17:13]; // @[pla.scala:81:23] assign rrd_cs_op_fcn = rrd_cs_decoder_4; // @[Decode.scala:50:77] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T \| _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T \| _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 \| _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T \| _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 7'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_182 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_182( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_178 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_195 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_178( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_195 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_22 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_214 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_215 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_22( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_214 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_215 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_123 = shr(io.in.a.bits.source, 3) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_130 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_240 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_314 = shr(io.in.a.bits.source, 3) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_321 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_428 = shr(io.in.a.bits.source, 3) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_435 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_538 = shr(io.in.a.bits.source, 3) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_545 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_651 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_752 = shr(io.in.a.bits.source, 3) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_759 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<27>(0h4000000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<13>(0h1000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = or(_T_772, _T_777) node _T_804 = or(_T_803, _T_782) node _T_805 = or(_T_804, _T_787) node _T_806 = or(_T_805, _T_792) node _T_807 = or(_T_806, _T_797) node _T_808 = or(_T_807, _T_802) node _T_809 = and(_T_767, _T_808) node _T_810 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_811 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_812 = cvt(_T_811) node _T_813 = and(_T_812, asSInt(UInt<17>(0h10000))) node _T_814 = asSInt(_T_813) node _T_815 = eq(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = and(_T_810, _T_815) node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_818 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_819 = and(_T_817, _T_818) node _T_820 = or(UInt<1>(0h0), _T_819) node _T_821 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_822 = cvt(_T_821) node _T_823 = and(_T_822, asSInt(UInt<17>(0h10000))) node _T_824 = asSInt(_T_823) node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0))) node _T_826 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<29>(0h10000000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = or(_T_825, _T_830) node _T_832 = and(_T_820, _T_831) node _T_833 = or(UInt<1>(0h0), _T_809) node _T_834 = or(_T_833, _T_816) node _T_835 = or(_T_834, _T_832) node _T_836 = and(_T_763, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_836, UInt<1>(0h1), "") : assert_36 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(source_ok, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(is_aligned, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_846 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_846, UInt<1>(0h1), "") : assert_39 node _T_850 = eq(io.in.a.bits.mask, mask) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_850, UInt<1>(0h1), "") : assert_40 node _T_854 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_854 : node _T_855 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_856 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_858 = shr(io.in.a.bits.source, 3) node _T_859 = eq(_T_858, UInt<1>(0h0)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_9) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_863 = and(_T_861, _T_862) node _T_864 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_865 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_866 = or(_T_863, _T_864) node _T_867 = or(_T_866, _T_865) node _T_868 = and(_T_857, _T_867) node _T_869 = or(UInt<1>(0h0), _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<13>(0h1000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<17>(0h10000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = and(_T_916, _T_921) node _T_923 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_924 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_925 = and(_T_923, _T_924) node _T_926 = or(UInt<1>(0h0), _T_925) node _T_927 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<29>(0h10000000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = or(_T_931, _T_936) node _T_938 = and(_T_926, _T_937) node _T_939 = or(UInt<1>(0h0), _T_915) node _T_940 = or(_T_939, _T_922) node _T_941 = or(_T_940, _T_938) node _T_942 = and(_T_869, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_942, UInt<1>(0h1), "") : assert_41 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(is_aligned, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_952 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_952, UInt<1>(0h1), "") : assert_44 node _T_956 = eq(io.in.a.bits.mask, mask) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_956, UInt<1>(0h1), "") : assert_45 node _T_960 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_960 : node _T_961 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_962 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_964 = shr(io.in.a.bits.source, 3) node _T_965 = eq(_T_964, UInt<1>(0h0)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_10) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_971 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_972 = or(_T_969, _T_970) node _T_973 = or(_T_972, _T_971) node _T_974 = and(_T_963, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<14>(0h2000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_991, _T_996) node _T_1023 = or(_T_1022, _T_1001) node _T_1024 = or(_T_1023, _T_1006) node _T_1025 = or(_T_1024, _T_1011) node _T_1026 = or(_T_1025, _T_1016) node _T_1027 = or(_T_1026, _T_1021) node _T_1028 = and(_T_986, _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<17>(0h10000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<29>(0h10000000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _T_1044 = and(_T_1032, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_985) node _T_1046 = or(_T_1045, _T_1028) node _T_1047 = or(_T_1046, _T_1044) node _T_1048 = and(_T_975, _T_1047) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_46 node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(is_aligned, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1058 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_49 node _T_1062 = eq(io.in.a.bits.mask, mask) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_50 node _T_1066 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1070 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1074 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1074 : node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(source_ok_1, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1078 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_54 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_55 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_56 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_57 node _T_1094 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1094 : node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(source_ok_1, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(sink_ok, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1101 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_60 node _T_1105 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_61 node _T_1109 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_62 node _T_1113 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_63 node _T_1117 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1118 = or(UInt<1>(0h1), _T_1117) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_64 node _T_1122 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(source_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(sink_ok, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1129 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_67 node _T_1133 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_68 node _T_1137 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_69 node _T_1141 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.d.bits.corrupt) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_70 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h1), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_71 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_73 node _T_1159 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_74 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(UInt<1>(0h1), _T_1163) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_75 node _T_1168 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1168 : node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(source_ok_1, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1172 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_77 node _T_1176 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1177 = or(_T_1176, io.in.d.bits.corrupt) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_78 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h1), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_79 node _T_1186 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1186 : node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(source_ok_1, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1190 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_81 node _T_1194 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_82 node _T_1198 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1199 = or(UInt<1>(0h1), _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1203 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1207 = shr(io.in.b.bits.source, 3) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) node _T_1214 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1213, _T_1218) node _T_1220 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = and(_T_1219, _T_1227) node _T_1237 = and(_T_1236, _T_1235) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1241 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1241 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1242 = shr(io.in.b.bits.source, 3) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1249 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1247 connect _WIRE_4[1], _T_1248 connect _WIRE_4[2], _T_1249 node _T_1250 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1251 = mux(_WIRE_4[0], _T_1250, UInt<1>(0h0)) node _T_1252 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1253 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1254 = or(_T_1251, _T_1252) node _T_1255 = or(_T_1254, _T_1253) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1255 node _T_1256 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1257 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = or(UInt<1>(0h0), _T_1258) node _T_1260 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<14>(0h2000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<13>(0h1000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<18>(0h2f000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<17>(0h10000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<27>(0h4000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1301 = cvt(_T_1300) node _T_1302 = and(_T_1301, asSInt(UInt<13>(0h1000))) node _T_1303 = asSInt(_T_1302) node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0))) node _T_1305 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = or(_T_1264, _T_1269) node _T_1311 = or(_T_1310, _T_1274) node _T_1312 = or(_T_1311, _T_1279) node _T_1313 = or(_T_1312, _T_1284) node _T_1314 = or(_T_1313, _T_1289) node _T_1315 = or(_T_1314, _T_1294) node _T_1316 = or(_T_1315, _T_1299) node _T_1317 = or(_T_1316, _T_1304) node _T_1318 = or(_T_1317, _T_1309) node _T_1319 = and(_T_1259, _T_1318) node _T_1320 = or(UInt<1>(0h0), _T_1319) node _T_1321 = and(_WIRE_5, _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_86 node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(address_ok, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(legal_source, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1334 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_90 node _T_1338 = eq(io.in.b.bits.mask, mask_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_91 node _T_1342 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_92 node _T_1346 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1346 : node _T_1347 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1348 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1349 = and(_T_1347, _T_1348) node _T_1350 = or(UInt<1>(0h0), _T_1349) node _T_1351 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<14>(0h2000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<13>(0h1000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<18>(0h2f000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<13>(0h1000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<17>(0h10000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<27>(0h4000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<29>(0h10000000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = or(_T_1355, _T_1360) node _T_1402 = or(_T_1401, _T_1365) node _T_1403 = or(_T_1402, _T_1370) node _T_1404 = or(_T_1403, _T_1375) node _T_1405 = or(_T_1404, _T_1380) node _T_1406 = or(_T_1405, _T_1385) node _T_1407 = or(_T_1406, _T_1390) node _T_1408 = or(_T_1407, _T_1395) node _T_1409 = or(_T_1408, _T_1400) node _T_1410 = and(_T_1350, _T_1409) node _T_1411 = or(UInt<1>(0h0), _T_1410) node _T_1412 = and(UInt<1>(0h0), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_93 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(address_ok, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(legal_source, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1425 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_97 node _T_1429 = eq(io.in.b.bits.mask, mask_1) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_98 node _T_1433 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_99 node _T_1437 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1437 : node _T_1438 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1439 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1440 = and(_T_1438, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<14>(0h2000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<13>(0h1000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<18>(0h2f000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<13>(0h1000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<17>(0h10000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<27>(0h4000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<13>(0h1000))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1488 = cvt(_T_1487) node _T_1489 = and(_T_1488, asSInt(UInt<29>(0h10000000))) node _T_1490 = asSInt(_T_1489) node _T_1491 = eq(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = or(_T_1446, _T_1451) node _T_1493 = or(_T_1492, _T_1456) node _T_1494 = or(_T_1493, _T_1461) node _T_1495 = or(_T_1494, _T_1466) node _T_1496 = or(_T_1495, _T_1471) node _T_1497 = or(_T_1496, _T_1476) node _T_1498 = or(_T_1497, _T_1481) node _T_1499 = or(_T_1498, _T_1486) node _T_1500 = or(_T_1499, _T_1491) node _T_1501 = and(_T_1441, _T_1500) node _T_1502 = or(UInt<1>(0h0), _T_1501) node _T_1503 = and(UInt<1>(0h0), _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_100 node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(address_ok, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(legal_source, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1516 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_104 node _T_1520 = eq(io.in.b.bits.mask, mask_1) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_105 node _T_1524 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1524 : node _T_1525 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1526 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = or(UInt<1>(0h0), _T_1527) node _T_1529 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<14>(0h2000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<13>(0h1000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<18>(0h2f000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<27>(0h4000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<29>(0h10000000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = or(_T_1533, _T_1538) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1548) node _T_1582 = or(_T_1581, _T_1553) node _T_1583 = or(_T_1582, _T_1558) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1568) node _T_1586 = or(_T_1585, _T_1573) node _T_1587 = or(_T_1586, _T_1578) node _T_1588 = and(_T_1528, _T_1587) node _T_1589 = or(UInt<1>(0h0), _T_1588) node _T_1590 = and(UInt<1>(0h0), _T_1589) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_106 node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(address_ok, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(legal_source, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1603 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_110 node _T_1607 = not(mask_1) node _T_1608 = and(io.in.b.bits.mask, _T_1607) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_111 node _T_1613 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1613 : node _T_1614 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1615 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = or(UInt<1>(0h0), _T_1616) node _T_1618 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<14>(0h2000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<18>(0h2f000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<13>(0h1000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<17>(0h10000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<27>(0h4000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1659 = cvt(_T_1658) node _T_1660 = and(_T_1659, asSInt(UInt<13>(0h1000))) node _T_1661 = asSInt(_T_1660) node _T_1662 = eq(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1664 = cvt(_T_1663) node _T_1665 = and(_T_1664, asSInt(UInt<29>(0h10000000))) node _T_1666 = asSInt(_T_1665) node _T_1667 = eq(_T_1666, asSInt(UInt<1>(0h0))) node _T_1668 = or(_T_1622, _T_1627) node _T_1669 = or(_T_1668, _T_1632) node _T_1670 = or(_T_1669, _T_1637) node _T_1671 = or(_T_1670, _T_1642) node _T_1672 = or(_T_1671, _T_1647) node _T_1673 = or(_T_1672, _T_1652) node _T_1674 = or(_T_1673, _T_1657) node _T_1675 = or(_T_1674, _T_1662) node _T_1676 = or(_T_1675, _T_1667) node _T_1677 = and(_T_1617, _T_1676) node _T_1678 = or(UInt<1>(0h0), _T_1677) node _T_1679 = and(UInt<1>(0h0), _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_112 node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(address_ok, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(legal_source, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1689 = asUInt(reset) node _T_1690 = eq(_T_1689, UInt<1>(0h0)) when _T_1690 : node _T_1691 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1692 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_116 node _T_1696 = eq(io.in.b.bits.mask, mask_1) node _T_1697 = asUInt(reset) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) when _T_1698 : node _T_1699 = eq(_T_1696, UInt<1>(0h0)) when _T_1699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1696, UInt<1>(0h1), "") : assert_117 node _T_1700 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1700 : node _T_1701 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1702 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = or(UInt<1>(0h0), _T_1703) node _T_1705 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<14>(0h2000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<13>(0h1000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<18>(0h2f000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<13>(0h1000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<17>(0h10000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<27>(0h4000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1746 = cvt(_T_1745) node _T_1747 = and(_T_1746, asSInt(UInt<13>(0h1000))) node _T_1748 = asSInt(_T_1747) node _T_1749 = eq(_T_1748, asSInt(UInt<1>(0h0))) node _T_1750 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<29>(0h10000000))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = or(_T_1709, _T_1714) node _T_1756 = or(_T_1755, _T_1719) node _T_1757 = or(_T_1756, _T_1724) node _T_1758 = or(_T_1757, _T_1729) node _T_1759 = or(_T_1758, _T_1734) node _T_1760 = or(_T_1759, _T_1739) node _T_1761 = or(_T_1760, _T_1744) node _T_1762 = or(_T_1761, _T_1749) node _T_1763 = or(_T_1762, _T_1754) node _T_1764 = and(_T_1704, _T_1763) node _T_1765 = or(UInt<1>(0h0), _T_1764) node _T_1766 = and(UInt<1>(0h0), _T_1765) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_118 node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(address_ok, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(legal_source, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1779 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_122 node _T_1783 = eq(io.in.b.bits.mask, mask_1) node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(_T_1783, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1783, UInt<1>(0h1), "") : assert_123 node _T_1787 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1787 : node _T_1788 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1789 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1790 = and(_T_1788, _T_1789) node _T_1791 = or(UInt<1>(0h0), _T_1790) node _T_1792 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<14>(0h2000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<13>(0h1000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1796, _T_1801) node _T_1843 = or(_T_1842, _T_1806) node _T_1844 = or(_T_1843, _T_1811) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1821) node _T_1847 = or(_T_1846, _T_1826) node _T_1848 = or(_T_1847, _T_1831) node _T_1849 = or(_T_1848, _T_1836) node _T_1850 = or(_T_1849, _T_1841) node _T_1851 = and(_T_1791, _T_1850) node _T_1852 = or(UInt<1>(0h0), _T_1851) node _T_1853 = and(UInt<1>(0h0), _T_1852) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_124 node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(address_ok, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(legal_source, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1866 = eq(io.in.b.bits.mask, mask_1) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_128 node _T_1870 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1874 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1878 = shr(io.in.c.bits.source, 3) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) node _T_1885 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1892 = eq(_T_1891, UInt<1>(0h0)) node _T_1893 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = or(_T_1892, _T_1897) node _T_1899 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) node _T_1901 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1890, _T_1898) node _T_1908 = and(_T_1907, _T_1906) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_131 node _T_1912 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1912 : node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(address_ok_1, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok_2, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1919 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_134 node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1926 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_136 node _T_1930 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_137 node _T_1934 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1941 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_140 node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1948 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_142 node _T_1952 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1952 : node _T_1953 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1954 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1955 = and(_T_1953, _T_1954) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_1956 = shr(io.in.c.bits.source, 3) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) node _T_1958 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1959 = and(_T_1957, _T_1958) node _T_1960 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_1961 = and(_T_1959, _T_1960) node _T_1962 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1963 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1964 = or(_T_1961, _T_1962) node _T_1965 = or(_T_1964, _T_1963) node _T_1966 = and(_T_1955, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1966) node _T_1968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1969 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<14>(0h2000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<13>(0h1000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<18>(0h2f000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<17>(0h10000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2000 = cvt(_T_1999) node _T_2001 = and(_T_2000, asSInt(UInt<27>(0h4000000))) node _T_2002 = asSInt(_T_2001) node _T_2003 = eq(_T_2002, asSInt(UInt<1>(0h0))) node _T_2004 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2005 = cvt(_T_2004) node _T_2006 = and(_T_2005, asSInt(UInt<13>(0h1000))) node _T_2007 = asSInt(_T_2006) node _T_2008 = eq(_T_2007, asSInt(UInt<1>(0h0))) node _T_2009 = or(_T_1973, _T_1978) node _T_2010 = or(_T_2009, _T_1983) node _T_2011 = or(_T_2010, _T_1988) node _T_2012 = or(_T_2011, _T_1993) node _T_2013 = or(_T_2012, _T_1998) node _T_2014 = or(_T_2013, _T_2003) node _T_2015 = or(_T_2014, _T_2008) node _T_2016 = and(_T_1968, _T_2015) node _T_2017 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2018 = or(UInt<1>(0h0), _T_2017) node _T_2019 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2020 = cvt(_T_2019) node _T_2021 = and(_T_2020, asSInt(UInt<17>(0h10000))) node _T_2022 = asSInt(_T_2021) node _T_2023 = eq(_T_2022, asSInt(UInt<1>(0h0))) node _T_2024 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2025 = cvt(_T_2024) node _T_2026 = and(_T_2025, asSInt(UInt<29>(0h10000000))) node _T_2027 = asSInt(_T_2026) node _T_2028 = eq(_T_2027, asSInt(UInt<1>(0h0))) node _T_2029 = or(_T_2023, _T_2028) node _T_2030 = and(_T_2018, _T_2029) node _T_2031 = or(UInt<1>(0h0), _T_2016) node _T_2032 = or(_T_2031, _T_2030) node _T_2033 = and(_T_1967, _T_2032) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2037 = shr(io.in.c.bits.source, 3) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) node _T_2039 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2040 = and(_T_2038, _T_2039) node _T_2041 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2044 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2042 connect _WIRE_6[1], _T_2043 connect _WIRE_6[2], _T_2044 node _T_2045 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2046 = mux(_WIRE_6[0], _T_2045, UInt<1>(0h0)) node _T_2047 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2048 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = or(_T_2046, _T_2047) node _T_2050 = or(_T_2049, _T_2048) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2050 node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<14>(0h2000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<13>(0h1000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<18>(0h2f000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<13>(0h1000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<17>(0h10000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<29>(0h10000000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = or(_T_2059, _T_2064) node _T_2106 = or(_T_2105, _T_2069) node _T_2107 = or(_T_2106, _T_2074) node _T_2108 = or(_T_2107, _T_2079) node _T_2109 = or(_T_2108, _T_2084) node _T_2110 = or(_T_2109, _T_2089) node _T_2111 = or(_T_2110, _T_2094) node _T_2112 = or(_T_2111, _T_2099) node _T_2113 = or(_T_2112, _T_2104) node _T_2114 = and(_T_2054, _T_2113) node _T_2115 = or(UInt<1>(0h0), _T_2114) node _T_2116 = and(_WIRE_7, _T_2115) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_144 node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(source_ok_2, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2123 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_146 node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2130 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_148 node _T_2134 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2135 = asUInt(reset) node _T_2136 = eq(_T_2135, UInt<1>(0h0)) when _T_2136 : node _T_2137 = eq(_T_2134, UInt<1>(0h0)) when _T_2137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2134, UInt<1>(0h1), "") : assert_149 node _T_2138 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2138 : node _T_2139 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2140 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2141 = and(_T_2139, _T_2140) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2142 = shr(io.in.c.bits.source, 3) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) node _T_2144 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2149 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2150 = or(_T_2147, _T_2148) node _T_2151 = or(_T_2150, _T_2149) node _T_2152 = and(_T_2141, _T_2151) node _T_2153 = or(UInt<1>(0h0), _T_2152) node _T_2154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2155 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<14>(0h2000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<13>(0h1000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<18>(0h2f000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<17>(0h10000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2186 = cvt(_T_2185) node _T_2187 = and(_T_2186, asSInt(UInt<27>(0h4000000))) node _T_2188 = asSInt(_T_2187) node _T_2189 = eq(_T_2188, asSInt(UInt<1>(0h0))) node _T_2190 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<13>(0h1000))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2159, _T_2164) node _T_2196 = or(_T_2195, _T_2169) node _T_2197 = or(_T_2196, _T_2174) node _T_2198 = or(_T_2197, _T_2179) node _T_2199 = or(_T_2198, _T_2184) node _T_2200 = or(_T_2199, _T_2189) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = and(_T_2154, _T_2201) node _T_2203 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2204 = or(UInt<1>(0h0), _T_2203) node _T_2205 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2206 = cvt(_T_2205) node _T_2207 = and(_T_2206, asSInt(UInt<17>(0h10000))) node _T_2208 = asSInt(_T_2207) node _T_2209 = eq(_T_2208, asSInt(UInt<1>(0h0))) node _T_2210 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2211 = cvt(_T_2210) node _T_2212 = and(_T_2211, asSInt(UInt<29>(0h10000000))) node _T_2213 = asSInt(_T_2212) node _T_2214 = eq(_T_2213, asSInt(UInt<1>(0h0))) node _T_2215 = or(_T_2209, _T_2214) node _T_2216 = and(_T_2204, _T_2215) node _T_2217 = or(UInt<1>(0h0), _T_2202) node _T_2218 = or(_T_2217, _T_2216) node _T_2219 = and(_T_2153, _T_2218) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2223 = shr(io.in.c.bits.source, 3) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) node _T_2225 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2226 = and(_T_2224, _T_2225) node _T_2227 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2228 = and(_T_2226, _T_2227) node _T_2229 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2230 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2228 connect _WIRE_8[1], _T_2229 connect _WIRE_8[2], _T_2230 node _T_2231 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2232 = mux(_WIRE_8[0], _T_2231, UInt<1>(0h0)) node _T_2233 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2234 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2235 = or(_T_2232, _T_2233) node _T_2236 = or(_T_2235, _T_2234) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2236 node _T_2237 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2238 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2239 = and(_T_2237, _T_2238) node _T_2240 = or(UInt<1>(0h0), _T_2239) node _T_2241 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<14>(0h2000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<13>(0h1000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<18>(0h2f000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<13>(0h1000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<17>(0h10000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<27>(0h4000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2282 = cvt(_T_2281) node _T_2283 = and(_T_2282, asSInt(UInt<13>(0h1000))) node _T_2284 = asSInt(_T_2283) node _T_2285 = eq(_T_2284, asSInt(UInt<1>(0h0))) node _T_2286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2287 = cvt(_T_2286) node _T_2288 = and(_T_2287, asSInt(UInt<29>(0h10000000))) node _T_2289 = asSInt(_T_2288) node _T_2290 = eq(_T_2289, asSInt(UInt<1>(0h0))) node _T_2291 = or(_T_2245, _T_2250) node _T_2292 = or(_T_2291, _T_2255) node _T_2293 = or(_T_2292, _T_2260) node _T_2294 = or(_T_2293, _T_2265) node _T_2295 = or(_T_2294, _T_2270) node _T_2296 = or(_T_2295, _T_2275) node _T_2297 = or(_T_2296, _T_2280) node _T_2298 = or(_T_2297, _T_2285) node _T_2299 = or(_T_2298, _T_2290) node _T_2300 = and(_T_2240, _T_2299) node _T_2301 = or(UInt<1>(0h0), _T_2300) node _T_2302 = and(_WIRE_9, _T_2301) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_151 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(source_ok_2, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2309 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(_T_2309, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2309, UInt<1>(0h1), "") : assert_153 node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2316 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_155 node _T_2320 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2320 : node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(address_ok_1, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : node _T_2326 = eq(source_ok_2, UInt<1>(0h0)) when _T_2326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2330 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2331 = asUInt(reset) node _T_2332 = eq(_T_2331, UInt<1>(0h0)) when _T_2332 : node _T_2333 = eq(_T_2330, UInt<1>(0h0)) when _T_2333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2330, UInt<1>(0h1), "") : assert_159 node _T_2334 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(_T_2334, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2334, UInt<1>(0h1), "") : assert_160 node _T_2338 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2338 : node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(address_ok_1, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(source_ok_2, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2345 = asUInt(reset) node _T_2346 = eq(_T_2345, UInt<1>(0h0)) when _T_2346 : node _T_2347 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2348 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_164 node _T_2352 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2352 : node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(address_ok_1, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok_2, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2362 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_168 node _T_2366 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2373 = eq(a_first, UInt<1>(0h0)) node _T_2374 = and(io.in.a.valid, _T_2373) when _T_2374 : node _T_2375 = eq(io.in.a.bits.opcode, opcode) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_171 node _T_2379 = eq(io.in.a.bits.param, param) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_172 node _T_2383 = eq(io.in.a.bits.size, size) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_173 node _T_2387 = eq(io.in.a.bits.source, source) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_174 node _T_2391 = eq(io.in.a.bits.address, address) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_175 node _T_2395 = and(io.in.a.ready, io.in.a.valid) node _T_2396 = and(_T_2395, a_first) when _T_2396 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2397 = eq(d_first, UInt<1>(0h0)) node _T_2398 = and(io.in.d.valid, _T_2397) when _T_2398 : node _T_2399 = eq(io.in.d.bits.opcode, opcode_1) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_176 node _T_2403 = eq(io.in.d.bits.param, param_1) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_177 node _T_2407 = eq(io.in.d.bits.size, size_1) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_178 node _T_2411 = eq(io.in.d.bits.source, source_1) node _T_2412 = asUInt(reset) node _T_2413 = eq(_T_2412, UInt<1>(0h0)) when _T_2413 : node _T_2414 = eq(_T_2411, UInt<1>(0h0)) when _T_2414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2411, UInt<1>(0h1), "") : assert_179 node _T_2415 = eq(io.in.d.bits.sink, sink) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_180 node _T_2419 = eq(io.in.d.bits.denied, denied) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_181 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first) when _T_2424 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2425 = eq(b_first, UInt<1>(0h0)) node _T_2426 = and(io.in.b.valid, _T_2425) when _T_2426 : node _T_2427 = eq(io.in.b.bits.opcode, opcode_2) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_182 node _T_2431 = eq(io.in.b.bits.param, param_2) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_183 node _T_2435 = eq(io.in.b.bits.size, size_2) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_184 node _T_2439 = eq(io.in.b.bits.source, source_2) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_185 node _T_2443 = eq(io.in.b.bits.address, address_1) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_186 node _T_2447 = and(io.in.b.ready, io.in.b.valid) node _T_2448 = and(_T_2447, b_first) when _T_2448 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2449 = eq(c_first, UInt<1>(0h0)) node _T_2450 = and(io.in.c.valid, _T_2449) when _T_2450 : node _T_2451 = eq(io.in.c.bits.opcode, opcode_3) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_187 node _T_2455 = eq(io.in.c.bits.param, param_3) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_188 node _T_2459 = eq(io.in.c.bits.size, size_3) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_189 node _T_2463 = eq(io.in.c.bits.source, source_3) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_190 node _T_2467 = eq(io.in.c.bits.address, address_2) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_191 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(_T_2471, c_first) when _T_2472 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2473 = and(io.in.a.valid, a_first_1) node _T_2474 = and(_T_2473, UInt<1>(0h1)) when _T_2474 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2475 = and(io.in.a.ready, io.in.a.valid) node _T_2476 = and(_T_2475, a_first_1) node _T_2477 = and(_T_2476, UInt<1>(0h1)) when _T_2477 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2478 = dshr(inflight, io.in.a.bits.source) node _T_2479 = bits(_T_2478, 0, 0) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2484 = and(io.in.d.valid, d_first_1) node _T_2485 = and(_T_2484, UInt<1>(0h1)) node _T_2486 = eq(d_release_ack, UInt<1>(0h0)) node _T_2487 = and(_T_2485, _T_2486) when _T_2487 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2488 = and(io.in.d.ready, io.in.d.valid) node _T_2489 = and(_T_2488, d_first_1) node _T_2490 = and(_T_2489, UInt<1>(0h1)) node _T_2491 = eq(d_release_ack, UInt<1>(0h0)) node _T_2492 = and(_T_2490, _T_2491) when _T_2492 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2493 = and(io.in.d.valid, d_first_1) node _T_2494 = and(_T_2493, UInt<1>(0h1)) node _T_2495 = eq(d_release_ack, UInt<1>(0h0)) node _T_2496 = and(_T_2494, _T_2495) when _T_2496 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2497 = dshr(inflight, io.in.d.bits.source) node _T_2498 = bits(_T_2497, 0, 0) node _T_2499 = or(_T_2498, same_cycle_resp) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_194 node _T_2509 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_195 else : node _T_2513 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2514 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2515 = or(_T_2513, _T_2514) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_196 node _T_2519 = eq(io.in.d.bits.size, a_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_197 node _T_2523 = and(io.in.d.valid, d_first_1) node _T_2524 = and(_T_2523, a_first_1) node _T_2525 = and(_T_2524, io.in.a.valid) node _T_2526 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = eq(d_release_ack, UInt<1>(0h0)) node _T_2529 = and(_T_2527, _T_2528) when _T_2529 : node _T_2530 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2531 = or(_T_2530, io.in.a.ready) node _T_2532 = asUInt(reset) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) when _T_2533 : node _T_2534 = eq(_T_2531, UInt<1>(0h0)) when _T_2534 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2531, UInt<1>(0h1), "") : assert_198 node _T_2535 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2536 = orr(a_set_wo_ready) node _T_2537 = eq(_T_2536, UInt<1>(0h0)) node _T_2538 = or(_T_2535, _T_2537) node _T_2539 = asUInt(reset) node _T_2540 = eq(_T_2539, UInt<1>(0h0)) when _T_2540 : node _T_2541 = eq(_T_2538, UInt<1>(0h0)) when _T_2541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2538, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_8 node _T_2542 = orr(inflight) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) node _T_2544 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2545 = or(_T_2543, _T_2544) node _T_2546 = lt(watchdog, plusarg_reader.out) node _T_2547 = or(_T_2545, _T_2546) node _T_2548 = asUInt(reset) node _T_2549 = eq(_T_2548, UInt<1>(0h0)) when _T_2549 : node _T_2550 = eq(_T_2547, UInt<1>(0h0)) when _T_2550 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2547, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2551 = and(io.in.a.ready, io.in.a.valid) node _T_2552 = and(io.in.d.ready, io.in.d.valid) node _T_2553 = or(_T_2551, _T_2552) when _T_2553 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2554 = and(io.in.c.valid, c_first_1) node _T_2555 = bits(io.in.c.bits.opcode, 2, 2) node _T_2556 = bits(io.in.c.bits.opcode, 1, 1) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = and(_T_2554, _T_2557) when _T_2558 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2559 = and(io.in.c.ready, io.in.c.valid) node _T_2560 = and(_T_2559, c_first_1) node _T_2561 = bits(io.in.c.bits.opcode, 2, 2) node _T_2562 = bits(io.in.c.bits.opcode, 1, 1) node _T_2563 = and(_T_2561, _T_2562) node _T_2564 = and(_T_2560, _T_2563) when _T_2564 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2565 = dshr(inflight_1, io.in.c.bits.source) node _T_2566 = bits(_T_2565, 0, 0) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) node _T_2568 = asUInt(reset) node _T_2569 = eq(_T_2568, UInt<1>(0h0)) when _T_2569 : node _T_2570 = eq(_T_2567, UInt<1>(0h0)) when _T_2570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2567, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2571 = and(io.in.d.valid, d_first_2) node _T_2572 = and(_T_2571, UInt<1>(0h1)) node _T_2573 = and(_T_2572, d_release_ack_1) when _T_2573 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2574 = and(io.in.d.ready, io.in.d.valid) node _T_2575 = and(_T_2574, d_first_2) node _T_2576 = and(_T_2575, UInt<1>(0h1)) node _T_2577 = and(_T_2576, d_release_ack_1) when _T_2577 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2578 = and(io.in.d.valid, d_first_2) node _T_2579 = and(_T_2578, UInt<1>(0h1)) node _T_2580 = and(_T_2579, d_release_ack_1) when _T_2580 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2581 = dshr(inflight_1, io.in.d.bits.source) node _T_2582 = bits(_T_2581, 0, 0) node _T_2583 = or(_T_2582, same_cycle_resp_1) node _T_2584 = asUInt(reset) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) when _T_2585 : node _T_2586 = eq(_T_2583, UInt<1>(0h0)) when _T_2586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2583, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2587 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2588 = asUInt(reset) node _T_2589 = eq(_T_2588, UInt<1>(0h0)) when _T_2589 : node _T_2590 = eq(_T_2587, UInt<1>(0h0)) when _T_2590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2587, UInt<1>(0h1), "") : assert_203 else : node _T_2591 = eq(io.in.d.bits.size, c_size_lookup) node _T_2592 = asUInt(reset) node _T_2593 = eq(_T_2592, UInt<1>(0h0)) when _T_2593 : node _T_2594 = eq(_T_2591, UInt<1>(0h0)) when _T_2594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2591, UInt<1>(0h1), "") : assert_204 node _T_2595 = and(io.in.d.valid, d_first_2) node _T_2596 = and(_T_2595, c_first_1) node _T_2597 = and(_T_2596, io.in.c.valid) node _T_2598 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2599 = and(_T_2597, _T_2598) node _T_2600 = and(_T_2599, d_release_ack_1) node _T_2601 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2602 = and(_T_2600, _T_2601) when _T_2602 : node _T_2603 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2604 = or(_T_2603, io.in.c.ready) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_205 node _T_2608 = orr(c_set_wo_ready) when _T_2608 : node _T_2609 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_9 node _T_2613 = orr(inflight_1) node _T_2614 = eq(_T_2613, UInt<1>(0h0)) node _T_2615 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2616 = or(_T_2614, _T_2615) node _T_2617 = lt(watchdog_1, plusarg_reader_1.out) node _T_2618 = or(_T_2616, _T_2617) node _T_2619 = asUInt(reset) node _T_2620 = eq(_T_2619, UInt<1>(0h0)) when _T_2620 : node _T_2621 = eq(_T_2618, UInt<1>(0h0)) when _T_2621 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2618, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2622 = and(io.in.c.ready, io.in.c.valid) node _T_2623 = and(io.in.d.ready, io.in.d.valid) node _T_2624 = or(_T_2622, _T_2623) when _T_2624 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2625 = and(io.in.d.ready, io.in.d.valid) node _T_2626 = and(_T_2625, d_first_3) node _T_2627 = bits(io.in.d.bits.opcode, 2, 2) node _T_2628 = bits(io.in.d.bits.opcode, 1, 1) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) node _T_2630 = and(_T_2627, _T_2629) node _T_2631 = and(_T_2626, _T_2630) when _T_2631 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2632 = dshr(inflight_2, io.in.d.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = asUInt(reset) node _T_2636 = eq(_T_2635, UInt<1>(0h0)) when _T_2636 : node _T_2637 = eq(_T_2634, UInt<1>(0h0)) when _T_2637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2634, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2638 = and(io.in.e.ready, io.in.e.valid) node _T_2639 = and(_T_2638, UInt<1>(0h1)) node _T_2640 = and(_T_2639, UInt<1>(0h1)) when _T_2640 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2641 = or(d_set, inflight_2) node _T_2642 = dshr(_T_2641, io.in.e.bits.sink) node _T_2643 = bits(_T_2642, 0, 0) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[3]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_9 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_10 = {_legal_source_WIRE_2, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} \| _legal_source_T_10; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2551 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2551; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2551; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2625 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2625; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2622 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2622; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2622; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_20 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2551 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2477 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2477 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2477 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2477 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2477 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2523 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_22 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2523 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2625 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2492 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2492 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2492 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_23 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2564 = _T_2622 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2564 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2564 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2564 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2564 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2564 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2595 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2595 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2577 = _T_2625 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2577 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2577 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2577 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2631 = _T_2625 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_24 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2631 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2640 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = _T_2640 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module Tile_53 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_309 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_53( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_309 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomTile : input clock : Clock input reset : Reset output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>, custom : { rob_empty : UInt<1>}}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1 inst broadcast of BundleBridgeNexus_UInt1 inst broadcast_1 of BundleBridgeNexus_UInt32 inst nexus of BundleBridgeNexus_NoOutput_6 inst nexus_1 of BundleBridgeNexus_TraceAux inst broadcast_2 of BundleBridgeNexus_NoOutput_7 inst buffer of TLBuffer_a32d64s3k3z4c connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_a32d64s2k3z4c connect buffer_1.clock, clock connect buffer_1.reset, reset inst widget of TLWidthWidget8_8 connect widget.clock, clock connect widget.reset, reset inst dcache of BoomNonBlockingDCache connect dcache.clock, clock connect dcache.reset, reset inst frontend of BoomFrontend connect frontend.clock, clock connect frontend.reset, reset inst buffer_2 of TLBuffer_a32d64s1k3z4u connect buffer_2.clock, clock connect buffer_2.reset, reset inst widget_1 of TLWidthWidget8_9 connect widget_1.clock, clock connect widget_1.reset, reset inst buffer_3 of TLBuffer_a32d64s3k3z4c_1 connect buffer_3.clock, clock connect buffer_3.reset, reset inst buffer_4 of TLBuffer_1 connect buffer_4.clock, clock connect buffer_4.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeOut.e.bits.sink invalidate tlOtherMastersNodeOut.e.valid invalidate tlOtherMastersNodeOut.e.ready invalidate tlOtherMastersNodeOut.d.bits.corrupt invalidate tlOtherMastersNodeOut.d.bits.data invalidate tlOtherMastersNodeOut.d.bits.denied invalidate tlOtherMastersNodeOut.d.bits.sink invalidate tlOtherMastersNodeOut.d.bits.source invalidate tlOtherMastersNodeOut.d.bits.size invalidate tlOtherMastersNodeOut.d.bits.param invalidate tlOtherMastersNodeOut.d.bits.opcode invalidate tlOtherMastersNodeOut.d.valid invalidate tlOtherMastersNodeOut.d.ready invalidate tlOtherMastersNodeOut.c.bits.corrupt invalidate tlOtherMastersNodeOut.c.bits.data invalidate tlOtherMastersNodeOut.c.bits.address invalidate tlOtherMastersNodeOut.c.bits.source invalidate tlOtherMastersNodeOut.c.bits.size invalidate tlOtherMastersNodeOut.c.bits.param invalidate tlOtherMastersNodeOut.c.bits.opcode invalidate tlOtherMastersNodeOut.c.valid invalidate tlOtherMastersNodeOut.c.ready invalidate tlOtherMastersNodeOut.b.bits.corrupt invalidate tlOtherMastersNodeOut.b.bits.data invalidate tlOtherMastersNodeOut.b.bits.mask invalidate tlOtherMastersNodeOut.b.bits.address invalidate tlOtherMastersNodeOut.b.bits.source invalidate tlOtherMastersNodeOut.b.bits.size invalidate tlOtherMastersNodeOut.b.bits.param invalidate tlOtherMastersNodeOut.b.bits.opcode invalidate tlOtherMastersNodeOut.b.valid invalidate tlOtherMastersNodeOut.b.ready invalidate tlOtherMastersNodeOut.a.bits.corrupt invalidate tlOtherMastersNodeOut.a.bits.data invalidate tlOtherMastersNodeOut.a.bits.mask invalidate tlOtherMastersNodeOut.a.bits.address invalidate tlOtherMastersNodeOut.a.bits.source invalidate tlOtherMastersNodeOut.a.bits.size invalidate tlOtherMastersNodeOut.a.bits.param invalidate tlOtherMastersNodeOut.a.bits.opcode invalidate tlOtherMastersNodeOut.a.valid invalidate tlOtherMastersNodeOut.a.ready wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeIn.e.bits.sink invalidate tlOtherMastersNodeIn.e.valid invalidate tlOtherMastersNodeIn.e.ready invalidate tlOtherMastersNodeIn.d.bits.corrupt invalidate tlOtherMastersNodeIn.d.bits.data invalidate tlOtherMastersNodeIn.d.bits.denied invalidate tlOtherMastersNodeIn.d.bits.sink invalidate tlOtherMastersNodeIn.d.bits.source invalidate tlOtherMastersNodeIn.d.bits.size invalidate tlOtherMastersNodeIn.d.bits.param invalidate tlOtherMastersNodeIn.d.bits.opcode invalidate tlOtherMastersNodeIn.d.valid invalidate tlOtherMastersNodeIn.d.ready invalidate tlOtherMastersNodeIn.c.bits.corrupt invalidate tlOtherMastersNodeIn.c.bits.data invalidate tlOtherMastersNodeIn.c.bits.address invalidate tlOtherMastersNodeIn.c.bits.source invalidate tlOtherMastersNodeIn.c.bits.size invalidate tlOtherMastersNodeIn.c.bits.param invalidate tlOtherMastersNodeIn.c.bits.opcode invalidate tlOtherMastersNodeIn.c.valid invalidate tlOtherMastersNodeIn.c.ready invalidate tlOtherMastersNodeIn.b.bits.corrupt invalidate tlOtherMastersNodeIn.b.bits.data invalidate tlOtherMastersNodeIn.b.bits.mask invalidate tlOtherMastersNodeIn.b.bits.address invalidate tlOtherMastersNodeIn.b.bits.source invalidate tlOtherMastersNodeIn.b.bits.size invalidate tlOtherMastersNodeIn.b.bits.param invalidate tlOtherMastersNodeIn.b.bits.opcode invalidate tlOtherMastersNodeIn.b.valid invalidate tlOtherMastersNodeIn.b.ready invalidate tlOtherMastersNodeIn.a.bits.corrupt invalidate tlOtherMastersNodeIn.a.bits.data invalidate tlOtherMastersNodeIn.a.bits.mask invalidate tlOtherMastersNodeIn.a.bits.address invalidate tlOtherMastersNodeIn.a.bits.source invalidate tlOtherMastersNodeIn.a.bits.size invalidate tlOtherMastersNodeIn.a.bits.param invalidate tlOtherMastersNodeIn.a.bits.opcode invalidate tlOtherMastersNodeIn.a.valid invalidate tlOtherMastersNodeIn.a.ready connect tlOtherMastersNodeOut, tlOtherMastersNodeIn wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>, custom : { rob_empty : UInt<1>}} invalidate traceSourceNodeOut.custom.rob_empty invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid invalidate traceSourceNodeOut.insns[1].tval invalidate traceSourceNodeOut.insns[1].cause invalidate traceSourceNodeOut.insns[1].interrupt invalidate traceSourceNodeOut.insns[1].exception invalidate traceSourceNodeOut.insns[1].priv invalidate traceSourceNodeOut.insns[1].insn invalidate traceSourceNodeOut.insns[1].iaddr invalidate traceSourceNodeOut.insns[1].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[2], rvalid : UInt<1>[2], wvalid : UInt<1>[2], ivalid : UInt<1>[2], action : UInt<3>}[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeOut.e.bits.sink invalidate masterNodeOut.e.valid invalidate masterNodeOut.e.ready invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.c.bits.corrupt invalidate masterNodeOut.c.bits.data invalidate masterNodeOut.c.bits.address invalidate masterNodeOut.c.bits.source invalidate masterNodeOut.c.bits.size invalidate masterNodeOut.c.bits.param invalidate masterNodeOut.c.bits.opcode invalidate masterNodeOut.c.valid invalidate masterNodeOut.c.ready invalidate masterNodeOut.b.bits.corrupt invalidate masterNodeOut.b.bits.data invalidate masterNodeOut.b.bits.mask invalidate masterNodeOut.b.bits.address invalidate masterNodeOut.b.bits.source invalidate masterNodeOut.b.bits.size invalidate masterNodeOut.b.bits.param invalidate masterNodeOut.b.bits.opcode invalidate masterNodeOut.b.valid invalidate masterNodeOut.b.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready wire masterNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeIn.e.bits.sink invalidate masterNodeIn.e.valid invalidate masterNodeIn.e.ready invalidate masterNodeIn.d.bits.corrupt invalidate masterNodeIn.d.bits.data invalidate masterNodeIn.d.bits.denied invalidate masterNodeIn.d.bits.sink invalidate masterNodeIn.d.bits.source invalidate masterNodeIn.d.bits.size invalidate masterNodeIn.d.bits.param invalidate masterNodeIn.d.bits.opcode invalidate masterNodeIn.d.valid invalidate masterNodeIn.d.ready invalidate masterNodeIn.c.bits.corrupt invalidate masterNodeIn.c.bits.data invalidate masterNodeIn.c.bits.address invalidate masterNodeIn.c.bits.source invalidate masterNodeIn.c.bits.size invalidate masterNodeIn.c.bits.param invalidate masterNodeIn.c.bits.opcode invalidate masterNodeIn.c.valid invalidate masterNodeIn.c.ready invalidate masterNodeIn.b.bits.corrupt invalidate masterNodeIn.b.bits.data invalidate masterNodeIn.b.bits.mask invalidate masterNodeIn.b.bits.address invalidate masterNodeIn.b.bits.source invalidate masterNodeIn.b.bits.size invalidate masterNodeIn.b.bits.param invalidate masterNodeIn.b.bits.opcode invalidate masterNodeIn.b.valid invalidate masterNodeIn.b.ready invalidate masterNodeIn.a.bits.corrupt invalidate masterNodeIn.a.bits.data invalidate masterNodeIn.a.bits.mask invalidate masterNodeIn.a.bits.address invalidate masterNodeIn.a.bits.source invalidate masterNodeIn.a.bits.size invalidate masterNodeIn.a.bits.param invalidate masterNodeIn.a.bits.opcode invalidate masterNodeIn.a.valid invalidate masterNodeIn.a.ready connect masterNodeOut, masterNodeIn wire dCacheTapOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate dCacheTapOut.e.bits.sink invalidate dCacheTapOut.e.valid invalidate dCacheTapOut.e.ready invalidate dCacheTapOut.d.bits.corrupt invalidate dCacheTapOut.d.bits.data invalidate dCacheTapOut.d.bits.denied invalidate dCacheTapOut.d.bits.sink invalidate dCacheTapOut.d.bits.source invalidate dCacheTapOut.d.bits.size invalidate dCacheTapOut.d.bits.param invalidate dCacheTapOut.d.bits.opcode invalidate dCacheTapOut.d.valid invalidate dCacheTapOut.d.ready invalidate dCacheTapOut.c.bits.corrupt invalidate dCacheTapOut.c.bits.data invalidate dCacheTapOut.c.bits.address invalidate dCacheTapOut.c.bits.source invalidate dCacheTapOut.c.bits.size invalidate dCacheTapOut.c.bits.param invalidate dCacheTapOut.c.bits.opcode invalidate dCacheTapOut.c.valid invalidate dCacheTapOut.c.ready invalidate dCacheTapOut.b.bits.corrupt invalidate dCacheTapOut.b.bits.data invalidate dCacheTapOut.b.bits.mask invalidate dCacheTapOut.b.bits.address invalidate dCacheTapOut.b.bits.source invalidate dCacheTapOut.b.bits.size invalidate dCacheTapOut.b.bits.param invalidate dCacheTapOut.b.bits.opcode invalidate dCacheTapOut.b.valid invalidate dCacheTapOut.b.ready invalidate dCacheTapOut.a.bits.corrupt invalidate dCacheTapOut.a.bits.data invalidate dCacheTapOut.a.bits.mask invalidate dCacheTapOut.a.bits.address invalidate dCacheTapOut.a.bits.source invalidate dCacheTapOut.a.bits.size invalidate dCacheTapOut.a.bits.param invalidate dCacheTapOut.a.bits.opcode invalidate dCacheTapOut.a.valid invalidate dCacheTapOut.a.ready wire dCacheTapIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate dCacheTapIn.e.bits.sink invalidate dCacheTapIn.e.valid invalidate dCacheTapIn.e.ready invalidate dCacheTapIn.d.bits.corrupt invalidate dCacheTapIn.d.bits.data invalidate dCacheTapIn.d.bits.denied invalidate dCacheTapIn.d.bits.sink invalidate dCacheTapIn.d.bits.source invalidate dCacheTapIn.d.bits.size invalidate dCacheTapIn.d.bits.param invalidate dCacheTapIn.d.bits.opcode invalidate dCacheTapIn.d.valid invalidate dCacheTapIn.d.ready invalidate dCacheTapIn.c.bits.corrupt invalidate dCacheTapIn.c.bits.data invalidate dCacheTapIn.c.bits.address invalidate dCacheTapIn.c.bits.source invalidate dCacheTapIn.c.bits.size invalidate dCacheTapIn.c.bits.param invalidate dCacheTapIn.c.bits.opcode invalidate dCacheTapIn.c.valid invalidate dCacheTapIn.c.ready invalidate dCacheTapIn.b.bits.corrupt invalidate dCacheTapIn.b.bits.data invalidate dCacheTapIn.b.bits.mask invalidate dCacheTapIn.b.bits.address invalidate dCacheTapIn.b.bits.source invalidate dCacheTapIn.b.bits.size invalidate dCacheTapIn.b.bits.param invalidate dCacheTapIn.b.bits.opcode invalidate dCacheTapIn.b.valid invalidate dCacheTapIn.b.ready invalidate dCacheTapIn.a.bits.corrupt invalidate dCacheTapIn.a.bits.data invalidate dCacheTapIn.a.bits.mask invalidate dCacheTapIn.a.bits.address invalidate dCacheTapIn.a.bits.source invalidate dCacheTapIn.a.bits.size invalidate dCacheTapIn.a.bits.param invalidate dCacheTapIn.a.bits.opcode invalidate dCacheTapIn.a.valid invalidate dCacheTapIn.a.ready connect dCacheTapOut, dCacheTapIn connect masterNodeIn, tlOtherMastersNodeOut connect buffer.auto.in, tlMasterXbar.auto.anon_out connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect buffer_3.auto.in, masterNodeOut connect tlOtherMastersNodeIn.e.bits, buffer.auto.out.e.bits connect tlOtherMastersNodeIn.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, tlOtherMastersNodeIn.e.ready connect buffer.auto.out.d, tlOtherMastersNodeIn.d connect tlOtherMastersNodeIn.c.bits, buffer.auto.out.c.bits connect tlOtherMastersNodeIn.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, tlOtherMastersNodeIn.c.ready connect buffer.auto.out.b, tlOtherMastersNodeIn.b connect tlOtherMastersNodeIn.a.bits, buffer.auto.out.a.bits connect tlOtherMastersNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, tlOtherMastersNodeIn.a.ready connect tlMasterXbar.auto.anon_in_0, dCacheTapOut connect dCacheTapIn.e.bits, buffer_1.auto.out.e.bits connect dCacheTapIn.e.valid, buffer_1.auto.out.e.valid connect buffer_1.auto.out.e.ready, dCacheTapIn.e.ready connect buffer_1.auto.out.d, dCacheTapIn.d connect dCacheTapIn.c.bits, buffer_1.auto.out.c.bits connect dCacheTapIn.c.valid, buffer_1.auto.out.c.valid connect buffer_1.auto.out.c.ready, dCacheTapIn.c.ready connect buffer_1.auto.out.b, dCacheTapIn.b connect dCacheTapIn.a.bits, buffer_1.auto.out.a.bits connect dCacheTapIn.a.valid, buffer_1.auto.out.a.valid connect buffer_1.auto.out.a.ready, dCacheTapIn.a.ready connect buffer_1.auto.in, widget.auto.anon_out connect widget.auto.anon_in, dcache.auto.out connect widget_1.auto.anon_in, frontend.auto.icache_master_out connect tlMasterXbar.auto.anon_in_1, buffer_2.auto.out connect buffer_2.auto.in, widget_1.auto.anon_out connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect auto.buffer_out.e.bits, buffer_3.auto.out.e.bits connect auto.buffer_out.e.valid, buffer_3.auto.out.e.valid connect buffer_3.auto.out.e.ready, auto.buffer_out.e.ready connect buffer_3.auto.out.d, auto.buffer_out.d connect auto.buffer_out.c.bits, buffer_3.auto.out.c.bits connect auto.buffer_out.c.valid, buffer_3.auto.out.c.valid connect buffer_3.auto.out.c.ready, auto.buffer_out.c.ready connect buffer_3.auto.out.b, auto.buffer_out.b connect auto.buffer_out.a.bits, buffer_3.auto.out.a.bits connect auto.buffer_out.a.valid, buffer_3.auto.out.a.valid connect buffer_3.auto.out.a.ready, auto.buffer_out.a.ready inst core of BoomCore connect core.clock, clock connect core.reset, reset inst lsu of LSU connect lsu.clock, clock connect lsu.reset, reset connect wfiNodeOut[0], UInt<1>(0h0) connect core.io.interrupts.debug, intSinkNodeIn[0] connect core.io.interrupts.msip, intSinkNodeIn[1] connect core.io.interrupts.mtip, intSinkNodeIn[2] connect core.io.interrupts.meip, intSinkNodeIn[3] connect core.io.interrupts.seip, intSinkNodeIn[4] connect traceSourceNodeOut, core.io.trace connect core.io.hartid, hartIdSinkNodeIn connect frontend.io.cpu, core.io.ifu connect core.io.lsu, lsu.io.core invalidate core.io.rocc.exception invalidate core.io.rocc.interrupt invalidate core.io.rocc.busy invalidate core.io.rocc.mem.clock_enabled invalidate core.io.rocc.mem.keep_clock_enabled invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad invalidate core.io.rocc.mem.perf.blocked invalidate core.io.rocc.mem.perf.tlbMiss invalidate core.io.rocc.mem.perf.grant invalidate core.io.rocc.mem.perf.release invalidate core.io.rocc.mem.perf.acquire invalidate core.io.rocc.mem.store_pending invalidate core.io.rocc.mem.ordered invalidate core.io.rocc.mem.s2_gpa_is_pte invalidate core.io.rocc.mem.s2_gpa invalidate core.io.rocc.mem.s2_xcpt.ae.st invalidate core.io.rocc.mem.s2_xcpt.ae.ld invalidate core.io.rocc.mem.s2_xcpt.gf.st invalidate core.io.rocc.mem.s2_xcpt.gf.ld invalidate core.io.rocc.mem.s2_xcpt.pf.st invalidate core.io.rocc.mem.s2_xcpt.pf.ld invalidate core.io.rocc.mem.s2_xcpt.ma.st invalidate core.io.rocc.mem.s2_xcpt.ma.ld invalidate core.io.rocc.mem.replay_next invalidate core.io.rocc.mem.resp.bits.store_data invalidate core.io.rocc.mem.resp.bits.data_raw invalidate core.io.rocc.mem.resp.bits.data_word_bypass invalidate core.io.rocc.mem.resp.bits.has_data invalidate core.io.rocc.mem.resp.bits.replay invalidate core.io.rocc.mem.resp.bits.mask invalidate core.io.rocc.mem.resp.bits.data invalidate core.io.rocc.mem.resp.bits.dv invalidate core.io.rocc.mem.resp.bits.dprv invalidate core.io.rocc.mem.resp.bits.signed invalidate core.io.rocc.mem.resp.bits.size invalidate core.io.rocc.mem.resp.bits.cmd invalidate core.io.rocc.mem.resp.bits.tag invalidate core.io.rocc.mem.resp.bits.addr invalidate core.io.rocc.mem.resp.valid invalidate core.io.rocc.mem.s2_paddr invalidate core.io.rocc.mem.s2_uncached invalidate core.io.rocc.mem.s2_kill invalidate core.io.rocc.mem.s2_nack_cause_raw invalidate core.io.rocc.mem.s2_nack invalidate core.io.rocc.mem.s1_data.mask invalidate core.io.rocc.mem.s1_data.data invalidate core.io.rocc.mem.s1_kill invalidate core.io.rocc.mem.req.bits.mask invalidate core.io.rocc.mem.req.bits.data invalidate core.io.rocc.mem.req.bits.no_xcpt invalidate core.io.rocc.mem.req.bits.no_alloc invalidate core.io.rocc.mem.req.bits.no_resp invalidate core.io.rocc.mem.req.bits.phys invalidate core.io.rocc.mem.req.bits.dv invalidate core.io.rocc.mem.req.bits.dprv invalidate core.io.rocc.mem.req.bits.signed invalidate core.io.rocc.mem.req.bits.size invalidate core.io.rocc.mem.req.bits.cmd invalidate core.io.rocc.mem.req.bits.tag invalidate core.io.rocc.mem.req.bits.addr invalidate core.io.rocc.mem.req.valid invalidate core.io.rocc.mem.req.ready invalidate core.io.rocc.resp.bits.data invalidate core.io.rocc.resp.bits.rd invalidate core.io.rocc.resp.valid invalidate core.io.rocc.resp.ready invalidate core.io.rocc.cmd.bits.status.uie invalidate core.io.rocc.cmd.bits.status.sie invalidate core.io.rocc.cmd.bits.status.hie invalidate core.io.rocc.cmd.bits.status.mie invalidate core.io.rocc.cmd.bits.status.upie invalidate core.io.rocc.cmd.bits.status.spie invalidate core.io.rocc.cmd.bits.status.ube invalidate core.io.rocc.cmd.bits.status.mpie invalidate core.io.rocc.cmd.bits.status.spp invalidate core.io.rocc.cmd.bits.status.vs invalidate core.io.rocc.cmd.bits.status.mpp invalidate core.io.rocc.cmd.bits.status.fs invalidate core.io.rocc.cmd.bits.status.xs invalidate core.io.rocc.cmd.bits.status.mprv invalidate core.io.rocc.cmd.bits.status.sum invalidate core.io.rocc.cmd.bits.status.mxr invalidate core.io.rocc.cmd.bits.status.tvm invalidate core.io.rocc.cmd.bits.status.tw invalidate core.io.rocc.cmd.bits.status.tsr invalidate core.io.rocc.cmd.bits.status.zero1 invalidate core.io.rocc.cmd.bits.status.sd_rv32 invalidate core.io.rocc.cmd.bits.status.uxl invalidate core.io.rocc.cmd.bits.status.sxl invalidate core.io.rocc.cmd.bits.status.sbe invalidate core.io.rocc.cmd.bits.status.mbe invalidate core.io.rocc.cmd.bits.status.gva invalidate core.io.rocc.cmd.bits.status.mpv invalidate core.io.rocc.cmd.bits.status.zero2 invalidate core.io.rocc.cmd.bits.status.sd invalidate core.io.rocc.cmd.bits.status.v invalidate core.io.rocc.cmd.bits.status.prv invalidate core.io.rocc.cmd.bits.status.dv invalidate core.io.rocc.cmd.bits.status.dprv invalidate core.io.rocc.cmd.bits.status.isa invalidate core.io.rocc.cmd.bits.status.wfi invalidate core.io.rocc.cmd.bits.status.cease invalidate core.io.rocc.cmd.bits.status.debug invalidate core.io.rocc.cmd.bits.rs2 invalidate core.io.rocc.cmd.bits.rs1 invalidate core.io.rocc.cmd.bits.inst.opcode invalidate core.io.rocc.cmd.bits.inst.rd invalidate core.io.rocc.cmd.bits.inst.xs2 invalidate core.io.rocc.cmd.bits.inst.xs1 invalidate core.io.rocc.cmd.bits.inst.xd invalidate core.io.rocc.cmd.bits.inst.rs1 invalidate core.io.rocc.cmd.bits.inst.rs2 invalidate core.io.rocc.cmd.bits.inst.funct invalidate core.io.rocc.cmd.valid invalidate core.io.rocc.cmd.ready inst ptw of PTW connect ptw.clock, clock connect ptw.reset, reset connect core.io.ptw, ptw.io.dpath connect ptw.io.requestor[0], lsu.io.ptw connect ptw.io.requestor[1], frontend.io.ptw connect ptw.io.requestor[2], core.io.ptw_tlb inst hellaCacheArb of HellaCacheArbiter connect hellaCacheArb.clock, clock connect hellaCacheArb.reset, reset connect hellaCacheArb.io.requestor[0], ptw.io.mem connect lsu.io.hellacache, hellaCacheArb.io.mem connect dcache.io.lsu, lsu.io.dmem	module BoomTile( // @[tile.scala:154:7] input clock, // @[tile.scala:154:7] input reset, // @[tile.scala:154:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_custom_rob_empty, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire dCacheTapOut_e_ready; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire dCacheTapOut_c_ready; // @[MixedNode.scala:542:17] wire dCacheTapOut_b_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17] wire [7:0] dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17] wire dCacheTapOut_a_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17] wire [7:0] tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire buffer_3_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_3_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_c_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_3_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_3_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _hellaCacheArb_io_requestor_0_req_ready; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_nack; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_resp_valid; // @[tile.scala:242:29] wire [39:0] _hellaCacheArb_io_requestor_0_resp_bits_addr; // @[tile.scala:242:29] wire [1:0] _hellaCacheArb_io_requestor_0_resp_bits_dprv; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_resp_bits_dv; // @[tile.scala:242:29] wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data; // @[tile.scala:242:29] wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[tile.scala:242:29] wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data_raw; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_store_pending; // @[tile.scala:242:29] wire _hellaCacheArb_io_mem_req_valid; // @[tile.scala:242:29] wire [39:0] _hellaCacheArb_io_mem_req_bits_addr; // @[tile.scala:242:29] wire _hellaCacheArb_io_mem_req_bits_dv; // @[tile.scala:242:29] wire _hellaCacheArb_io_mem_s1_kill; // @[tile.scala:242:29] wire _ptw_io_requestor_0_req_ready; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_valid; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pf; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_gf; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_hr; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_hw; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_hx; // @[tile.scala:236:20] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[tile.scala:236:20] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[tile.scala:236:20] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_debug; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_cease; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_wfi; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_dv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_prv; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_v; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_sd; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mpv; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_gva; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_tsr; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_tw; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_tvm; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mxr; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_sum; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mprv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_fs; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_spp; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mpie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_spie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_sie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_req_ready; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_valid; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pf; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_gf; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_hr; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_hw; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_hx; // @[tile.scala:236:20] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[tile.scala:236:20] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[tile.scala:236:20] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_debug; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_cease; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_wfi; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_dv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_prv; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_v; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_sd; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mpv; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_gva; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_tsr; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_tw; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_tvm; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mxr; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_sum; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mprv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_fs; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_spp; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mpie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_spie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_sie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_req_ready; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_valid; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_ae_final; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pf; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_gf; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_hr; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_hw; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_hx; // @[tile.scala:236:20] wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_d; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_g; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_u; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_r; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_v; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[tile.scala:236:20] wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[tile.scala:236:20] wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_debug; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_cease; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_wfi; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_dprv; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_dv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_prv; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_v; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_sd; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mpv; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_gva; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_tsr; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_tw; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_tvm; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mxr; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_sum; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mprv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_fs; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_mpp; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_spp; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mpie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_spie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_sie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[tile.scala:236:20] wire _ptw_io_mem_req_valid; // @[tile.scala:236:20] wire [39:0] _ptw_io_mem_req_bits_addr; // @[tile.scala:236:20] wire _ptw_io_mem_req_bits_dv; // @[tile.scala:236:20] wire _ptw_io_mem_s1_kill; // @[tile.scala:236:20] wire _ptw_io_dpath_perf_l2miss; // @[tile.scala:236:20] wire _ptw_io_dpath_perf_l2hit; // @[tile.scala:236:20] wire _ptw_io_dpath_perf_pte_miss; // @[tile.scala:236:20] wire _ptw_io_dpath_clock_enabled; // @[tile.scala:236:20] wire _lsu_io_ptw_req_valid; // @[tile.scala:159:20] wire _lsu_io_ptw_req_bits_valid; // @[tile.scala:159:20] wire [26:0] _lsu_io_ptw_req_bits_bits_addr; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iwakeups_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iwakeups_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_iwakeups_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_iwakeups_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_iwakeups_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_iwakeups_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_bypassable; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_speculative_mask; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_rebusy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iresp_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iresp_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_iresp_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_iresp_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_iresp_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_iresp_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_iresp_0_bits_data; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_fresp_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_fresp_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_fresp_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_fresp_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_fresp_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_fresp_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_fresp_0_bits_data; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_ldq_idx_0; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_ldq_idx_1; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_stq_idx_0; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_stq_idx_1; // @[tile.scala:159:20] wire _lsu_io_core_ldq_full_0; // @[tile.scala:159:20] wire _lsu_io_core_ldq_full_1; // @[tile.scala:159:20] wire _lsu_io_core_stq_full_0; // @[tile.scala:159:20] wire _lsu_io_core_stq_full_1; // @[tile.scala:159:20] wire _lsu_io_core_clr_bsy_0_valid; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_clr_bsy_0_bits; // @[tile.scala:159:20] wire _lsu_io_core_clr_bsy_1_valid; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_clr_bsy_1_bits; // @[tile.scala:159:20] wire _lsu_io_core_clr_unsafe_0_valid; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_clr_unsafe_0_bits; // @[tile.scala:159:20] wire _lsu_io_core_fencei_rdy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tile.scala:159:20] wire _lsu_io_core_perf_acquire; // @[tile.scala:159:20] wire _lsu_io_core_perf_release; // @[tile.scala:159:20] wire _lsu_io_core_perf_tlbMiss; // @[tile.scala:159:20] wire _lsu_io_dmem_req_valid; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tile.scala:159:20] wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tile.scala:159:20] wire _lsu_io_dmem_s1_kill_0; // @[tile.scala:159:20] wire _lsu_io_dmem_ll_resp_ready; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_brupdate_b1_resolve_mask; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_brupdate_b1_mispredict_mask; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_brupdate_b2_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_brupdate_b2_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_taken; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_dmem_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_dmem_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_mispredict; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_taken; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_cfi_type; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_pc_sel; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_brupdate_b2_jalr_target; // @[tile.scala:159:20] wire [20:0] _lsu_io_dmem_brupdate_b2_target_offset; // @[tile.scala:159:20] wire _lsu_io_dmem_exception; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_rob_pnr_idx; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_rob_head_idx; // @[tile.scala:159:20] wire _lsu_io_dmem_release_ready; // @[tile.scala:159:20] wire _lsu_io_dmem_force_order; // @[tile.scala:159:20] wire _lsu_io_hellacache_req_ready; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_nack; // @[tile.scala:159:20] wire _lsu_io_hellacache_resp_valid; // @[tile.scala:159:20] wire [39:0] _lsu_io_hellacache_resp_bits_addr; // @[tile.scala:159:20] wire [1:0] _lsu_io_hellacache_resp_bits_dprv; // @[tile.scala:159:20] wire _lsu_io_hellacache_resp_bits_dv; // @[tile.scala:159:20] wire [63:0] _lsu_io_hellacache_resp_bits_data; // @[tile.scala:159:20] wire [63:0] _lsu_io_hellacache_resp_bits_data_word_bypass; // @[tile.scala:159:20] wire [63:0] _lsu_io_hellacache_resp_bits_data_raw; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ma_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ma_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_pf_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_pf_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_gf_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_gf_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ae_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ae_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_store_pending; // @[tile.scala:159:20] wire _core_io_ifu_fetchpacket_ready; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_arb_ftq_reqs_0; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_arb_ftq_reqs_1; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_arb_ftq_reqs_2; // @[tile.scala:158:20] wire _core_io_ifu_status_debug; // @[tile.scala:158:20] wire _core_io_ifu_status_cease; // @[tile.scala:158:20] wire _core_io_ifu_status_wfi; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_dprv; // @[tile.scala:158:20] wire _core_io_ifu_status_dv; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_prv; // @[tile.scala:158:20] wire _core_io_ifu_status_v; // @[tile.scala:158:20] wire _core_io_ifu_status_sd; // @[tile.scala:158:20] wire _core_io_ifu_status_mpv; // @[tile.scala:158:20] wire _core_io_ifu_status_gva; // @[tile.scala:158:20] wire _core_io_ifu_status_tsr; // @[tile.scala:158:20] wire _core_io_ifu_status_tw; // @[tile.scala:158:20] wire _core_io_ifu_status_tvm; // @[tile.scala:158:20] wire _core_io_ifu_status_mxr; // @[tile.scala:158:20] wire _core_io_ifu_status_sum; // @[tile.scala:158:20] wire _core_io_ifu_status_mprv; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_fs; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_mpp; // @[tile.scala:158:20] wire _core_io_ifu_status_spp; // @[tile.scala:158:20] wire _core_io_ifu_status_mpie; // @[tile.scala:158:20] wire _core_io_ifu_status_spie; // @[tile.scala:158:20] wire _core_io_ifu_status_mie; // @[tile.scala:158:20] wire _core_io_ifu_status_sie; // @[tile.scala:158:20] wire _core_io_ifu_sfence_valid; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_rs1; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_rs2; // @[tile.scala:158:20] wire [38:0] _core_io_ifu_sfence_bits_addr; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_asid; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_hv; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_hg; // @[tile.scala:158:20] wire [11:0] _core_io_ifu_brupdate_b1_resolve_mask; // @[tile.scala:158:20] wire [11:0] _core_io_ifu_brupdate_b1_mispredict_mask; // @[tile.scala:158:20] wire [31:0] _core_io_ifu_brupdate_b2_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_ifu_brupdate_b2_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_ifu_brupdate_b2_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_ifu_brupdate_b2_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_br_type; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_fence; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_amo; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_eret; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_taken; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_ifu_brupdate_b2_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_ppred; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_ifu_brupdate_b2_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_mem_size; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_unique; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_mispredict; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_taken; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_cfi_type; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_pc_sel; // @[tile.scala:158:20] wire [39:0] _core_io_ifu_brupdate_b2_jalr_target; // @[tile.scala:158:20] wire [20:0] _core_io_ifu_brupdate_b2_target_offset; // @[tile.scala:158:20] wire _core_io_ifu_redirect_flush; // @[tile.scala:158:20] wire _core_io_ifu_redirect_val; // @[tile.scala:158:20] wire [39:0] _core_io_ifu_redirect_pc; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_redirect_ftq_idx; // @[tile.scala:158:20] wire [63:0] _core_io_ifu_redirect_ghist_old_history; // @[tile.scala:158:20] wire _core_io_ifu_redirect_ghist_current_saw_branch_not_taken; // @[tile.scala:158:20] wire _core_io_ifu_redirect_ghist_new_saw_branch_not_taken; // @[tile.scala:158:20] wire _core_io_ifu_redirect_ghist_new_saw_branch_taken; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_redirect_ghist_ras_idx; // @[tile.scala:158:20] wire _core_io_ifu_commit_valid; // @[tile.scala:158:20] wire [31:0] _core_io_ifu_commit_bits; // @[tile.scala:158:20] wire _core_io_ifu_flush_icache; // @[tile.scala:158:20] wire _core_io_ifu_enable_bpd; // @[tile.scala:158:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[tile.scala:158:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[tile.scala:158:20] wire _core_io_ptw_sfence_valid; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_rs1; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_rs2; // @[tile.scala:158:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_asid; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_hv; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_hg; // @[tile.scala:158:20] wire _core_io_ptw_status_debug; // @[tile.scala:158:20] wire _core_io_ptw_status_cease; // @[tile.scala:158:20] wire _core_io_ptw_status_wfi; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_dprv; // @[tile.scala:158:20] wire _core_io_ptw_status_dv; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_prv; // @[tile.scala:158:20] wire _core_io_ptw_status_v; // @[tile.scala:158:20] wire _core_io_ptw_status_sd; // @[tile.scala:158:20] wire _core_io_ptw_status_mpv; // @[tile.scala:158:20] wire _core_io_ptw_status_gva; // @[tile.scala:158:20] wire _core_io_ptw_status_tsr; // @[tile.scala:158:20] wire _core_io_ptw_status_tw; // @[tile.scala:158:20] wire _core_io_ptw_status_tvm; // @[tile.scala:158:20] wire _core_io_ptw_status_mxr; // @[tile.scala:158:20] wire _core_io_ptw_status_sum; // @[tile.scala:158:20] wire _core_io_ptw_status_mprv; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_fs; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_mpp; // @[tile.scala:158:20] wire _core_io_ptw_status_spp; // @[tile.scala:158:20] wire _core_io_ptw_status_mpie; // @[tile.scala:158:20] wire _core_io_ptw_status_spie; // @[tile.scala:158:20] wire _core_io_ptw_status_mie; // @[tile.scala:158:20] wire _core_io_ptw_status_sie; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_agen_0_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_agen_0_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_agen_0_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_agen_0_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_agen_0_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_agen_0_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_agen_0_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_0_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_0_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dgen_0_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dgen_0_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dgen_0_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_0_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_0_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_1_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_1_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dgen_1_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dgen_1_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dgen_1_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_1_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_1_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_2_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_2_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dgen_2_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dgen_2_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dgen_2_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_2_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_2_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_sfence_valid; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_rs1; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_rs2; // @[tile.scala:158:20] wire [38:0] _core_io_lsu_sfence_bits_addr; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_asid; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_hv; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_hg; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_0_bits_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_0_bits_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dis_uops_0_bits_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dis_uops_0_bits_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_taken; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dis_uops_0_bits_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dis_uops_0_bits_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_1_bits_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_1_bits_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dis_uops_1_bits_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dis_uops_1_bits_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_taken; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dis_uops_1_bits_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dis_uops_1_bits_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_commit_valids_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_valids_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_arch_valids_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_arch_valids_1; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_0_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_0_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_commit_uops_0_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_commit_uops_0_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_br_type; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_taken; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_commit_uops_0_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_ppred; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_uops_0_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_debug_tsrc; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_1_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_1_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_commit_uops_1_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_commit_uops_1_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_br_type; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_taken; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_commit_uops_1_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_ppred; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_uops_1_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_commit_fflags_valid; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_fflags_bits; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_debug_wdata_0; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_debug_wdata_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_load_at_rob_head; // @[tile.scala:158:20] wire _core_io_lsu_fence_dmem; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_brupdate_b1_resolve_mask; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_brupdate_b1_mispredict_mask; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_brupdate_b2_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_brupdate_b2_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_brupdate_b2_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_brupdate_b2_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_brupdate_b2_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_brupdate_b2_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_mispredict; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_taken; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_cfi_type; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_pc_sel; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_brupdate_b2_jalr_target; // @[tile.scala:158:20] wire [20:0] _core_io_lsu_brupdate_b2_target_offset; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_rob_pnr_idx; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_rob_head_idx; // @[tile.scala:158:20] wire _core_io_lsu_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_tsc_reg; // @[tile.scala:158:20] wire _core_io_lsu_status_debug; // @[tile.scala:158:20] wire _core_io_lsu_status_cease; // @[tile.scala:158:20] wire _core_io_lsu_status_wfi; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_dprv; // @[tile.scala:158:20] wire _core_io_lsu_status_dv; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_prv; // @[tile.scala:158:20] wire _core_io_lsu_status_v; // @[tile.scala:158:20] wire _core_io_lsu_status_sd; // @[tile.scala:158:20] wire _core_io_lsu_status_mpv; // @[tile.scala:158:20] wire _core_io_lsu_status_gva; // @[tile.scala:158:20] wire _core_io_lsu_status_tsr; // @[tile.scala:158:20] wire _core_io_lsu_status_tw; // @[tile.scala:158:20] wire _core_io_lsu_status_tvm; // @[tile.scala:158:20] wire _core_io_lsu_status_mxr; // @[tile.scala:158:20] wire _core_io_lsu_status_sum; // @[tile.scala:158:20] wire _core_io_lsu_status_mprv; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_fs; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_mpp; // @[tile.scala:158:20] wire _core_io_lsu_status_spp; // @[tile.scala:158:20] wire _core_io_lsu_status_mpie; // @[tile.scala:158:20] wire _core_io_lsu_status_spie; // @[tile.scala:158:20] wire _core_io_lsu_status_mie; // @[tile.scala:158:20] wire _core_io_lsu_status_sie; // @[tile.scala:158:20] wire _buffer_2_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_2_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_2_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire _buffer_2_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_2_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_2_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_2_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_2_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_2_auto_out_d_ready; // @[Buffer.scala:75:28] wire _frontend_io_cpu_fetchpacket_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_valid; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst; // @[tile.scala:137:28] wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_valid; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst; // @[tile.scala:137:28] wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid; // @[tile.scala:137:28] wire [1:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_type; // @[tile.scala:137:28] wire [3:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_br_mask; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_call; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_ras_top; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_ras_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_start_bank; // @[tile.scala:137:28] wire [63:0] _frontend_io_cpu_rrd_ftq_resps_0_ghist_old_history; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_0_ghist_ras_idx; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_0_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid; // @[tile.scala:137:28] wire [1:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_type; // @[tile.scala:137:28] wire [3:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_br_mask; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_call; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_ras_top; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_ras_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_start_bank; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_1_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid; // @[tile.scala:137:28] wire [1:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_type; // @[tile.scala:137:28] wire [3:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_br_mask; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_call; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_ras_top; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_ras_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_start_bank; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_2_pc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_com_pc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_debug_fetch_pc_0; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_debug_fetch_pc_1; // @[tile.scala:137:28] wire _frontend_io_cpu_perf_acquire; // @[tile.scala:137:28] wire _frontend_io_cpu_perf_tlbMiss; // @[tile.scala:137:28] wire _frontend_io_ptw_req_valid; // @[tile.scala:137:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[tile.scala:137:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[tile.scala:137:28] wire _dcache_io_lsu_req_ready; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_store_ack_0_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_store_ack_0_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_store_ack_0_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_store_ack_0_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_store_ack_0_bits_addr; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_store_ack_0_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_nack_0_bits_addr; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_ll_resp_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_ll_resp_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_ll_resp_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_ll_resp_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_ll_resp_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_ll_resp_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_ll_resp_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_release_valid; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_release_bits_param; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_release_bits_size; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_release_bits_source; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_release_bits_address; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_release_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_ordered; // @[tile.scala:132:54] wire _dcache_io_lsu_perf_acquire; // @[tile.scala:132:54] wire _dcache_io_lsu_perf_release; // @[tile.scala:132:54] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_b_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_b_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_b_bits_size; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_b_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_auto_in_b_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_in_b_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_b_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_c_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_e_ready; // @[Buffer.scala:75:28] wire _tlMasterXbar_auto_anon_in_1_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_1_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_1_d_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_1_d_bits_size; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_1_d_bits_sink; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_bits_denied; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_1_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_a_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_a_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_a_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_out_a_bits_size; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_a_bits_source; // @[HierarchicalElement.scala:55:42] wire [31:0] _tlMasterXbar_auto_anon_out_a_bits_address; // @[HierarchicalElement.scala:55:42] wire [7:0] _tlMasterXbar_auto_anon_out_a_bits_mask; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_out_a_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_a_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_b_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_c_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_c_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_c_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_out_c_bits_size; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_c_bits_source; // @[HierarchicalElement.scala:55:42] wire [31:0] _tlMasterXbar_auto_anon_out_c_bits_address; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_out_c_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_c_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_d_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_e_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_e_bits_sink; // @[HierarchicalElement.scala:55:42] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tile.scala:154:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tile.scala:154:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tile.scala:154:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tile.scala:154:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tile.scala:154:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tile.scala:154:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tile.scala:154:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tile.scala:154:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tile.scala:154:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tile.scala:154:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tile.scala:154:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tile.scala:154:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[tile.scala:154:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[tile.scala:154:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[tile.scala:154:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[tile.scala:154:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tile.scala:154:7] wire auto_hartid_in_0 = auto_hartid_in; // @[tile.scala:154:7] wire auto_wfi_out_0 = 1'h0; // @[tile.scala:154:7] wire auto_cease_out_0 = 1'h0; // @[tile.scala:154:7] wire auto_halt_out_0 = 1'h0; // @[tile.scala:154:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tile.scala:154:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_1_valid = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_1_exception = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_1_interrupt = 1'h0; // @[tile.scala:154:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] reset_vectorOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] reset_vectorIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] auto_trace_source_out_insns_1_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] traceSourceNodeOut_insns_1_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_trace_source_out_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] traceSourceNodeOut_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tile.scala:154:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tile.scala:154:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_source_out_insns_1_insn = 32'h0; // @[tile.scala:154:7] wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire buffer_3_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_3_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_3_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[MixedNode.scala:551:17] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[MixedNode.scala:551:17] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_a_bits_source_0; // @[tile.scala:154:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[tile.scala:154:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[tile.scala:154:7] wire auto_buffer_out_a_bits_corrupt_0; // @[tile.scala:154:7] wire auto_buffer_out_a_valid_0; // @[tile.scala:154:7] wire auto_buffer_out_b_ready_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_c_bits_source_0; // @[tile.scala:154:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[tile.scala:154:7] wire auto_buffer_out_c_bits_corrupt_0; // @[tile.scala:154:7] wire auto_buffer_out_c_valid_0; // @[tile.scala:154:7] wire auto_buffer_out_d_ready_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[tile.scala:154:7] wire auto_buffer_out_e_valid_0; // @[tile.scala:154:7] wire auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:154:7] wire [63:0] auto_trace_source_out_time_0; // @[tile.scala:154:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_source = widget_1_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_source = widget_1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_source = widget_1_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_3_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_a_ready = buffer_3_auto_in_a_ready; // @[Buffer.scala:40:9] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_a_valid = buffer_3_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_a_bits_opcode = buffer_3_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_a_bits_param = buffer_3_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_3_nodeIn_a_bits_size = buffer_3_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_a_bits_source = buffer_3_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_3_nodeIn_a_bits_address = buffer_3_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_3_nodeIn_a_bits_mask = buffer_3_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_3_nodeIn_a_bits_data = buffer_3_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_a_bits_corrupt = buffer_3_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_b_ready = buffer_3_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_3_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_b_valid = buffer_3_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_b_bits_opcode = buffer_3_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_b_bits_param = buffer_3_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_b_bits_size = buffer_3_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_b_bits_source = buffer_3_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_3_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] masterNodeOut_b_bits_address = buffer_3_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] masterNodeOut_b_bits_mask = buffer_3_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_b_bits_data = buffer_3_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_b_bits_corrupt = buffer_3_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_c_ready = buffer_3_auto_in_c_ready; // @[Buffer.scala:40:9] wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_c_valid = buffer_3_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_c_bits_opcode = buffer_3_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_c_bits_param = buffer_3_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_3_nodeIn_c_bits_size = buffer_3_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_c_bits_source = buffer_3_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_3_nodeIn_c_bits_address = buffer_3_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_3_nodeIn_c_bits_data = buffer_3_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_c_bits_corrupt = buffer_3_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_d_ready = buffer_3_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_3_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_d_valid = buffer_3_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_opcode = buffer_3_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_d_bits_param = buffer_3_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_d_bits_size = buffer_3_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_source = buffer_3_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_sink = buffer_3_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_denied = buffer_3_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_d_bits_data = buffer_3_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_corrupt = buffer_3_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_e_ready = buffer_3_auto_in_e_ready; // @[Buffer.scala:40:9] wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_e_valid = buffer_3_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_e_bits_sink = buffer_3_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_a_ready = buffer_3_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_3_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_3_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_3_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_3_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_3_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_3_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_3_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_3_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_3_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_corrupt_0 = buffer_3_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_3_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_b_valid = buffer_3_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_b_bits_opcode = buffer_3_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeOut_b_bits_param = buffer_3_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_b_bits_size = buffer_3_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_b_bits_source = buffer_3_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeOut_b_bits_address = buffer_3_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_3_nodeOut_b_bits_mask = buffer_3_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_b_bits_data = buffer_3_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_b_bits_corrupt = buffer_3_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_c_ready = buffer_3_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_3_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_3_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_3_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_3_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_3_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_3_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_3_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_corrupt_0 = buffer_3_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_3_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_valid = buffer_3_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_d_bits_opcode = buffer_3_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeOut_d_bits_param = buffer_3_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_d_bits_size = buffer_3_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_d_bits_source = buffer_3_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_d_bits_sink = buffer_3_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_bits_denied = buffer_3_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_d_bits_data = buffer_3_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_bits_corrupt = buffer_3_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_e_ready = buffer_3_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_3_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_3_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_3_nodeIn_a_ready = buffer_3_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_out_a_valid = buffer_3_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_opcode = buffer_3_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_param = buffer_3_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_size = buffer_3_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_source = buffer_3_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_address = buffer_3_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_mask = buffer_3_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_data = buffer_3_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_corrupt = buffer_3_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_out_b_ready = buffer_3_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeIn_b_valid = buffer_3_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_opcode = buffer_3_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_param = buffer_3_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_size = buffer_3_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_source = buffer_3_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_address = buffer_3_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_mask = buffer_3_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_data = buffer_3_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_corrupt = buffer_3_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_c_ready = buffer_3_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_out_c_valid = buffer_3_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_opcode = buffer_3_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_param = buffer_3_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_size = buffer_3_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_source = buffer_3_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_address = buffer_3_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_data = buffer_3_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_corrupt = buffer_3_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_out_d_ready = buffer_3_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeIn_d_valid = buffer_3_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_opcode = buffer_3_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_param = buffer_3_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_size = buffer_3_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_source = buffer_3_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_sink = buffer_3_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_denied = buffer_3_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_data = buffer_3_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_corrupt = buffer_3_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_e_ready = buffer_3_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_out_e_valid = buffer_3_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_out_e_bits_sink = buffer_3_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_ready = buffer_3_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeOut_a_valid = buffer_3_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_opcode = buffer_3_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_param = buffer_3_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_size = buffer_3_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_source = buffer_3_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_address = buffer_3_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_mask = buffer_3_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_data = buffer_3_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_corrupt = buffer_3_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_b_ready = buffer_3_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_b_valid = buffer_3_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_opcode = buffer_3_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_param = buffer_3_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_size = buffer_3_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_source = buffer_3_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_address = buffer_3_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_mask = buffer_3_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_data = buffer_3_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_corrupt = buffer_3_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_ready = buffer_3_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeOut_c_valid = buffer_3_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_opcode = buffer_3_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_param = buffer_3_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_size = buffer_3_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_source = buffer_3_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_address = buffer_3_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_data = buffer_3_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_corrupt = buffer_3_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_d_ready = buffer_3_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_d_valid = buffer_3_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_opcode = buffer_3_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_param = buffer_3_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_size = buffer_3_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_source = buffer_3_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_sink = buffer_3_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_denied = buffer_3_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_data = buffer_3_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_corrupt = buffer_3_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_e_ready = buffer_3_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeOut_e_valid = buffer_3_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_e_bits_sink = buffer_3_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeIn_a_valid = tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeIn_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] masterNodeIn_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] masterNodeIn_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeIn_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] wire masterNodeIn_a_bits_corrupt = tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_ready = tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_valid; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] masterNodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] masterNodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [7:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeIn_c_valid = tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeIn_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] wire [31:0] masterNodeIn_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeIn_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] wire masterNodeIn_c_bits_corrupt = tlOtherMastersNodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_ready = tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_valid; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] wire masterNodeIn_e_valid = tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_corrupt = tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_corrupt = tlOtherMastersNodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[MixedNode.scala:542:17] assign auto_trace_source_out_custom_rob_empty_0 = traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_corrupt = masterNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9] assign masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_corrupt = masterNodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9] assign masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_ready = masterNodeIn_a_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_corrupt = masterNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_valid = masterNodeIn_b_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_opcode = masterNodeIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_param = masterNodeIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_size = masterNodeIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_source = masterNodeIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_address = masterNodeIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_mask = masterNodeIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_data = masterNodeIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_corrupt = masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_ready = masterNodeIn_c_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_corrupt = masterNodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_valid = masterNodeIn_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_opcode = masterNodeIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_param = masterNodeIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_size = masterNodeIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_source = masterNodeIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_sink = masterNodeIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_denied = masterNodeIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_data = masterNodeIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_corrupt = masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_ready = masterNodeIn_e_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_a_ready = dCacheTapOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_a_valid; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] dCacheTapIn_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] dCacheTapIn_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dCacheTapIn_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] dCacheTapIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] dCacheTapIn_a_bits_data; // @[MixedNode.scala:551:17] wire dCacheTapIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire dCacheTapIn_b_ready; // @[MixedNode.scala:551:17] wire dCacheTapIn_b_valid = dCacheTapOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] dCacheTapIn_b_bits_opcode = dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_b_bits_param = dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] dCacheTapIn_b_bits_size = dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_b_bits_source = dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] dCacheTapIn_b_bits_address = dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] dCacheTapIn_b_bits_mask = dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] dCacheTapIn_b_bits_data = dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_b_bits_corrupt = dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_c_ready = dCacheTapOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_c_valid; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] dCacheTapIn_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] dCacheTapIn_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dCacheTapIn_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] dCacheTapIn_c_bits_data; // @[MixedNode.scala:551:17] wire dCacheTapIn_c_bits_corrupt; // @[MixedNode.scala:551:17] wire dCacheTapIn_d_ready; // @[MixedNode.scala:551:17] wire dCacheTapIn_d_valid = dCacheTapOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] dCacheTapIn_d_bits_opcode = dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_d_bits_param = dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] dCacheTapIn_d_bits_size = dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_d_bits_source = dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] dCacheTapIn_d_bits_sink = dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_d_bits_denied = dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] dCacheTapIn_d_bits_data = dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_d_bits_corrupt = dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_e_ready = dCacheTapOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_e_valid; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_e_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] dCacheTapOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] dCacheTapOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_a_bits_data; // @[MixedNode.scala:542:17] wire dCacheTapOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire dCacheTapOut_a_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_b_ready; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] dCacheTapOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_c_bits_data; // @[MixedNode.scala:542:17] wire dCacheTapOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire dCacheTapOut_c_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_ready; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_e_bits_sink; // @[MixedNode.scala:542:17] wire dCacheTapOut_e_valid; // @[MixedNode.scala:542:17] assign dCacheTapOut_a_valid = dCacheTapIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_opcode = dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_param = dCacheTapIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_size = dCacheTapIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_source = dCacheTapIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_address = dCacheTapIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_mask = dCacheTapIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_data = dCacheTapIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_corrupt = dCacheTapIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_b_ready = dCacheTapIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_valid = dCacheTapIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_opcode = dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_param = dCacheTapIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_size = dCacheTapIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_source = dCacheTapIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_address = dCacheTapIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_data = dCacheTapIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_corrupt = dCacheTapIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_d_ready = dCacheTapIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_e_valid = dCacheTapIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_e_bits_sink = dCacheTapIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (_tlMasterXbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_buffer_2_auto_out_a_valid), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_opcode (_buffer_2_auto_out_a_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_param (_buffer_2_auto_out_a_bits_param), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_size (_buffer_2_auto_out_a_bits_size), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_source (_buffer_2_auto_out_a_bits_source), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_address (_buffer_2_auto_out_a_bits_address), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_mask (_buffer_2_auto_out_a_bits_mask), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_data (_buffer_2_auto_out_a_bits_data), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_corrupt (_buffer_2_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_in_1_d_ready (_buffer_2_auto_out_d_ready), // @[Buffer.scala:75:28] .auto_anon_in_1_d_valid (_tlMasterXbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_tlMasterXbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_tlMasterXbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_tlMasterXbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_sink (_tlMasterXbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_tlMasterXbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_tlMasterXbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_tlMasterXbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (dCacheTapOut_a_ready), .auto_anon_in_0_a_valid (dCacheTapOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_opcode (dCacheTapOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_param (dCacheTapOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_size (dCacheTapOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_source (dCacheTapOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_address (dCacheTapOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_mask (dCacheTapOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_data (dCacheTapOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_corrupt (dCacheTapOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_0_b_ready (dCacheTapOut_b_ready), // @[MixedNode.scala:542:17] .auto_anon_in_0_b_valid (dCacheTapOut_b_valid), .auto_anon_in_0_b_bits_opcode (dCacheTapOut_b_bits_opcode), .auto_anon_in_0_b_bits_param (dCacheTapOut_b_bits_param), .auto_anon_in_0_b_bits_size (dCacheTapOut_b_bits_size), .auto_anon_in_0_b_bits_source (dCacheTapOut_b_bits_source), .auto_anon_in_0_b_bits_address (dCacheTapOut_b_bits_address), .auto_anon_in_0_b_bits_mask (dCacheTapOut_b_bits_mask), .auto_anon_in_0_b_bits_data (dCacheTapOut_b_bits_data), .auto_anon_in_0_b_bits_corrupt (dCacheTapOut_b_bits_corrupt), .auto_anon_in_0_c_ready (dCacheTapOut_c_ready), .auto_anon_in_0_c_valid (dCacheTapOut_c_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_opcode (dCacheTapOut_c_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_param (dCacheTapOut_c_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_size (dCacheTapOut_c_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_source (dCacheTapOut_c_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_address (dCacheTapOut_c_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_data (dCacheTapOut_c_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_corrupt (dCacheTapOut_c_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_0_d_ready (dCacheTapOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_0_d_valid (dCacheTapOut_d_valid), .auto_anon_in_0_d_bits_opcode (dCacheTapOut_d_bits_opcode), .auto_anon_in_0_d_bits_param (dCacheTapOut_d_bits_param), .auto_anon_in_0_d_bits_size (dCacheTapOut_d_bits_size), .auto_anon_in_0_d_bits_source (dCacheTapOut_d_bits_source), .auto_anon_in_0_d_bits_sink (dCacheTapOut_d_bits_sink), .auto_anon_in_0_d_bits_denied (dCacheTapOut_d_bits_denied), .auto_anon_in_0_d_bits_data (dCacheTapOut_d_bits_data), .auto_anon_in_0_d_bits_corrupt (dCacheTapOut_d_bits_corrupt), .auto_anon_in_0_e_ready (dCacheTapOut_e_ready), .auto_anon_in_0_e_valid (dCacheTapOut_e_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_e_bits_sink (dCacheTapOut_e_bits_sink), // @[MixedNode.scala:542:17] .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_tlMasterXbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_tlMasterXbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_tlMasterXbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_tlMasterXbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_tlMasterXbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_tlMasterXbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_tlMasterXbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_tlMasterXbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_tlMasterXbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_b_ready (_tlMasterXbar_auto_anon_out_b_ready), .auto_anon_out_b_valid (_buffer_auto_in_b_valid), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_opcode (_buffer_auto_in_b_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_param (_buffer_auto_in_b_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_size (_buffer_auto_in_b_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_source (_buffer_auto_in_b_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_address (_buffer_auto_in_b_bits_address), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_mask (_buffer_auto_in_b_bits_mask), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_data (_buffer_auto_in_b_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_out_c_ready (_buffer_auto_in_c_ready), // @[Buffer.scala:75:28] .auto_anon_out_c_valid (_tlMasterXbar_auto_anon_out_c_valid), .auto_anon_out_c_bits_opcode (_tlMasterXbar_auto_anon_out_c_bits_opcode), .auto_anon_out_c_bits_param (_tlMasterXbar_auto_anon_out_c_bits_param), .auto_anon_out_c_bits_size (_tlMasterXbar_auto_anon_out_c_bits_size), .auto_anon_out_c_bits_source (_tlMasterXbar_auto_anon_out_c_bits_source), .auto_anon_out_c_bits_address (_tlMasterXbar_auto_anon_out_c_bits_address), .auto_anon_out_c_bits_data (_tlMasterXbar_auto_anon_out_c_bits_data), .auto_anon_out_c_bits_corrupt (_tlMasterXbar_auto_anon_out_c_bits_corrupt), .auto_anon_out_d_ready (_tlMasterXbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_out_e_ready (_buffer_auto_in_e_ready), // @[Buffer.scala:75:28] .auto_anon_out_e_valid (_tlMasterXbar_auto_anon_out_e_valid), .auto_anon_out_e_bits_sink (_tlMasterXbar_auto_anon_out_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] TLBuffer_a32d64s3k3z4c buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_tlMasterXbar_auto_anon_out_a_valid), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_opcode (_tlMasterXbar_auto_anon_out_a_bits_opcode), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_param (_tlMasterXbar_auto_anon_out_a_bits_param), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_size (_tlMasterXbar_auto_anon_out_a_bits_size), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_source (_tlMasterXbar_auto_anon_out_a_bits_source), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_address (_tlMasterXbar_auto_anon_out_a_bits_address), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_mask (_tlMasterXbar_auto_anon_out_a_bits_mask), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_data (_tlMasterXbar_auto_anon_out_a_bits_data), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_corrupt (_tlMasterXbar_auto_anon_out_a_bits_corrupt), // @[HierarchicalElement.scala:55:42] .auto_in_b_ready (_tlMasterXbar_auto_anon_out_b_ready), // @[HierarchicalElement.scala:55:42] .auto_in_b_valid (_buffer_auto_in_b_valid), .auto_in_b_bits_opcode (_buffer_auto_in_b_bits_opcode), .auto_in_b_bits_param (_buffer_auto_in_b_bits_param), .auto_in_b_bits_size (_buffer_auto_in_b_bits_size), .auto_in_b_bits_source (_buffer_auto_in_b_bits_source), .auto_in_b_bits_address (_buffer_auto_in_b_bits_address), .auto_in_b_bits_mask (_buffer_auto_in_b_bits_mask), .auto_in_b_bits_data (_buffer_auto_in_b_bits_data), .auto_in_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), .auto_in_c_ready (_buffer_auto_in_c_ready), .auto_in_c_valid (_tlMasterXbar_auto_anon_out_c_valid), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_opcode (_tlMasterXbar_auto_anon_out_c_bits_opcode), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_param (_tlMasterXbar_auto_anon_out_c_bits_param), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_size (_tlMasterXbar_auto_anon_out_c_bits_size), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_source (_tlMasterXbar_auto_anon_out_c_bits_source), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_address (_tlMasterXbar_auto_anon_out_c_bits_address), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_data (_tlMasterXbar_auto_anon_out_c_bits_data), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_corrupt (_tlMasterXbar_auto_anon_out_c_bits_corrupt), // @[HierarchicalElement.scala:55:42] .auto_in_d_ready (_tlMasterXbar_auto_anon_out_d_ready), // @[HierarchicalElement.scala:55:42] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_in_e_ready (_buffer_auto_in_e_ready), .auto_in_e_valid (_tlMasterXbar_auto_anon_out_e_valid), // @[HierarchicalElement.scala:55:42] .auto_in_e_bits_sink (_tlMasterXbar_auto_anon_out_e_bits_sink), // @[HierarchicalElement.scala:55:42] .auto_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_out_a_bits_corrupt (tlOtherMastersNodeIn_a_bits_corrupt), .auto_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_out_c_bits_corrupt (tlOtherMastersNodeIn_c_bits_corrupt), .auto_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[Buffer.scala:75:28] TLBuffer_a32d64s2k3z4c buffer_1 ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (widget_auto_anon_out_a_ready), .auto_in_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_in_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_in_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_in_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_in_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_in_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_in_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_in_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_in_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_in_b_valid (widget_auto_anon_out_b_valid), .auto_in_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_in_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_in_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_in_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_in_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_in_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_in_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_in_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_in_c_ready (widget_auto_anon_out_c_ready), .auto_in_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_in_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_in_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_in_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_in_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_in_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_in_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_in_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_in_d_valid (widget_auto_anon_out_d_valid), .auto_in_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_in_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_in_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_in_e_ready (widget_auto_anon_out_e_ready), .auto_in_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_in_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_a_ready (dCacheTapIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (dCacheTapIn_a_valid), .auto_out_a_bits_opcode (dCacheTapIn_a_bits_opcode), .auto_out_a_bits_param (dCacheTapIn_a_bits_param), .auto_out_a_bits_size (dCacheTapIn_a_bits_size), .auto_out_a_bits_source (dCacheTapIn_a_bits_source), .auto_out_a_bits_address (dCacheTapIn_a_bits_address), .auto_out_a_bits_mask (dCacheTapIn_a_bits_mask), .auto_out_a_bits_data (dCacheTapIn_a_bits_data), .auto_out_a_bits_corrupt (dCacheTapIn_a_bits_corrupt), .auto_out_b_ready (dCacheTapIn_b_ready), .auto_out_b_valid (dCacheTapIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_opcode (dCacheTapIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (dCacheTapIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_size (dCacheTapIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (dCacheTapIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (dCacheTapIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_b_bits_mask (dCacheTapIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_out_b_bits_data (dCacheTapIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_out_b_bits_corrupt (dCacheTapIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_c_ready (dCacheTapIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (dCacheTapIn_c_valid), .auto_out_c_bits_opcode (dCacheTapIn_c_bits_opcode), .auto_out_c_bits_param (dCacheTapIn_c_bits_param), .auto_out_c_bits_size (dCacheTapIn_c_bits_size), .auto_out_c_bits_source (dCacheTapIn_c_bits_source), .auto_out_c_bits_address (dCacheTapIn_c_bits_address), .auto_out_c_bits_data (dCacheTapIn_c_bits_data), .auto_out_c_bits_corrupt (dCacheTapIn_c_bits_corrupt), .auto_out_d_ready (dCacheTapIn_d_ready), .auto_out_d_valid (dCacheTapIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (dCacheTapIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (dCacheTapIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (dCacheTapIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (dCacheTapIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (dCacheTapIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (dCacheTapIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (dCacheTapIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (dCacheTapIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (dCacheTapIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (dCacheTapIn_e_valid), .auto_out_e_bits_sink (dCacheTapIn_e_bits_sink) ); // @[Buffer.scala:75:28] BoomNonBlockingDCache dcache ( // @[tile.scala:132:54] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_lsu_req_ready (_dcache_io_lsu_req_ready), .io_lsu_req_valid (_lsu_io_dmem_req_valid), // @[tile.scala:159:20] .io_lsu_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_0 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_1 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_2 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_3 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_0 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_1 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_2 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_3 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_4 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_5 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_6 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_7 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_8 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_9 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_issued (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_dis_col_sel (_lsu_io_dmem_req_bits_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_br_type (_lsu_io_dmem_req_bits_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_sfence (_lsu_io_dmem_req_bits_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_eret (_lsu_io_dmem_req_bits_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_rocc (_lsu_io_dmem_req_bits_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_mov (_lsu_io_dmem_req_bits_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_imm_rename (_lsu_io_dmem_req_bits_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_pimm (_lsu_io_dmem_req_bits_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_wen (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_toint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_fma (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_div (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_vec (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fcn_op (_lsu_io_dmem_req_bits_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_rm (_lsu_io_dmem_req_bits_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_typ (_lsu_io_dmem_req_bits_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), // @[tile.scala:159:20] .io_lsu_s1_kill_0 (_lsu_io_dmem_s1_kill_0), // @[tile.scala:159:20] .io_lsu_resp_0_valid (_dcache_io_lsu_resp_0_valid), .io_lsu_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), .io_lsu_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), .io_lsu_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), .io_lsu_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), .io_lsu_resp_0_bits_uop_iq_type_0 (_dcache_io_lsu_resp_0_bits_uop_iq_type_0), .io_lsu_resp_0_bits_uop_iq_type_1 (_dcache_io_lsu_resp_0_bits_uop_iq_type_1), .io_lsu_resp_0_bits_uop_iq_type_2 (_dcache_io_lsu_resp_0_bits_uop_iq_type_2), .io_lsu_resp_0_bits_uop_iq_type_3 (_dcache_io_lsu_resp_0_bits_uop_iq_type_3), .io_lsu_resp_0_bits_uop_fu_code_0 (_dcache_io_lsu_resp_0_bits_uop_fu_code_0), .io_lsu_resp_0_bits_uop_fu_code_1 (_dcache_io_lsu_resp_0_bits_uop_fu_code_1), .io_lsu_resp_0_bits_uop_fu_code_2 (_dcache_io_lsu_resp_0_bits_uop_fu_code_2), .io_lsu_resp_0_bits_uop_fu_code_3 (_dcache_io_lsu_resp_0_bits_uop_fu_code_3), .io_lsu_resp_0_bits_uop_fu_code_4 (_dcache_io_lsu_resp_0_bits_uop_fu_code_4), .io_lsu_resp_0_bits_uop_fu_code_5 (_dcache_io_lsu_resp_0_bits_uop_fu_code_5), .io_lsu_resp_0_bits_uop_fu_code_6 (_dcache_io_lsu_resp_0_bits_uop_fu_code_6), .io_lsu_resp_0_bits_uop_fu_code_7 (_dcache_io_lsu_resp_0_bits_uop_fu_code_7), .io_lsu_resp_0_bits_uop_fu_code_8 (_dcache_io_lsu_resp_0_bits_uop_fu_code_8), .io_lsu_resp_0_bits_uop_fu_code_9 (_dcache_io_lsu_resp_0_bits_uop_fu_code_9), .io_lsu_resp_0_bits_uop_iw_issued (_dcache_io_lsu_resp_0_bits_uop_iw_issued), .io_lsu_resp_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_agen), .io_lsu_resp_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_dgen), .io_lsu_resp_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p1_speculative_child), .io_lsu_resp_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p2_speculative_child), .io_lsu_resp_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p1_bypass_hint), .io_lsu_resp_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p2_bypass_hint), .io_lsu_resp_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p3_bypass_hint), .io_lsu_resp_0_bits_uop_dis_col_sel (_dcache_io_lsu_resp_0_bits_uop_dis_col_sel), .io_lsu_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), .io_lsu_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), .io_lsu_resp_0_bits_uop_br_type (_dcache_io_lsu_resp_0_bits_uop_br_type), .io_lsu_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), .io_lsu_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), .io_lsu_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), .io_lsu_resp_0_bits_uop_is_sfence (_dcache_io_lsu_resp_0_bits_uop_is_sfence), .io_lsu_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), .io_lsu_resp_0_bits_uop_is_eret (_dcache_io_lsu_resp_0_bits_uop_is_eret), .io_lsu_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), .io_lsu_resp_0_bits_uop_is_rocc (_dcache_io_lsu_resp_0_bits_uop_is_rocc), .io_lsu_resp_0_bits_uop_is_mov (_dcache_io_lsu_resp_0_bits_uop_is_mov), .io_lsu_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), .io_lsu_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), .io_lsu_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), .io_lsu_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), .io_lsu_resp_0_bits_uop_imm_rename (_dcache_io_lsu_resp_0_bits_uop_imm_rename), .io_lsu_resp_0_bits_uop_imm_sel (_dcache_io_lsu_resp_0_bits_uop_imm_sel), .io_lsu_resp_0_bits_uop_pimm (_dcache_io_lsu_resp_0_bits_uop_pimm), .io_lsu_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), .io_lsu_resp_0_bits_uop_op1_sel (_dcache_io_lsu_resp_0_bits_uop_op1_sel), .io_lsu_resp_0_bits_uop_op2_sel (_dcache_io_lsu_resp_0_bits_uop_op2_sel), .io_lsu_resp_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ldst), .io_lsu_resp_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wen), .io_lsu_resp_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren1), .io_lsu_resp_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren2), .io_lsu_resp_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren3), .io_lsu_resp_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap12), .io_lsu_resp_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap23), .io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_resp_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fromint), .io_lsu_resp_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_toint), .io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_resp_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fma), .io_lsu_resp_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_div), .io_lsu_resp_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_sqrt), .io_lsu_resp_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wflags), .io_lsu_resp_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_vec), .io_lsu_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), .io_lsu_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), .io_lsu_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), .io_lsu_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), .io_lsu_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), .io_lsu_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), .io_lsu_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), .io_lsu_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), .io_lsu_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), .io_lsu_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), .io_lsu_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), .io_lsu_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), .io_lsu_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), .io_lsu_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), .io_lsu_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), .io_lsu_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), .io_lsu_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), .io_lsu_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), .io_lsu_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), .io_lsu_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), .io_lsu_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), .io_lsu_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), .io_lsu_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), .io_lsu_resp_0_bits_uop_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_csr_cmd), .io_lsu_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), .io_lsu_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), .io_lsu_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), .io_lsu_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), .io_lsu_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), .io_lsu_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), .io_lsu_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), .io_lsu_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), .io_lsu_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), .io_lsu_resp_0_bits_uop_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_fcn_dw), .io_lsu_resp_0_bits_uop_fcn_op (_dcache_io_lsu_resp_0_bits_uop_fcn_op), .io_lsu_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), .io_lsu_resp_0_bits_uop_fp_rm (_dcache_io_lsu_resp_0_bits_uop_fp_rm), .io_lsu_resp_0_bits_uop_fp_typ (_dcache_io_lsu_resp_0_bits_uop_fp_typ), .io_lsu_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), .io_lsu_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), .io_lsu_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), .io_lsu_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), .io_lsu_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), .io_lsu_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), .io_lsu_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), .io_lsu_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), .io_lsu_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), .io_lsu_store_ack_0_valid (_dcache_io_lsu_store_ack_0_valid), .io_lsu_store_ack_0_bits_uop_inst (_dcache_io_lsu_store_ack_0_bits_uop_inst), .io_lsu_store_ack_0_bits_uop_debug_inst (_dcache_io_lsu_store_ack_0_bits_uop_debug_inst), .io_lsu_store_ack_0_bits_uop_is_rvc (_dcache_io_lsu_store_ack_0_bits_uop_is_rvc), .io_lsu_store_ack_0_bits_uop_debug_pc (_dcache_io_lsu_store_ack_0_bits_uop_debug_pc), .io_lsu_store_ack_0_bits_uop_iq_type_0 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_0), .io_lsu_store_ack_0_bits_uop_iq_type_1 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_1), .io_lsu_store_ack_0_bits_uop_iq_type_2 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_2), .io_lsu_store_ack_0_bits_uop_iq_type_3 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_3), .io_lsu_store_ack_0_bits_uop_fu_code_0 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_0), .io_lsu_store_ack_0_bits_uop_fu_code_1 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_1), .io_lsu_store_ack_0_bits_uop_fu_code_2 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_2), .io_lsu_store_ack_0_bits_uop_fu_code_3 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_3), .io_lsu_store_ack_0_bits_uop_fu_code_4 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_4), .io_lsu_store_ack_0_bits_uop_fu_code_5 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_5), .io_lsu_store_ack_0_bits_uop_fu_code_6 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_6), .io_lsu_store_ack_0_bits_uop_fu_code_7 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_7), .io_lsu_store_ack_0_bits_uop_fu_code_8 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_8), .io_lsu_store_ack_0_bits_uop_fu_code_9 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_9), .io_lsu_store_ack_0_bits_uop_iw_issued (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued), .io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen), .io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen), .io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child), .io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child), .io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint), .io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint), .io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint), .io_lsu_store_ack_0_bits_uop_dis_col_sel (_dcache_io_lsu_store_ack_0_bits_uop_dis_col_sel), .io_lsu_store_ack_0_bits_uop_br_mask (_dcache_io_lsu_store_ack_0_bits_uop_br_mask), .io_lsu_store_ack_0_bits_uop_br_tag (_dcache_io_lsu_store_ack_0_bits_uop_br_tag), .io_lsu_store_ack_0_bits_uop_br_type (_dcache_io_lsu_store_ack_0_bits_uop_br_type), .io_lsu_store_ack_0_bits_uop_is_sfb (_dcache_io_lsu_store_ack_0_bits_uop_is_sfb), .io_lsu_store_ack_0_bits_uop_is_fence (_dcache_io_lsu_store_ack_0_bits_uop_is_fence), .io_lsu_store_ack_0_bits_uop_is_fencei (_dcache_io_lsu_store_ack_0_bits_uop_is_fencei), .io_lsu_store_ack_0_bits_uop_is_sfence (_dcache_io_lsu_store_ack_0_bits_uop_is_sfence), .io_lsu_store_ack_0_bits_uop_is_amo (_dcache_io_lsu_store_ack_0_bits_uop_is_amo), .io_lsu_store_ack_0_bits_uop_is_eret (_dcache_io_lsu_store_ack_0_bits_uop_is_eret), .io_lsu_store_ack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_store_ack_0_bits_uop_is_sys_pc2epc), .io_lsu_store_ack_0_bits_uop_is_rocc (_dcache_io_lsu_store_ack_0_bits_uop_is_rocc), .io_lsu_store_ack_0_bits_uop_is_mov (_dcache_io_lsu_store_ack_0_bits_uop_is_mov), .io_lsu_store_ack_0_bits_uop_ftq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ftq_idx), .io_lsu_store_ack_0_bits_uop_edge_inst (_dcache_io_lsu_store_ack_0_bits_uop_edge_inst), .io_lsu_store_ack_0_bits_uop_pc_lob (_dcache_io_lsu_store_ack_0_bits_uop_pc_lob), .io_lsu_store_ack_0_bits_uop_taken (_dcache_io_lsu_store_ack_0_bits_uop_taken), .io_lsu_store_ack_0_bits_uop_imm_rename (_dcache_io_lsu_store_ack_0_bits_uop_imm_rename), .io_lsu_store_ack_0_bits_uop_imm_sel (_dcache_io_lsu_store_ack_0_bits_uop_imm_sel), .io_lsu_store_ack_0_bits_uop_pimm (_dcache_io_lsu_store_ack_0_bits_uop_pimm), .io_lsu_store_ack_0_bits_uop_imm_packed (_dcache_io_lsu_store_ack_0_bits_uop_imm_packed), .io_lsu_store_ack_0_bits_uop_op1_sel (_dcache_io_lsu_store_ack_0_bits_uop_op1_sel), .io_lsu_store_ack_0_bits_uop_op2_sel (_dcache_io_lsu_store_ack_0_bits_uop_op2_sel), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst), .io_lsu_store_ack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wen), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3), .io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12), .io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23), .io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint), .io_lsu_store_ack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_toint), .io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_store_ack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fma), .io_lsu_store_ack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_div), .io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt), .io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags), .io_lsu_store_ack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_vec), .io_lsu_store_ack_0_bits_uop_rob_idx (_dcache_io_lsu_store_ack_0_bits_uop_rob_idx), .io_lsu_store_ack_0_bits_uop_ldq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ldq_idx), .io_lsu_store_ack_0_bits_uop_stq_idx (_dcache_io_lsu_store_ack_0_bits_uop_stq_idx), .io_lsu_store_ack_0_bits_uop_rxq_idx (_dcache_io_lsu_store_ack_0_bits_uop_rxq_idx), .io_lsu_store_ack_0_bits_uop_pdst (_dcache_io_lsu_store_ack_0_bits_uop_pdst), .io_lsu_store_ack_0_bits_uop_prs1 (_dcache_io_lsu_store_ack_0_bits_uop_prs1), .io_lsu_store_ack_0_bits_uop_prs2 (_dcache_io_lsu_store_ack_0_bits_uop_prs2), .io_lsu_store_ack_0_bits_uop_prs3 (_dcache_io_lsu_store_ack_0_bits_uop_prs3), .io_lsu_store_ack_0_bits_uop_ppred (_dcache_io_lsu_store_ack_0_bits_uop_ppred), .io_lsu_store_ack_0_bits_uop_prs1_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs1_busy), .io_lsu_store_ack_0_bits_uop_prs2_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs2_busy), .io_lsu_store_ack_0_bits_uop_prs3_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs3_busy), .io_lsu_store_ack_0_bits_uop_ppred_busy (_dcache_io_lsu_store_ack_0_bits_uop_ppred_busy), .io_lsu_store_ack_0_bits_uop_stale_pdst (_dcache_io_lsu_store_ack_0_bits_uop_stale_pdst), .io_lsu_store_ack_0_bits_uop_exception (_dcache_io_lsu_store_ack_0_bits_uop_exception), .io_lsu_store_ack_0_bits_uop_exc_cause (_dcache_io_lsu_store_ack_0_bits_uop_exc_cause), .io_lsu_store_ack_0_bits_uop_mem_cmd (_dcache_io_lsu_store_ack_0_bits_uop_mem_cmd), .io_lsu_store_ack_0_bits_uop_mem_size (_dcache_io_lsu_store_ack_0_bits_uop_mem_size), .io_lsu_store_ack_0_bits_uop_mem_signed (_dcache_io_lsu_store_ack_0_bits_uop_mem_signed), .io_lsu_store_ack_0_bits_uop_uses_ldq (_dcache_io_lsu_store_ack_0_bits_uop_uses_ldq), .io_lsu_store_ack_0_bits_uop_uses_stq (_dcache_io_lsu_store_ack_0_bits_uop_uses_stq), .io_lsu_store_ack_0_bits_uop_is_unique (_dcache_io_lsu_store_ack_0_bits_uop_is_unique), .io_lsu_store_ack_0_bits_uop_flush_on_commit (_dcache_io_lsu_store_ack_0_bits_uop_flush_on_commit), .io_lsu_store_ack_0_bits_uop_csr_cmd (_dcache_io_lsu_store_ack_0_bits_uop_csr_cmd), .io_lsu_store_ack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_store_ack_0_bits_uop_ldst_is_rs1), .io_lsu_store_ack_0_bits_uop_ldst (_dcache_io_lsu_store_ack_0_bits_uop_ldst), .io_lsu_store_ack_0_bits_uop_lrs1 (_dcache_io_lsu_store_ack_0_bits_uop_lrs1), .io_lsu_store_ack_0_bits_uop_lrs2 (_dcache_io_lsu_store_ack_0_bits_uop_lrs2), .io_lsu_store_ack_0_bits_uop_lrs3 (_dcache_io_lsu_store_ack_0_bits_uop_lrs3), .io_lsu_store_ack_0_bits_uop_dst_rtype (_dcache_io_lsu_store_ack_0_bits_uop_dst_rtype), .io_lsu_store_ack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs1_rtype), .io_lsu_store_ack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs2_rtype), .io_lsu_store_ack_0_bits_uop_frs3_en (_dcache_io_lsu_store_ack_0_bits_uop_frs3_en), .io_lsu_store_ack_0_bits_uop_fcn_dw (_dcache_io_lsu_store_ack_0_bits_uop_fcn_dw), .io_lsu_store_ack_0_bits_uop_fcn_op (_dcache_io_lsu_store_ack_0_bits_uop_fcn_op), .io_lsu_store_ack_0_bits_uop_fp_val (_dcache_io_lsu_store_ack_0_bits_uop_fp_val), .io_lsu_store_ack_0_bits_uop_fp_rm (_dcache_io_lsu_store_ack_0_bits_uop_fp_rm), .io_lsu_store_ack_0_bits_uop_fp_typ (_dcache_io_lsu_store_ack_0_bits_uop_fp_typ), .io_lsu_store_ack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_pf_if), .io_lsu_store_ack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ae_if), .io_lsu_store_ack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ma_if), .io_lsu_store_ack_0_bits_uop_bp_debug_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_debug_if), .io_lsu_store_ack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_xcpt_if), .io_lsu_store_ack_0_bits_uop_debug_fsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_fsrc), .io_lsu_store_ack_0_bits_uop_debug_tsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_tsrc), .io_lsu_store_ack_0_bits_addr (_dcache_io_lsu_store_ack_0_bits_addr), .io_lsu_store_ack_0_bits_data (_dcache_io_lsu_store_ack_0_bits_data), .io_lsu_store_ack_0_bits_is_hella (_dcache_io_lsu_store_ack_0_bits_is_hella), .io_lsu_nack_0_valid (_dcache_io_lsu_nack_0_valid), .io_lsu_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), .io_lsu_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), .io_lsu_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), .io_lsu_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), .io_lsu_nack_0_bits_uop_iq_type_0 (_dcache_io_lsu_nack_0_bits_uop_iq_type_0), .io_lsu_nack_0_bits_uop_iq_type_1 (_dcache_io_lsu_nack_0_bits_uop_iq_type_1), .io_lsu_nack_0_bits_uop_iq_type_2 (_dcache_io_lsu_nack_0_bits_uop_iq_type_2), .io_lsu_nack_0_bits_uop_iq_type_3 (_dcache_io_lsu_nack_0_bits_uop_iq_type_3), .io_lsu_nack_0_bits_uop_fu_code_0 (_dcache_io_lsu_nack_0_bits_uop_fu_code_0), .io_lsu_nack_0_bits_uop_fu_code_1 (_dcache_io_lsu_nack_0_bits_uop_fu_code_1), .io_lsu_nack_0_bits_uop_fu_code_2 (_dcache_io_lsu_nack_0_bits_uop_fu_code_2), .io_lsu_nack_0_bits_uop_fu_code_3 (_dcache_io_lsu_nack_0_bits_uop_fu_code_3), .io_lsu_nack_0_bits_uop_fu_code_4 (_dcache_io_lsu_nack_0_bits_uop_fu_code_4), .io_lsu_nack_0_bits_uop_fu_code_5 (_dcache_io_lsu_nack_0_bits_uop_fu_code_5), .io_lsu_nack_0_bits_uop_fu_code_6 (_dcache_io_lsu_nack_0_bits_uop_fu_code_6), .io_lsu_nack_0_bits_uop_fu_code_7 (_dcache_io_lsu_nack_0_bits_uop_fu_code_7), .io_lsu_nack_0_bits_uop_fu_code_8 (_dcache_io_lsu_nack_0_bits_uop_fu_code_8), .io_lsu_nack_0_bits_uop_fu_code_9 (_dcache_io_lsu_nack_0_bits_uop_fu_code_9), .io_lsu_nack_0_bits_uop_iw_issued (_dcache_io_lsu_nack_0_bits_uop_iw_issued), .io_lsu_nack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_agen), .io_lsu_nack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_dgen), .io_lsu_nack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p1_speculative_child), .io_lsu_nack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p2_speculative_child), .io_lsu_nack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p1_bypass_hint), .io_lsu_nack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p2_bypass_hint), .io_lsu_nack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p3_bypass_hint), .io_lsu_nack_0_bits_uop_dis_col_sel (_dcache_io_lsu_nack_0_bits_uop_dis_col_sel), .io_lsu_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), .io_lsu_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), .io_lsu_nack_0_bits_uop_br_type (_dcache_io_lsu_nack_0_bits_uop_br_type), .io_lsu_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), .io_lsu_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), .io_lsu_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), .io_lsu_nack_0_bits_uop_is_sfence (_dcache_io_lsu_nack_0_bits_uop_is_sfence), .io_lsu_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), .io_lsu_nack_0_bits_uop_is_eret (_dcache_io_lsu_nack_0_bits_uop_is_eret), .io_lsu_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), .io_lsu_nack_0_bits_uop_is_rocc (_dcache_io_lsu_nack_0_bits_uop_is_rocc), .io_lsu_nack_0_bits_uop_is_mov (_dcache_io_lsu_nack_0_bits_uop_is_mov), .io_lsu_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), .io_lsu_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), .io_lsu_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), .io_lsu_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), .io_lsu_nack_0_bits_uop_imm_rename (_dcache_io_lsu_nack_0_bits_uop_imm_rename), .io_lsu_nack_0_bits_uop_imm_sel (_dcache_io_lsu_nack_0_bits_uop_imm_sel), .io_lsu_nack_0_bits_uop_pimm (_dcache_io_lsu_nack_0_bits_uop_pimm), .io_lsu_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), .io_lsu_nack_0_bits_uop_op1_sel (_dcache_io_lsu_nack_0_bits_uop_op1_sel), .io_lsu_nack_0_bits_uop_op2_sel (_dcache_io_lsu_nack_0_bits_uop_op2_sel), .io_lsu_nack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ldst), .io_lsu_nack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wen), .io_lsu_nack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren1), .io_lsu_nack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren2), .io_lsu_nack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren3), .io_lsu_nack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap12), .io_lsu_nack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap23), .io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_nack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fromint), .io_lsu_nack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_toint), .io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_nack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fma), .io_lsu_nack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_div), .io_lsu_nack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_sqrt), .io_lsu_nack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wflags), .io_lsu_nack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_vec), .io_lsu_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), .io_lsu_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), .io_lsu_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), .io_lsu_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), .io_lsu_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), .io_lsu_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), .io_lsu_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), .io_lsu_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), .io_lsu_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), .io_lsu_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), .io_lsu_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), .io_lsu_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), .io_lsu_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), .io_lsu_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), .io_lsu_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), .io_lsu_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), .io_lsu_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), .io_lsu_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), .io_lsu_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), .io_lsu_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), .io_lsu_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), .io_lsu_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), .io_lsu_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), .io_lsu_nack_0_bits_uop_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_csr_cmd), .io_lsu_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), .io_lsu_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), .io_lsu_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), .io_lsu_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), .io_lsu_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), .io_lsu_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), .io_lsu_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), .io_lsu_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), .io_lsu_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), .io_lsu_nack_0_bits_uop_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_fcn_dw), .io_lsu_nack_0_bits_uop_fcn_op (_dcache_io_lsu_nack_0_bits_uop_fcn_op), .io_lsu_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), .io_lsu_nack_0_bits_uop_fp_rm (_dcache_io_lsu_nack_0_bits_uop_fp_rm), .io_lsu_nack_0_bits_uop_fp_typ (_dcache_io_lsu_nack_0_bits_uop_fp_typ), .io_lsu_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), .io_lsu_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), .io_lsu_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), .io_lsu_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), .io_lsu_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), .io_lsu_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), .io_lsu_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), .io_lsu_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), .io_lsu_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), .io_lsu_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), .io_lsu_ll_resp_ready (_lsu_io_dmem_ll_resp_ready), // @[tile.scala:159:20] .io_lsu_ll_resp_valid (_dcache_io_lsu_ll_resp_valid), .io_lsu_ll_resp_bits_uop_inst (_dcache_io_lsu_ll_resp_bits_uop_inst), .io_lsu_ll_resp_bits_uop_debug_inst (_dcache_io_lsu_ll_resp_bits_uop_debug_inst), .io_lsu_ll_resp_bits_uop_is_rvc (_dcache_io_lsu_ll_resp_bits_uop_is_rvc), .io_lsu_ll_resp_bits_uop_debug_pc (_dcache_io_lsu_ll_resp_bits_uop_debug_pc), .io_lsu_ll_resp_bits_uop_iq_type_0 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_0), .io_lsu_ll_resp_bits_uop_iq_type_1 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_1), .io_lsu_ll_resp_bits_uop_iq_type_2 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_2), .io_lsu_ll_resp_bits_uop_iq_type_3 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_3), .io_lsu_ll_resp_bits_uop_fu_code_0 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_0), .io_lsu_ll_resp_bits_uop_fu_code_1 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_1), .io_lsu_ll_resp_bits_uop_fu_code_2 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_2), .io_lsu_ll_resp_bits_uop_fu_code_3 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_3), .io_lsu_ll_resp_bits_uop_fu_code_4 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_4), .io_lsu_ll_resp_bits_uop_fu_code_5 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_5), .io_lsu_ll_resp_bits_uop_fu_code_6 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_6), .io_lsu_ll_resp_bits_uop_fu_code_7 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_7), .io_lsu_ll_resp_bits_uop_fu_code_8 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_8), .io_lsu_ll_resp_bits_uop_fu_code_9 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_9), .io_lsu_ll_resp_bits_uop_iw_issued (_dcache_io_lsu_ll_resp_bits_uop_iw_issued), .io_lsu_ll_resp_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_agen), .io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen), .io_lsu_ll_resp_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_speculative_child), .io_lsu_ll_resp_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_speculative_child), .io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint), .io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint), .io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint), .io_lsu_ll_resp_bits_uop_dis_col_sel (_dcache_io_lsu_ll_resp_bits_uop_dis_col_sel), .io_lsu_ll_resp_bits_uop_br_mask (_dcache_io_lsu_ll_resp_bits_uop_br_mask), .io_lsu_ll_resp_bits_uop_br_tag (_dcache_io_lsu_ll_resp_bits_uop_br_tag), .io_lsu_ll_resp_bits_uop_br_type (_dcache_io_lsu_ll_resp_bits_uop_br_type), .io_lsu_ll_resp_bits_uop_is_sfb (_dcache_io_lsu_ll_resp_bits_uop_is_sfb), .io_lsu_ll_resp_bits_uop_is_fence (_dcache_io_lsu_ll_resp_bits_uop_is_fence), .io_lsu_ll_resp_bits_uop_is_fencei (_dcache_io_lsu_ll_resp_bits_uop_is_fencei), .io_lsu_ll_resp_bits_uop_is_sfence (_dcache_io_lsu_ll_resp_bits_uop_is_sfence), .io_lsu_ll_resp_bits_uop_is_amo (_dcache_io_lsu_ll_resp_bits_uop_is_amo), .io_lsu_ll_resp_bits_uop_is_eret (_dcache_io_lsu_ll_resp_bits_uop_is_eret), .io_lsu_ll_resp_bits_uop_is_sys_pc2epc (_dcache_io_lsu_ll_resp_bits_uop_is_sys_pc2epc), .io_lsu_ll_resp_bits_uop_is_rocc (_dcache_io_lsu_ll_resp_bits_uop_is_rocc), .io_lsu_ll_resp_bits_uop_is_mov (_dcache_io_lsu_ll_resp_bits_uop_is_mov), .io_lsu_ll_resp_bits_uop_ftq_idx (_dcache_io_lsu_ll_resp_bits_uop_ftq_idx), .io_lsu_ll_resp_bits_uop_edge_inst (_dcache_io_lsu_ll_resp_bits_uop_edge_inst), .io_lsu_ll_resp_bits_uop_pc_lob (_dcache_io_lsu_ll_resp_bits_uop_pc_lob), .io_lsu_ll_resp_bits_uop_taken (_dcache_io_lsu_ll_resp_bits_uop_taken), .io_lsu_ll_resp_bits_uop_imm_rename (_dcache_io_lsu_ll_resp_bits_uop_imm_rename), .io_lsu_ll_resp_bits_uop_imm_sel (_dcache_io_lsu_ll_resp_bits_uop_imm_sel), .io_lsu_ll_resp_bits_uop_pimm (_dcache_io_lsu_ll_resp_bits_uop_pimm), .io_lsu_ll_resp_bits_uop_imm_packed (_dcache_io_lsu_ll_resp_bits_uop_imm_packed), .io_lsu_ll_resp_bits_uop_op1_sel (_dcache_io_lsu_ll_resp_bits_uop_op1_sel), .io_lsu_ll_resp_bits_uop_op2_sel (_dcache_io_lsu_ll_resp_bits_uop_op2_sel), .io_lsu_ll_resp_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ldst), .io_lsu_ll_resp_bits_uop_fp_ctrl_wen (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wen), .io_lsu_ll_resp_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren1), .io_lsu_ll_resp_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren2), .io_lsu_ll_resp_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren3), .io_lsu_ll_resp_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap12), .io_lsu_ll_resp_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap23), .io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn), .io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut), .io_lsu_ll_resp_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fromint), .io_lsu_ll_resp_bits_uop_fp_ctrl_toint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_toint), .io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe), .io_lsu_ll_resp_bits_uop_fp_ctrl_fma (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fma), .io_lsu_ll_resp_bits_uop_fp_ctrl_div (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_div), .io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt), .io_lsu_ll_resp_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wflags), .io_lsu_ll_resp_bits_uop_fp_ctrl_vec (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_vec), .io_lsu_ll_resp_bits_uop_rob_idx (_dcache_io_lsu_ll_resp_bits_uop_rob_idx), .io_lsu_ll_resp_bits_uop_ldq_idx (_dcache_io_lsu_ll_resp_bits_uop_ldq_idx), .io_lsu_ll_resp_bits_uop_stq_idx (_dcache_io_lsu_ll_resp_bits_uop_stq_idx), .io_lsu_ll_resp_bits_uop_rxq_idx (_dcache_io_lsu_ll_resp_bits_uop_rxq_idx), .io_lsu_ll_resp_bits_uop_pdst (_dcache_io_lsu_ll_resp_bits_uop_pdst), .io_lsu_ll_resp_bits_uop_prs1 (_dcache_io_lsu_ll_resp_bits_uop_prs1), .io_lsu_ll_resp_bits_uop_prs2 (_dcache_io_lsu_ll_resp_bits_uop_prs2), .io_lsu_ll_resp_bits_uop_prs3 (_dcache_io_lsu_ll_resp_bits_uop_prs3), .io_lsu_ll_resp_bits_uop_ppred (_dcache_io_lsu_ll_resp_bits_uop_ppred), .io_lsu_ll_resp_bits_uop_prs1_busy (_dcache_io_lsu_ll_resp_bits_uop_prs1_busy), .io_lsu_ll_resp_bits_uop_prs2_busy (_dcache_io_lsu_ll_resp_bits_uop_prs2_busy), .io_lsu_ll_resp_bits_uop_prs3_busy (_dcache_io_lsu_ll_resp_bits_uop_prs3_busy), .io_lsu_ll_resp_bits_uop_ppred_busy (_dcache_io_lsu_ll_resp_bits_uop_ppred_busy), .io_lsu_ll_resp_bits_uop_stale_pdst (_dcache_io_lsu_ll_resp_bits_uop_stale_pdst), .io_lsu_ll_resp_bits_uop_exception (_dcache_io_lsu_ll_resp_bits_uop_exception), .io_lsu_ll_resp_bits_uop_exc_cause (_dcache_io_lsu_ll_resp_bits_uop_exc_cause), .io_lsu_ll_resp_bits_uop_mem_cmd (_dcache_io_lsu_ll_resp_bits_uop_mem_cmd), .io_lsu_ll_resp_bits_uop_mem_size (_dcache_io_lsu_ll_resp_bits_uop_mem_size), .io_lsu_ll_resp_bits_uop_mem_signed (_dcache_io_lsu_ll_resp_bits_uop_mem_signed), .io_lsu_ll_resp_bits_uop_uses_ldq (_dcache_io_lsu_ll_resp_bits_uop_uses_ldq), .io_lsu_ll_resp_bits_uop_uses_stq (_dcache_io_lsu_ll_resp_bits_uop_uses_stq), .io_lsu_ll_resp_bits_uop_is_unique (_dcache_io_lsu_ll_resp_bits_uop_is_unique), .io_lsu_ll_resp_bits_uop_flush_on_commit (_dcache_io_lsu_ll_resp_bits_uop_flush_on_commit), .io_lsu_ll_resp_bits_uop_csr_cmd (_dcache_io_lsu_ll_resp_bits_uop_csr_cmd), .io_lsu_ll_resp_bits_uop_ldst_is_rs1 (_dcache_io_lsu_ll_resp_bits_uop_ldst_is_rs1), .io_lsu_ll_resp_bits_uop_ldst (_dcache_io_lsu_ll_resp_bits_uop_ldst), .io_lsu_ll_resp_bits_uop_lrs1 (_dcache_io_lsu_ll_resp_bits_uop_lrs1), .io_lsu_ll_resp_bits_uop_lrs2 (_dcache_io_lsu_ll_resp_bits_uop_lrs2), .io_lsu_ll_resp_bits_uop_lrs3 (_dcache_io_lsu_ll_resp_bits_uop_lrs3), .io_lsu_ll_resp_bits_uop_dst_rtype (_dcache_io_lsu_ll_resp_bits_uop_dst_rtype), .io_lsu_ll_resp_bits_uop_lrs1_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs1_rtype), .io_lsu_ll_resp_bits_uop_lrs2_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs2_rtype), .io_lsu_ll_resp_bits_uop_frs3_en (_dcache_io_lsu_ll_resp_bits_uop_frs3_en), .io_lsu_ll_resp_bits_uop_fcn_dw (_dcache_io_lsu_ll_resp_bits_uop_fcn_dw), .io_lsu_ll_resp_bits_uop_fcn_op (_dcache_io_lsu_ll_resp_bits_uop_fcn_op), .io_lsu_ll_resp_bits_uop_fp_val (_dcache_io_lsu_ll_resp_bits_uop_fp_val), .io_lsu_ll_resp_bits_uop_fp_rm (_dcache_io_lsu_ll_resp_bits_uop_fp_rm), .io_lsu_ll_resp_bits_uop_fp_typ (_dcache_io_lsu_ll_resp_bits_uop_fp_typ), .io_lsu_ll_resp_bits_uop_xcpt_pf_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_pf_if), .io_lsu_ll_resp_bits_uop_xcpt_ae_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ae_if), .io_lsu_ll_resp_bits_uop_xcpt_ma_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ma_if), .io_lsu_ll_resp_bits_uop_bp_debug_if (_dcache_io_lsu_ll_resp_bits_uop_bp_debug_if), .io_lsu_ll_resp_bits_uop_bp_xcpt_if (_dcache_io_lsu_ll_resp_bits_uop_bp_xcpt_if), .io_lsu_ll_resp_bits_uop_debug_fsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_fsrc), .io_lsu_ll_resp_bits_uop_debug_tsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_tsrc), .io_lsu_ll_resp_bits_data (_dcache_io_lsu_ll_resp_bits_data), .io_lsu_ll_resp_bits_is_hella (_dcache_io_lsu_ll_resp_bits_is_hella), .io_lsu_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), // @[tile.scala:159:20] .io_lsu_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_0 (_lsu_io_dmem_brupdate_b2_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_1 (_lsu_io_dmem_brupdate_b2_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_2 (_lsu_io_dmem_brupdate_b2_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_3 (_lsu_io_dmem_brupdate_b2_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_0 (_lsu_io_dmem_brupdate_b2_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_1 (_lsu_io_dmem_brupdate_b2_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_2 (_lsu_io_dmem_brupdate_b2_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_3 (_lsu_io_dmem_brupdate_b2_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_4 (_lsu_io_dmem_brupdate_b2_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_5 (_lsu_io_dmem_brupdate_b2_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_6 (_lsu_io_dmem_brupdate_b2_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_7 (_lsu_io_dmem_brupdate_b2_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_8 (_lsu_io_dmem_brupdate_b2_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_9 (_lsu_io_dmem_brupdate_b2_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_issued (_lsu_io_dmem_brupdate_b2_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_issued_partial_agen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_issued_partial_dgen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p1_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p2_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p1_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p2_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p3_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_dis_col_sel (_lsu_io_dmem_brupdate_b2_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_br_type (_lsu_io_dmem_brupdate_b2_uop_br_type), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_sfence (_lsu_io_dmem_brupdate_b2_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_eret (_lsu_io_dmem_brupdate_b2_uop_is_eret), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_rocc (_lsu_io_dmem_brupdate_b2_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_mov (_lsu_io_dmem_brupdate_b2_uop_is_mov), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_imm_rename (_lsu_io_dmem_brupdate_b2_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_imm_sel (_lsu_io_dmem_brupdate_b2_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_pimm (_lsu_io_dmem_brupdate_b2_uop_pimm), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_op1_sel (_lsu_io_dmem_brupdate_b2_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_op2_sel (_lsu_io_dmem_brupdate_b2_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ldst (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_wen (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ren1 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ren2 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ren3 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_swap12 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_swap23 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_fromint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_toint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_fma (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_div (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_sqrt (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_wflags (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_vec (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fcn_op (_lsu_io_dmem_brupdate_b2_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_rm (_lsu_io_dmem_brupdate_b2_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_typ (_lsu_io_dmem_brupdate_b2_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), // @[tile.scala:159:20] .io_lsu_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), // @[tile.scala:159:20] .io_lsu_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), // @[tile.scala:159:20] .io_lsu_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), // @[tile.scala:159:20] .io_lsu_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), // @[tile.scala:159:20] .io_lsu_exception (_lsu_io_dmem_exception), // @[tile.scala:159:20] .io_lsu_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), // @[tile.scala:159:20] .io_lsu_rob_head_idx (_lsu_io_dmem_rob_head_idx), // @[tile.scala:159:20] .io_lsu_release_ready (_lsu_io_dmem_release_ready), // @[tile.scala:159:20] .io_lsu_release_valid (_dcache_io_lsu_release_valid), .io_lsu_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), .io_lsu_release_bits_param (_dcache_io_lsu_release_bits_param), .io_lsu_release_bits_size (_dcache_io_lsu_release_bits_size), .io_lsu_release_bits_source (_dcache_io_lsu_release_bits_source), .io_lsu_release_bits_address (_dcache_io_lsu_release_bits_address), .io_lsu_release_bits_data (_dcache_io_lsu_release_bits_data), .io_lsu_force_order (_lsu_io_dmem_force_order), // @[tile.scala:159:20] .io_lsu_ordered (_dcache_io_lsu_ordered), .io_lsu_perf_acquire (_dcache_io_lsu_perf_acquire), .io_lsu_perf_release (_dcache_io_lsu_perf_release) ); // @[tile.scala:132:54] BoomFrontend frontend ( // @[tile.scala:137:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_source (widget_1_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), // @[tile.scala:158:20] .io_cpu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), .io_cpu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), .io_cpu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), .io_cpu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), .io_cpu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), .io_cpu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), .io_cpu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), .io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), .io_cpu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), .io_cpu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), .io_cpu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), .io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), .io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), .io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), .io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), .io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), .io_cpu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), .io_cpu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), .io_cpu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), .io_cpu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), .io_cpu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), .io_cpu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), .io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), .io_cpu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), .io_cpu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), .io_cpu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), .io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), .io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), .io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), .io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), .io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), .io_cpu_arb_ftq_reqs_0 (_core_io_ifu_arb_ftq_reqs_0), // @[tile.scala:158:20] .io_cpu_arb_ftq_reqs_1 (_core_io_ifu_arb_ftq_reqs_1), // @[tile.scala:158:20] .io_cpu_arb_ftq_reqs_2 (_core_io_ifu_arb_ftq_reqs_2), // @[tile.scala:158:20] .io_cpu_rrd_ftq_resps_0_valid (_frontend_io_cpu_rrd_ftq_resps_0_valid), .io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid), .io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits), .io_cpu_rrd_ftq_resps_0_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_taken), .io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted), .io_cpu_rrd_ftq_resps_0_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_type), .io_cpu_rrd_ftq_resps_0_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_0_entry_br_mask), .io_cpu_rrd_ftq_resps_0_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_call), .io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret), .io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4), .io_cpu_rrd_ftq_resps_0_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_top), .io_cpu_rrd_ftq_resps_0_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_idx), .io_cpu_rrd_ftq_resps_0_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_0_entry_start_bank), .io_cpu_rrd_ftq_resps_0_ghist_old_history (_frontend_io_cpu_rrd_ftq_resps_0_ghist_old_history), .io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken), .io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken), .io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken), .io_cpu_rrd_ftq_resps_0_ghist_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_ghist_ras_idx), .io_cpu_rrd_ftq_resps_0_pc (_frontend_io_cpu_rrd_ftq_resps_0_pc), .io_cpu_rrd_ftq_resps_1_valid (_frontend_io_cpu_rrd_ftq_resps_1_valid), .io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid), .io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits), .io_cpu_rrd_ftq_resps_1_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_taken), .io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted), .io_cpu_rrd_ftq_resps_1_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_type), .io_cpu_rrd_ftq_resps_1_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_1_entry_br_mask), .io_cpu_rrd_ftq_resps_1_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_call), .io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret), .io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4), .io_cpu_rrd_ftq_resps_1_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_top), .io_cpu_rrd_ftq_resps_1_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_idx), .io_cpu_rrd_ftq_resps_1_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_1_entry_start_bank), .io_cpu_rrd_ftq_resps_1_pc (_frontend_io_cpu_rrd_ftq_resps_1_pc), .io_cpu_rrd_ftq_resps_2_valid (_frontend_io_cpu_rrd_ftq_resps_2_valid), .io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid), .io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits), .io_cpu_rrd_ftq_resps_2_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_taken), .io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted), .io_cpu_rrd_ftq_resps_2_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_type), .io_cpu_rrd_ftq_resps_2_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_2_entry_br_mask), .io_cpu_rrd_ftq_resps_2_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_call), .io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret), .io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4), .io_cpu_rrd_ftq_resps_2_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_top), .io_cpu_rrd_ftq_resps_2_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_idx), .io_cpu_rrd_ftq_resps_2_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_2_entry_start_bank), .io_cpu_rrd_ftq_resps_2_pc (_frontend_io_cpu_rrd_ftq_resps_2_pc), .io_cpu_com_pc (_frontend_io_cpu_com_pc), .io_cpu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), .io_cpu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), .io_cpu_status_debug (_core_io_ifu_status_debug), // @[tile.scala:158:20] .io_cpu_status_cease (_core_io_ifu_status_cease), // @[tile.scala:158:20] .io_cpu_status_wfi (_core_io_ifu_status_wfi), // @[tile.scala:158:20] .io_cpu_status_dprv (_core_io_ifu_status_dprv), // @[tile.scala:158:20] .io_cpu_status_dv (_core_io_ifu_status_dv), // @[tile.scala:158:20] .io_cpu_status_prv (_core_io_ifu_status_prv), // @[tile.scala:158:20] .io_cpu_status_v (_core_io_ifu_status_v), // @[tile.scala:158:20] .io_cpu_status_sd (_core_io_ifu_status_sd), // @[tile.scala:158:20] .io_cpu_status_mpv (_core_io_ifu_status_mpv), // @[tile.scala:158:20] .io_cpu_status_gva (_core_io_ifu_status_gva), // @[tile.scala:158:20] .io_cpu_status_tsr (_core_io_ifu_status_tsr), // @[tile.scala:158:20] .io_cpu_status_tw (_core_io_ifu_status_tw), // @[tile.scala:158:20] .io_cpu_status_tvm (_core_io_ifu_status_tvm), // @[tile.scala:158:20] .io_cpu_status_mxr (_core_io_ifu_status_mxr), // @[tile.scala:158:20] .io_cpu_status_sum (_core_io_ifu_status_sum), // @[tile.scala:158:20] .io_cpu_status_mprv (_core_io_ifu_status_mprv), // @[tile.scala:158:20] .io_cpu_status_fs (_core_io_ifu_status_fs), // @[tile.scala:158:20] .io_cpu_status_mpp (_core_io_ifu_status_mpp), // @[tile.scala:158:20] .io_cpu_status_spp (_core_io_ifu_status_spp), // @[tile.scala:158:20] .io_cpu_status_mpie (_core_io_ifu_status_mpie), // @[tile.scala:158:20] .io_cpu_status_spie (_core_io_ifu_status_spie), // @[tile.scala:158:20] .io_cpu_status_mie (_core_io_ifu_status_mie), // @[tile.scala:158:20] .io_cpu_status_sie (_core_io_ifu_status_sie), // @[tile.scala:158:20] .io_cpu_sfence_valid (_core_io_ifu_sfence_valid), // @[tile.scala:158:20] .io_cpu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), // @[tile.scala:158:20] .io_cpu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), // @[tile.scala:158:20] .io_cpu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), // @[tile.scala:158:20] .io_cpu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), // @[tile.scala:158:20] .io_cpu_sfence_bits_hv (_core_io_ifu_sfence_bits_hv), // @[tile.scala:158:20] .io_cpu_sfence_bits_hg (_core_io_ifu_sfence_bits_hg), // @[tile.scala:158:20] .io_cpu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), // @[tile.scala:158:20] .io_cpu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_0 (_core_io_ifu_brupdate_b2_uop_iq_type_0), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_1 (_core_io_ifu_brupdate_b2_uop_iq_type_1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_2 (_core_io_ifu_brupdate_b2_uop_iq_type_2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_3 (_core_io_ifu_brupdate_b2_uop_iq_type_3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_0 (_core_io_ifu_brupdate_b2_uop_fu_code_0), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_1 (_core_io_ifu_brupdate_b2_uop_fu_code_1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_2 (_core_io_ifu_brupdate_b2_uop_fu_code_2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_3 (_core_io_ifu_brupdate_b2_uop_fu_code_3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_4 (_core_io_ifu_brupdate_b2_uop_fu_code_4), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_5 (_core_io_ifu_brupdate_b2_uop_fu_code_5), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_6 (_core_io_ifu_brupdate_b2_uop_fu_code_6), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_7 (_core_io_ifu_brupdate_b2_uop_fu_code_7), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_8 (_core_io_ifu_brupdate_b2_uop_fu_code_8), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_9 (_core_io_ifu_brupdate_b2_uop_fu_code_9), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_issued (_core_io_ifu_brupdate_b2_uop_iw_issued), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_issued_partial_agen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p1_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p2_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_dis_col_sel (_core_io_ifu_brupdate_b2_uop_dis_col_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_br_type (_core_io_ifu_brupdate_b2_uop_br_type), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_sfence (_core_io_ifu_brupdate_b2_uop_is_sfence), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_eret (_core_io_ifu_brupdate_b2_uop_is_eret), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_rocc (_core_io_ifu_brupdate_b2_uop_is_rocc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_mov (_core_io_ifu_brupdate_b2_uop_is_mov), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_imm_rename (_core_io_ifu_brupdate_b2_uop_imm_rename), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_imm_sel (_core_io_ifu_brupdate_b2_uop_imm_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_pimm (_core_io_ifu_brupdate_b2_uop_pimm), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_op1_sel (_core_io_ifu_brupdate_b2_uop_op1_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_op2_sel (_core_io_ifu_brupdate_b2_uop_op2_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ldst (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_wen (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_fromint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_toint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_fma (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_div (_core_io_ifu_brupdate_b2_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_ifu_brupdate_b2_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_wflags (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_vec (_core_io_ifu_brupdate_b2_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_csr_cmd (_core_io_ifu_brupdate_b2_uop_csr_cmd), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fcn_dw (_core_io_ifu_brupdate_b2_uop_fcn_dw), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fcn_op (_core_io_ifu_brupdate_b2_uop_fcn_op), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_rm (_core_io_ifu_brupdate_b2_uop_fp_rm), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_typ (_core_io_ifu_brupdate_b2_uop_fp_typ), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), // @[tile.scala:158:20] .io_cpu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), // @[tile.scala:158:20] .io_cpu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), // @[tile.scala:158:20] .io_cpu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), // @[tile.scala:158:20] .io_cpu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), // @[tile.scala:158:20] .io_cpu_redirect_flush (_core_io_ifu_redirect_flush), // @[tile.scala:158:20] .io_cpu_redirect_val (_core_io_ifu_redirect_val), // @[tile.scala:158:20] .io_cpu_redirect_pc (_core_io_ifu_redirect_pc), // @[tile.scala:158:20] .io_cpu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), // @[tile.scala:158:20] .io_cpu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), // @[tile.scala:158:20] .io_cpu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), // @[tile.scala:158:20] .io_cpu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), // @[tile.scala:158:20] .io_cpu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), // @[tile.scala:158:20] .io_cpu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), // @[tile.scala:158:20] .io_cpu_commit_valid (_core_io_ifu_commit_valid), // @[tile.scala:158:20] .io_cpu_commit_bits (_core_io_ifu_commit_bits), // @[tile.scala:158:20] .io_cpu_flush_icache (_core_io_ifu_flush_icache), // @[tile.scala:158:20] .io_cpu_enable_bpd (_core_io_ifu_enable_bpd), // @[tile.scala:158:20] .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[tile.scala:236:20] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[tile.scala:236:20] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[tile.scala:236:20] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[tile.scala:236:20] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[tile.scala:236:20] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[tile.scala:236:20] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[tile.scala:236:20] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[tile.scala:236:20] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[tile.scala:236:20] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[tile.scala:236:20] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[tile.scala:236:20] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[tile.scala:236:20] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[tile.scala:236:20] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[tile.scala:236:20] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[tile.scala:236:20] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[tile.scala:236:20] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[tile.scala:236:20] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[tile.scala:236:20] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[tile.scala:236:20] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[tile.scala:236:20] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[tile.scala:236:20] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[tile.scala:236:20] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[tile.scala:236:20] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[tile.scala:236:20] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[tile.scala:236:20] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[tile.scala:236:20] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[tile.scala:236:20] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[tile.scala:236:20] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[tile.scala:236:20] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[tile.scala:236:20] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[tile.scala:236:20] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[tile.scala:236:20] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[tile.scala:236:20] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[tile.scala:236:20] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[tile.scala:236:20] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[tile.scala:236:20] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[tile.scala:236:20] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[tile.scala:236:20] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[tile.scala:236:20] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[tile.scala:236:20] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[tile.scala:236:20] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask) // @[tile.scala:236:20] ); // @[tile.scala:137:28] TLBuffer_a32d64s1k3z4u buffer_2 ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (widget_1_auto_anon_out_a_ready), .auto_in_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_in_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_in_d_valid (widget_1_auto_anon_out_d_valid), .auto_in_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_in_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_in_d_bits_source (widget_1_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_tlMasterXbar_auto_anon_in_1_a_ready), // @[HierarchicalElement.scala:55:42] .auto_out_a_valid (_buffer_2_auto_out_a_valid), .auto_out_a_bits_opcode (_buffer_2_auto_out_a_bits_opcode), .auto_out_a_bits_param (_buffer_2_auto_out_a_bits_param), .auto_out_a_bits_size (_buffer_2_auto_out_a_bits_size), .auto_out_a_bits_source (_buffer_2_auto_out_a_bits_source), .auto_out_a_bits_address (_buffer_2_auto_out_a_bits_address), .auto_out_a_bits_mask (_buffer_2_auto_out_a_bits_mask), .auto_out_a_bits_data (_buffer_2_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_buffer_2_auto_out_a_bits_corrupt), .auto_out_d_ready (_buffer_2_auto_out_d_ready), .auto_out_d_valid (_tlMasterXbar_auto_anon_in_1_d_valid), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_opcode (_tlMasterXbar_auto_anon_in_1_d_bits_opcode), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_param (_tlMasterXbar_auto_anon_in_1_d_bits_param), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_size (_tlMasterXbar_auto_anon_in_1_d_bits_size), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_sink (_tlMasterXbar_auto_anon_in_1_d_bits_sink), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_denied (_tlMasterXbar_auto_anon_in_1_d_bits_denied), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_data (_tlMasterXbar_auto_anon_in_1_d_bits_data), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_corrupt (_tlMasterXbar_auto_anon_in_1_d_bits_corrupt) // @[HierarchicalElement.scala:55:42] ); // @[Buffer.scala:75:28] BoomCore core ( // @[tile.scala:158:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_ifu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), .io_ifu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), // @[tile.scala:137:28] .io_ifu_arb_ftq_reqs_0 (_core_io_ifu_arb_ftq_reqs_0), .io_ifu_arb_ftq_reqs_1 (_core_io_ifu_arb_ftq_reqs_1), .io_ifu_arb_ftq_reqs_2 (_core_io_ifu_arb_ftq_reqs_2), .io_ifu_rrd_ftq_resps_0_valid (_frontend_io_cpu_rrd_ftq_resps_0_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_type), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_0_entry_br_mask), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_call), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_top), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_0_entry_start_bank), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_old_history (_frontend_io_cpu_rrd_ftq_resps_0_ghist_old_history), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_ghist_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_pc (_frontend_io_cpu_rrd_ftq_resps_0_pc), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_valid (_frontend_io_cpu_rrd_ftq_resps_1_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_type), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_1_entry_br_mask), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_call), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_top), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_1_entry_start_bank), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_pc (_frontend_io_cpu_rrd_ftq_resps_1_pc), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_valid (_frontend_io_cpu_rrd_ftq_resps_2_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_type), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_2_entry_br_mask), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_call), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_top), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_2_entry_start_bank), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_pc (_frontend_io_cpu_rrd_ftq_resps_2_pc), // @[tile.scala:137:28] .io_ifu_com_pc (_frontend_io_cpu_com_pc), // @[tile.scala:137:28] .io_ifu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), // @[tile.scala:137:28] .io_ifu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), // @[tile.scala:137:28] .io_ifu_status_debug (_core_io_ifu_status_debug), .io_ifu_status_cease (_core_io_ifu_status_cease), .io_ifu_status_wfi (_core_io_ifu_status_wfi), .io_ifu_status_dprv (_core_io_ifu_status_dprv), .io_ifu_status_dv (_core_io_ifu_status_dv), .io_ifu_status_prv (_core_io_ifu_status_prv), .io_ifu_status_v (_core_io_ifu_status_v), .io_ifu_status_sd (_core_io_ifu_status_sd), .io_ifu_status_mpv (_core_io_ifu_status_mpv), .io_ifu_status_gva (_core_io_ifu_status_gva), .io_ifu_status_tsr (_core_io_ifu_status_tsr), .io_ifu_status_tw (_core_io_ifu_status_tw), .io_ifu_status_tvm (_core_io_ifu_status_tvm), .io_ifu_status_mxr (_core_io_ifu_status_mxr), .io_ifu_status_sum (_core_io_ifu_status_sum), .io_ifu_status_mprv (_core_io_ifu_status_mprv), .io_ifu_status_fs (_core_io_ifu_status_fs), .io_ifu_status_mpp (_core_io_ifu_status_mpp), .io_ifu_status_spp (_core_io_ifu_status_spp), .io_ifu_status_mpie (_core_io_ifu_status_mpie), .io_ifu_status_spie (_core_io_ifu_status_spie), .io_ifu_status_mie (_core_io_ifu_status_mie), .io_ifu_status_sie (_core_io_ifu_status_sie), .io_ifu_sfence_valid (_core_io_ifu_sfence_valid), .io_ifu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), .io_ifu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), .io_ifu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), .io_ifu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), .io_ifu_sfence_bits_hv (_core_io_ifu_sfence_bits_hv), .io_ifu_sfence_bits_hg (_core_io_ifu_sfence_bits_hg), .io_ifu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), .io_ifu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), .io_ifu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), .io_ifu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), .io_ifu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), .io_ifu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), .io_ifu_brupdate_b2_uop_iq_type_0 (_core_io_ifu_brupdate_b2_uop_iq_type_0), .io_ifu_brupdate_b2_uop_iq_type_1 (_core_io_ifu_brupdate_b2_uop_iq_type_1), .io_ifu_brupdate_b2_uop_iq_type_2 (_core_io_ifu_brupdate_b2_uop_iq_type_2), .io_ifu_brupdate_b2_uop_iq_type_3 (_core_io_ifu_brupdate_b2_uop_iq_type_3), .io_ifu_brupdate_b2_uop_fu_code_0 (_core_io_ifu_brupdate_b2_uop_fu_code_0), .io_ifu_brupdate_b2_uop_fu_code_1 (_core_io_ifu_brupdate_b2_uop_fu_code_1), .io_ifu_brupdate_b2_uop_fu_code_2 (_core_io_ifu_brupdate_b2_uop_fu_code_2), .io_ifu_brupdate_b2_uop_fu_code_3 (_core_io_ifu_brupdate_b2_uop_fu_code_3), .io_ifu_brupdate_b2_uop_fu_code_4 (_core_io_ifu_brupdate_b2_uop_fu_code_4), .io_ifu_brupdate_b2_uop_fu_code_5 (_core_io_ifu_brupdate_b2_uop_fu_code_5), .io_ifu_brupdate_b2_uop_fu_code_6 (_core_io_ifu_brupdate_b2_uop_fu_code_6), .io_ifu_brupdate_b2_uop_fu_code_7 (_core_io_ifu_brupdate_b2_uop_fu_code_7), .io_ifu_brupdate_b2_uop_fu_code_8 (_core_io_ifu_brupdate_b2_uop_fu_code_8), .io_ifu_brupdate_b2_uop_fu_code_9 (_core_io_ifu_brupdate_b2_uop_fu_code_9), .io_ifu_brupdate_b2_uop_iw_issued (_core_io_ifu_brupdate_b2_uop_iw_issued), .io_ifu_brupdate_b2_uop_iw_issued_partial_agen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_agen), .io_ifu_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_dgen), .io_ifu_brupdate_b2_uop_iw_p1_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p1_speculative_child), .io_ifu_brupdate_b2_uop_iw_p2_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p2_speculative_child), .io_ifu_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p1_bypass_hint), .io_ifu_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p2_bypass_hint), .io_ifu_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p3_bypass_hint), .io_ifu_brupdate_b2_uop_dis_col_sel (_core_io_ifu_brupdate_b2_uop_dis_col_sel), .io_ifu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), .io_ifu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), .io_ifu_brupdate_b2_uop_br_type (_core_io_ifu_brupdate_b2_uop_br_type), .io_ifu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), .io_ifu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), .io_ifu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), .io_ifu_brupdate_b2_uop_is_sfence (_core_io_ifu_brupdate_b2_uop_is_sfence), .io_ifu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), .io_ifu_brupdate_b2_uop_is_eret (_core_io_ifu_brupdate_b2_uop_is_eret), .io_ifu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), .io_ifu_brupdate_b2_uop_is_rocc (_core_io_ifu_brupdate_b2_uop_is_rocc), .io_ifu_brupdate_b2_uop_is_mov (_core_io_ifu_brupdate_b2_uop_is_mov), .io_ifu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), .io_ifu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), .io_ifu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), .io_ifu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), .io_ifu_brupdate_b2_uop_imm_rename (_core_io_ifu_brupdate_b2_uop_imm_rename), .io_ifu_brupdate_b2_uop_imm_sel (_core_io_ifu_brupdate_b2_uop_imm_sel), .io_ifu_brupdate_b2_uop_pimm (_core_io_ifu_brupdate_b2_uop_pimm), .io_ifu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), .io_ifu_brupdate_b2_uop_op1_sel (_core_io_ifu_brupdate_b2_uop_op1_sel), .io_ifu_brupdate_b2_uop_op2_sel (_core_io_ifu_brupdate_b2_uop_op2_sel), .io_ifu_brupdate_b2_uop_fp_ctrl_ldst (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ldst), .io_ifu_brupdate_b2_uop_fp_ctrl_wen (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wen), .io_ifu_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren1), .io_ifu_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren2), .io_ifu_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren3), .io_ifu_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap12), .io_ifu_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap23), .io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn), .io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut), .io_ifu_brupdate_b2_uop_fp_ctrl_fromint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fromint), .io_ifu_brupdate_b2_uop_fp_ctrl_toint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_toint), .io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe), .io_ifu_brupdate_b2_uop_fp_ctrl_fma (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fma), .io_ifu_brupdate_b2_uop_fp_ctrl_div (_core_io_ifu_brupdate_b2_uop_fp_ctrl_div), .io_ifu_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_ifu_brupdate_b2_uop_fp_ctrl_sqrt), .io_ifu_brupdate_b2_uop_fp_ctrl_wflags (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wflags), .io_ifu_brupdate_b2_uop_fp_ctrl_vec (_core_io_ifu_brupdate_b2_uop_fp_ctrl_vec), .io_ifu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), .io_ifu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), .io_ifu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), .io_ifu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), .io_ifu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), .io_ifu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), .io_ifu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), .io_ifu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), .io_ifu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), .io_ifu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), .io_ifu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), .io_ifu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), .io_ifu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), .io_ifu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), .io_ifu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), .io_ifu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), .io_ifu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), .io_ifu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), .io_ifu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), .io_ifu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), .io_ifu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), .io_ifu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), .io_ifu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), .io_ifu_brupdate_b2_uop_csr_cmd (_core_io_ifu_brupdate_b2_uop_csr_cmd), .io_ifu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), .io_ifu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), .io_ifu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), .io_ifu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), .io_ifu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), .io_ifu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), .io_ifu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), .io_ifu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), .io_ifu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), .io_ifu_brupdate_b2_uop_fcn_dw (_core_io_ifu_brupdate_b2_uop_fcn_dw), .io_ifu_brupdate_b2_uop_fcn_op (_core_io_ifu_brupdate_b2_uop_fcn_op), .io_ifu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), .io_ifu_brupdate_b2_uop_fp_rm (_core_io_ifu_brupdate_b2_uop_fp_rm), .io_ifu_brupdate_b2_uop_fp_typ (_core_io_ifu_brupdate_b2_uop_fp_typ), .io_ifu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), .io_ifu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), .io_ifu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), .io_ifu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), .io_ifu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), .io_ifu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), .io_ifu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), .io_ifu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), .io_ifu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), .io_ifu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), .io_ifu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), .io_ifu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), .io_ifu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), .io_ifu_redirect_flush (_core_io_ifu_redirect_flush), .io_ifu_redirect_val (_core_io_ifu_redirect_val), .io_ifu_redirect_pc (_core_io_ifu_redirect_pc), .io_ifu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), .io_ifu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), .io_ifu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), .io_ifu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), .io_ifu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), .io_ifu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), .io_ifu_commit_valid (_core_io_ifu_commit_valid), .io_ifu_commit_bits (_core_io_ifu_commit_bits), .io_ifu_flush_icache (_core_io_ifu_flush_icache), .io_ifu_enable_bpd (_core_io_ifu_enable_bpd), .io_ifu_perf_acquire (_frontend_io_cpu_perf_acquire), // @[tile.scala:137:28] .io_ifu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[tile.scala:137:28] .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_l2miss (_ptw_io_dpath_perf_l2miss), // @[tile.scala:236:20] .io_ptw_perf_l2hit (_ptw_io_dpath_perf_l2hit), // @[tile.scala:236:20] .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[tile.scala:236:20] .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[tile.scala:236:20] .io_lsu_agen_0_valid (_core_io_lsu_agen_0_valid), .io_lsu_agen_0_bits_uop_inst (_core_io_lsu_agen_0_bits_uop_inst), .io_lsu_agen_0_bits_uop_debug_inst (_core_io_lsu_agen_0_bits_uop_debug_inst), .io_lsu_agen_0_bits_uop_is_rvc (_core_io_lsu_agen_0_bits_uop_is_rvc), .io_lsu_agen_0_bits_uop_debug_pc (_core_io_lsu_agen_0_bits_uop_debug_pc), .io_lsu_agen_0_bits_uop_iq_type_0 (_core_io_lsu_agen_0_bits_uop_iq_type_0), .io_lsu_agen_0_bits_uop_iq_type_1 (_core_io_lsu_agen_0_bits_uop_iq_type_1), .io_lsu_agen_0_bits_uop_iq_type_2 (_core_io_lsu_agen_0_bits_uop_iq_type_2), .io_lsu_agen_0_bits_uop_iq_type_3 (_core_io_lsu_agen_0_bits_uop_iq_type_3), .io_lsu_agen_0_bits_uop_fu_code_0 (_core_io_lsu_agen_0_bits_uop_fu_code_0), .io_lsu_agen_0_bits_uop_fu_code_1 (_core_io_lsu_agen_0_bits_uop_fu_code_1), .io_lsu_agen_0_bits_uop_fu_code_2 (_core_io_lsu_agen_0_bits_uop_fu_code_2), .io_lsu_agen_0_bits_uop_fu_code_3 (_core_io_lsu_agen_0_bits_uop_fu_code_3), .io_lsu_agen_0_bits_uop_fu_code_4 (_core_io_lsu_agen_0_bits_uop_fu_code_4), .io_lsu_agen_0_bits_uop_fu_code_5 (_core_io_lsu_agen_0_bits_uop_fu_code_5), .io_lsu_agen_0_bits_uop_fu_code_6 (_core_io_lsu_agen_0_bits_uop_fu_code_6), .io_lsu_agen_0_bits_uop_fu_code_7 (_core_io_lsu_agen_0_bits_uop_fu_code_7), .io_lsu_agen_0_bits_uop_fu_code_8 (_core_io_lsu_agen_0_bits_uop_fu_code_8), .io_lsu_agen_0_bits_uop_fu_code_9 (_core_io_lsu_agen_0_bits_uop_fu_code_9), .io_lsu_agen_0_bits_uop_iw_issued (_core_io_lsu_agen_0_bits_uop_iw_issued), .io_lsu_agen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_agen), .io_lsu_agen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_dgen), .io_lsu_agen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p1_speculative_child), .io_lsu_agen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p2_speculative_child), .io_lsu_agen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p1_bypass_hint), .io_lsu_agen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p2_bypass_hint), .io_lsu_agen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p3_bypass_hint), .io_lsu_agen_0_bits_uop_dis_col_sel (_core_io_lsu_agen_0_bits_uop_dis_col_sel), .io_lsu_agen_0_bits_uop_br_mask (_core_io_lsu_agen_0_bits_uop_br_mask), .io_lsu_agen_0_bits_uop_br_tag (_core_io_lsu_agen_0_bits_uop_br_tag), .io_lsu_agen_0_bits_uop_br_type (_core_io_lsu_agen_0_bits_uop_br_type), .io_lsu_agen_0_bits_uop_is_sfb (_core_io_lsu_agen_0_bits_uop_is_sfb), .io_lsu_agen_0_bits_uop_is_fence (_core_io_lsu_agen_0_bits_uop_is_fence), .io_lsu_agen_0_bits_uop_is_fencei (_core_io_lsu_agen_0_bits_uop_is_fencei), .io_lsu_agen_0_bits_uop_is_sfence (_core_io_lsu_agen_0_bits_uop_is_sfence), .io_lsu_agen_0_bits_uop_is_amo (_core_io_lsu_agen_0_bits_uop_is_amo), .io_lsu_agen_0_bits_uop_is_eret (_core_io_lsu_agen_0_bits_uop_is_eret), .io_lsu_agen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_agen_0_bits_uop_is_sys_pc2epc), .io_lsu_agen_0_bits_uop_is_rocc (_core_io_lsu_agen_0_bits_uop_is_rocc), .io_lsu_agen_0_bits_uop_is_mov (_core_io_lsu_agen_0_bits_uop_is_mov), .io_lsu_agen_0_bits_uop_ftq_idx (_core_io_lsu_agen_0_bits_uop_ftq_idx), .io_lsu_agen_0_bits_uop_edge_inst (_core_io_lsu_agen_0_bits_uop_edge_inst), .io_lsu_agen_0_bits_uop_pc_lob (_core_io_lsu_agen_0_bits_uop_pc_lob), .io_lsu_agen_0_bits_uop_taken (_core_io_lsu_agen_0_bits_uop_taken), .io_lsu_agen_0_bits_uop_imm_rename (_core_io_lsu_agen_0_bits_uop_imm_rename), .io_lsu_agen_0_bits_uop_imm_sel (_core_io_lsu_agen_0_bits_uop_imm_sel), .io_lsu_agen_0_bits_uop_pimm (_core_io_lsu_agen_0_bits_uop_pimm), .io_lsu_agen_0_bits_uop_imm_packed (_core_io_lsu_agen_0_bits_uop_imm_packed), .io_lsu_agen_0_bits_uop_op1_sel (_core_io_lsu_agen_0_bits_uop_op1_sel), .io_lsu_agen_0_bits_uop_op2_sel (_core_io_lsu_agen_0_bits_uop_op2_sel), .io_lsu_agen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ldst), .io_lsu_agen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wen), .io_lsu_agen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren1), .io_lsu_agen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren2), .io_lsu_agen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren3), .io_lsu_agen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap12), .io_lsu_agen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap23), .io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_agen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fromint), .io_lsu_agen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_toint), .io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_agen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fma), .io_lsu_agen_0_bits_uop_fp_ctrl_div (_core_io_lsu_agen_0_bits_uop_fp_ctrl_div), .io_lsu_agen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_agen_0_bits_uop_fp_ctrl_sqrt), .io_lsu_agen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wflags), .io_lsu_agen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_agen_0_bits_uop_fp_ctrl_vec), .io_lsu_agen_0_bits_uop_rob_idx (_core_io_lsu_agen_0_bits_uop_rob_idx), .io_lsu_agen_0_bits_uop_ldq_idx (_core_io_lsu_agen_0_bits_uop_ldq_idx), .io_lsu_agen_0_bits_uop_stq_idx (_core_io_lsu_agen_0_bits_uop_stq_idx), .io_lsu_agen_0_bits_uop_rxq_idx (_core_io_lsu_agen_0_bits_uop_rxq_idx), .io_lsu_agen_0_bits_uop_pdst (_core_io_lsu_agen_0_bits_uop_pdst), .io_lsu_agen_0_bits_uop_prs1 (_core_io_lsu_agen_0_bits_uop_prs1), .io_lsu_agen_0_bits_uop_prs2 (_core_io_lsu_agen_0_bits_uop_prs2), .io_lsu_agen_0_bits_uop_prs3 (_core_io_lsu_agen_0_bits_uop_prs3), .io_lsu_agen_0_bits_uop_ppred (_core_io_lsu_agen_0_bits_uop_ppred), .io_lsu_agen_0_bits_uop_prs1_busy (_core_io_lsu_agen_0_bits_uop_prs1_busy), .io_lsu_agen_0_bits_uop_prs2_busy (_core_io_lsu_agen_0_bits_uop_prs2_busy), .io_lsu_agen_0_bits_uop_prs3_busy (_core_io_lsu_agen_0_bits_uop_prs3_busy), .io_lsu_agen_0_bits_uop_ppred_busy (_core_io_lsu_agen_0_bits_uop_ppred_busy), .io_lsu_agen_0_bits_uop_stale_pdst (_core_io_lsu_agen_0_bits_uop_stale_pdst), .io_lsu_agen_0_bits_uop_exception (_core_io_lsu_agen_0_bits_uop_exception), .io_lsu_agen_0_bits_uop_exc_cause (_core_io_lsu_agen_0_bits_uop_exc_cause), .io_lsu_agen_0_bits_uop_mem_cmd (_core_io_lsu_agen_0_bits_uop_mem_cmd), .io_lsu_agen_0_bits_uop_mem_size (_core_io_lsu_agen_0_bits_uop_mem_size), .io_lsu_agen_0_bits_uop_mem_signed (_core_io_lsu_agen_0_bits_uop_mem_signed), .io_lsu_agen_0_bits_uop_uses_ldq (_core_io_lsu_agen_0_bits_uop_uses_ldq), .io_lsu_agen_0_bits_uop_uses_stq (_core_io_lsu_agen_0_bits_uop_uses_stq), .io_lsu_agen_0_bits_uop_is_unique (_core_io_lsu_agen_0_bits_uop_is_unique), .io_lsu_agen_0_bits_uop_flush_on_commit (_core_io_lsu_agen_0_bits_uop_flush_on_commit), .io_lsu_agen_0_bits_uop_csr_cmd (_core_io_lsu_agen_0_bits_uop_csr_cmd), .io_lsu_agen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_agen_0_bits_uop_ldst_is_rs1), .io_lsu_agen_0_bits_uop_ldst (_core_io_lsu_agen_0_bits_uop_ldst), .io_lsu_agen_0_bits_uop_lrs1 (_core_io_lsu_agen_0_bits_uop_lrs1), .io_lsu_agen_0_bits_uop_lrs2 (_core_io_lsu_agen_0_bits_uop_lrs2), .io_lsu_agen_0_bits_uop_lrs3 (_core_io_lsu_agen_0_bits_uop_lrs3), .io_lsu_agen_0_bits_uop_dst_rtype (_core_io_lsu_agen_0_bits_uop_dst_rtype), .io_lsu_agen_0_bits_uop_lrs1_rtype (_core_io_lsu_agen_0_bits_uop_lrs1_rtype), .io_lsu_agen_0_bits_uop_lrs2_rtype (_core_io_lsu_agen_0_bits_uop_lrs2_rtype), .io_lsu_agen_0_bits_uop_frs3_en (_core_io_lsu_agen_0_bits_uop_frs3_en), .io_lsu_agen_0_bits_uop_fcn_dw (_core_io_lsu_agen_0_bits_uop_fcn_dw), .io_lsu_agen_0_bits_uop_fcn_op (_core_io_lsu_agen_0_bits_uop_fcn_op), .io_lsu_agen_0_bits_uop_fp_val (_core_io_lsu_agen_0_bits_uop_fp_val), .io_lsu_agen_0_bits_uop_fp_rm (_core_io_lsu_agen_0_bits_uop_fp_rm), .io_lsu_agen_0_bits_uop_fp_typ (_core_io_lsu_agen_0_bits_uop_fp_typ), .io_lsu_agen_0_bits_uop_xcpt_pf_if (_core_io_lsu_agen_0_bits_uop_xcpt_pf_if), .io_lsu_agen_0_bits_uop_xcpt_ae_if (_core_io_lsu_agen_0_bits_uop_xcpt_ae_if), .io_lsu_agen_0_bits_uop_xcpt_ma_if (_core_io_lsu_agen_0_bits_uop_xcpt_ma_if), .io_lsu_agen_0_bits_uop_bp_debug_if (_core_io_lsu_agen_0_bits_uop_bp_debug_if), .io_lsu_agen_0_bits_uop_bp_xcpt_if (_core_io_lsu_agen_0_bits_uop_bp_xcpt_if), .io_lsu_agen_0_bits_uop_debug_fsrc (_core_io_lsu_agen_0_bits_uop_debug_fsrc), .io_lsu_agen_0_bits_uop_debug_tsrc (_core_io_lsu_agen_0_bits_uop_debug_tsrc), .io_lsu_agen_0_bits_data (_core_io_lsu_agen_0_bits_data), .io_lsu_dgen_0_valid (_core_io_lsu_dgen_0_valid), .io_lsu_dgen_0_bits_uop_inst (_core_io_lsu_dgen_0_bits_uop_inst), .io_lsu_dgen_0_bits_uop_debug_inst (_core_io_lsu_dgen_0_bits_uop_debug_inst), .io_lsu_dgen_0_bits_uop_is_rvc (_core_io_lsu_dgen_0_bits_uop_is_rvc), .io_lsu_dgen_0_bits_uop_debug_pc (_core_io_lsu_dgen_0_bits_uop_debug_pc), .io_lsu_dgen_0_bits_uop_iq_type_0 (_core_io_lsu_dgen_0_bits_uop_iq_type_0), .io_lsu_dgen_0_bits_uop_iq_type_1 (_core_io_lsu_dgen_0_bits_uop_iq_type_1), .io_lsu_dgen_0_bits_uop_iq_type_2 (_core_io_lsu_dgen_0_bits_uop_iq_type_2), .io_lsu_dgen_0_bits_uop_iq_type_3 (_core_io_lsu_dgen_0_bits_uop_iq_type_3), .io_lsu_dgen_0_bits_uop_fu_code_0 (_core_io_lsu_dgen_0_bits_uop_fu_code_0), .io_lsu_dgen_0_bits_uop_fu_code_1 (_core_io_lsu_dgen_0_bits_uop_fu_code_1), .io_lsu_dgen_0_bits_uop_fu_code_2 (_core_io_lsu_dgen_0_bits_uop_fu_code_2), .io_lsu_dgen_0_bits_uop_fu_code_3 (_core_io_lsu_dgen_0_bits_uop_fu_code_3), .io_lsu_dgen_0_bits_uop_fu_code_4 (_core_io_lsu_dgen_0_bits_uop_fu_code_4), .io_lsu_dgen_0_bits_uop_fu_code_5 (_core_io_lsu_dgen_0_bits_uop_fu_code_5), .io_lsu_dgen_0_bits_uop_fu_code_6 (_core_io_lsu_dgen_0_bits_uop_fu_code_6), .io_lsu_dgen_0_bits_uop_fu_code_7 (_core_io_lsu_dgen_0_bits_uop_fu_code_7), .io_lsu_dgen_0_bits_uop_fu_code_8 (_core_io_lsu_dgen_0_bits_uop_fu_code_8), .io_lsu_dgen_0_bits_uop_fu_code_9 (_core_io_lsu_dgen_0_bits_uop_fu_code_9), .io_lsu_dgen_0_bits_uop_iw_issued (_core_io_lsu_dgen_0_bits_uop_iw_issued), .io_lsu_dgen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_agen), .io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen), .io_lsu_dgen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p1_speculative_child), .io_lsu_dgen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p2_speculative_child), .io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint), .io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint), .io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint), .io_lsu_dgen_0_bits_uop_dis_col_sel (_core_io_lsu_dgen_0_bits_uop_dis_col_sel), .io_lsu_dgen_0_bits_uop_br_mask (_core_io_lsu_dgen_0_bits_uop_br_mask), .io_lsu_dgen_0_bits_uop_br_tag (_core_io_lsu_dgen_0_bits_uop_br_tag), .io_lsu_dgen_0_bits_uop_br_type (_core_io_lsu_dgen_0_bits_uop_br_type), .io_lsu_dgen_0_bits_uop_is_sfb (_core_io_lsu_dgen_0_bits_uop_is_sfb), .io_lsu_dgen_0_bits_uop_is_fence (_core_io_lsu_dgen_0_bits_uop_is_fence), .io_lsu_dgen_0_bits_uop_is_fencei (_core_io_lsu_dgen_0_bits_uop_is_fencei), .io_lsu_dgen_0_bits_uop_is_sfence (_core_io_lsu_dgen_0_bits_uop_is_sfence), .io_lsu_dgen_0_bits_uop_is_amo (_core_io_lsu_dgen_0_bits_uop_is_amo), .io_lsu_dgen_0_bits_uop_is_eret (_core_io_lsu_dgen_0_bits_uop_is_eret), .io_lsu_dgen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_0_bits_uop_is_sys_pc2epc), .io_lsu_dgen_0_bits_uop_is_rocc (_core_io_lsu_dgen_0_bits_uop_is_rocc), .io_lsu_dgen_0_bits_uop_is_mov (_core_io_lsu_dgen_0_bits_uop_is_mov), .io_lsu_dgen_0_bits_uop_ftq_idx (_core_io_lsu_dgen_0_bits_uop_ftq_idx), .io_lsu_dgen_0_bits_uop_edge_inst (_core_io_lsu_dgen_0_bits_uop_edge_inst), .io_lsu_dgen_0_bits_uop_pc_lob (_core_io_lsu_dgen_0_bits_uop_pc_lob), .io_lsu_dgen_0_bits_uop_taken (_core_io_lsu_dgen_0_bits_uop_taken), .io_lsu_dgen_0_bits_uop_imm_rename (_core_io_lsu_dgen_0_bits_uop_imm_rename), .io_lsu_dgen_0_bits_uop_imm_sel (_core_io_lsu_dgen_0_bits_uop_imm_sel), .io_lsu_dgen_0_bits_uop_pimm (_core_io_lsu_dgen_0_bits_uop_pimm), .io_lsu_dgen_0_bits_uop_imm_packed (_core_io_lsu_dgen_0_bits_uop_imm_packed), .io_lsu_dgen_0_bits_uop_op1_sel (_core_io_lsu_dgen_0_bits_uop_op1_sel), .io_lsu_dgen_0_bits_uop_op2_sel (_core_io_lsu_dgen_0_bits_uop_op2_sel), .io_lsu_dgen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ldst), .io_lsu_dgen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wen), .io_lsu_dgen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren1), .io_lsu_dgen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren2), .io_lsu_dgen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren3), .io_lsu_dgen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap12), .io_lsu_dgen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap23), .io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_dgen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fromint), .io_lsu_dgen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_toint), .io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_dgen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fma), .io_lsu_dgen_0_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_div), .io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt), .io_lsu_dgen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wflags), .io_lsu_dgen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_vec), .io_lsu_dgen_0_bits_uop_rob_idx (_core_io_lsu_dgen_0_bits_uop_rob_idx), .io_lsu_dgen_0_bits_uop_ldq_idx (_core_io_lsu_dgen_0_bits_uop_ldq_idx), .io_lsu_dgen_0_bits_uop_stq_idx (_core_io_lsu_dgen_0_bits_uop_stq_idx), .io_lsu_dgen_0_bits_uop_rxq_idx (_core_io_lsu_dgen_0_bits_uop_rxq_idx), .io_lsu_dgen_0_bits_uop_pdst (_core_io_lsu_dgen_0_bits_uop_pdst), .io_lsu_dgen_0_bits_uop_prs1 (_core_io_lsu_dgen_0_bits_uop_prs1), .io_lsu_dgen_0_bits_uop_prs2 (_core_io_lsu_dgen_0_bits_uop_prs2), .io_lsu_dgen_0_bits_uop_prs3 (_core_io_lsu_dgen_0_bits_uop_prs3), .io_lsu_dgen_0_bits_uop_ppred (_core_io_lsu_dgen_0_bits_uop_ppred), .io_lsu_dgen_0_bits_uop_prs1_busy (_core_io_lsu_dgen_0_bits_uop_prs1_busy), .io_lsu_dgen_0_bits_uop_prs2_busy (_core_io_lsu_dgen_0_bits_uop_prs2_busy), .io_lsu_dgen_0_bits_uop_prs3_busy (_core_io_lsu_dgen_0_bits_uop_prs3_busy), .io_lsu_dgen_0_bits_uop_ppred_busy (_core_io_lsu_dgen_0_bits_uop_ppred_busy), .io_lsu_dgen_0_bits_uop_stale_pdst (_core_io_lsu_dgen_0_bits_uop_stale_pdst), .io_lsu_dgen_0_bits_uop_exception (_core_io_lsu_dgen_0_bits_uop_exception), .io_lsu_dgen_0_bits_uop_exc_cause (_core_io_lsu_dgen_0_bits_uop_exc_cause), .io_lsu_dgen_0_bits_uop_mem_cmd (_core_io_lsu_dgen_0_bits_uop_mem_cmd), .io_lsu_dgen_0_bits_uop_mem_size (_core_io_lsu_dgen_0_bits_uop_mem_size), .io_lsu_dgen_0_bits_uop_mem_signed (_core_io_lsu_dgen_0_bits_uop_mem_signed), .io_lsu_dgen_0_bits_uop_uses_ldq (_core_io_lsu_dgen_0_bits_uop_uses_ldq), .io_lsu_dgen_0_bits_uop_uses_stq (_core_io_lsu_dgen_0_bits_uop_uses_stq), .io_lsu_dgen_0_bits_uop_is_unique (_core_io_lsu_dgen_0_bits_uop_is_unique), .io_lsu_dgen_0_bits_uop_flush_on_commit (_core_io_lsu_dgen_0_bits_uop_flush_on_commit), .io_lsu_dgen_0_bits_uop_csr_cmd (_core_io_lsu_dgen_0_bits_uop_csr_cmd), .io_lsu_dgen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_0_bits_uop_ldst_is_rs1), .io_lsu_dgen_0_bits_uop_ldst (_core_io_lsu_dgen_0_bits_uop_ldst), .io_lsu_dgen_0_bits_uop_lrs1 (_core_io_lsu_dgen_0_bits_uop_lrs1), .io_lsu_dgen_0_bits_uop_lrs2 (_core_io_lsu_dgen_0_bits_uop_lrs2), .io_lsu_dgen_0_bits_uop_lrs3 (_core_io_lsu_dgen_0_bits_uop_lrs3), .io_lsu_dgen_0_bits_uop_dst_rtype (_core_io_lsu_dgen_0_bits_uop_dst_rtype), .io_lsu_dgen_0_bits_uop_lrs1_rtype (_core_io_lsu_dgen_0_bits_uop_lrs1_rtype), .io_lsu_dgen_0_bits_uop_lrs2_rtype (_core_io_lsu_dgen_0_bits_uop_lrs2_rtype), .io_lsu_dgen_0_bits_uop_frs3_en (_core_io_lsu_dgen_0_bits_uop_frs3_en), .io_lsu_dgen_0_bits_uop_fcn_dw (_core_io_lsu_dgen_0_bits_uop_fcn_dw), .io_lsu_dgen_0_bits_uop_fcn_op (_core_io_lsu_dgen_0_bits_uop_fcn_op), .io_lsu_dgen_0_bits_uop_fp_val (_core_io_lsu_dgen_0_bits_uop_fp_val), .io_lsu_dgen_0_bits_uop_fp_rm (_core_io_lsu_dgen_0_bits_uop_fp_rm), .io_lsu_dgen_0_bits_uop_fp_typ (_core_io_lsu_dgen_0_bits_uop_fp_typ), .io_lsu_dgen_0_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_0_bits_uop_xcpt_pf_if), .io_lsu_dgen_0_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ae_if), .io_lsu_dgen_0_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ma_if), .io_lsu_dgen_0_bits_uop_bp_debug_if (_core_io_lsu_dgen_0_bits_uop_bp_debug_if), .io_lsu_dgen_0_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_0_bits_uop_bp_xcpt_if), .io_lsu_dgen_0_bits_uop_debug_fsrc (_core_io_lsu_dgen_0_bits_uop_debug_fsrc), .io_lsu_dgen_0_bits_uop_debug_tsrc (_core_io_lsu_dgen_0_bits_uop_debug_tsrc), .io_lsu_dgen_0_bits_data (_core_io_lsu_dgen_0_bits_data), .io_lsu_dgen_1_valid (_core_io_lsu_dgen_1_valid), .io_lsu_dgen_1_bits_uop_inst (_core_io_lsu_dgen_1_bits_uop_inst), .io_lsu_dgen_1_bits_uop_debug_inst (_core_io_lsu_dgen_1_bits_uop_debug_inst), .io_lsu_dgen_1_bits_uop_is_rvc (_core_io_lsu_dgen_1_bits_uop_is_rvc), .io_lsu_dgen_1_bits_uop_debug_pc (_core_io_lsu_dgen_1_bits_uop_debug_pc), .io_lsu_dgen_1_bits_uop_iq_type_0 (_core_io_lsu_dgen_1_bits_uop_iq_type_0), .io_lsu_dgen_1_bits_uop_iq_type_1 (_core_io_lsu_dgen_1_bits_uop_iq_type_1), .io_lsu_dgen_1_bits_uop_iq_type_2 (_core_io_lsu_dgen_1_bits_uop_iq_type_2), .io_lsu_dgen_1_bits_uop_iq_type_3 (_core_io_lsu_dgen_1_bits_uop_iq_type_3), .io_lsu_dgen_1_bits_uop_fu_code_0 (_core_io_lsu_dgen_1_bits_uop_fu_code_0), .io_lsu_dgen_1_bits_uop_fu_code_1 (_core_io_lsu_dgen_1_bits_uop_fu_code_1), .io_lsu_dgen_1_bits_uop_fu_code_2 (_core_io_lsu_dgen_1_bits_uop_fu_code_2), .io_lsu_dgen_1_bits_uop_fu_code_3 (_core_io_lsu_dgen_1_bits_uop_fu_code_3), .io_lsu_dgen_1_bits_uop_fu_code_4 (_core_io_lsu_dgen_1_bits_uop_fu_code_4), .io_lsu_dgen_1_bits_uop_fu_code_5 (_core_io_lsu_dgen_1_bits_uop_fu_code_5), .io_lsu_dgen_1_bits_uop_fu_code_6 (_core_io_lsu_dgen_1_bits_uop_fu_code_6), .io_lsu_dgen_1_bits_uop_fu_code_7 (_core_io_lsu_dgen_1_bits_uop_fu_code_7), .io_lsu_dgen_1_bits_uop_fu_code_8 (_core_io_lsu_dgen_1_bits_uop_fu_code_8), .io_lsu_dgen_1_bits_uop_fu_code_9 (_core_io_lsu_dgen_1_bits_uop_fu_code_9), .io_lsu_dgen_1_bits_uop_iw_issued (_core_io_lsu_dgen_1_bits_uop_iw_issued), .io_lsu_dgen_1_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_agen), .io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen), .io_lsu_dgen_1_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p1_speculative_child), .io_lsu_dgen_1_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p2_speculative_child), .io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint), .io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint), .io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint), .io_lsu_dgen_1_bits_uop_dis_col_sel (_core_io_lsu_dgen_1_bits_uop_dis_col_sel), .io_lsu_dgen_1_bits_uop_br_mask (_core_io_lsu_dgen_1_bits_uop_br_mask), .io_lsu_dgen_1_bits_uop_br_tag (_core_io_lsu_dgen_1_bits_uop_br_tag), .io_lsu_dgen_1_bits_uop_br_type (_core_io_lsu_dgen_1_bits_uop_br_type), .io_lsu_dgen_1_bits_uop_is_sfb (_core_io_lsu_dgen_1_bits_uop_is_sfb), .io_lsu_dgen_1_bits_uop_is_fence (_core_io_lsu_dgen_1_bits_uop_is_fence), .io_lsu_dgen_1_bits_uop_is_fencei (_core_io_lsu_dgen_1_bits_uop_is_fencei), .io_lsu_dgen_1_bits_uop_is_sfence (_core_io_lsu_dgen_1_bits_uop_is_sfence), .io_lsu_dgen_1_bits_uop_is_amo (_core_io_lsu_dgen_1_bits_uop_is_amo), .io_lsu_dgen_1_bits_uop_is_eret (_core_io_lsu_dgen_1_bits_uop_is_eret), .io_lsu_dgen_1_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_1_bits_uop_is_sys_pc2epc), .io_lsu_dgen_1_bits_uop_is_rocc (_core_io_lsu_dgen_1_bits_uop_is_rocc), .io_lsu_dgen_1_bits_uop_is_mov (_core_io_lsu_dgen_1_bits_uop_is_mov), .io_lsu_dgen_1_bits_uop_ftq_idx (_core_io_lsu_dgen_1_bits_uop_ftq_idx), .io_lsu_dgen_1_bits_uop_edge_inst (_core_io_lsu_dgen_1_bits_uop_edge_inst), .io_lsu_dgen_1_bits_uop_pc_lob (_core_io_lsu_dgen_1_bits_uop_pc_lob), .io_lsu_dgen_1_bits_uop_taken (_core_io_lsu_dgen_1_bits_uop_taken), .io_lsu_dgen_1_bits_uop_imm_rename (_core_io_lsu_dgen_1_bits_uop_imm_rename), .io_lsu_dgen_1_bits_uop_imm_sel (_core_io_lsu_dgen_1_bits_uop_imm_sel), .io_lsu_dgen_1_bits_uop_pimm (_core_io_lsu_dgen_1_bits_uop_pimm), .io_lsu_dgen_1_bits_uop_imm_packed (_core_io_lsu_dgen_1_bits_uop_imm_packed), .io_lsu_dgen_1_bits_uop_op1_sel (_core_io_lsu_dgen_1_bits_uop_op1_sel), .io_lsu_dgen_1_bits_uop_op2_sel (_core_io_lsu_dgen_1_bits_uop_op2_sel), .io_lsu_dgen_1_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ldst), .io_lsu_dgen_1_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wen), .io_lsu_dgen_1_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren1), .io_lsu_dgen_1_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren2), .io_lsu_dgen_1_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren3), .io_lsu_dgen_1_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap12), .io_lsu_dgen_1_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap23), .io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn), .io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut), .io_lsu_dgen_1_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fromint), .io_lsu_dgen_1_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_toint), .io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe), .io_lsu_dgen_1_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fma), .io_lsu_dgen_1_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_div), .io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt), .io_lsu_dgen_1_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wflags), .io_lsu_dgen_1_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_vec), .io_lsu_dgen_1_bits_uop_rob_idx (_core_io_lsu_dgen_1_bits_uop_rob_idx), .io_lsu_dgen_1_bits_uop_ldq_idx (_core_io_lsu_dgen_1_bits_uop_ldq_idx), .io_lsu_dgen_1_bits_uop_stq_idx (_core_io_lsu_dgen_1_bits_uop_stq_idx), .io_lsu_dgen_1_bits_uop_rxq_idx (_core_io_lsu_dgen_1_bits_uop_rxq_idx), .io_lsu_dgen_1_bits_uop_pdst (_core_io_lsu_dgen_1_bits_uop_pdst), .io_lsu_dgen_1_bits_uop_prs1 (_core_io_lsu_dgen_1_bits_uop_prs1), .io_lsu_dgen_1_bits_uop_prs2 (_core_io_lsu_dgen_1_bits_uop_prs2), .io_lsu_dgen_1_bits_uop_prs3 (_core_io_lsu_dgen_1_bits_uop_prs3), .io_lsu_dgen_1_bits_uop_ppred (_core_io_lsu_dgen_1_bits_uop_ppred), .io_lsu_dgen_1_bits_uop_prs1_busy (_core_io_lsu_dgen_1_bits_uop_prs1_busy), .io_lsu_dgen_1_bits_uop_prs2_busy (_core_io_lsu_dgen_1_bits_uop_prs2_busy), .io_lsu_dgen_1_bits_uop_prs3_busy (_core_io_lsu_dgen_1_bits_uop_prs3_busy), .io_lsu_dgen_1_bits_uop_ppred_busy (_core_io_lsu_dgen_1_bits_uop_ppred_busy), .io_lsu_dgen_1_bits_uop_stale_pdst (_core_io_lsu_dgen_1_bits_uop_stale_pdst), .io_lsu_dgen_1_bits_uop_exception (_core_io_lsu_dgen_1_bits_uop_exception), .io_lsu_dgen_1_bits_uop_exc_cause (_core_io_lsu_dgen_1_bits_uop_exc_cause), .io_lsu_dgen_1_bits_uop_mem_cmd (_core_io_lsu_dgen_1_bits_uop_mem_cmd), .io_lsu_dgen_1_bits_uop_mem_size (_core_io_lsu_dgen_1_bits_uop_mem_size), .io_lsu_dgen_1_bits_uop_mem_signed (_core_io_lsu_dgen_1_bits_uop_mem_signed), .io_lsu_dgen_1_bits_uop_uses_ldq (_core_io_lsu_dgen_1_bits_uop_uses_ldq), .io_lsu_dgen_1_bits_uop_uses_stq (_core_io_lsu_dgen_1_bits_uop_uses_stq), .io_lsu_dgen_1_bits_uop_is_unique (_core_io_lsu_dgen_1_bits_uop_is_unique), .io_lsu_dgen_1_bits_uop_flush_on_commit (_core_io_lsu_dgen_1_bits_uop_flush_on_commit), .io_lsu_dgen_1_bits_uop_csr_cmd (_core_io_lsu_dgen_1_bits_uop_csr_cmd), .io_lsu_dgen_1_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_1_bits_uop_ldst_is_rs1), .io_lsu_dgen_1_bits_uop_ldst (_core_io_lsu_dgen_1_bits_uop_ldst), .io_lsu_dgen_1_bits_uop_lrs1 (_core_io_lsu_dgen_1_bits_uop_lrs1), .io_lsu_dgen_1_bits_uop_lrs2 (_core_io_lsu_dgen_1_bits_uop_lrs2), .io_lsu_dgen_1_bits_uop_lrs3 (_core_io_lsu_dgen_1_bits_uop_lrs3), .io_lsu_dgen_1_bits_uop_dst_rtype (_core_io_lsu_dgen_1_bits_uop_dst_rtype), .io_lsu_dgen_1_bits_uop_lrs1_rtype (_core_io_lsu_dgen_1_bits_uop_lrs1_rtype), .io_lsu_dgen_1_bits_uop_lrs2_rtype (_core_io_lsu_dgen_1_bits_uop_lrs2_rtype), .io_lsu_dgen_1_bits_uop_frs3_en (_core_io_lsu_dgen_1_bits_uop_frs3_en), .io_lsu_dgen_1_bits_uop_fcn_dw (_core_io_lsu_dgen_1_bits_uop_fcn_dw), .io_lsu_dgen_1_bits_uop_fcn_op (_core_io_lsu_dgen_1_bits_uop_fcn_op), .io_lsu_dgen_1_bits_uop_fp_val (_core_io_lsu_dgen_1_bits_uop_fp_val), .io_lsu_dgen_1_bits_uop_fp_rm (_core_io_lsu_dgen_1_bits_uop_fp_rm), .io_lsu_dgen_1_bits_uop_fp_typ (_core_io_lsu_dgen_1_bits_uop_fp_typ), .io_lsu_dgen_1_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_1_bits_uop_xcpt_pf_if), .io_lsu_dgen_1_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ae_if), .io_lsu_dgen_1_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ma_if), .io_lsu_dgen_1_bits_uop_bp_debug_if (_core_io_lsu_dgen_1_bits_uop_bp_debug_if), .io_lsu_dgen_1_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_1_bits_uop_bp_xcpt_if), .io_lsu_dgen_1_bits_uop_debug_fsrc (_core_io_lsu_dgen_1_bits_uop_debug_fsrc), .io_lsu_dgen_1_bits_uop_debug_tsrc (_core_io_lsu_dgen_1_bits_uop_debug_tsrc), .io_lsu_dgen_1_bits_data (_core_io_lsu_dgen_1_bits_data), .io_lsu_dgen_2_valid (_core_io_lsu_dgen_2_valid), .io_lsu_dgen_2_bits_uop_inst (_core_io_lsu_dgen_2_bits_uop_inst), .io_lsu_dgen_2_bits_uop_debug_inst (_core_io_lsu_dgen_2_bits_uop_debug_inst), .io_lsu_dgen_2_bits_uop_is_rvc (_core_io_lsu_dgen_2_bits_uop_is_rvc), .io_lsu_dgen_2_bits_uop_debug_pc (_core_io_lsu_dgen_2_bits_uop_debug_pc), .io_lsu_dgen_2_bits_uop_iq_type_0 (_core_io_lsu_dgen_2_bits_uop_iq_type_0), .io_lsu_dgen_2_bits_uop_iq_type_1 (_core_io_lsu_dgen_2_bits_uop_iq_type_1), .io_lsu_dgen_2_bits_uop_iq_type_2 (_core_io_lsu_dgen_2_bits_uop_iq_type_2), .io_lsu_dgen_2_bits_uop_iq_type_3 (_core_io_lsu_dgen_2_bits_uop_iq_type_3), .io_lsu_dgen_2_bits_uop_fu_code_0 (_core_io_lsu_dgen_2_bits_uop_fu_code_0), .io_lsu_dgen_2_bits_uop_fu_code_1 (_core_io_lsu_dgen_2_bits_uop_fu_code_1), .io_lsu_dgen_2_bits_uop_fu_code_2 (_core_io_lsu_dgen_2_bits_uop_fu_code_2), .io_lsu_dgen_2_bits_uop_fu_code_3 (_core_io_lsu_dgen_2_bits_uop_fu_code_3), .io_lsu_dgen_2_bits_uop_fu_code_4 (_core_io_lsu_dgen_2_bits_uop_fu_code_4), .io_lsu_dgen_2_bits_uop_fu_code_5 (_core_io_lsu_dgen_2_bits_uop_fu_code_5), .io_lsu_dgen_2_bits_uop_fu_code_6 (_core_io_lsu_dgen_2_bits_uop_fu_code_6), .io_lsu_dgen_2_bits_uop_fu_code_7 (_core_io_lsu_dgen_2_bits_uop_fu_code_7), .io_lsu_dgen_2_bits_uop_fu_code_8 (_core_io_lsu_dgen_2_bits_uop_fu_code_8), .io_lsu_dgen_2_bits_uop_fu_code_9 (_core_io_lsu_dgen_2_bits_uop_fu_code_9), .io_lsu_dgen_2_bits_uop_iw_issued (_core_io_lsu_dgen_2_bits_uop_iw_issued), .io_lsu_dgen_2_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_agen), .io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen), .io_lsu_dgen_2_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p1_speculative_child), .io_lsu_dgen_2_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p2_speculative_child), .io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint), .io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint), .io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint), .io_lsu_dgen_2_bits_uop_dis_col_sel (_core_io_lsu_dgen_2_bits_uop_dis_col_sel), .io_lsu_dgen_2_bits_uop_br_mask (_core_io_lsu_dgen_2_bits_uop_br_mask), .io_lsu_dgen_2_bits_uop_br_tag (_core_io_lsu_dgen_2_bits_uop_br_tag), .io_lsu_dgen_2_bits_uop_br_type (_core_io_lsu_dgen_2_bits_uop_br_type), .io_lsu_dgen_2_bits_uop_is_sfb (_core_io_lsu_dgen_2_bits_uop_is_sfb), .io_lsu_dgen_2_bits_uop_is_fence (_core_io_lsu_dgen_2_bits_uop_is_fence), .io_lsu_dgen_2_bits_uop_is_fencei (_core_io_lsu_dgen_2_bits_uop_is_fencei), .io_lsu_dgen_2_bits_uop_is_sfence (_core_io_lsu_dgen_2_bits_uop_is_sfence), .io_lsu_dgen_2_bits_uop_is_amo (_core_io_lsu_dgen_2_bits_uop_is_amo), .io_lsu_dgen_2_bits_uop_is_eret (_core_io_lsu_dgen_2_bits_uop_is_eret), .io_lsu_dgen_2_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_2_bits_uop_is_sys_pc2epc), .io_lsu_dgen_2_bits_uop_is_rocc (_core_io_lsu_dgen_2_bits_uop_is_rocc), .io_lsu_dgen_2_bits_uop_is_mov (_core_io_lsu_dgen_2_bits_uop_is_mov), .io_lsu_dgen_2_bits_uop_ftq_idx (_core_io_lsu_dgen_2_bits_uop_ftq_idx), .io_lsu_dgen_2_bits_uop_edge_inst (_core_io_lsu_dgen_2_bits_uop_edge_inst), .io_lsu_dgen_2_bits_uop_pc_lob (_core_io_lsu_dgen_2_bits_uop_pc_lob), .io_lsu_dgen_2_bits_uop_taken (_core_io_lsu_dgen_2_bits_uop_taken), .io_lsu_dgen_2_bits_uop_imm_rename (_core_io_lsu_dgen_2_bits_uop_imm_rename), .io_lsu_dgen_2_bits_uop_imm_sel (_core_io_lsu_dgen_2_bits_uop_imm_sel), .io_lsu_dgen_2_bits_uop_pimm (_core_io_lsu_dgen_2_bits_uop_pimm), .io_lsu_dgen_2_bits_uop_imm_packed (_core_io_lsu_dgen_2_bits_uop_imm_packed), .io_lsu_dgen_2_bits_uop_op1_sel (_core_io_lsu_dgen_2_bits_uop_op1_sel), .io_lsu_dgen_2_bits_uop_op2_sel (_core_io_lsu_dgen_2_bits_uop_op2_sel), .io_lsu_dgen_2_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ldst), .io_lsu_dgen_2_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wen), .io_lsu_dgen_2_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren1), .io_lsu_dgen_2_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren2), .io_lsu_dgen_2_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren3), .io_lsu_dgen_2_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap12), .io_lsu_dgen_2_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap23), .io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn), .io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut), .io_lsu_dgen_2_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fromint), .io_lsu_dgen_2_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_toint), .io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe), .io_lsu_dgen_2_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fma), .io_lsu_dgen_2_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_div), .io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt), .io_lsu_dgen_2_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wflags), .io_lsu_dgen_2_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_vec), .io_lsu_dgen_2_bits_uop_rob_idx (_core_io_lsu_dgen_2_bits_uop_rob_idx), .io_lsu_dgen_2_bits_uop_ldq_idx (_core_io_lsu_dgen_2_bits_uop_ldq_idx), .io_lsu_dgen_2_bits_uop_stq_idx (_core_io_lsu_dgen_2_bits_uop_stq_idx), .io_lsu_dgen_2_bits_uop_rxq_idx (_core_io_lsu_dgen_2_bits_uop_rxq_idx), .io_lsu_dgen_2_bits_uop_pdst (_core_io_lsu_dgen_2_bits_uop_pdst), .io_lsu_dgen_2_bits_uop_prs1 (_core_io_lsu_dgen_2_bits_uop_prs1), .io_lsu_dgen_2_bits_uop_prs2 (_core_io_lsu_dgen_2_bits_uop_prs2), .io_lsu_dgen_2_bits_uop_prs3 (_core_io_lsu_dgen_2_bits_uop_prs3), .io_lsu_dgen_2_bits_uop_ppred (_core_io_lsu_dgen_2_bits_uop_ppred), .io_lsu_dgen_2_bits_uop_prs1_busy (_core_io_lsu_dgen_2_bits_uop_prs1_busy), .io_lsu_dgen_2_bits_uop_prs2_busy (_core_io_lsu_dgen_2_bits_uop_prs2_busy), .io_lsu_dgen_2_bits_uop_prs3_busy (_core_io_lsu_dgen_2_bits_uop_prs3_busy), .io_lsu_dgen_2_bits_uop_ppred_busy (_core_io_lsu_dgen_2_bits_uop_ppred_busy), .io_lsu_dgen_2_bits_uop_stale_pdst (_core_io_lsu_dgen_2_bits_uop_stale_pdst), .io_lsu_dgen_2_bits_uop_exception (_core_io_lsu_dgen_2_bits_uop_exception), .io_lsu_dgen_2_bits_uop_exc_cause (_core_io_lsu_dgen_2_bits_uop_exc_cause), .io_lsu_dgen_2_bits_uop_mem_cmd (_core_io_lsu_dgen_2_bits_uop_mem_cmd), .io_lsu_dgen_2_bits_uop_mem_size (_core_io_lsu_dgen_2_bits_uop_mem_size), .io_lsu_dgen_2_bits_uop_mem_signed (_core_io_lsu_dgen_2_bits_uop_mem_signed), .io_lsu_dgen_2_bits_uop_uses_ldq (_core_io_lsu_dgen_2_bits_uop_uses_ldq), .io_lsu_dgen_2_bits_uop_uses_stq (_core_io_lsu_dgen_2_bits_uop_uses_stq), .io_lsu_dgen_2_bits_uop_is_unique (_core_io_lsu_dgen_2_bits_uop_is_unique), .io_lsu_dgen_2_bits_uop_flush_on_commit (_core_io_lsu_dgen_2_bits_uop_flush_on_commit), .io_lsu_dgen_2_bits_uop_csr_cmd (_core_io_lsu_dgen_2_bits_uop_csr_cmd), .io_lsu_dgen_2_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_2_bits_uop_ldst_is_rs1), .io_lsu_dgen_2_bits_uop_ldst (_core_io_lsu_dgen_2_bits_uop_ldst), .io_lsu_dgen_2_bits_uop_lrs1 (_core_io_lsu_dgen_2_bits_uop_lrs1), .io_lsu_dgen_2_bits_uop_lrs2 (_core_io_lsu_dgen_2_bits_uop_lrs2), .io_lsu_dgen_2_bits_uop_lrs3 (_core_io_lsu_dgen_2_bits_uop_lrs3), .io_lsu_dgen_2_bits_uop_dst_rtype (_core_io_lsu_dgen_2_bits_uop_dst_rtype), .io_lsu_dgen_2_bits_uop_lrs1_rtype (_core_io_lsu_dgen_2_bits_uop_lrs1_rtype), .io_lsu_dgen_2_bits_uop_lrs2_rtype (_core_io_lsu_dgen_2_bits_uop_lrs2_rtype), .io_lsu_dgen_2_bits_uop_frs3_en (_core_io_lsu_dgen_2_bits_uop_frs3_en), .io_lsu_dgen_2_bits_uop_fcn_dw (_core_io_lsu_dgen_2_bits_uop_fcn_dw), .io_lsu_dgen_2_bits_uop_fcn_op (_core_io_lsu_dgen_2_bits_uop_fcn_op), .io_lsu_dgen_2_bits_uop_fp_val (_core_io_lsu_dgen_2_bits_uop_fp_val), .io_lsu_dgen_2_bits_uop_fp_rm (_core_io_lsu_dgen_2_bits_uop_fp_rm), .io_lsu_dgen_2_bits_uop_fp_typ (_core_io_lsu_dgen_2_bits_uop_fp_typ), .io_lsu_dgen_2_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_2_bits_uop_xcpt_pf_if), .io_lsu_dgen_2_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ae_if), .io_lsu_dgen_2_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ma_if), .io_lsu_dgen_2_bits_uop_bp_debug_if (_core_io_lsu_dgen_2_bits_uop_bp_debug_if), .io_lsu_dgen_2_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_2_bits_uop_bp_xcpt_if), .io_lsu_dgen_2_bits_uop_debug_fsrc (_core_io_lsu_dgen_2_bits_uop_debug_fsrc), .io_lsu_dgen_2_bits_uop_debug_tsrc (_core_io_lsu_dgen_2_bits_uop_debug_tsrc), .io_lsu_dgen_2_bits_data (_core_io_lsu_dgen_2_bits_data), .io_lsu_iwakeups_0_valid (_lsu_io_core_iwakeups_0_valid), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_inst (_lsu_io_core_iwakeups_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_inst (_lsu_io_core_iwakeups_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_rvc (_lsu_io_core_iwakeups_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_pc (_lsu_io_core_iwakeups_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_0 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_1 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_2 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_3 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_0 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_1 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_2 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_3 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_4 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_5 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_6 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_7 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_8 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_9 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_issued (_lsu_io_core_iwakeups_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_dis_col_sel (_lsu_io_core_iwakeups_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_br_mask (_lsu_io_core_iwakeups_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_br_tag (_lsu_io_core_iwakeups_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_br_type (_lsu_io_core_iwakeups_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_sfb (_lsu_io_core_iwakeups_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_fence (_lsu_io_core_iwakeups_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_fencei (_lsu_io_core_iwakeups_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_sfence (_lsu_io_core_iwakeups_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_amo (_lsu_io_core_iwakeups_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_eret (_lsu_io_core_iwakeups_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iwakeups_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_rocc (_lsu_io_core_iwakeups_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_mov (_lsu_io_core_iwakeups_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ftq_idx (_lsu_io_core_iwakeups_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_edge_inst (_lsu_io_core_iwakeups_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_pc_lob (_lsu_io_core_iwakeups_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_taken (_lsu_io_core_iwakeups_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_imm_rename (_lsu_io_core_iwakeups_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_imm_sel (_lsu_io_core_iwakeups_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_pimm (_lsu_io_core_iwakeups_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_imm_packed (_lsu_io_core_iwakeups_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_op1_sel (_lsu_io_core_iwakeups_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_op2_sel (_lsu_io_core_iwakeups_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_div (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_rob_idx (_lsu_io_core_iwakeups_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ldq_idx (_lsu_io_core_iwakeups_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_stq_idx (_lsu_io_core_iwakeups_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_rxq_idx (_lsu_io_core_iwakeups_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_pdst (_lsu_io_core_iwakeups_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs1 (_lsu_io_core_iwakeups_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs2 (_lsu_io_core_iwakeups_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs3 (_lsu_io_core_iwakeups_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ppred (_lsu_io_core_iwakeups_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs1_busy (_lsu_io_core_iwakeups_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs2_busy (_lsu_io_core_iwakeups_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs3_busy (_lsu_io_core_iwakeups_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ppred_busy (_lsu_io_core_iwakeups_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_stale_pdst (_lsu_io_core_iwakeups_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_exception (_lsu_io_core_iwakeups_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_exc_cause (_lsu_io_core_iwakeups_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_mem_cmd (_lsu_io_core_iwakeups_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_mem_size (_lsu_io_core_iwakeups_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_mem_signed (_lsu_io_core_iwakeups_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_uses_ldq (_lsu_io_core_iwakeups_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_uses_stq (_lsu_io_core_iwakeups_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_unique (_lsu_io_core_iwakeups_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_flush_on_commit (_lsu_io_core_iwakeups_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_csr_cmd (_lsu_io_core_iwakeups_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iwakeups_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ldst (_lsu_io_core_iwakeups_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs1 (_lsu_io_core_iwakeups_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs2 (_lsu_io_core_iwakeups_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs3 (_lsu_io_core_iwakeups_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_dst_rtype (_lsu_io_core_iwakeups_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs1_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs2_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_frs3_en (_lsu_io_core_iwakeups_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fcn_dw (_lsu_io_core_iwakeups_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fcn_op (_lsu_io_core_iwakeups_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_val (_lsu_io_core_iwakeups_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_rm (_lsu_io_core_iwakeups_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_typ (_lsu_io_core_iwakeups_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_xcpt_pf_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_xcpt_ae_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_xcpt_ma_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_bp_debug_if (_lsu_io_core_iwakeups_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_bp_xcpt_if (_lsu_io_core_iwakeups_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_fsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_tsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_bypassable (_lsu_io_core_iwakeups_0_bits_bypassable), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_speculative_mask (_lsu_io_core_iwakeups_0_bits_speculative_mask), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_rebusy (_lsu_io_core_iwakeups_0_bits_rebusy), // @[tile.scala:159:20] .io_lsu_iresp_0_valid (_lsu_io_core_iresp_0_valid), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_inst (_lsu_io_core_iresp_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_inst (_lsu_io_core_iresp_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_rvc (_lsu_io_core_iresp_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_pc (_lsu_io_core_iresp_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_0 (_lsu_io_core_iresp_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_1 (_lsu_io_core_iresp_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_2 (_lsu_io_core_iresp_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_3 (_lsu_io_core_iresp_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_0 (_lsu_io_core_iresp_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_1 (_lsu_io_core_iresp_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_2 (_lsu_io_core_iresp_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_3 (_lsu_io_core_iresp_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_4 (_lsu_io_core_iresp_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_5 (_lsu_io_core_iresp_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_6 (_lsu_io_core_iresp_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_7 (_lsu_io_core_iresp_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_8 (_lsu_io_core_iresp_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_9 (_lsu_io_core_iresp_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_issued (_lsu_io_core_iresp_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_dis_col_sel (_lsu_io_core_iresp_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_br_mask (_lsu_io_core_iresp_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_br_tag (_lsu_io_core_iresp_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_br_type (_lsu_io_core_iresp_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_sfb (_lsu_io_core_iresp_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_fence (_lsu_io_core_iresp_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_fencei (_lsu_io_core_iresp_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_sfence (_lsu_io_core_iresp_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_amo (_lsu_io_core_iresp_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_eret (_lsu_io_core_iresp_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iresp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_rocc (_lsu_io_core_iresp_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_mov (_lsu_io_core_iresp_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ftq_idx (_lsu_io_core_iresp_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_edge_inst (_lsu_io_core_iresp_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_pc_lob (_lsu_io_core_iresp_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_taken (_lsu_io_core_iresp_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_imm_rename (_lsu_io_core_iresp_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_imm_sel (_lsu_io_core_iresp_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_pimm (_lsu_io_core_iresp_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_imm_packed (_lsu_io_core_iresp_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_op1_sel (_lsu_io_core_iresp_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_op2_sel (_lsu_io_core_iresp_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_rob_idx (_lsu_io_core_iresp_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ldq_idx (_lsu_io_core_iresp_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_stq_idx (_lsu_io_core_iresp_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_rxq_idx (_lsu_io_core_iresp_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_pdst (_lsu_io_core_iresp_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs1 (_lsu_io_core_iresp_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs2 (_lsu_io_core_iresp_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs3 (_lsu_io_core_iresp_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ppred (_lsu_io_core_iresp_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs1_busy (_lsu_io_core_iresp_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs2_busy (_lsu_io_core_iresp_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs3_busy (_lsu_io_core_iresp_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ppred_busy (_lsu_io_core_iresp_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_stale_pdst (_lsu_io_core_iresp_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_exception (_lsu_io_core_iresp_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_exc_cause (_lsu_io_core_iresp_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_mem_cmd (_lsu_io_core_iresp_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_mem_size (_lsu_io_core_iresp_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_mem_signed (_lsu_io_core_iresp_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_uses_ldq (_lsu_io_core_iresp_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_uses_stq (_lsu_io_core_iresp_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_unique (_lsu_io_core_iresp_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_flush_on_commit (_lsu_io_core_iresp_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_csr_cmd (_lsu_io_core_iresp_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iresp_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ldst (_lsu_io_core_iresp_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs1 (_lsu_io_core_iresp_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs2 (_lsu_io_core_iresp_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs3 (_lsu_io_core_iresp_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_dst_rtype (_lsu_io_core_iresp_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs1_rtype (_lsu_io_core_iresp_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs2_rtype (_lsu_io_core_iresp_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_frs3_en (_lsu_io_core_iresp_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fcn_dw (_lsu_io_core_iresp_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fcn_op (_lsu_io_core_iresp_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_val (_lsu_io_core_iresp_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_rm (_lsu_io_core_iresp_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_typ (_lsu_io_core_iresp_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_iresp_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_bp_debug_if (_lsu_io_core_iresp_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_iresp_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_fsrc (_lsu_io_core_iresp_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_tsrc (_lsu_io_core_iresp_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_data (_lsu_io_core_iresp_0_bits_data), // @[tile.scala:159:20] .io_lsu_fresp_0_valid (_lsu_io_core_fresp_0_valid), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_inst (_lsu_io_core_fresp_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_inst (_lsu_io_core_fresp_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_rvc (_lsu_io_core_fresp_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_pc (_lsu_io_core_fresp_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_0 (_lsu_io_core_fresp_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_1 (_lsu_io_core_fresp_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_2 (_lsu_io_core_fresp_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_3 (_lsu_io_core_fresp_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_0 (_lsu_io_core_fresp_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_1 (_lsu_io_core_fresp_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_2 (_lsu_io_core_fresp_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_3 (_lsu_io_core_fresp_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_4 (_lsu_io_core_fresp_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_5 (_lsu_io_core_fresp_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_6 (_lsu_io_core_fresp_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_7 (_lsu_io_core_fresp_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_8 (_lsu_io_core_fresp_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_9 (_lsu_io_core_fresp_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_issued (_lsu_io_core_fresp_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_dis_col_sel (_lsu_io_core_fresp_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_br_mask (_lsu_io_core_fresp_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_br_tag (_lsu_io_core_fresp_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_br_type (_lsu_io_core_fresp_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_sfb (_lsu_io_core_fresp_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_fence (_lsu_io_core_fresp_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_fencei (_lsu_io_core_fresp_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_sfence (_lsu_io_core_fresp_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_amo (_lsu_io_core_fresp_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_eret (_lsu_io_core_fresp_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_fresp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_rocc (_lsu_io_core_fresp_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_mov (_lsu_io_core_fresp_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ftq_idx (_lsu_io_core_fresp_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_edge_inst (_lsu_io_core_fresp_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_pc_lob (_lsu_io_core_fresp_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_taken (_lsu_io_core_fresp_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_imm_rename (_lsu_io_core_fresp_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_imm_sel (_lsu_io_core_fresp_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_pimm (_lsu_io_core_fresp_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_imm_packed (_lsu_io_core_fresp_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_op1_sel (_lsu_io_core_fresp_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_op2_sel (_lsu_io_core_fresp_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_rob_idx (_lsu_io_core_fresp_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ldq_idx (_lsu_io_core_fresp_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_stq_idx (_lsu_io_core_fresp_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_rxq_idx (_lsu_io_core_fresp_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_pdst (_lsu_io_core_fresp_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs1 (_lsu_io_core_fresp_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs2 (_lsu_io_core_fresp_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs3 (_lsu_io_core_fresp_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ppred (_lsu_io_core_fresp_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs1_busy (_lsu_io_core_fresp_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs2_busy (_lsu_io_core_fresp_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs3_busy (_lsu_io_core_fresp_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ppred_busy (_lsu_io_core_fresp_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_stale_pdst (_lsu_io_core_fresp_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_exception (_lsu_io_core_fresp_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_exc_cause (_lsu_io_core_fresp_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_mem_cmd (_lsu_io_core_fresp_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_mem_size (_lsu_io_core_fresp_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_mem_signed (_lsu_io_core_fresp_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_uses_ldq (_lsu_io_core_fresp_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_uses_stq (_lsu_io_core_fresp_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_unique (_lsu_io_core_fresp_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_flush_on_commit (_lsu_io_core_fresp_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_csr_cmd (_lsu_io_core_fresp_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_fresp_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ldst (_lsu_io_core_fresp_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs1 (_lsu_io_core_fresp_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs2 (_lsu_io_core_fresp_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs3 (_lsu_io_core_fresp_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_dst_rtype (_lsu_io_core_fresp_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs1_rtype (_lsu_io_core_fresp_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs2_rtype (_lsu_io_core_fresp_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_frs3_en (_lsu_io_core_fresp_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fcn_dw (_lsu_io_core_fresp_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fcn_op (_lsu_io_core_fresp_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_val (_lsu_io_core_fresp_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_rm (_lsu_io_core_fresp_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_typ (_lsu_io_core_fresp_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_fresp_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_bp_debug_if (_lsu_io_core_fresp_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_fresp_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_fsrc (_lsu_io_core_fresp_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_tsrc (_lsu_io_core_fresp_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_data (_lsu_io_core_fresp_0_bits_data), // @[tile.scala:159:20] .io_lsu_sfence_valid (_core_io_lsu_sfence_valid), .io_lsu_sfence_bits_rs1 (_core_io_lsu_sfence_bits_rs1), .io_lsu_sfence_bits_rs2 (_core_io_lsu_sfence_bits_rs2), .io_lsu_sfence_bits_addr (_core_io_lsu_sfence_bits_addr), .io_lsu_sfence_bits_asid (_core_io_lsu_sfence_bits_asid), .io_lsu_sfence_bits_hv (_core_io_lsu_sfence_bits_hv), .io_lsu_sfence_bits_hg (_core_io_lsu_sfence_bits_hg), .io_lsu_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), .io_lsu_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), .io_lsu_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), .io_lsu_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), .io_lsu_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), .io_lsu_dis_uops_0_bits_iq_type_0 (_core_io_lsu_dis_uops_0_bits_iq_type_0), .io_lsu_dis_uops_0_bits_iq_type_1 (_core_io_lsu_dis_uops_0_bits_iq_type_1), .io_lsu_dis_uops_0_bits_iq_type_2 (_core_io_lsu_dis_uops_0_bits_iq_type_2), .io_lsu_dis_uops_0_bits_iq_type_3 (_core_io_lsu_dis_uops_0_bits_iq_type_3), .io_lsu_dis_uops_0_bits_fu_code_0 (_core_io_lsu_dis_uops_0_bits_fu_code_0), .io_lsu_dis_uops_0_bits_fu_code_1 (_core_io_lsu_dis_uops_0_bits_fu_code_1), .io_lsu_dis_uops_0_bits_fu_code_2 (_core_io_lsu_dis_uops_0_bits_fu_code_2), .io_lsu_dis_uops_0_bits_fu_code_3 (_core_io_lsu_dis_uops_0_bits_fu_code_3), .io_lsu_dis_uops_0_bits_fu_code_4 (_core_io_lsu_dis_uops_0_bits_fu_code_4), .io_lsu_dis_uops_0_bits_fu_code_5 (_core_io_lsu_dis_uops_0_bits_fu_code_5), .io_lsu_dis_uops_0_bits_fu_code_6 (_core_io_lsu_dis_uops_0_bits_fu_code_6), .io_lsu_dis_uops_0_bits_fu_code_7 (_core_io_lsu_dis_uops_0_bits_fu_code_7), .io_lsu_dis_uops_0_bits_fu_code_8 (_core_io_lsu_dis_uops_0_bits_fu_code_8), .io_lsu_dis_uops_0_bits_fu_code_9 (_core_io_lsu_dis_uops_0_bits_fu_code_9), .io_lsu_dis_uops_0_bits_iw_issued (_core_io_lsu_dis_uops_0_bits_iw_issued), .io_lsu_dis_uops_0_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_agen), .io_lsu_dis_uops_0_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_dgen), .io_lsu_dis_uops_0_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p1_speculative_child), .io_lsu_dis_uops_0_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p2_speculative_child), .io_lsu_dis_uops_0_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p1_bypass_hint), .io_lsu_dis_uops_0_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p2_bypass_hint), .io_lsu_dis_uops_0_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p3_bypass_hint), .io_lsu_dis_uops_0_bits_dis_col_sel (_core_io_lsu_dis_uops_0_bits_dis_col_sel), .io_lsu_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), .io_lsu_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), .io_lsu_dis_uops_0_bits_br_type (_core_io_lsu_dis_uops_0_bits_br_type), .io_lsu_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), .io_lsu_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), .io_lsu_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), .io_lsu_dis_uops_0_bits_is_sfence (_core_io_lsu_dis_uops_0_bits_is_sfence), .io_lsu_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), .io_lsu_dis_uops_0_bits_is_eret (_core_io_lsu_dis_uops_0_bits_is_eret), .io_lsu_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), .io_lsu_dis_uops_0_bits_is_rocc (_core_io_lsu_dis_uops_0_bits_is_rocc), .io_lsu_dis_uops_0_bits_is_mov (_core_io_lsu_dis_uops_0_bits_is_mov), .io_lsu_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), .io_lsu_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), .io_lsu_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), .io_lsu_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), .io_lsu_dis_uops_0_bits_imm_rename (_core_io_lsu_dis_uops_0_bits_imm_rename), .io_lsu_dis_uops_0_bits_imm_sel (_core_io_lsu_dis_uops_0_bits_imm_sel), .io_lsu_dis_uops_0_bits_pimm (_core_io_lsu_dis_uops_0_bits_pimm), .io_lsu_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), .io_lsu_dis_uops_0_bits_op1_sel (_core_io_lsu_dis_uops_0_bits_op1_sel), .io_lsu_dis_uops_0_bits_op2_sel (_core_io_lsu_dis_uops_0_bits_op2_sel), .io_lsu_dis_uops_0_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ldst), .io_lsu_dis_uops_0_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wen), .io_lsu_dis_uops_0_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren1), .io_lsu_dis_uops_0_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren2), .io_lsu_dis_uops_0_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren3), .io_lsu_dis_uops_0_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap12), .io_lsu_dis_uops_0_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap23), .io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn), .io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut), .io_lsu_dis_uops_0_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fromint), .io_lsu_dis_uops_0_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_toint), .io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe), .io_lsu_dis_uops_0_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fma), .io_lsu_dis_uops_0_bits_fp_ctrl_div (_core_io_lsu_dis_uops_0_bits_fp_ctrl_div), .io_lsu_dis_uops_0_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_0_bits_fp_ctrl_sqrt), .io_lsu_dis_uops_0_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wflags), .io_lsu_dis_uops_0_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_0_bits_fp_ctrl_vec), .io_lsu_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), .io_lsu_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), .io_lsu_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), .io_lsu_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), .io_lsu_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), .io_lsu_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), .io_lsu_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), .io_lsu_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), .io_lsu_dis_uops_0_bits_ppred (_core_io_lsu_dis_uops_0_bits_ppred), .io_lsu_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), .io_lsu_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), .io_lsu_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), .io_lsu_dis_uops_0_bits_ppred_busy (_core_io_lsu_dis_uops_0_bits_ppred_busy), .io_lsu_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), .io_lsu_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), .io_lsu_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), .io_lsu_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), .io_lsu_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), .io_lsu_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), .io_lsu_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), .io_lsu_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), .io_lsu_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), .io_lsu_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), .io_lsu_dis_uops_0_bits_csr_cmd (_core_io_lsu_dis_uops_0_bits_csr_cmd), .io_lsu_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), .io_lsu_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), .io_lsu_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), .io_lsu_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), .io_lsu_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), .io_lsu_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), .io_lsu_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), .io_lsu_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), .io_lsu_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), .io_lsu_dis_uops_0_bits_fcn_dw (_core_io_lsu_dis_uops_0_bits_fcn_dw), .io_lsu_dis_uops_0_bits_fcn_op (_core_io_lsu_dis_uops_0_bits_fcn_op), .io_lsu_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), .io_lsu_dis_uops_0_bits_fp_rm (_core_io_lsu_dis_uops_0_bits_fp_rm), .io_lsu_dis_uops_0_bits_fp_typ (_core_io_lsu_dis_uops_0_bits_fp_typ), .io_lsu_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), .io_lsu_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), .io_lsu_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), .io_lsu_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), .io_lsu_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), .io_lsu_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), .io_lsu_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), .io_lsu_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), .io_lsu_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), .io_lsu_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), .io_lsu_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), .io_lsu_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), .io_lsu_dis_uops_1_bits_iq_type_0 (_core_io_lsu_dis_uops_1_bits_iq_type_0), .io_lsu_dis_uops_1_bits_iq_type_1 (_core_io_lsu_dis_uops_1_bits_iq_type_1), .io_lsu_dis_uops_1_bits_iq_type_2 (_core_io_lsu_dis_uops_1_bits_iq_type_2), .io_lsu_dis_uops_1_bits_iq_type_3 (_core_io_lsu_dis_uops_1_bits_iq_type_3), .io_lsu_dis_uops_1_bits_fu_code_0 (_core_io_lsu_dis_uops_1_bits_fu_code_0), .io_lsu_dis_uops_1_bits_fu_code_1 (_core_io_lsu_dis_uops_1_bits_fu_code_1), .io_lsu_dis_uops_1_bits_fu_code_2 (_core_io_lsu_dis_uops_1_bits_fu_code_2), .io_lsu_dis_uops_1_bits_fu_code_3 (_core_io_lsu_dis_uops_1_bits_fu_code_3), .io_lsu_dis_uops_1_bits_fu_code_4 (_core_io_lsu_dis_uops_1_bits_fu_code_4), .io_lsu_dis_uops_1_bits_fu_code_5 (_core_io_lsu_dis_uops_1_bits_fu_code_5), .io_lsu_dis_uops_1_bits_fu_code_6 (_core_io_lsu_dis_uops_1_bits_fu_code_6), .io_lsu_dis_uops_1_bits_fu_code_7 (_core_io_lsu_dis_uops_1_bits_fu_code_7), .io_lsu_dis_uops_1_bits_fu_code_8 (_core_io_lsu_dis_uops_1_bits_fu_code_8), .io_lsu_dis_uops_1_bits_fu_code_9 (_core_io_lsu_dis_uops_1_bits_fu_code_9), .io_lsu_dis_uops_1_bits_iw_issued (_core_io_lsu_dis_uops_1_bits_iw_issued), .io_lsu_dis_uops_1_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_agen), .io_lsu_dis_uops_1_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_dgen), .io_lsu_dis_uops_1_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p1_speculative_child), .io_lsu_dis_uops_1_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p2_speculative_child), .io_lsu_dis_uops_1_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p1_bypass_hint), .io_lsu_dis_uops_1_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p2_bypass_hint), .io_lsu_dis_uops_1_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p3_bypass_hint), .io_lsu_dis_uops_1_bits_dis_col_sel (_core_io_lsu_dis_uops_1_bits_dis_col_sel), .io_lsu_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), .io_lsu_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), .io_lsu_dis_uops_1_bits_br_type (_core_io_lsu_dis_uops_1_bits_br_type), .io_lsu_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), .io_lsu_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), .io_lsu_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), .io_lsu_dis_uops_1_bits_is_sfence (_core_io_lsu_dis_uops_1_bits_is_sfence), .io_lsu_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), .io_lsu_dis_uops_1_bits_is_eret (_core_io_lsu_dis_uops_1_bits_is_eret), .io_lsu_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), .io_lsu_dis_uops_1_bits_is_rocc (_core_io_lsu_dis_uops_1_bits_is_rocc), .io_lsu_dis_uops_1_bits_is_mov (_core_io_lsu_dis_uops_1_bits_is_mov), .io_lsu_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), .io_lsu_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), .io_lsu_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), .io_lsu_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), .io_lsu_dis_uops_1_bits_imm_rename (_core_io_lsu_dis_uops_1_bits_imm_rename), .io_lsu_dis_uops_1_bits_imm_sel (_core_io_lsu_dis_uops_1_bits_imm_sel), .io_lsu_dis_uops_1_bits_pimm (_core_io_lsu_dis_uops_1_bits_pimm), .io_lsu_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), .io_lsu_dis_uops_1_bits_op1_sel (_core_io_lsu_dis_uops_1_bits_op1_sel), .io_lsu_dis_uops_1_bits_op2_sel (_core_io_lsu_dis_uops_1_bits_op2_sel), .io_lsu_dis_uops_1_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ldst), .io_lsu_dis_uops_1_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wen), .io_lsu_dis_uops_1_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren1), .io_lsu_dis_uops_1_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren2), .io_lsu_dis_uops_1_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren3), .io_lsu_dis_uops_1_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap12), .io_lsu_dis_uops_1_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap23), .io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn), .io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut), .io_lsu_dis_uops_1_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fromint), .io_lsu_dis_uops_1_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_toint), .io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe), .io_lsu_dis_uops_1_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fma), .io_lsu_dis_uops_1_bits_fp_ctrl_div (_core_io_lsu_dis_uops_1_bits_fp_ctrl_div), .io_lsu_dis_uops_1_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_1_bits_fp_ctrl_sqrt), .io_lsu_dis_uops_1_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wflags), .io_lsu_dis_uops_1_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_1_bits_fp_ctrl_vec), .io_lsu_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), .io_lsu_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), .io_lsu_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), .io_lsu_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), .io_lsu_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), .io_lsu_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), .io_lsu_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), .io_lsu_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), .io_lsu_dis_uops_1_bits_ppred (_core_io_lsu_dis_uops_1_bits_ppred), .io_lsu_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), .io_lsu_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), .io_lsu_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), .io_lsu_dis_uops_1_bits_ppred_busy (_core_io_lsu_dis_uops_1_bits_ppred_busy), .io_lsu_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), .io_lsu_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), .io_lsu_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), .io_lsu_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), .io_lsu_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), .io_lsu_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), .io_lsu_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), .io_lsu_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), .io_lsu_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), .io_lsu_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), .io_lsu_dis_uops_1_bits_csr_cmd (_core_io_lsu_dis_uops_1_bits_csr_cmd), .io_lsu_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), .io_lsu_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), .io_lsu_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), .io_lsu_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), .io_lsu_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), .io_lsu_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), .io_lsu_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), .io_lsu_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), .io_lsu_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), .io_lsu_dis_uops_1_bits_fcn_dw (_core_io_lsu_dis_uops_1_bits_fcn_dw), .io_lsu_dis_uops_1_bits_fcn_op (_core_io_lsu_dis_uops_1_bits_fcn_op), .io_lsu_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), .io_lsu_dis_uops_1_bits_fp_rm (_core_io_lsu_dis_uops_1_bits_fp_rm), .io_lsu_dis_uops_1_bits_fp_typ (_core_io_lsu_dis_uops_1_bits_fp_typ), .io_lsu_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), .io_lsu_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), .io_lsu_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), .io_lsu_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), .io_lsu_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), .io_lsu_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), .io_lsu_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), .io_lsu_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), // @[tile.scala:159:20] .io_lsu_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), // @[tile.scala:159:20] .io_lsu_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), // @[tile.scala:159:20] .io_lsu_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), // @[tile.scala:159:20] .io_lsu_ldq_full_0 (_lsu_io_core_ldq_full_0), // @[tile.scala:159:20] .io_lsu_ldq_full_1 (_lsu_io_core_ldq_full_1), // @[tile.scala:159:20] .io_lsu_stq_full_0 (_lsu_io_core_stq_full_0), // @[tile.scala:159:20] .io_lsu_stq_full_1 (_lsu_io_core_stq_full_1), // @[tile.scala:159:20] .io_lsu_commit_valids_0 (_core_io_lsu_commit_valids_0), .io_lsu_commit_valids_1 (_core_io_lsu_commit_valids_1), .io_lsu_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), .io_lsu_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), .io_lsu_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), .io_lsu_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), .io_lsu_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), .io_lsu_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), .io_lsu_commit_uops_0_iq_type_0 (_core_io_lsu_commit_uops_0_iq_type_0), .io_lsu_commit_uops_0_iq_type_1 (_core_io_lsu_commit_uops_0_iq_type_1), .io_lsu_commit_uops_0_iq_type_2 (_core_io_lsu_commit_uops_0_iq_type_2), .io_lsu_commit_uops_0_iq_type_3 (_core_io_lsu_commit_uops_0_iq_type_3), .io_lsu_commit_uops_0_fu_code_0 (_core_io_lsu_commit_uops_0_fu_code_0), .io_lsu_commit_uops_0_fu_code_1 (_core_io_lsu_commit_uops_0_fu_code_1), .io_lsu_commit_uops_0_fu_code_2 (_core_io_lsu_commit_uops_0_fu_code_2), .io_lsu_commit_uops_0_fu_code_3 (_core_io_lsu_commit_uops_0_fu_code_3), .io_lsu_commit_uops_0_fu_code_4 (_core_io_lsu_commit_uops_0_fu_code_4), .io_lsu_commit_uops_0_fu_code_5 (_core_io_lsu_commit_uops_0_fu_code_5), .io_lsu_commit_uops_0_fu_code_6 (_core_io_lsu_commit_uops_0_fu_code_6), .io_lsu_commit_uops_0_fu_code_7 (_core_io_lsu_commit_uops_0_fu_code_7), .io_lsu_commit_uops_0_fu_code_8 (_core_io_lsu_commit_uops_0_fu_code_8), .io_lsu_commit_uops_0_fu_code_9 (_core_io_lsu_commit_uops_0_fu_code_9), .io_lsu_commit_uops_0_iw_issued (_core_io_lsu_commit_uops_0_iw_issued), .io_lsu_commit_uops_0_iw_issued_partial_agen (_core_io_lsu_commit_uops_0_iw_issued_partial_agen), .io_lsu_commit_uops_0_iw_issued_partial_dgen (_core_io_lsu_commit_uops_0_iw_issued_partial_dgen), .io_lsu_commit_uops_0_iw_p1_speculative_child (_core_io_lsu_commit_uops_0_iw_p1_speculative_child), .io_lsu_commit_uops_0_iw_p2_speculative_child (_core_io_lsu_commit_uops_0_iw_p2_speculative_child), .io_lsu_commit_uops_0_iw_p1_bypass_hint (_core_io_lsu_commit_uops_0_iw_p1_bypass_hint), .io_lsu_commit_uops_0_iw_p2_bypass_hint (_core_io_lsu_commit_uops_0_iw_p2_bypass_hint), .io_lsu_commit_uops_0_iw_p3_bypass_hint (_core_io_lsu_commit_uops_0_iw_p3_bypass_hint), .io_lsu_commit_uops_0_dis_col_sel (_core_io_lsu_commit_uops_0_dis_col_sel), .io_lsu_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), .io_lsu_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), .io_lsu_commit_uops_0_br_type (_core_io_lsu_commit_uops_0_br_type), .io_lsu_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), .io_lsu_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), .io_lsu_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), .io_lsu_commit_uops_0_is_sfence (_core_io_lsu_commit_uops_0_is_sfence), .io_lsu_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), .io_lsu_commit_uops_0_is_eret (_core_io_lsu_commit_uops_0_is_eret), .io_lsu_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), .io_lsu_commit_uops_0_is_rocc (_core_io_lsu_commit_uops_0_is_rocc), .io_lsu_commit_uops_0_is_mov (_core_io_lsu_commit_uops_0_is_mov), .io_lsu_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), .io_lsu_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), .io_lsu_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), .io_lsu_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), .io_lsu_commit_uops_0_imm_rename (_core_io_lsu_commit_uops_0_imm_rename), .io_lsu_commit_uops_0_imm_sel (_core_io_lsu_commit_uops_0_imm_sel), .io_lsu_commit_uops_0_pimm (_core_io_lsu_commit_uops_0_pimm), .io_lsu_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), .io_lsu_commit_uops_0_op1_sel (_core_io_lsu_commit_uops_0_op1_sel), .io_lsu_commit_uops_0_op2_sel (_core_io_lsu_commit_uops_0_op2_sel), .io_lsu_commit_uops_0_fp_ctrl_ldst (_core_io_lsu_commit_uops_0_fp_ctrl_ldst), .io_lsu_commit_uops_0_fp_ctrl_wen (_core_io_lsu_commit_uops_0_fp_ctrl_wen), .io_lsu_commit_uops_0_fp_ctrl_ren1 (_core_io_lsu_commit_uops_0_fp_ctrl_ren1), .io_lsu_commit_uops_0_fp_ctrl_ren2 (_core_io_lsu_commit_uops_0_fp_ctrl_ren2), .io_lsu_commit_uops_0_fp_ctrl_ren3 (_core_io_lsu_commit_uops_0_fp_ctrl_ren3), .io_lsu_commit_uops_0_fp_ctrl_swap12 (_core_io_lsu_commit_uops_0_fp_ctrl_swap12), .io_lsu_commit_uops_0_fp_ctrl_swap23 (_core_io_lsu_commit_uops_0_fp_ctrl_swap23), .io_lsu_commit_uops_0_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagIn), .io_lsu_commit_uops_0_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagOut), .io_lsu_commit_uops_0_fp_ctrl_fromint (_core_io_lsu_commit_uops_0_fp_ctrl_fromint), .io_lsu_commit_uops_0_fp_ctrl_toint (_core_io_lsu_commit_uops_0_fp_ctrl_toint), .io_lsu_commit_uops_0_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_0_fp_ctrl_fastpipe), .io_lsu_commit_uops_0_fp_ctrl_fma (_core_io_lsu_commit_uops_0_fp_ctrl_fma), .io_lsu_commit_uops_0_fp_ctrl_div (_core_io_lsu_commit_uops_0_fp_ctrl_div), .io_lsu_commit_uops_0_fp_ctrl_sqrt (_core_io_lsu_commit_uops_0_fp_ctrl_sqrt), .io_lsu_commit_uops_0_fp_ctrl_wflags (_core_io_lsu_commit_uops_0_fp_ctrl_wflags), .io_lsu_commit_uops_0_fp_ctrl_vec (_core_io_lsu_commit_uops_0_fp_ctrl_vec), .io_lsu_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), .io_lsu_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), .io_lsu_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), .io_lsu_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), .io_lsu_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), .io_lsu_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), .io_lsu_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), .io_lsu_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), .io_lsu_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), .io_lsu_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), .io_lsu_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), .io_lsu_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), .io_lsu_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), .io_lsu_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), .io_lsu_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), .io_lsu_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), .io_lsu_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), .io_lsu_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), .io_lsu_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), .io_lsu_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), .io_lsu_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), .io_lsu_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), .io_lsu_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), .io_lsu_commit_uops_0_csr_cmd (_core_io_lsu_commit_uops_0_csr_cmd), .io_lsu_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), .io_lsu_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), .io_lsu_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), .io_lsu_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), .io_lsu_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), .io_lsu_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), .io_lsu_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), .io_lsu_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), .io_lsu_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), .io_lsu_commit_uops_0_fcn_dw (_core_io_lsu_commit_uops_0_fcn_dw), .io_lsu_commit_uops_0_fcn_op (_core_io_lsu_commit_uops_0_fcn_op), .io_lsu_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), .io_lsu_commit_uops_0_fp_rm (_core_io_lsu_commit_uops_0_fp_rm), .io_lsu_commit_uops_0_fp_typ (_core_io_lsu_commit_uops_0_fp_typ), .io_lsu_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), .io_lsu_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), .io_lsu_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), .io_lsu_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), .io_lsu_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), .io_lsu_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), .io_lsu_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), .io_lsu_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), .io_lsu_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), .io_lsu_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), .io_lsu_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), .io_lsu_commit_uops_1_iq_type_0 (_core_io_lsu_commit_uops_1_iq_type_0), .io_lsu_commit_uops_1_iq_type_1 (_core_io_lsu_commit_uops_1_iq_type_1), .io_lsu_commit_uops_1_iq_type_2 (_core_io_lsu_commit_uops_1_iq_type_2), .io_lsu_commit_uops_1_iq_type_3 (_core_io_lsu_commit_uops_1_iq_type_3), .io_lsu_commit_uops_1_fu_code_0 (_core_io_lsu_commit_uops_1_fu_code_0), .io_lsu_commit_uops_1_fu_code_1 (_core_io_lsu_commit_uops_1_fu_code_1), .io_lsu_commit_uops_1_fu_code_2 (_core_io_lsu_commit_uops_1_fu_code_2), .io_lsu_commit_uops_1_fu_code_3 (_core_io_lsu_commit_uops_1_fu_code_3), .io_lsu_commit_uops_1_fu_code_4 (_core_io_lsu_commit_uops_1_fu_code_4), .io_lsu_commit_uops_1_fu_code_5 (_core_io_lsu_commit_uops_1_fu_code_5), .io_lsu_commit_uops_1_fu_code_6 (_core_io_lsu_commit_uops_1_fu_code_6), .io_lsu_commit_uops_1_fu_code_7 (_core_io_lsu_commit_uops_1_fu_code_7), .io_lsu_commit_uops_1_fu_code_8 (_core_io_lsu_commit_uops_1_fu_code_8), .io_lsu_commit_uops_1_fu_code_9 (_core_io_lsu_commit_uops_1_fu_code_9), .io_lsu_commit_uops_1_iw_issued (_core_io_lsu_commit_uops_1_iw_issued), .io_lsu_commit_uops_1_iw_issued_partial_agen (_core_io_lsu_commit_uops_1_iw_issued_partial_agen), .io_lsu_commit_uops_1_iw_issued_partial_dgen (_core_io_lsu_commit_uops_1_iw_issued_partial_dgen), .io_lsu_commit_uops_1_iw_p1_speculative_child (_core_io_lsu_commit_uops_1_iw_p1_speculative_child), .io_lsu_commit_uops_1_iw_p2_speculative_child (_core_io_lsu_commit_uops_1_iw_p2_speculative_child), .io_lsu_commit_uops_1_iw_p1_bypass_hint (_core_io_lsu_commit_uops_1_iw_p1_bypass_hint), .io_lsu_commit_uops_1_iw_p2_bypass_hint (_core_io_lsu_commit_uops_1_iw_p2_bypass_hint), .io_lsu_commit_uops_1_iw_p3_bypass_hint (_core_io_lsu_commit_uops_1_iw_p3_bypass_hint), .io_lsu_commit_uops_1_dis_col_sel (_core_io_lsu_commit_uops_1_dis_col_sel), .io_lsu_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), .io_lsu_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), .io_lsu_commit_uops_1_br_type (_core_io_lsu_commit_uops_1_br_type), .io_lsu_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), .io_lsu_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), .io_lsu_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), .io_lsu_commit_uops_1_is_sfence (_core_io_lsu_commit_uops_1_is_sfence), .io_lsu_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), .io_lsu_commit_uops_1_is_eret (_core_io_lsu_commit_uops_1_is_eret), .io_lsu_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), .io_lsu_commit_uops_1_is_rocc (_core_io_lsu_commit_uops_1_is_rocc), .io_lsu_commit_uops_1_is_mov (_core_io_lsu_commit_uops_1_is_mov), .io_lsu_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), .io_lsu_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), .io_lsu_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), .io_lsu_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), .io_lsu_commit_uops_1_imm_rename (_core_io_lsu_commit_uops_1_imm_rename), .io_lsu_commit_uops_1_imm_sel (_core_io_lsu_commit_uops_1_imm_sel), .io_lsu_commit_uops_1_pimm (_core_io_lsu_commit_uops_1_pimm), .io_lsu_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), .io_lsu_commit_uops_1_op1_sel (_core_io_lsu_commit_uops_1_op1_sel), .io_lsu_commit_uops_1_op2_sel (_core_io_lsu_commit_uops_1_op2_sel), .io_lsu_commit_uops_1_fp_ctrl_ldst (_core_io_lsu_commit_uops_1_fp_ctrl_ldst), .io_lsu_commit_uops_1_fp_ctrl_wen (_core_io_lsu_commit_uops_1_fp_ctrl_wen), .io_lsu_commit_uops_1_fp_ctrl_ren1 (_core_io_lsu_commit_uops_1_fp_ctrl_ren1), .io_lsu_commit_uops_1_fp_ctrl_ren2 (_core_io_lsu_commit_uops_1_fp_ctrl_ren2), .io_lsu_commit_uops_1_fp_ctrl_ren3 (_core_io_lsu_commit_uops_1_fp_ctrl_ren3), .io_lsu_commit_uops_1_fp_ctrl_swap12 (_core_io_lsu_commit_uops_1_fp_ctrl_swap12), .io_lsu_commit_uops_1_fp_ctrl_swap23 (_core_io_lsu_commit_uops_1_fp_ctrl_swap23), .io_lsu_commit_uops_1_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagIn), .io_lsu_commit_uops_1_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagOut), .io_lsu_commit_uops_1_fp_ctrl_fromint (_core_io_lsu_commit_uops_1_fp_ctrl_fromint), .io_lsu_commit_uops_1_fp_ctrl_toint (_core_io_lsu_commit_uops_1_fp_ctrl_toint), .io_lsu_commit_uops_1_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_1_fp_ctrl_fastpipe), .io_lsu_commit_uops_1_fp_ctrl_fma (_core_io_lsu_commit_uops_1_fp_ctrl_fma), .io_lsu_commit_uops_1_fp_ctrl_div (_core_io_lsu_commit_uops_1_fp_ctrl_div), .io_lsu_commit_uops_1_fp_ctrl_sqrt (_core_io_lsu_commit_uops_1_fp_ctrl_sqrt), .io_lsu_commit_uops_1_fp_ctrl_wflags (_core_io_lsu_commit_uops_1_fp_ctrl_wflags), .io_lsu_commit_uops_1_fp_ctrl_vec (_core_io_lsu_commit_uops_1_fp_ctrl_vec), .io_lsu_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), .io_lsu_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), .io_lsu_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), .io_lsu_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), .io_lsu_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), .io_lsu_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), .io_lsu_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), .io_lsu_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), .io_lsu_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), .io_lsu_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), .io_lsu_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), .io_lsu_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), .io_lsu_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), .io_lsu_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), .io_lsu_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), .io_lsu_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), .io_lsu_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), .io_lsu_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), .io_lsu_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), .io_lsu_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), .io_lsu_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), .io_lsu_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), .io_lsu_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), .io_lsu_commit_uops_1_csr_cmd (_core_io_lsu_commit_uops_1_csr_cmd), .io_lsu_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), .io_lsu_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), .io_lsu_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), .io_lsu_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), .io_lsu_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), .io_lsu_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), .io_lsu_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), .io_lsu_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), .io_lsu_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), .io_lsu_commit_uops_1_fcn_dw (_core_io_lsu_commit_uops_1_fcn_dw), .io_lsu_commit_uops_1_fcn_op (_core_io_lsu_commit_uops_1_fcn_op), .io_lsu_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), .io_lsu_commit_uops_1_fp_rm (_core_io_lsu_commit_uops_1_fp_rm), .io_lsu_commit_uops_1_fp_typ (_core_io_lsu_commit_uops_1_fp_typ), .io_lsu_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), .io_lsu_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), .io_lsu_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), .io_lsu_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), .io_lsu_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), .io_lsu_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), .io_lsu_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), .io_lsu_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), .io_lsu_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), .io_lsu_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), .io_lsu_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), .io_lsu_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), .io_lsu_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), // @[tile.scala:159:20] .io_lsu_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), // @[tile.scala:159:20] .io_lsu_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), // @[tile.scala:159:20] .io_lsu_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), // @[tile.scala:159:20] .io_lsu_clr_unsafe_0_valid (_lsu_io_core_clr_unsafe_0_valid), // @[tile.scala:159:20] .io_lsu_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), // @[tile.scala:159:20] .io_lsu_fence_dmem (_core_io_lsu_fence_dmem), .io_lsu_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), .io_lsu_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), .io_lsu_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), .io_lsu_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), .io_lsu_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), .io_lsu_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), .io_lsu_brupdate_b2_uop_iq_type_0 (_core_io_lsu_brupdate_b2_uop_iq_type_0), .io_lsu_brupdate_b2_uop_iq_type_1 (_core_io_lsu_brupdate_b2_uop_iq_type_1), .io_lsu_brupdate_b2_uop_iq_type_2 (_core_io_lsu_brupdate_b2_uop_iq_type_2), .io_lsu_brupdate_b2_uop_iq_type_3 (_core_io_lsu_brupdate_b2_uop_iq_type_3), .io_lsu_brupdate_b2_uop_fu_code_0 (_core_io_lsu_brupdate_b2_uop_fu_code_0), .io_lsu_brupdate_b2_uop_fu_code_1 (_core_io_lsu_brupdate_b2_uop_fu_code_1), .io_lsu_brupdate_b2_uop_fu_code_2 (_core_io_lsu_brupdate_b2_uop_fu_code_2), .io_lsu_brupdate_b2_uop_fu_code_3 (_core_io_lsu_brupdate_b2_uop_fu_code_3), .io_lsu_brupdate_b2_uop_fu_code_4 (_core_io_lsu_brupdate_b2_uop_fu_code_4), .io_lsu_brupdate_b2_uop_fu_code_5 (_core_io_lsu_brupdate_b2_uop_fu_code_5), .io_lsu_brupdate_b2_uop_fu_code_6 (_core_io_lsu_brupdate_b2_uop_fu_code_6), .io_lsu_brupdate_b2_uop_fu_code_7 (_core_io_lsu_brupdate_b2_uop_fu_code_7), .io_lsu_brupdate_b2_uop_fu_code_8 (_core_io_lsu_brupdate_b2_uop_fu_code_8), .io_lsu_brupdate_b2_uop_fu_code_9 (_core_io_lsu_brupdate_b2_uop_fu_code_9), .io_lsu_brupdate_b2_uop_iw_issued (_core_io_lsu_brupdate_b2_uop_iw_issued), .io_lsu_brupdate_b2_uop_iw_issued_partial_agen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_agen), .io_lsu_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_dgen), .io_lsu_brupdate_b2_uop_iw_p1_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p1_speculative_child), .io_lsu_brupdate_b2_uop_iw_p2_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p2_speculative_child), .io_lsu_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p1_bypass_hint), .io_lsu_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p2_bypass_hint), .io_lsu_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p3_bypass_hint), .io_lsu_brupdate_b2_uop_dis_col_sel (_core_io_lsu_brupdate_b2_uop_dis_col_sel), .io_lsu_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), .io_lsu_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), .io_lsu_brupdate_b2_uop_br_type (_core_io_lsu_brupdate_b2_uop_br_type), .io_lsu_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), .io_lsu_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), .io_lsu_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), .io_lsu_brupdate_b2_uop_is_sfence (_core_io_lsu_brupdate_b2_uop_is_sfence), .io_lsu_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), .io_lsu_brupdate_b2_uop_is_eret (_core_io_lsu_brupdate_b2_uop_is_eret), .io_lsu_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), .io_lsu_brupdate_b2_uop_is_rocc (_core_io_lsu_brupdate_b2_uop_is_rocc), .io_lsu_brupdate_b2_uop_is_mov (_core_io_lsu_brupdate_b2_uop_is_mov), .io_lsu_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), .io_lsu_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), .io_lsu_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), .io_lsu_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), .io_lsu_brupdate_b2_uop_imm_rename (_core_io_lsu_brupdate_b2_uop_imm_rename), .io_lsu_brupdate_b2_uop_imm_sel (_core_io_lsu_brupdate_b2_uop_imm_sel), .io_lsu_brupdate_b2_uop_pimm (_core_io_lsu_brupdate_b2_uop_pimm), .io_lsu_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), .io_lsu_brupdate_b2_uop_op1_sel (_core_io_lsu_brupdate_b2_uop_op1_sel), .io_lsu_brupdate_b2_uop_op2_sel (_core_io_lsu_brupdate_b2_uop_op2_sel), .io_lsu_brupdate_b2_uop_fp_ctrl_ldst (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ldst), .io_lsu_brupdate_b2_uop_fp_ctrl_wen (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wen), .io_lsu_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren1), .io_lsu_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren2), .io_lsu_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren3), .io_lsu_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap12), .io_lsu_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap23), .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn), .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut), .io_lsu_brupdate_b2_uop_fp_ctrl_fromint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fromint), .io_lsu_brupdate_b2_uop_fp_ctrl_toint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_toint), .io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe), .io_lsu_brupdate_b2_uop_fp_ctrl_fma (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fma), .io_lsu_brupdate_b2_uop_fp_ctrl_div (_core_io_lsu_brupdate_b2_uop_fp_ctrl_div), .io_lsu_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_lsu_brupdate_b2_uop_fp_ctrl_sqrt), .io_lsu_brupdate_b2_uop_fp_ctrl_wflags (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wflags), .io_lsu_brupdate_b2_uop_fp_ctrl_vec (_core_io_lsu_brupdate_b2_uop_fp_ctrl_vec), .io_lsu_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), .io_lsu_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), .io_lsu_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), .io_lsu_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), .io_lsu_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), .io_lsu_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), .io_lsu_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), .io_lsu_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), .io_lsu_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), .io_lsu_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), .io_lsu_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), .io_lsu_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), .io_lsu_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), .io_lsu_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), .io_lsu_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), .io_lsu_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), .io_lsu_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), .io_lsu_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), .io_lsu_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), .io_lsu_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), .io_lsu_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), .io_lsu_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), .io_lsu_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), .io_lsu_brupdate_b2_uop_csr_cmd (_core_io_lsu_brupdate_b2_uop_csr_cmd), .io_lsu_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), .io_lsu_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), .io_lsu_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), .io_lsu_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), .io_lsu_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), .io_lsu_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), .io_lsu_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), .io_lsu_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), .io_lsu_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), .io_lsu_brupdate_b2_uop_fcn_dw (_core_io_lsu_brupdate_b2_uop_fcn_dw), .io_lsu_brupdate_b2_uop_fcn_op (_core_io_lsu_brupdate_b2_uop_fcn_op), .io_lsu_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), .io_lsu_brupdate_b2_uop_fp_rm (_core_io_lsu_brupdate_b2_uop_fp_rm), .io_lsu_brupdate_b2_uop_fp_typ (_core_io_lsu_brupdate_b2_uop_fp_typ), .io_lsu_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), .io_lsu_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), .io_lsu_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), .io_lsu_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), .io_lsu_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), .io_lsu_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), .io_lsu_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), .io_lsu_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), .io_lsu_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), .io_lsu_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), .io_lsu_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), .io_lsu_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), .io_lsu_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), .io_lsu_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), .io_lsu_rob_head_idx (_core_io_lsu_rob_head_idx), .io_lsu_exception (_core_io_lsu_exception), .io_lsu_fencei_rdy (_lsu_io_core_fencei_rdy), // @[tile.scala:159:20] .io_lsu_lxcpt_valid (_lsu_io_core_lxcpt_valid), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_0 (_lsu_io_core_lxcpt_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_1 (_lsu_io_core_lxcpt_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_2 (_lsu_io_core_lxcpt_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_3 (_lsu_io_core_lxcpt_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_0 (_lsu_io_core_lxcpt_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_1 (_lsu_io_core_lxcpt_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_2 (_lsu_io_core_lxcpt_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_3 (_lsu_io_core_lxcpt_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_4 (_lsu_io_core_lxcpt_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_5 (_lsu_io_core_lxcpt_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_6 (_lsu_io_core_lxcpt_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_7 (_lsu_io_core_lxcpt_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_8 (_lsu_io_core_lxcpt_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_9 (_lsu_io_core_lxcpt_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_issued (_lsu_io_core_lxcpt_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_issued_partial_agen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p1_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p2_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_dis_col_sel (_lsu_io_core_lxcpt_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_br_type (_lsu_io_core_lxcpt_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_sfence (_lsu_io_core_lxcpt_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_eret (_lsu_io_core_lxcpt_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_rocc (_lsu_io_core_lxcpt_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_mov (_lsu_io_core_lxcpt_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_imm_rename (_lsu_io_core_lxcpt_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_imm_sel (_lsu_io_core_lxcpt_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_pimm (_lsu_io_core_lxcpt_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_op1_sel (_lsu_io_core_lxcpt_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_op2_sel (_lsu_io_core_lxcpt_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ldst (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_wen (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ren1 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ren2 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ren3 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_swap12 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_swap23 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_fromint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_toint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_fma (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_div (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_wflags (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_vec (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_csr_cmd (_lsu_io_core_lxcpt_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fcn_dw (_lsu_io_core_lxcpt_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fcn_op (_lsu_io_core_lxcpt_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_rm (_lsu_io_core_lxcpt_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_typ (_lsu_io_core_lxcpt_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), // @[tile.scala:159:20] .io_lsu_tsc_reg (_core_io_lsu_tsc_reg), .io_lsu_status_debug (_core_io_lsu_status_debug), .io_lsu_status_cease (_core_io_lsu_status_cease), .io_lsu_status_wfi (_core_io_lsu_status_wfi), .io_lsu_status_dprv (_core_io_lsu_status_dprv), .io_lsu_status_dv (_core_io_lsu_status_dv), .io_lsu_status_prv (_core_io_lsu_status_prv), .io_lsu_status_v (_core_io_lsu_status_v), .io_lsu_status_sd (_core_io_lsu_status_sd), .io_lsu_status_mpv (_core_io_lsu_status_mpv), .io_lsu_status_gva (_core_io_lsu_status_gva), .io_lsu_status_tsr (_core_io_lsu_status_tsr), .io_lsu_status_tw (_core_io_lsu_status_tw), .io_lsu_status_tvm (_core_io_lsu_status_tvm), .io_lsu_status_mxr (_core_io_lsu_status_mxr), .io_lsu_status_sum (_core_io_lsu_status_sum), .io_lsu_status_mprv (_core_io_lsu_status_mprv), .io_lsu_status_fs (_core_io_lsu_status_fs), .io_lsu_status_mpp (_core_io_lsu_status_mpp), .io_lsu_status_spp (_core_io_lsu_status_spp), .io_lsu_status_mpie (_core_io_lsu_status_mpie), .io_lsu_status_spie (_core_io_lsu_status_spie), .io_lsu_status_mie (_core_io_lsu_status_mie), .io_lsu_status_sie (_core_io_lsu_status_sie), .io_lsu_perf_acquire (_lsu_io_core_perf_acquire), // @[tile.scala:159:20] .io_lsu_perf_release (_lsu_io_core_perf_release), // @[tile.scala:159:20] .io_lsu_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), // @[tile.scala:159:20] .io_ptw_tlb_req_ready (_ptw_io_requestor_2_req_ready), // @[tile.scala:236:20] .io_ptw_tlb_resp_valid (_ptw_io_requestor_2_resp_valid), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[tile.scala:236:20] .io_ptw_tlb_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[tile.scala:236:20] .io_ptw_tlb_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[tile.scala:236:20] .io_ptw_tlb_status_debug (_ptw_io_requestor_2_status_debug), // @[tile.scala:236:20] .io_ptw_tlb_status_cease (_ptw_io_requestor_2_status_cease), // @[tile.scala:236:20] .io_ptw_tlb_status_wfi (_ptw_io_requestor_2_status_wfi), // @[tile.scala:236:20] .io_ptw_tlb_status_dprv (_ptw_io_requestor_2_status_dprv), // @[tile.scala:236:20] .io_ptw_tlb_status_dv (_ptw_io_requestor_2_status_dv), // @[tile.scala:236:20] .io_ptw_tlb_status_prv (_ptw_io_requestor_2_status_prv), // @[tile.scala:236:20] .io_ptw_tlb_status_v (_ptw_io_requestor_2_status_v), // @[tile.scala:236:20] .io_ptw_tlb_status_sd (_ptw_io_requestor_2_status_sd), // @[tile.scala:236:20] .io_ptw_tlb_status_mpv (_ptw_io_requestor_2_status_mpv), // @[tile.scala:236:20] .io_ptw_tlb_status_gva (_ptw_io_requestor_2_status_gva), // @[tile.scala:236:20] .io_ptw_tlb_status_tsr (_ptw_io_requestor_2_status_tsr), // @[tile.scala:236:20] .io_ptw_tlb_status_tw (_ptw_io_requestor_2_status_tw), // @[tile.scala:236:20] .io_ptw_tlb_status_tvm (_ptw_io_requestor_2_status_tvm), // @[tile.scala:236:20] .io_ptw_tlb_status_mxr (_ptw_io_requestor_2_status_mxr), // @[tile.scala:236:20] .io_ptw_tlb_status_sum (_ptw_io_requestor_2_status_sum), // @[tile.scala:236:20] .io_ptw_tlb_status_mprv (_ptw_io_requestor_2_status_mprv), // @[tile.scala:236:20] .io_ptw_tlb_status_fs (_ptw_io_requestor_2_status_fs), // @[tile.scala:236:20] .io_ptw_tlb_status_mpp (_ptw_io_requestor_2_status_mpp), // @[tile.scala:236:20] .io_ptw_tlb_status_spp (_ptw_io_requestor_2_status_spp), // @[tile.scala:236:20] .io_ptw_tlb_status_mpie (_ptw_io_requestor_2_status_mpie), // @[tile.scala:236:20] .io_ptw_tlb_status_spie (_ptw_io_requestor_2_status_spie), // @[tile.scala:236:20] .io_ptw_tlb_status_mie (_ptw_io_requestor_2_status_mie), // @[tile.scala:236:20] .io_ptw_tlb_status_sie (_ptw_io_requestor_2_status_sie), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[tile.scala:236:20] .io_trace_time (traceSourceNodeOut_time), .io_trace_custom_rob_empty (traceSourceNodeOut_custom_rob_empty) ); // @[tile.scala:158:20] LSU lsu ( // @[tile.scala:159:20] .clock (clock), .reset (reset), .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[tile.scala:236:20] .io_ptw_req_valid (_lsu_io_ptw_req_valid), .io_ptw_req_bits_valid (_lsu_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[tile.scala:236:20] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[tile.scala:236:20] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[tile.scala:236:20] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[tile.scala:236:20] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[tile.scala:236:20] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[tile.scala:236:20] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[tile.scala:236:20] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[tile.scala:236:20] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[tile.scala:236:20] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[tile.scala:236:20] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[tile.scala:236:20] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[tile.scala:236:20] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[tile.scala:236:20] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[tile.scala:236:20] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[tile.scala:236:20] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[tile.scala:236:20] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[tile.scala:236:20] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[tile.scala:236:20] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[tile.scala:236:20] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[tile.scala:236:20] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[tile.scala:236:20] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[tile.scala:236:20] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[tile.scala:236:20] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[tile.scala:236:20] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[tile.scala:236:20] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[tile.scala:236:20] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[tile.scala:236:20] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[tile.scala:236:20] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[tile.scala:236:20] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[tile.scala:236:20] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[tile.scala:236:20] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[tile.scala:236:20] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[tile.scala:236:20] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[tile.scala:236:20] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[tile.scala:236:20] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[tile.scala:236:20] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[tile.scala:236:20] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[tile.scala:236:20] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[tile.scala:236:20] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[tile.scala:236:20] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[tile.scala:236:20] .io_core_agen_0_valid (_core_io_lsu_agen_0_valid), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_inst (_core_io_lsu_agen_0_bits_uop_inst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_inst (_core_io_lsu_agen_0_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_rvc (_core_io_lsu_agen_0_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_pc (_core_io_lsu_agen_0_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_0 (_core_io_lsu_agen_0_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_1 (_core_io_lsu_agen_0_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_2 (_core_io_lsu_agen_0_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_3 (_core_io_lsu_agen_0_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_0 (_core_io_lsu_agen_0_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_1 (_core_io_lsu_agen_0_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_2 (_core_io_lsu_agen_0_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_3 (_core_io_lsu_agen_0_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_4 (_core_io_lsu_agen_0_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_5 (_core_io_lsu_agen_0_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_6 (_core_io_lsu_agen_0_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_7 (_core_io_lsu_agen_0_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_8 (_core_io_lsu_agen_0_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_9 (_core_io_lsu_agen_0_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_issued (_core_io_lsu_agen_0_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_dis_col_sel (_core_io_lsu_agen_0_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_br_mask (_core_io_lsu_agen_0_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_br_tag (_core_io_lsu_agen_0_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_br_type (_core_io_lsu_agen_0_bits_uop_br_type), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_sfb (_core_io_lsu_agen_0_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_fence (_core_io_lsu_agen_0_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_fencei (_core_io_lsu_agen_0_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_sfence (_core_io_lsu_agen_0_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_amo (_core_io_lsu_agen_0_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_eret (_core_io_lsu_agen_0_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_agen_0_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_rocc (_core_io_lsu_agen_0_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_mov (_core_io_lsu_agen_0_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ftq_idx (_core_io_lsu_agen_0_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_edge_inst (_core_io_lsu_agen_0_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_pc_lob (_core_io_lsu_agen_0_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_taken (_core_io_lsu_agen_0_bits_uop_taken), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_imm_rename (_core_io_lsu_agen_0_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_imm_sel (_core_io_lsu_agen_0_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_pimm (_core_io_lsu_agen_0_bits_uop_pimm), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_imm_packed (_core_io_lsu_agen_0_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_op1_sel (_core_io_lsu_agen_0_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_op2_sel (_core_io_lsu_agen_0_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_div (_core_io_lsu_agen_0_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_agen_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_agen_0_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_rob_idx (_core_io_lsu_agen_0_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ldq_idx (_core_io_lsu_agen_0_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_stq_idx (_core_io_lsu_agen_0_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_rxq_idx (_core_io_lsu_agen_0_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_pdst (_core_io_lsu_agen_0_bits_uop_pdst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs1 (_core_io_lsu_agen_0_bits_uop_prs1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs2 (_core_io_lsu_agen_0_bits_uop_prs2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs3 (_core_io_lsu_agen_0_bits_uop_prs3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ppred (_core_io_lsu_agen_0_bits_uop_ppred), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs1_busy (_core_io_lsu_agen_0_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs2_busy (_core_io_lsu_agen_0_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs3_busy (_core_io_lsu_agen_0_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ppred_busy (_core_io_lsu_agen_0_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_stale_pdst (_core_io_lsu_agen_0_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_exception (_core_io_lsu_agen_0_bits_uop_exception), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_exc_cause (_core_io_lsu_agen_0_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_mem_cmd (_core_io_lsu_agen_0_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_mem_size (_core_io_lsu_agen_0_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_mem_signed (_core_io_lsu_agen_0_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_uses_ldq (_core_io_lsu_agen_0_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_uses_stq (_core_io_lsu_agen_0_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_unique (_core_io_lsu_agen_0_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_flush_on_commit (_core_io_lsu_agen_0_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_csr_cmd (_core_io_lsu_agen_0_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_agen_0_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ldst (_core_io_lsu_agen_0_bits_uop_ldst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs1 (_core_io_lsu_agen_0_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs2 (_core_io_lsu_agen_0_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs3 (_core_io_lsu_agen_0_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_dst_rtype (_core_io_lsu_agen_0_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs1_rtype (_core_io_lsu_agen_0_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs2_rtype (_core_io_lsu_agen_0_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_frs3_en (_core_io_lsu_agen_0_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fcn_dw (_core_io_lsu_agen_0_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fcn_op (_core_io_lsu_agen_0_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_val (_core_io_lsu_agen_0_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_rm (_core_io_lsu_agen_0_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_typ (_core_io_lsu_agen_0_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_xcpt_pf_if (_core_io_lsu_agen_0_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_xcpt_ae_if (_core_io_lsu_agen_0_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_xcpt_ma_if (_core_io_lsu_agen_0_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_bp_debug_if (_core_io_lsu_agen_0_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_bp_xcpt_if (_core_io_lsu_agen_0_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_fsrc (_core_io_lsu_agen_0_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_tsrc (_core_io_lsu_agen_0_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_agen_0_bits_data (_core_io_lsu_agen_0_bits_data), // @[tile.scala:158:20] .io_core_dgen_0_valid (_core_io_lsu_dgen_0_valid), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_inst (_core_io_lsu_dgen_0_bits_uop_inst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_inst (_core_io_lsu_dgen_0_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_rvc (_core_io_lsu_dgen_0_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_pc (_core_io_lsu_dgen_0_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_0 (_core_io_lsu_dgen_0_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_1 (_core_io_lsu_dgen_0_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_2 (_core_io_lsu_dgen_0_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_3 (_core_io_lsu_dgen_0_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_0 (_core_io_lsu_dgen_0_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_1 (_core_io_lsu_dgen_0_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_2 (_core_io_lsu_dgen_0_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_3 (_core_io_lsu_dgen_0_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_4 (_core_io_lsu_dgen_0_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_5 (_core_io_lsu_dgen_0_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_6 (_core_io_lsu_dgen_0_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_7 (_core_io_lsu_dgen_0_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_8 (_core_io_lsu_dgen_0_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_9 (_core_io_lsu_dgen_0_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_issued (_core_io_lsu_dgen_0_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_dis_col_sel (_core_io_lsu_dgen_0_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_br_mask (_core_io_lsu_dgen_0_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_br_tag (_core_io_lsu_dgen_0_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_br_type (_core_io_lsu_dgen_0_bits_uop_br_type), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_sfb (_core_io_lsu_dgen_0_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_fence (_core_io_lsu_dgen_0_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_fencei (_core_io_lsu_dgen_0_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_sfence (_core_io_lsu_dgen_0_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_amo (_core_io_lsu_dgen_0_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_eret (_core_io_lsu_dgen_0_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_0_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_rocc (_core_io_lsu_dgen_0_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_mov (_core_io_lsu_dgen_0_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ftq_idx (_core_io_lsu_dgen_0_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_edge_inst (_core_io_lsu_dgen_0_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_pc_lob (_core_io_lsu_dgen_0_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_taken (_core_io_lsu_dgen_0_bits_uop_taken), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_imm_rename (_core_io_lsu_dgen_0_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_imm_sel (_core_io_lsu_dgen_0_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_pimm (_core_io_lsu_dgen_0_bits_uop_pimm), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_imm_packed (_core_io_lsu_dgen_0_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_op1_sel (_core_io_lsu_dgen_0_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_op2_sel (_core_io_lsu_dgen_0_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_rob_idx (_core_io_lsu_dgen_0_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ldq_idx (_core_io_lsu_dgen_0_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_stq_idx (_core_io_lsu_dgen_0_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_rxq_idx (_core_io_lsu_dgen_0_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_pdst (_core_io_lsu_dgen_0_bits_uop_pdst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs1 (_core_io_lsu_dgen_0_bits_uop_prs1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs2 (_core_io_lsu_dgen_0_bits_uop_prs2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs3 (_core_io_lsu_dgen_0_bits_uop_prs3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ppred (_core_io_lsu_dgen_0_bits_uop_ppred), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs1_busy (_core_io_lsu_dgen_0_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs2_busy (_core_io_lsu_dgen_0_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs3_busy (_core_io_lsu_dgen_0_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ppred_busy (_core_io_lsu_dgen_0_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_stale_pdst (_core_io_lsu_dgen_0_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_exception (_core_io_lsu_dgen_0_bits_uop_exception), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_exc_cause (_core_io_lsu_dgen_0_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_mem_cmd (_core_io_lsu_dgen_0_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_mem_size (_core_io_lsu_dgen_0_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_mem_signed (_core_io_lsu_dgen_0_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_uses_ldq (_core_io_lsu_dgen_0_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_uses_stq (_core_io_lsu_dgen_0_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_unique (_core_io_lsu_dgen_0_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_flush_on_commit (_core_io_lsu_dgen_0_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_csr_cmd (_core_io_lsu_dgen_0_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_0_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ldst (_core_io_lsu_dgen_0_bits_uop_ldst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs1 (_core_io_lsu_dgen_0_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs2 (_core_io_lsu_dgen_0_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs3 (_core_io_lsu_dgen_0_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_dst_rtype (_core_io_lsu_dgen_0_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs1_rtype (_core_io_lsu_dgen_0_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs2_rtype (_core_io_lsu_dgen_0_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_frs3_en (_core_io_lsu_dgen_0_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fcn_dw (_core_io_lsu_dgen_0_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fcn_op (_core_io_lsu_dgen_0_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_val (_core_io_lsu_dgen_0_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_rm (_core_io_lsu_dgen_0_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_typ (_core_io_lsu_dgen_0_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_0_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_bp_debug_if (_core_io_lsu_dgen_0_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_0_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_fsrc (_core_io_lsu_dgen_0_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_tsrc (_core_io_lsu_dgen_0_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_dgen_0_bits_data (_core_io_lsu_dgen_0_bits_data), // @[tile.scala:158:20] .io_core_dgen_1_valid (_core_io_lsu_dgen_1_valid), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_inst (_core_io_lsu_dgen_1_bits_uop_inst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_inst (_core_io_lsu_dgen_1_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_rvc (_core_io_lsu_dgen_1_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_pc (_core_io_lsu_dgen_1_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_0 (_core_io_lsu_dgen_1_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_1 (_core_io_lsu_dgen_1_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_2 (_core_io_lsu_dgen_1_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_3 (_core_io_lsu_dgen_1_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_0 (_core_io_lsu_dgen_1_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_1 (_core_io_lsu_dgen_1_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_2 (_core_io_lsu_dgen_1_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_3 (_core_io_lsu_dgen_1_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_4 (_core_io_lsu_dgen_1_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_5 (_core_io_lsu_dgen_1_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_6 (_core_io_lsu_dgen_1_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_7 (_core_io_lsu_dgen_1_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_8 (_core_io_lsu_dgen_1_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_9 (_core_io_lsu_dgen_1_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_issued (_core_io_lsu_dgen_1_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_dis_col_sel (_core_io_lsu_dgen_1_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_br_mask (_core_io_lsu_dgen_1_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_br_tag (_core_io_lsu_dgen_1_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_br_type (_core_io_lsu_dgen_1_bits_uop_br_type), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_sfb (_core_io_lsu_dgen_1_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_fence (_core_io_lsu_dgen_1_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_fencei (_core_io_lsu_dgen_1_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_sfence (_core_io_lsu_dgen_1_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_amo (_core_io_lsu_dgen_1_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_eret (_core_io_lsu_dgen_1_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_1_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_rocc (_core_io_lsu_dgen_1_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_mov (_core_io_lsu_dgen_1_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ftq_idx (_core_io_lsu_dgen_1_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_edge_inst (_core_io_lsu_dgen_1_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_pc_lob (_core_io_lsu_dgen_1_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_taken (_core_io_lsu_dgen_1_bits_uop_taken), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_imm_rename (_core_io_lsu_dgen_1_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_imm_sel (_core_io_lsu_dgen_1_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_pimm (_core_io_lsu_dgen_1_bits_uop_pimm), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_imm_packed (_core_io_lsu_dgen_1_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_op1_sel (_core_io_lsu_dgen_1_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_op2_sel (_core_io_lsu_dgen_1_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_rob_idx (_core_io_lsu_dgen_1_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ldq_idx (_core_io_lsu_dgen_1_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_stq_idx (_core_io_lsu_dgen_1_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_rxq_idx (_core_io_lsu_dgen_1_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_pdst (_core_io_lsu_dgen_1_bits_uop_pdst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs1 (_core_io_lsu_dgen_1_bits_uop_prs1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs2 (_core_io_lsu_dgen_1_bits_uop_prs2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs3 (_core_io_lsu_dgen_1_bits_uop_prs3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ppred (_core_io_lsu_dgen_1_bits_uop_ppred), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs1_busy (_core_io_lsu_dgen_1_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs2_busy (_core_io_lsu_dgen_1_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs3_busy (_core_io_lsu_dgen_1_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ppred_busy (_core_io_lsu_dgen_1_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_stale_pdst (_core_io_lsu_dgen_1_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_exception (_core_io_lsu_dgen_1_bits_uop_exception), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_exc_cause (_core_io_lsu_dgen_1_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_mem_cmd (_core_io_lsu_dgen_1_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_mem_size (_core_io_lsu_dgen_1_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_mem_signed (_core_io_lsu_dgen_1_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_uses_ldq (_core_io_lsu_dgen_1_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_uses_stq (_core_io_lsu_dgen_1_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_unique (_core_io_lsu_dgen_1_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_flush_on_commit (_core_io_lsu_dgen_1_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_csr_cmd (_core_io_lsu_dgen_1_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_1_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ldst (_core_io_lsu_dgen_1_bits_uop_ldst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs1 (_core_io_lsu_dgen_1_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs2 (_core_io_lsu_dgen_1_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs3 (_core_io_lsu_dgen_1_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_dst_rtype (_core_io_lsu_dgen_1_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs1_rtype (_core_io_lsu_dgen_1_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs2_rtype (_core_io_lsu_dgen_1_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_frs3_en (_core_io_lsu_dgen_1_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fcn_dw (_core_io_lsu_dgen_1_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fcn_op (_core_io_lsu_dgen_1_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_val (_core_io_lsu_dgen_1_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_rm (_core_io_lsu_dgen_1_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_typ (_core_io_lsu_dgen_1_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_1_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_bp_debug_if (_core_io_lsu_dgen_1_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_1_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_fsrc (_core_io_lsu_dgen_1_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_tsrc (_core_io_lsu_dgen_1_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_dgen_1_bits_data (_core_io_lsu_dgen_1_bits_data), // @[tile.scala:158:20] .io_core_dgen_2_valid (_core_io_lsu_dgen_2_valid), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_inst (_core_io_lsu_dgen_2_bits_uop_inst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_inst (_core_io_lsu_dgen_2_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_rvc (_core_io_lsu_dgen_2_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_pc (_core_io_lsu_dgen_2_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_0 (_core_io_lsu_dgen_2_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_1 (_core_io_lsu_dgen_2_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_2 (_core_io_lsu_dgen_2_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_3 (_core_io_lsu_dgen_2_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_0 (_core_io_lsu_dgen_2_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_1 (_core_io_lsu_dgen_2_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_2 (_core_io_lsu_dgen_2_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_3 (_core_io_lsu_dgen_2_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_4 (_core_io_lsu_dgen_2_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_5 (_core_io_lsu_dgen_2_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_6 (_core_io_lsu_dgen_2_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_7 (_core_io_lsu_dgen_2_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_8 (_core_io_lsu_dgen_2_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_9 (_core_io_lsu_dgen_2_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_issued (_core_io_lsu_dgen_2_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_dis_col_sel (_core_io_lsu_dgen_2_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_br_mask (_core_io_lsu_dgen_2_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_br_tag (_core_io_lsu_dgen_2_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_br_type (_core_io_lsu_dgen_2_bits_uop_br_type), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_sfb (_core_io_lsu_dgen_2_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_fence (_core_io_lsu_dgen_2_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_fencei (_core_io_lsu_dgen_2_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_sfence (_core_io_lsu_dgen_2_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_amo (_core_io_lsu_dgen_2_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_eret (_core_io_lsu_dgen_2_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_2_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_rocc (_core_io_lsu_dgen_2_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_mov (_core_io_lsu_dgen_2_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ftq_idx (_core_io_lsu_dgen_2_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_edge_inst (_core_io_lsu_dgen_2_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_pc_lob (_core_io_lsu_dgen_2_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_taken (_core_io_lsu_dgen_2_bits_uop_taken), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_imm_rename (_core_io_lsu_dgen_2_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_imm_sel (_core_io_lsu_dgen_2_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_pimm (_core_io_lsu_dgen_2_bits_uop_pimm), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_imm_packed (_core_io_lsu_dgen_2_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_op1_sel (_core_io_lsu_dgen_2_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_op2_sel (_core_io_lsu_dgen_2_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_rob_idx (_core_io_lsu_dgen_2_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ldq_idx (_core_io_lsu_dgen_2_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_stq_idx (_core_io_lsu_dgen_2_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_rxq_idx (_core_io_lsu_dgen_2_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_pdst (_core_io_lsu_dgen_2_bits_uop_pdst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs1 (_core_io_lsu_dgen_2_bits_uop_prs1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs2 (_core_io_lsu_dgen_2_bits_uop_prs2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs3 (_core_io_lsu_dgen_2_bits_uop_prs3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ppred (_core_io_lsu_dgen_2_bits_uop_ppred), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs1_busy (_core_io_lsu_dgen_2_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs2_busy (_core_io_lsu_dgen_2_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs3_busy (_core_io_lsu_dgen_2_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ppred_busy (_core_io_lsu_dgen_2_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_stale_pdst (_core_io_lsu_dgen_2_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_exception (_core_io_lsu_dgen_2_bits_uop_exception), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_exc_cause (_core_io_lsu_dgen_2_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_mem_cmd (_core_io_lsu_dgen_2_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_mem_size (_core_io_lsu_dgen_2_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_mem_signed (_core_io_lsu_dgen_2_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_uses_ldq (_core_io_lsu_dgen_2_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_uses_stq (_core_io_lsu_dgen_2_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_unique (_core_io_lsu_dgen_2_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_flush_on_commit (_core_io_lsu_dgen_2_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_csr_cmd (_core_io_lsu_dgen_2_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_2_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ldst (_core_io_lsu_dgen_2_bits_uop_ldst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs1 (_core_io_lsu_dgen_2_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs2 (_core_io_lsu_dgen_2_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs3 (_core_io_lsu_dgen_2_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_dst_rtype (_core_io_lsu_dgen_2_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs1_rtype (_core_io_lsu_dgen_2_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs2_rtype (_core_io_lsu_dgen_2_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_frs3_en (_core_io_lsu_dgen_2_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fcn_dw (_core_io_lsu_dgen_2_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fcn_op (_core_io_lsu_dgen_2_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_val (_core_io_lsu_dgen_2_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_rm (_core_io_lsu_dgen_2_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_typ (_core_io_lsu_dgen_2_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_2_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_bp_debug_if (_core_io_lsu_dgen_2_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_2_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_fsrc (_core_io_lsu_dgen_2_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_tsrc (_core_io_lsu_dgen_2_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_dgen_2_bits_data (_core_io_lsu_dgen_2_bits_data), // @[tile.scala:158:20] .io_core_iwakeups_0_valid (_lsu_io_core_iwakeups_0_valid), .io_core_iwakeups_0_bits_uop_inst (_lsu_io_core_iwakeups_0_bits_uop_inst), .io_core_iwakeups_0_bits_uop_debug_inst (_lsu_io_core_iwakeups_0_bits_uop_debug_inst), .io_core_iwakeups_0_bits_uop_is_rvc (_lsu_io_core_iwakeups_0_bits_uop_is_rvc), .io_core_iwakeups_0_bits_uop_debug_pc (_lsu_io_core_iwakeups_0_bits_uop_debug_pc), .io_core_iwakeups_0_bits_uop_iq_type_0 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_0), .io_core_iwakeups_0_bits_uop_iq_type_1 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_1), .io_core_iwakeups_0_bits_uop_iq_type_2 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_2), .io_core_iwakeups_0_bits_uop_iq_type_3 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_3), .io_core_iwakeups_0_bits_uop_fu_code_0 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_0), .io_core_iwakeups_0_bits_uop_fu_code_1 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_1), .io_core_iwakeups_0_bits_uop_fu_code_2 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_2), .io_core_iwakeups_0_bits_uop_fu_code_3 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_3), .io_core_iwakeups_0_bits_uop_fu_code_4 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_4), .io_core_iwakeups_0_bits_uop_fu_code_5 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_5), .io_core_iwakeups_0_bits_uop_fu_code_6 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_6), .io_core_iwakeups_0_bits_uop_fu_code_7 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_7), .io_core_iwakeups_0_bits_uop_fu_code_8 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_8), .io_core_iwakeups_0_bits_uop_fu_code_9 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_9), .io_core_iwakeups_0_bits_uop_iw_issued (_lsu_io_core_iwakeups_0_bits_uop_iw_issued), .io_core_iwakeups_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_agen), .io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen), .io_core_iwakeups_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_speculative_child), .io_core_iwakeups_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_speculative_child), .io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint), .io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint), .io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint), .io_core_iwakeups_0_bits_uop_dis_col_sel (_lsu_io_core_iwakeups_0_bits_uop_dis_col_sel), .io_core_iwakeups_0_bits_uop_br_mask (_lsu_io_core_iwakeups_0_bits_uop_br_mask), .io_core_iwakeups_0_bits_uop_br_tag (_lsu_io_core_iwakeups_0_bits_uop_br_tag), .io_core_iwakeups_0_bits_uop_br_type (_lsu_io_core_iwakeups_0_bits_uop_br_type), .io_core_iwakeups_0_bits_uop_is_sfb (_lsu_io_core_iwakeups_0_bits_uop_is_sfb), .io_core_iwakeups_0_bits_uop_is_fence (_lsu_io_core_iwakeups_0_bits_uop_is_fence), .io_core_iwakeups_0_bits_uop_is_fencei (_lsu_io_core_iwakeups_0_bits_uop_is_fencei), .io_core_iwakeups_0_bits_uop_is_sfence (_lsu_io_core_iwakeups_0_bits_uop_is_sfence), .io_core_iwakeups_0_bits_uop_is_amo (_lsu_io_core_iwakeups_0_bits_uop_is_amo), .io_core_iwakeups_0_bits_uop_is_eret (_lsu_io_core_iwakeups_0_bits_uop_is_eret), .io_core_iwakeups_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iwakeups_0_bits_uop_is_sys_pc2epc), .io_core_iwakeups_0_bits_uop_is_rocc (_lsu_io_core_iwakeups_0_bits_uop_is_rocc), .io_core_iwakeups_0_bits_uop_is_mov (_lsu_io_core_iwakeups_0_bits_uop_is_mov), .io_core_iwakeups_0_bits_uop_ftq_idx (_lsu_io_core_iwakeups_0_bits_uop_ftq_idx), .io_core_iwakeups_0_bits_uop_edge_inst (_lsu_io_core_iwakeups_0_bits_uop_edge_inst), .io_core_iwakeups_0_bits_uop_pc_lob (_lsu_io_core_iwakeups_0_bits_uop_pc_lob), .io_core_iwakeups_0_bits_uop_taken (_lsu_io_core_iwakeups_0_bits_uop_taken), .io_core_iwakeups_0_bits_uop_imm_rename (_lsu_io_core_iwakeups_0_bits_uop_imm_rename), .io_core_iwakeups_0_bits_uop_imm_sel (_lsu_io_core_iwakeups_0_bits_uop_imm_sel), .io_core_iwakeups_0_bits_uop_pimm (_lsu_io_core_iwakeups_0_bits_uop_pimm), .io_core_iwakeups_0_bits_uop_imm_packed (_lsu_io_core_iwakeups_0_bits_uop_imm_packed), .io_core_iwakeups_0_bits_uop_op1_sel (_lsu_io_core_iwakeups_0_bits_uop_op1_sel), .io_core_iwakeups_0_bits_uop_op2_sel (_lsu_io_core_iwakeups_0_bits_uop_op2_sel), .io_core_iwakeups_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ldst), .io_core_iwakeups_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wen), .io_core_iwakeups_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren1), .io_core_iwakeups_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren2), .io_core_iwakeups_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren3), .io_core_iwakeups_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap12), .io_core_iwakeups_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap23), .io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn), .io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut), .io_core_iwakeups_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fromint), .io_core_iwakeups_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_toint), .io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe), .io_core_iwakeups_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fma), .io_core_iwakeups_0_bits_uop_fp_ctrl_div (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_div), .io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt), .io_core_iwakeups_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wflags), .io_core_iwakeups_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_vec), .io_core_iwakeups_0_bits_uop_rob_idx (_lsu_io_core_iwakeups_0_bits_uop_rob_idx), .io_core_iwakeups_0_bits_uop_ldq_idx (_lsu_io_core_iwakeups_0_bits_uop_ldq_idx), .io_core_iwakeups_0_bits_uop_stq_idx (_lsu_io_core_iwakeups_0_bits_uop_stq_idx), .io_core_iwakeups_0_bits_uop_rxq_idx (_lsu_io_core_iwakeups_0_bits_uop_rxq_idx), .io_core_iwakeups_0_bits_uop_pdst (_lsu_io_core_iwakeups_0_bits_uop_pdst), .io_core_iwakeups_0_bits_uop_prs1 (_lsu_io_core_iwakeups_0_bits_uop_prs1), .io_core_iwakeups_0_bits_uop_prs2 (_lsu_io_core_iwakeups_0_bits_uop_prs2), .io_core_iwakeups_0_bits_uop_prs3 (_lsu_io_core_iwakeups_0_bits_uop_prs3), .io_core_iwakeups_0_bits_uop_ppred (_lsu_io_core_iwakeups_0_bits_uop_ppred), .io_core_iwakeups_0_bits_uop_prs1_busy (_lsu_io_core_iwakeups_0_bits_uop_prs1_busy), .io_core_iwakeups_0_bits_uop_prs2_busy (_lsu_io_core_iwakeups_0_bits_uop_prs2_busy), .io_core_iwakeups_0_bits_uop_prs3_busy (_lsu_io_core_iwakeups_0_bits_uop_prs3_busy), .io_core_iwakeups_0_bits_uop_ppred_busy (_lsu_io_core_iwakeups_0_bits_uop_ppred_busy), .io_core_iwakeups_0_bits_uop_stale_pdst (_lsu_io_core_iwakeups_0_bits_uop_stale_pdst), .io_core_iwakeups_0_bits_uop_exception (_lsu_io_core_iwakeups_0_bits_uop_exception), .io_core_iwakeups_0_bits_uop_exc_cause (_lsu_io_core_iwakeups_0_bits_uop_exc_cause), .io_core_iwakeups_0_bits_uop_mem_cmd (_lsu_io_core_iwakeups_0_bits_uop_mem_cmd), .io_core_iwakeups_0_bits_uop_mem_size (_lsu_io_core_iwakeups_0_bits_uop_mem_size), .io_core_iwakeups_0_bits_uop_mem_signed (_lsu_io_core_iwakeups_0_bits_uop_mem_signed), .io_core_iwakeups_0_bits_uop_uses_ldq (_lsu_io_core_iwakeups_0_bits_uop_uses_ldq), .io_core_iwakeups_0_bits_uop_uses_stq (_lsu_io_core_iwakeups_0_bits_uop_uses_stq), .io_core_iwakeups_0_bits_uop_is_unique (_lsu_io_core_iwakeups_0_bits_uop_is_unique), .io_core_iwakeups_0_bits_uop_flush_on_commit (_lsu_io_core_iwakeups_0_bits_uop_flush_on_commit), .io_core_iwakeups_0_bits_uop_csr_cmd (_lsu_io_core_iwakeups_0_bits_uop_csr_cmd), .io_core_iwakeups_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iwakeups_0_bits_uop_ldst_is_rs1), .io_core_iwakeups_0_bits_uop_ldst (_lsu_io_core_iwakeups_0_bits_uop_ldst), .io_core_iwakeups_0_bits_uop_lrs1 (_lsu_io_core_iwakeups_0_bits_uop_lrs1), .io_core_iwakeups_0_bits_uop_lrs2 (_lsu_io_core_iwakeups_0_bits_uop_lrs2), .io_core_iwakeups_0_bits_uop_lrs3 (_lsu_io_core_iwakeups_0_bits_uop_lrs3), .io_core_iwakeups_0_bits_uop_dst_rtype (_lsu_io_core_iwakeups_0_bits_uop_dst_rtype), .io_core_iwakeups_0_bits_uop_lrs1_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs1_rtype), .io_core_iwakeups_0_bits_uop_lrs2_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs2_rtype), .io_core_iwakeups_0_bits_uop_frs3_en (_lsu_io_core_iwakeups_0_bits_uop_frs3_en), .io_core_iwakeups_0_bits_uop_fcn_dw (_lsu_io_core_iwakeups_0_bits_uop_fcn_dw), .io_core_iwakeups_0_bits_uop_fcn_op (_lsu_io_core_iwakeups_0_bits_uop_fcn_op), .io_core_iwakeups_0_bits_uop_fp_val (_lsu_io_core_iwakeups_0_bits_uop_fp_val), .io_core_iwakeups_0_bits_uop_fp_rm (_lsu_io_core_iwakeups_0_bits_uop_fp_rm), .io_core_iwakeups_0_bits_uop_fp_typ (_lsu_io_core_iwakeups_0_bits_uop_fp_typ), .io_core_iwakeups_0_bits_uop_xcpt_pf_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_pf_if), .io_core_iwakeups_0_bits_uop_xcpt_ae_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ae_if), .io_core_iwakeups_0_bits_uop_xcpt_ma_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ma_if), .io_core_iwakeups_0_bits_uop_bp_debug_if (_lsu_io_core_iwakeups_0_bits_uop_bp_debug_if), .io_core_iwakeups_0_bits_uop_bp_xcpt_if (_lsu_io_core_iwakeups_0_bits_uop_bp_xcpt_if), .io_core_iwakeups_0_bits_uop_debug_fsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_fsrc), .io_core_iwakeups_0_bits_uop_debug_tsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_tsrc), .io_core_iwakeups_0_bits_bypassable (_lsu_io_core_iwakeups_0_bits_bypassable), .io_core_iwakeups_0_bits_speculative_mask (_lsu_io_core_iwakeups_0_bits_speculative_mask), .io_core_iwakeups_0_bits_rebusy (_lsu_io_core_iwakeups_0_bits_rebusy), .io_core_iresp_0_valid (_lsu_io_core_iresp_0_valid), .io_core_iresp_0_bits_uop_inst (_lsu_io_core_iresp_0_bits_uop_inst), .io_core_iresp_0_bits_uop_debug_inst (_lsu_io_core_iresp_0_bits_uop_debug_inst), .io_core_iresp_0_bits_uop_is_rvc (_lsu_io_core_iresp_0_bits_uop_is_rvc), .io_core_iresp_0_bits_uop_debug_pc (_lsu_io_core_iresp_0_bits_uop_debug_pc), .io_core_iresp_0_bits_uop_iq_type_0 (_lsu_io_core_iresp_0_bits_uop_iq_type_0), .io_core_iresp_0_bits_uop_iq_type_1 (_lsu_io_core_iresp_0_bits_uop_iq_type_1), .io_core_iresp_0_bits_uop_iq_type_2 (_lsu_io_core_iresp_0_bits_uop_iq_type_2), .io_core_iresp_0_bits_uop_iq_type_3 (_lsu_io_core_iresp_0_bits_uop_iq_type_3), .io_core_iresp_0_bits_uop_fu_code_0 (_lsu_io_core_iresp_0_bits_uop_fu_code_0), .io_core_iresp_0_bits_uop_fu_code_1 (_lsu_io_core_iresp_0_bits_uop_fu_code_1), .io_core_iresp_0_bits_uop_fu_code_2 (_lsu_io_core_iresp_0_bits_uop_fu_code_2), .io_core_iresp_0_bits_uop_fu_code_3 (_lsu_io_core_iresp_0_bits_uop_fu_code_3), .io_core_iresp_0_bits_uop_fu_code_4 (_lsu_io_core_iresp_0_bits_uop_fu_code_4), .io_core_iresp_0_bits_uop_fu_code_5 (_lsu_io_core_iresp_0_bits_uop_fu_code_5), .io_core_iresp_0_bits_uop_fu_code_6 (_lsu_io_core_iresp_0_bits_uop_fu_code_6), .io_core_iresp_0_bits_uop_fu_code_7 (_lsu_io_core_iresp_0_bits_uop_fu_code_7), .io_core_iresp_0_bits_uop_fu_code_8 (_lsu_io_core_iresp_0_bits_uop_fu_code_8), .io_core_iresp_0_bits_uop_fu_code_9 (_lsu_io_core_iresp_0_bits_uop_fu_code_9), .io_core_iresp_0_bits_uop_iw_issued (_lsu_io_core_iresp_0_bits_uop_iw_issued), .io_core_iresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_agen), .io_core_iresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_dgen), .io_core_iresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p1_speculative_child), .io_core_iresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p2_speculative_child), .io_core_iresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p1_bypass_hint), .io_core_iresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p2_bypass_hint), .io_core_iresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p3_bypass_hint), .io_core_iresp_0_bits_uop_dis_col_sel (_lsu_io_core_iresp_0_bits_uop_dis_col_sel), .io_core_iresp_0_bits_uop_br_mask (_lsu_io_core_iresp_0_bits_uop_br_mask), .io_core_iresp_0_bits_uop_br_tag (_lsu_io_core_iresp_0_bits_uop_br_tag), .io_core_iresp_0_bits_uop_br_type (_lsu_io_core_iresp_0_bits_uop_br_type), .io_core_iresp_0_bits_uop_is_sfb (_lsu_io_core_iresp_0_bits_uop_is_sfb), .io_core_iresp_0_bits_uop_is_fence (_lsu_io_core_iresp_0_bits_uop_is_fence), .io_core_iresp_0_bits_uop_is_fencei (_lsu_io_core_iresp_0_bits_uop_is_fencei), .io_core_iresp_0_bits_uop_is_sfence (_lsu_io_core_iresp_0_bits_uop_is_sfence), .io_core_iresp_0_bits_uop_is_amo (_lsu_io_core_iresp_0_bits_uop_is_amo), .io_core_iresp_0_bits_uop_is_eret (_lsu_io_core_iresp_0_bits_uop_is_eret), .io_core_iresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iresp_0_bits_uop_is_sys_pc2epc), .io_core_iresp_0_bits_uop_is_rocc (_lsu_io_core_iresp_0_bits_uop_is_rocc), .io_core_iresp_0_bits_uop_is_mov (_lsu_io_core_iresp_0_bits_uop_is_mov), .io_core_iresp_0_bits_uop_ftq_idx (_lsu_io_core_iresp_0_bits_uop_ftq_idx), .io_core_iresp_0_bits_uop_edge_inst (_lsu_io_core_iresp_0_bits_uop_edge_inst), .io_core_iresp_0_bits_uop_pc_lob (_lsu_io_core_iresp_0_bits_uop_pc_lob), .io_core_iresp_0_bits_uop_taken (_lsu_io_core_iresp_0_bits_uop_taken), .io_core_iresp_0_bits_uop_imm_rename (_lsu_io_core_iresp_0_bits_uop_imm_rename), .io_core_iresp_0_bits_uop_imm_sel (_lsu_io_core_iresp_0_bits_uop_imm_sel), .io_core_iresp_0_bits_uop_pimm (_lsu_io_core_iresp_0_bits_uop_pimm), .io_core_iresp_0_bits_uop_imm_packed (_lsu_io_core_iresp_0_bits_uop_imm_packed), .io_core_iresp_0_bits_uop_op1_sel (_lsu_io_core_iresp_0_bits_uop_op1_sel), .io_core_iresp_0_bits_uop_op2_sel (_lsu_io_core_iresp_0_bits_uop_op2_sel), .io_core_iresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ldst), .io_core_iresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wen), .io_core_iresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren1), .io_core_iresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren2), .io_core_iresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren3), .io_core_iresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap12), .io_core_iresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap23), .io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn), .io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut), .io_core_iresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fromint), .io_core_iresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_toint), .io_core_iresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fastpipe), .io_core_iresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fma), .io_core_iresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_div), .io_core_iresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_sqrt), .io_core_iresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wflags), .io_core_iresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_vec), .io_core_iresp_0_bits_uop_rob_idx (_lsu_io_core_iresp_0_bits_uop_rob_idx), .io_core_iresp_0_bits_uop_ldq_idx (_lsu_io_core_iresp_0_bits_uop_ldq_idx), .io_core_iresp_0_bits_uop_stq_idx (_lsu_io_core_iresp_0_bits_uop_stq_idx), .io_core_iresp_0_bits_uop_rxq_idx (_lsu_io_core_iresp_0_bits_uop_rxq_idx), .io_core_iresp_0_bits_uop_pdst (_lsu_io_core_iresp_0_bits_uop_pdst), .io_core_iresp_0_bits_uop_prs1 (_lsu_io_core_iresp_0_bits_uop_prs1), .io_core_iresp_0_bits_uop_prs2 (_lsu_io_core_iresp_0_bits_uop_prs2), .io_core_iresp_0_bits_uop_prs3 (_lsu_io_core_iresp_0_bits_uop_prs3), .io_core_iresp_0_bits_uop_ppred (_lsu_io_core_iresp_0_bits_uop_ppred), .io_core_iresp_0_bits_uop_prs1_busy (_lsu_io_core_iresp_0_bits_uop_prs1_busy), .io_core_iresp_0_bits_uop_prs2_busy (_lsu_io_core_iresp_0_bits_uop_prs2_busy), .io_core_iresp_0_bits_uop_prs3_busy (_lsu_io_core_iresp_0_bits_uop_prs3_busy), .io_core_iresp_0_bits_uop_ppred_busy (_lsu_io_core_iresp_0_bits_uop_ppred_busy), .io_core_iresp_0_bits_uop_stale_pdst (_lsu_io_core_iresp_0_bits_uop_stale_pdst), .io_core_iresp_0_bits_uop_exception (_lsu_io_core_iresp_0_bits_uop_exception), .io_core_iresp_0_bits_uop_exc_cause (_lsu_io_core_iresp_0_bits_uop_exc_cause), .io_core_iresp_0_bits_uop_mem_cmd (_lsu_io_core_iresp_0_bits_uop_mem_cmd), .io_core_iresp_0_bits_uop_mem_size (_lsu_io_core_iresp_0_bits_uop_mem_size), .io_core_iresp_0_bits_uop_mem_signed (_lsu_io_core_iresp_0_bits_uop_mem_signed), .io_core_iresp_0_bits_uop_uses_ldq (_lsu_io_core_iresp_0_bits_uop_uses_ldq), .io_core_iresp_0_bits_uop_uses_stq (_lsu_io_core_iresp_0_bits_uop_uses_stq), .io_core_iresp_0_bits_uop_is_unique (_lsu_io_core_iresp_0_bits_uop_is_unique), .io_core_iresp_0_bits_uop_flush_on_commit (_lsu_io_core_iresp_0_bits_uop_flush_on_commit), .io_core_iresp_0_bits_uop_csr_cmd (_lsu_io_core_iresp_0_bits_uop_csr_cmd), .io_core_iresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iresp_0_bits_uop_ldst_is_rs1), .io_core_iresp_0_bits_uop_ldst (_lsu_io_core_iresp_0_bits_uop_ldst), .io_core_iresp_0_bits_uop_lrs1 (_lsu_io_core_iresp_0_bits_uop_lrs1), .io_core_iresp_0_bits_uop_lrs2 (_lsu_io_core_iresp_0_bits_uop_lrs2), .io_core_iresp_0_bits_uop_lrs3 (_lsu_io_core_iresp_0_bits_uop_lrs3), .io_core_iresp_0_bits_uop_dst_rtype (_lsu_io_core_iresp_0_bits_uop_dst_rtype), .io_core_iresp_0_bits_uop_lrs1_rtype (_lsu_io_core_iresp_0_bits_uop_lrs1_rtype), .io_core_iresp_0_bits_uop_lrs2_rtype (_lsu_io_core_iresp_0_bits_uop_lrs2_rtype), .io_core_iresp_0_bits_uop_frs3_en (_lsu_io_core_iresp_0_bits_uop_frs3_en), .io_core_iresp_0_bits_uop_fcn_dw (_lsu_io_core_iresp_0_bits_uop_fcn_dw), .io_core_iresp_0_bits_uop_fcn_op (_lsu_io_core_iresp_0_bits_uop_fcn_op), .io_core_iresp_0_bits_uop_fp_val (_lsu_io_core_iresp_0_bits_uop_fp_val), .io_core_iresp_0_bits_uop_fp_rm (_lsu_io_core_iresp_0_bits_uop_fp_rm), .io_core_iresp_0_bits_uop_fp_typ (_lsu_io_core_iresp_0_bits_uop_fp_typ), .io_core_iresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_iresp_0_bits_uop_xcpt_pf_if), .io_core_iresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ae_if), .io_core_iresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ma_if), .io_core_iresp_0_bits_uop_bp_debug_if (_lsu_io_core_iresp_0_bits_uop_bp_debug_if), .io_core_iresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_iresp_0_bits_uop_bp_xcpt_if), .io_core_iresp_0_bits_uop_debug_fsrc (_lsu_io_core_iresp_0_bits_uop_debug_fsrc), .io_core_iresp_0_bits_uop_debug_tsrc (_lsu_io_core_iresp_0_bits_uop_debug_tsrc), .io_core_iresp_0_bits_data (_lsu_io_core_iresp_0_bits_data), .io_core_fresp_0_valid (_lsu_io_core_fresp_0_valid), .io_core_fresp_0_bits_uop_inst (_lsu_io_core_fresp_0_bits_uop_inst), .io_core_fresp_0_bits_uop_debug_inst (_lsu_io_core_fresp_0_bits_uop_debug_inst), .io_core_fresp_0_bits_uop_is_rvc (_lsu_io_core_fresp_0_bits_uop_is_rvc), .io_core_fresp_0_bits_uop_debug_pc (_lsu_io_core_fresp_0_bits_uop_debug_pc), .io_core_fresp_0_bits_uop_iq_type_0 (_lsu_io_core_fresp_0_bits_uop_iq_type_0), .io_core_fresp_0_bits_uop_iq_type_1 (_lsu_io_core_fresp_0_bits_uop_iq_type_1), .io_core_fresp_0_bits_uop_iq_type_2 (_lsu_io_core_fresp_0_bits_uop_iq_type_2), .io_core_fresp_0_bits_uop_iq_type_3 (_lsu_io_core_fresp_0_bits_uop_iq_type_3), .io_core_fresp_0_bits_uop_fu_code_0 (_lsu_io_core_fresp_0_bits_uop_fu_code_0), .io_core_fresp_0_bits_uop_fu_code_1 (_lsu_io_core_fresp_0_bits_uop_fu_code_1), .io_core_fresp_0_bits_uop_fu_code_2 (_lsu_io_core_fresp_0_bits_uop_fu_code_2), .io_core_fresp_0_bits_uop_fu_code_3 (_lsu_io_core_fresp_0_bits_uop_fu_code_3), .io_core_fresp_0_bits_uop_fu_code_4 (_lsu_io_core_fresp_0_bits_uop_fu_code_4), .io_core_fresp_0_bits_uop_fu_code_5 (_lsu_io_core_fresp_0_bits_uop_fu_code_5), .io_core_fresp_0_bits_uop_fu_code_6 (_lsu_io_core_fresp_0_bits_uop_fu_code_6), .io_core_fresp_0_bits_uop_fu_code_7 (_lsu_io_core_fresp_0_bits_uop_fu_code_7), .io_core_fresp_0_bits_uop_fu_code_8 (_lsu_io_core_fresp_0_bits_uop_fu_code_8), .io_core_fresp_0_bits_uop_fu_code_9 (_lsu_io_core_fresp_0_bits_uop_fu_code_9), .io_core_fresp_0_bits_uop_iw_issued (_lsu_io_core_fresp_0_bits_uop_iw_issued), .io_core_fresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_agen), .io_core_fresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_dgen), .io_core_fresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p1_speculative_child), .io_core_fresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p2_speculative_child), .io_core_fresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p1_bypass_hint), .io_core_fresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p2_bypass_hint), .io_core_fresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p3_bypass_hint), .io_core_fresp_0_bits_uop_dis_col_sel (_lsu_io_core_fresp_0_bits_uop_dis_col_sel), .io_core_fresp_0_bits_uop_br_mask (_lsu_io_core_fresp_0_bits_uop_br_mask), .io_core_fresp_0_bits_uop_br_tag (_lsu_io_core_fresp_0_bits_uop_br_tag), .io_core_fresp_0_bits_uop_br_type (_lsu_io_core_fresp_0_bits_uop_br_type), .io_core_fresp_0_bits_uop_is_sfb (_lsu_io_core_fresp_0_bits_uop_is_sfb), .io_core_fresp_0_bits_uop_is_fence (_lsu_io_core_fresp_0_bits_uop_is_fence), .io_core_fresp_0_bits_uop_is_fencei (_lsu_io_core_fresp_0_bits_uop_is_fencei), .io_core_fresp_0_bits_uop_is_sfence (_lsu_io_core_fresp_0_bits_uop_is_sfence), .io_core_fresp_0_bits_uop_is_amo (_lsu_io_core_fresp_0_bits_uop_is_amo), .io_core_fresp_0_bits_uop_is_eret (_lsu_io_core_fresp_0_bits_uop_is_eret), .io_core_fresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_fresp_0_bits_uop_is_sys_pc2epc), .io_core_fresp_0_bits_uop_is_rocc (_lsu_io_core_fresp_0_bits_uop_is_rocc), .io_core_fresp_0_bits_uop_is_mov (_lsu_io_core_fresp_0_bits_uop_is_mov), .io_core_fresp_0_bits_uop_ftq_idx (_lsu_io_core_fresp_0_bits_uop_ftq_idx), .io_core_fresp_0_bits_uop_edge_inst (_lsu_io_core_fresp_0_bits_uop_edge_inst), .io_core_fresp_0_bits_uop_pc_lob (_lsu_io_core_fresp_0_bits_uop_pc_lob), .io_core_fresp_0_bits_uop_taken (_lsu_io_core_fresp_0_bits_uop_taken), .io_core_fresp_0_bits_uop_imm_rename (_lsu_io_core_fresp_0_bits_uop_imm_rename), .io_core_fresp_0_bits_uop_imm_sel (_lsu_io_core_fresp_0_bits_uop_imm_sel), .io_core_fresp_0_bits_uop_pimm (_lsu_io_core_fresp_0_bits_uop_pimm), .io_core_fresp_0_bits_uop_imm_packed (_lsu_io_core_fresp_0_bits_uop_imm_packed), .io_core_fresp_0_bits_uop_op1_sel (_lsu_io_core_fresp_0_bits_uop_op1_sel), .io_core_fresp_0_bits_uop_op2_sel (_lsu_io_core_fresp_0_bits_uop_op2_sel), .io_core_fresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ldst), .io_core_fresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wen), .io_core_fresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren1), .io_core_fresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren2), .io_core_fresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren3), .io_core_fresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap12), .io_core_fresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap23), .io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn), .io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut), .io_core_fresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fromint), .io_core_fresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_toint), .io_core_fresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fastpipe), .io_core_fresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fma), .io_core_fresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_div), .io_core_fresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_sqrt), .io_core_fresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wflags), .io_core_fresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_vec), .io_core_fresp_0_bits_uop_rob_idx (_lsu_io_core_fresp_0_bits_uop_rob_idx), .io_core_fresp_0_bits_uop_ldq_idx (_lsu_io_core_fresp_0_bits_uop_ldq_idx), .io_core_fresp_0_bits_uop_stq_idx (_lsu_io_core_fresp_0_bits_uop_stq_idx), .io_core_fresp_0_bits_uop_rxq_idx (_lsu_io_core_fresp_0_bits_uop_rxq_idx), .io_core_fresp_0_bits_uop_pdst (_lsu_io_core_fresp_0_bits_uop_pdst), .io_core_fresp_0_bits_uop_prs1 (_lsu_io_core_fresp_0_bits_uop_prs1), .io_core_fresp_0_bits_uop_prs2 (_lsu_io_core_fresp_0_bits_uop_prs2), .io_core_fresp_0_bits_uop_prs3 (_lsu_io_core_fresp_0_bits_uop_prs3), .io_core_fresp_0_bits_uop_ppred (_lsu_io_core_fresp_0_bits_uop_ppred), .io_core_fresp_0_bits_uop_prs1_busy (_lsu_io_core_fresp_0_bits_uop_prs1_busy), .io_core_fresp_0_bits_uop_prs2_busy (_lsu_io_core_fresp_0_bits_uop_prs2_busy), .io_core_fresp_0_bits_uop_prs3_busy (_lsu_io_core_fresp_0_bits_uop_prs3_busy), .io_core_fresp_0_bits_uop_ppred_busy (_lsu_io_core_fresp_0_bits_uop_ppred_busy), .io_core_fresp_0_bits_uop_stale_pdst (_lsu_io_core_fresp_0_bits_uop_stale_pdst), .io_core_fresp_0_bits_uop_exception (_lsu_io_core_fresp_0_bits_uop_exception), .io_core_fresp_0_bits_uop_exc_cause (_lsu_io_core_fresp_0_bits_uop_exc_cause), .io_core_fresp_0_bits_uop_mem_cmd (_lsu_io_core_fresp_0_bits_uop_mem_cmd), .io_core_fresp_0_bits_uop_mem_size (_lsu_io_core_fresp_0_bits_uop_mem_size), .io_core_fresp_0_bits_uop_mem_signed (_lsu_io_core_fresp_0_bits_uop_mem_signed), .io_core_fresp_0_bits_uop_uses_ldq (_lsu_io_core_fresp_0_bits_uop_uses_ldq), .io_core_fresp_0_bits_uop_uses_stq (_lsu_io_core_fresp_0_bits_uop_uses_stq), .io_core_fresp_0_bits_uop_is_unique (_lsu_io_core_fresp_0_bits_uop_is_unique), .io_core_fresp_0_bits_uop_flush_on_commit (_lsu_io_core_fresp_0_bits_uop_flush_on_commit), .io_core_fresp_0_bits_uop_csr_cmd (_lsu_io_core_fresp_0_bits_uop_csr_cmd), .io_core_fresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_fresp_0_bits_uop_ldst_is_rs1), .io_core_fresp_0_bits_uop_ldst (_lsu_io_core_fresp_0_bits_uop_ldst), .io_core_fresp_0_bits_uop_lrs1 (_lsu_io_core_fresp_0_bits_uop_lrs1), .io_core_fresp_0_bits_uop_lrs2 (_lsu_io_core_fresp_0_bits_uop_lrs2), .io_core_fresp_0_bits_uop_lrs3 (_lsu_io_core_fresp_0_bits_uop_lrs3), .io_core_fresp_0_bits_uop_dst_rtype (_lsu_io_core_fresp_0_bits_uop_dst_rtype), .io_core_fresp_0_bits_uop_lrs1_rtype (_lsu_io_core_fresp_0_bits_uop_lrs1_rtype), .io_core_fresp_0_bits_uop_lrs2_rtype (_lsu_io_core_fresp_0_bits_uop_lrs2_rtype), .io_core_fresp_0_bits_uop_frs3_en (_lsu_io_core_fresp_0_bits_uop_frs3_en), .io_core_fresp_0_bits_uop_fcn_dw (_lsu_io_core_fresp_0_bits_uop_fcn_dw), .io_core_fresp_0_bits_uop_fcn_op (_lsu_io_core_fresp_0_bits_uop_fcn_op), .io_core_fresp_0_bits_uop_fp_val (_lsu_io_core_fresp_0_bits_uop_fp_val), .io_core_fresp_0_bits_uop_fp_rm (_lsu_io_core_fresp_0_bits_uop_fp_rm), .io_core_fresp_0_bits_uop_fp_typ (_lsu_io_core_fresp_0_bits_uop_fp_typ), .io_core_fresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_fresp_0_bits_uop_xcpt_pf_if), .io_core_fresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ae_if), .io_core_fresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ma_if), .io_core_fresp_0_bits_uop_bp_debug_if (_lsu_io_core_fresp_0_bits_uop_bp_debug_if), .io_core_fresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_fresp_0_bits_uop_bp_xcpt_if), .io_core_fresp_0_bits_uop_debug_fsrc (_lsu_io_core_fresp_0_bits_uop_debug_fsrc), .io_core_fresp_0_bits_uop_debug_tsrc (_lsu_io_core_fresp_0_bits_uop_debug_tsrc), .io_core_fresp_0_bits_data (_lsu_io_core_fresp_0_bits_data), .io_core_sfence_valid (_core_io_lsu_sfence_valid), // @[tile.scala:158:20] .io_core_sfence_bits_rs1 (_core_io_lsu_sfence_bits_rs1), // @[tile.scala:158:20] .io_core_sfence_bits_rs2 (_core_io_lsu_sfence_bits_rs2), // @[tile.scala:158:20] .io_core_sfence_bits_addr (_core_io_lsu_sfence_bits_addr), // @[tile.scala:158:20] .io_core_sfence_bits_asid (_core_io_lsu_sfence_bits_asid), // @[tile.scala:158:20] .io_core_sfence_bits_hv (_core_io_lsu_sfence_bits_hv), // @[tile.scala:158:20] .io_core_sfence_bits_hg (_core_io_lsu_sfence_bits_hg), // @[tile.scala:158:20] .io_core_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_0 (_core_io_lsu_dis_uops_0_bits_iq_type_0), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_1 (_core_io_lsu_dis_uops_0_bits_iq_type_1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_2 (_core_io_lsu_dis_uops_0_bits_iq_type_2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_3 (_core_io_lsu_dis_uops_0_bits_iq_type_3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_0 (_core_io_lsu_dis_uops_0_bits_fu_code_0), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_1 (_core_io_lsu_dis_uops_0_bits_fu_code_1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_2 (_core_io_lsu_dis_uops_0_bits_fu_code_2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_3 (_core_io_lsu_dis_uops_0_bits_fu_code_3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_4 (_core_io_lsu_dis_uops_0_bits_fu_code_4), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_5 (_core_io_lsu_dis_uops_0_bits_fu_code_5), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_6 (_core_io_lsu_dis_uops_0_bits_fu_code_6), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_7 (_core_io_lsu_dis_uops_0_bits_fu_code_7), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_8 (_core_io_lsu_dis_uops_0_bits_fu_code_8), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_9 (_core_io_lsu_dis_uops_0_bits_fu_code_9), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_issued (_core_io_lsu_dis_uops_0_bits_iw_issued), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_dis_col_sel (_core_io_lsu_dis_uops_0_bits_dis_col_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_br_type (_core_io_lsu_dis_uops_0_bits_br_type), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_sfence (_core_io_lsu_dis_uops_0_bits_is_sfence), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_eret (_core_io_lsu_dis_uops_0_bits_is_eret), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_rocc (_core_io_lsu_dis_uops_0_bits_is_rocc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_mov (_core_io_lsu_dis_uops_0_bits_is_mov), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_imm_rename (_core_io_lsu_dis_uops_0_bits_imm_rename), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_imm_sel (_core_io_lsu_dis_uops_0_bits_imm_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_pimm (_core_io_lsu_dis_uops_0_bits_pimm), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_op1_sel (_core_io_lsu_dis_uops_0_bits_op1_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_op2_sel (_core_io_lsu_dis_uops_0_bits_op2_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_div (_core_io_lsu_dis_uops_0_bits_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_0_bits_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_0_bits_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ppred (_core_io_lsu_dis_uops_0_bits_ppred), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ppred_busy (_core_io_lsu_dis_uops_0_bits_ppred_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_csr_cmd (_core_io_lsu_dis_uops_0_bits_csr_cmd), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fcn_dw (_core_io_lsu_dis_uops_0_bits_fcn_dw), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fcn_op (_core_io_lsu_dis_uops_0_bits_fcn_op), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_rm (_core_io_lsu_dis_uops_0_bits_fp_rm), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_typ (_core_io_lsu_dis_uops_0_bits_fp_typ), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), // @[tile.scala:158:20] .io_core_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_0 (_core_io_lsu_dis_uops_1_bits_iq_type_0), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_1 (_core_io_lsu_dis_uops_1_bits_iq_type_1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_2 (_core_io_lsu_dis_uops_1_bits_iq_type_2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_3 (_core_io_lsu_dis_uops_1_bits_iq_type_3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_0 (_core_io_lsu_dis_uops_1_bits_fu_code_0), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_1 (_core_io_lsu_dis_uops_1_bits_fu_code_1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_2 (_core_io_lsu_dis_uops_1_bits_fu_code_2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_3 (_core_io_lsu_dis_uops_1_bits_fu_code_3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_4 (_core_io_lsu_dis_uops_1_bits_fu_code_4), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_5 (_core_io_lsu_dis_uops_1_bits_fu_code_5), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_6 (_core_io_lsu_dis_uops_1_bits_fu_code_6), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_7 (_core_io_lsu_dis_uops_1_bits_fu_code_7), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_8 (_core_io_lsu_dis_uops_1_bits_fu_code_8), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_9 (_core_io_lsu_dis_uops_1_bits_fu_code_9), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_issued (_core_io_lsu_dis_uops_1_bits_iw_issued), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_dis_col_sel (_core_io_lsu_dis_uops_1_bits_dis_col_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_br_type (_core_io_lsu_dis_uops_1_bits_br_type), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_sfence (_core_io_lsu_dis_uops_1_bits_is_sfence), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_eret (_core_io_lsu_dis_uops_1_bits_is_eret), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_rocc (_core_io_lsu_dis_uops_1_bits_is_rocc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_mov (_core_io_lsu_dis_uops_1_bits_is_mov), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_imm_rename (_core_io_lsu_dis_uops_1_bits_imm_rename), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_imm_sel (_core_io_lsu_dis_uops_1_bits_imm_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_pimm (_core_io_lsu_dis_uops_1_bits_pimm), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_op1_sel (_core_io_lsu_dis_uops_1_bits_op1_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_op2_sel (_core_io_lsu_dis_uops_1_bits_op2_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_div (_core_io_lsu_dis_uops_1_bits_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_1_bits_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_1_bits_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ppred (_core_io_lsu_dis_uops_1_bits_ppred), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ppred_busy (_core_io_lsu_dis_uops_1_bits_ppred_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_csr_cmd (_core_io_lsu_dis_uops_1_bits_csr_cmd), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fcn_dw (_core_io_lsu_dis_uops_1_bits_fcn_dw), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fcn_op (_core_io_lsu_dis_uops_1_bits_fcn_op), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_rm (_core_io_lsu_dis_uops_1_bits_fp_rm), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_typ (_core_io_lsu_dis_uops_1_bits_fp_typ), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), // @[tile.scala:158:20] .io_core_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), .io_core_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), .io_core_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), .io_core_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), .io_core_ldq_full_0 (_lsu_io_core_ldq_full_0), .io_core_ldq_full_1 (_lsu_io_core_ldq_full_1), .io_core_stq_full_0 (_lsu_io_core_stq_full_0), .io_core_stq_full_1 (_lsu_io_core_stq_full_1), .io_core_commit_valids_0 (_core_io_lsu_commit_valids_0), // @[tile.scala:158:20] .io_core_commit_valids_1 (_core_io_lsu_commit_valids_1), // @[tile.scala:158:20] .io_core_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), // @[tile.scala:158:20] .io_core_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), // @[tile.scala:158:20] .io_core_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), // @[tile.scala:158:20] .io_core_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_0 (_core_io_lsu_commit_uops_0_iq_type_0), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_1 (_core_io_lsu_commit_uops_0_iq_type_1), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_2 (_core_io_lsu_commit_uops_0_iq_type_2), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_3 (_core_io_lsu_commit_uops_0_iq_type_3), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_0 (_core_io_lsu_commit_uops_0_fu_code_0), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_1 (_core_io_lsu_commit_uops_0_fu_code_1), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_2 (_core_io_lsu_commit_uops_0_fu_code_2), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_3 (_core_io_lsu_commit_uops_0_fu_code_3), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_4 (_core_io_lsu_commit_uops_0_fu_code_4), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_5 (_core_io_lsu_commit_uops_0_fu_code_5), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_6 (_core_io_lsu_commit_uops_0_fu_code_6), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_7 (_core_io_lsu_commit_uops_0_fu_code_7), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_8 (_core_io_lsu_commit_uops_0_fu_code_8), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_9 (_core_io_lsu_commit_uops_0_fu_code_9), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_issued (_core_io_lsu_commit_uops_0_iw_issued), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_issued_partial_agen (_core_io_lsu_commit_uops_0_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_issued_partial_dgen (_core_io_lsu_commit_uops_0_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p1_speculative_child (_core_io_lsu_commit_uops_0_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p2_speculative_child (_core_io_lsu_commit_uops_0_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p1_bypass_hint (_core_io_lsu_commit_uops_0_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p2_bypass_hint (_core_io_lsu_commit_uops_0_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p3_bypass_hint (_core_io_lsu_commit_uops_0_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_0_dis_col_sel (_core_io_lsu_commit_uops_0_dis_col_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), // @[tile.scala:158:20] .io_core_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), // @[tile.scala:158:20] .io_core_commit_uops_0_br_type (_core_io_lsu_commit_uops_0_br_type), // @[tile.scala:158:20] .io_core_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), // @[tile.scala:158:20] .io_core_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), // @[tile.scala:158:20] .io_core_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), // @[tile.scala:158:20] .io_core_commit_uops_0_is_sfence (_core_io_lsu_commit_uops_0_is_sfence), // @[tile.scala:158:20] .io_core_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), // @[tile.scala:158:20] .io_core_commit_uops_0_is_eret (_core_io_lsu_commit_uops_0_is_eret), // @[tile.scala:158:20] .io_core_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_commit_uops_0_is_rocc (_core_io_lsu_commit_uops_0_is_rocc), // @[tile.scala:158:20] .io_core_commit_uops_0_is_mov (_core_io_lsu_commit_uops_0_is_mov), // @[tile.scala:158:20] .io_core_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), // @[tile.scala:158:20] .io_core_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), // @[tile.scala:158:20] .io_core_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), // @[tile.scala:158:20] .io_core_commit_uops_0_imm_rename (_core_io_lsu_commit_uops_0_imm_rename), // @[tile.scala:158:20] .io_core_commit_uops_0_imm_sel (_core_io_lsu_commit_uops_0_imm_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_pimm (_core_io_lsu_commit_uops_0_pimm), // @[tile.scala:158:20] .io_core_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), // @[tile.scala:158:20] .io_core_commit_uops_0_op1_sel (_core_io_lsu_commit_uops_0_op1_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_op2_sel (_core_io_lsu_commit_uops_0_op2_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ldst (_core_io_lsu_commit_uops_0_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_wen (_core_io_lsu_commit_uops_0_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ren1 (_core_io_lsu_commit_uops_0_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ren2 (_core_io_lsu_commit_uops_0_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ren3 (_core_io_lsu_commit_uops_0_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_swap12 (_core_io_lsu_commit_uops_0_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_swap23 (_core_io_lsu_commit_uops_0_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_fromint (_core_io_lsu_commit_uops_0_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_toint (_core_io_lsu_commit_uops_0_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_0_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_fma (_core_io_lsu_commit_uops_0_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_div (_core_io_lsu_commit_uops_0_fp_ctrl_div), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_sqrt (_core_io_lsu_commit_uops_0_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_wflags (_core_io_lsu_commit_uops_0_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_vec (_core_io_lsu_commit_uops_0_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), // @[tile.scala:158:20] .io_core_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), // @[tile.scala:158:20] .io_core_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), // @[tile.scala:158:20] .io_core_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), // @[tile.scala:158:20] .io_core_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), // @[tile.scala:158:20] .io_core_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), // @[tile.scala:158:20] .io_core_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), // @[tile.scala:158:20] .io_core_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), // @[tile.scala:158:20] .io_core_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), // @[tile.scala:158:20] .io_core_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), // @[tile.scala:158:20] .io_core_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), // @[tile.scala:158:20] .io_core_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), // @[tile.scala:158:20] .io_core_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), // @[tile.scala:158:20] .io_core_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), // @[tile.scala:158:20] .io_core_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), // @[tile.scala:158:20] .io_core_commit_uops_0_csr_cmd (_core_io_lsu_commit_uops_0_csr_cmd), // @[tile.scala:158:20] .io_core_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), // @[tile.scala:158:20] .io_core_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), // @[tile.scala:158:20] .io_core_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), // @[tile.scala:158:20] .io_core_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), // @[tile.scala:158:20] .io_core_commit_uops_0_fcn_dw (_core_io_lsu_commit_uops_0_fcn_dw), // @[tile.scala:158:20] .io_core_commit_uops_0_fcn_op (_core_io_lsu_commit_uops_0_fcn_op), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_rm (_core_io_lsu_commit_uops_0_fp_rm), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_typ (_core_io_lsu_commit_uops_0_fp_typ), // @[tile.scala:158:20] .io_core_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), // @[tile.scala:158:20] .io_core_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), // @[tile.scala:158:20] .io_core_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), // @[tile.scala:158:20] .io_core_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), // @[tile.scala:158:20] .io_core_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), // @[tile.scala:158:20] .io_core_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), // @[tile.scala:158:20] .io_core_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_0 (_core_io_lsu_commit_uops_1_iq_type_0), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_1 (_core_io_lsu_commit_uops_1_iq_type_1), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_2 (_core_io_lsu_commit_uops_1_iq_type_2), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_3 (_core_io_lsu_commit_uops_1_iq_type_3), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_0 (_core_io_lsu_commit_uops_1_fu_code_0), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_1 (_core_io_lsu_commit_uops_1_fu_code_1), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_2 (_core_io_lsu_commit_uops_1_fu_code_2), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_3 (_core_io_lsu_commit_uops_1_fu_code_3), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_4 (_core_io_lsu_commit_uops_1_fu_code_4), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_5 (_core_io_lsu_commit_uops_1_fu_code_5), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_6 (_core_io_lsu_commit_uops_1_fu_code_6), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_7 (_core_io_lsu_commit_uops_1_fu_code_7), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_8 (_core_io_lsu_commit_uops_1_fu_code_8), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_9 (_core_io_lsu_commit_uops_1_fu_code_9), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_issued (_core_io_lsu_commit_uops_1_iw_issued), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_issued_partial_agen (_core_io_lsu_commit_uops_1_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_issued_partial_dgen (_core_io_lsu_commit_uops_1_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p1_speculative_child (_core_io_lsu_commit_uops_1_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p2_speculative_child (_core_io_lsu_commit_uops_1_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p1_bypass_hint (_core_io_lsu_commit_uops_1_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p2_bypass_hint (_core_io_lsu_commit_uops_1_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p3_bypass_hint (_core_io_lsu_commit_uops_1_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_1_dis_col_sel (_core_io_lsu_commit_uops_1_dis_col_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), // @[tile.scala:158:20] .io_core_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), // @[tile.scala:158:20] .io_core_commit_uops_1_br_type (_core_io_lsu_commit_uops_1_br_type), // @[tile.scala:158:20] .io_core_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), // @[tile.scala:158:20] .io_core_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), // @[tile.scala:158:20] .io_core_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), // @[tile.scala:158:20] .io_core_commit_uops_1_is_sfence (_core_io_lsu_commit_uops_1_is_sfence), // @[tile.scala:158:20] .io_core_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), // @[tile.scala:158:20] .io_core_commit_uops_1_is_eret (_core_io_lsu_commit_uops_1_is_eret), // @[tile.scala:158:20] .io_core_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_commit_uops_1_is_rocc (_core_io_lsu_commit_uops_1_is_rocc), // @[tile.scala:158:20] .io_core_commit_uops_1_is_mov (_core_io_lsu_commit_uops_1_is_mov), // @[tile.scala:158:20] .io_core_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), // @[tile.scala:158:20] .io_core_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), // @[tile.scala:158:20] .io_core_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), // @[tile.scala:158:20] .io_core_commit_uops_1_imm_rename (_core_io_lsu_commit_uops_1_imm_rename), // @[tile.scala:158:20] .io_core_commit_uops_1_imm_sel (_core_io_lsu_commit_uops_1_imm_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_pimm (_core_io_lsu_commit_uops_1_pimm), // @[tile.scala:158:20] .io_core_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), // @[tile.scala:158:20] .io_core_commit_uops_1_op1_sel (_core_io_lsu_commit_uops_1_op1_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_op2_sel (_core_io_lsu_commit_uops_1_op2_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ldst (_core_io_lsu_commit_uops_1_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_wen (_core_io_lsu_commit_uops_1_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ren1 (_core_io_lsu_commit_uops_1_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ren2 (_core_io_lsu_commit_uops_1_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ren3 (_core_io_lsu_commit_uops_1_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_swap12 (_core_io_lsu_commit_uops_1_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_swap23 (_core_io_lsu_commit_uops_1_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_fromint (_core_io_lsu_commit_uops_1_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_toint (_core_io_lsu_commit_uops_1_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_1_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_fma (_core_io_lsu_commit_uops_1_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_div (_core_io_lsu_commit_uops_1_fp_ctrl_div), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_sqrt (_core_io_lsu_commit_uops_1_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_wflags (_core_io_lsu_commit_uops_1_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_vec (_core_io_lsu_commit_uops_1_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), // @[tile.scala:158:20] .io_core_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), // @[tile.scala:158:20] .io_core_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), // @[tile.scala:158:20] .io_core_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), // @[tile.scala:158:20] .io_core_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), // @[tile.scala:158:20] .io_core_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), // @[tile.scala:158:20] .io_core_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), // @[tile.scala:158:20] .io_core_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), // @[tile.scala:158:20] .io_core_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), // @[tile.scala:158:20] .io_core_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), // @[tile.scala:158:20] .io_core_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), // @[tile.scala:158:20] .io_core_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), // @[tile.scala:158:20] .io_core_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), // @[tile.scala:158:20] .io_core_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), // @[tile.scala:158:20] .io_core_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), // @[tile.scala:158:20] .io_core_commit_uops_1_csr_cmd (_core_io_lsu_commit_uops_1_csr_cmd), // @[tile.scala:158:20] .io_core_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), // @[tile.scala:158:20] .io_core_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), // @[tile.scala:158:20] .io_core_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), // @[tile.scala:158:20] .io_core_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), // @[tile.scala:158:20] .io_core_commit_uops_1_fcn_dw (_core_io_lsu_commit_uops_1_fcn_dw), // @[tile.scala:158:20] .io_core_commit_uops_1_fcn_op (_core_io_lsu_commit_uops_1_fcn_op), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_rm (_core_io_lsu_commit_uops_1_fp_rm), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_typ (_core_io_lsu_commit_uops_1_fp_typ), // @[tile.scala:158:20] .io_core_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), // @[tile.scala:158:20] .io_core_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), // @[tile.scala:158:20] .io_core_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), // @[tile.scala:158:20] .io_core_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), // @[tile.scala:158:20] .io_core_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), // @[tile.scala:158:20] .io_core_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), // @[tile.scala:158:20] .io_core_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), // @[tile.scala:158:20] .io_core_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), // @[tile.scala:158:20] .io_core_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), // @[tile.scala:158:20] .io_core_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), // @[tile.scala:158:20] .io_core_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), .io_core_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), .io_core_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), .io_core_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), .io_core_clr_unsafe_0_valid (_lsu_io_core_clr_unsafe_0_valid), .io_core_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), .io_core_fence_dmem (_core_io_lsu_fence_dmem), // @[tile.scala:158:20] .io_core_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), // @[tile.scala:158:20] .io_core_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_0 (_core_io_lsu_brupdate_b2_uop_iq_type_0), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_1 (_core_io_lsu_brupdate_b2_uop_iq_type_1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_2 (_core_io_lsu_brupdate_b2_uop_iq_type_2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_3 (_core_io_lsu_brupdate_b2_uop_iq_type_3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_0 (_core_io_lsu_brupdate_b2_uop_fu_code_0), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_1 (_core_io_lsu_brupdate_b2_uop_fu_code_1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_2 (_core_io_lsu_brupdate_b2_uop_fu_code_2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_3 (_core_io_lsu_brupdate_b2_uop_fu_code_3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_4 (_core_io_lsu_brupdate_b2_uop_fu_code_4), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_5 (_core_io_lsu_brupdate_b2_uop_fu_code_5), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_6 (_core_io_lsu_brupdate_b2_uop_fu_code_6), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_7 (_core_io_lsu_brupdate_b2_uop_fu_code_7), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_8 (_core_io_lsu_brupdate_b2_uop_fu_code_8), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_9 (_core_io_lsu_brupdate_b2_uop_fu_code_9), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_issued (_core_io_lsu_brupdate_b2_uop_iw_issued), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_issued_partial_agen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p1_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p2_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_dis_col_sel (_core_io_lsu_brupdate_b2_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_br_type (_core_io_lsu_brupdate_b2_uop_br_type), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_sfence (_core_io_lsu_brupdate_b2_uop_is_sfence), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_eret (_core_io_lsu_brupdate_b2_uop_is_eret), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_rocc (_core_io_lsu_brupdate_b2_uop_is_rocc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_mov (_core_io_lsu_brupdate_b2_uop_is_mov), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_imm_rename (_core_io_lsu_brupdate_b2_uop_imm_rename), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_imm_sel (_core_io_lsu_brupdate_b2_uop_imm_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_pimm (_core_io_lsu_brupdate_b2_uop_pimm), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_op1_sel (_core_io_lsu_brupdate_b2_uop_op1_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_op2_sel (_core_io_lsu_brupdate_b2_uop_op2_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ldst (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_wen (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_fromint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_toint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_fma (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_div (_core_io_lsu_brupdate_b2_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_lsu_brupdate_b2_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_wflags (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_vec (_core_io_lsu_brupdate_b2_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_csr_cmd (_core_io_lsu_brupdate_b2_uop_csr_cmd), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fcn_dw (_core_io_lsu_brupdate_b2_uop_fcn_dw), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fcn_op (_core_io_lsu_brupdate_b2_uop_fcn_op), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_rm (_core_io_lsu_brupdate_b2_uop_fp_rm), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_typ (_core_io_lsu_brupdate_b2_uop_fp_typ), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), // @[tile.scala:158:20] .io_core_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), // @[tile.scala:158:20] .io_core_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), // @[tile.scala:158:20] .io_core_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), // @[tile.scala:158:20] .io_core_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), // @[tile.scala:158:20] .io_core_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), // @[tile.scala:158:20] .io_core_rob_head_idx (_core_io_lsu_rob_head_idx), // @[tile.scala:158:20] .io_core_exception (_core_io_lsu_exception), // @[tile.scala:158:20] .io_core_fencei_rdy (_lsu_io_core_fencei_rdy), .io_core_lxcpt_valid (_lsu_io_core_lxcpt_valid), .io_core_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), .io_core_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), .io_core_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), .io_core_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), .io_core_lxcpt_bits_uop_iq_type_0 (_lsu_io_core_lxcpt_bits_uop_iq_type_0), .io_core_lxcpt_bits_uop_iq_type_1 (_lsu_io_core_lxcpt_bits_uop_iq_type_1), .io_core_lxcpt_bits_uop_iq_type_2 (_lsu_io_core_lxcpt_bits_uop_iq_type_2), .io_core_lxcpt_bits_uop_iq_type_3 (_lsu_io_core_lxcpt_bits_uop_iq_type_3), .io_core_lxcpt_bits_uop_fu_code_0 (_lsu_io_core_lxcpt_bits_uop_fu_code_0), .io_core_lxcpt_bits_uop_fu_code_1 (_lsu_io_core_lxcpt_bits_uop_fu_code_1), .io_core_lxcpt_bits_uop_fu_code_2 (_lsu_io_core_lxcpt_bits_uop_fu_code_2), .io_core_lxcpt_bits_uop_fu_code_3 (_lsu_io_core_lxcpt_bits_uop_fu_code_3), .io_core_lxcpt_bits_uop_fu_code_4 (_lsu_io_core_lxcpt_bits_uop_fu_code_4), .io_core_lxcpt_bits_uop_fu_code_5 (_lsu_io_core_lxcpt_bits_uop_fu_code_5), .io_core_lxcpt_bits_uop_fu_code_6 (_lsu_io_core_lxcpt_bits_uop_fu_code_6), .io_core_lxcpt_bits_uop_fu_code_7 (_lsu_io_core_lxcpt_bits_uop_fu_code_7), .io_core_lxcpt_bits_uop_fu_code_8 (_lsu_io_core_lxcpt_bits_uop_fu_code_8), .io_core_lxcpt_bits_uop_fu_code_9 (_lsu_io_core_lxcpt_bits_uop_fu_code_9), .io_core_lxcpt_bits_uop_iw_issued (_lsu_io_core_lxcpt_bits_uop_iw_issued), .io_core_lxcpt_bits_uop_iw_issued_partial_agen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_agen), .io_core_lxcpt_bits_uop_iw_issued_partial_dgen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_dgen), .io_core_lxcpt_bits_uop_iw_p1_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p1_speculative_child), .io_core_lxcpt_bits_uop_iw_p2_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p2_speculative_child), .io_core_lxcpt_bits_uop_iw_p1_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p1_bypass_hint), .io_core_lxcpt_bits_uop_iw_p2_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p2_bypass_hint), .io_core_lxcpt_bits_uop_iw_p3_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p3_bypass_hint), .io_core_lxcpt_bits_uop_dis_col_sel (_lsu_io_core_lxcpt_bits_uop_dis_col_sel), .io_core_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), .io_core_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), .io_core_lxcpt_bits_uop_br_type (_lsu_io_core_lxcpt_bits_uop_br_type), .io_core_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), .io_core_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), .io_core_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), .io_core_lxcpt_bits_uop_is_sfence (_lsu_io_core_lxcpt_bits_uop_is_sfence), .io_core_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), .io_core_lxcpt_bits_uop_is_eret (_lsu_io_core_lxcpt_bits_uop_is_eret), .io_core_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), .io_core_lxcpt_bits_uop_is_rocc (_lsu_io_core_lxcpt_bits_uop_is_rocc), .io_core_lxcpt_bits_uop_is_mov (_lsu_io_core_lxcpt_bits_uop_is_mov), .io_core_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), .io_core_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), .io_core_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), .io_core_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), .io_core_lxcpt_bits_uop_imm_rename (_lsu_io_core_lxcpt_bits_uop_imm_rename), .io_core_lxcpt_bits_uop_imm_sel (_lsu_io_core_lxcpt_bits_uop_imm_sel), .io_core_lxcpt_bits_uop_pimm (_lsu_io_core_lxcpt_bits_uop_pimm), .io_core_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), .io_core_lxcpt_bits_uop_op1_sel (_lsu_io_core_lxcpt_bits_uop_op1_sel), .io_core_lxcpt_bits_uop_op2_sel (_lsu_io_core_lxcpt_bits_uop_op2_sel), .io_core_lxcpt_bits_uop_fp_ctrl_ldst (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ldst), .io_core_lxcpt_bits_uop_fp_ctrl_wen (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wen), .io_core_lxcpt_bits_uop_fp_ctrl_ren1 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren1), .io_core_lxcpt_bits_uop_fp_ctrl_ren2 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren2), .io_core_lxcpt_bits_uop_fp_ctrl_ren3 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren3), .io_core_lxcpt_bits_uop_fp_ctrl_swap12 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap12), .io_core_lxcpt_bits_uop_fp_ctrl_swap23 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap23), .io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn), .io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut), .io_core_lxcpt_bits_uop_fp_ctrl_fromint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fromint), .io_core_lxcpt_bits_uop_fp_ctrl_toint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_toint), .io_core_lxcpt_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fastpipe), .io_core_lxcpt_bits_uop_fp_ctrl_fma (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fma), .io_core_lxcpt_bits_uop_fp_ctrl_div (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_div), .io_core_lxcpt_bits_uop_fp_ctrl_sqrt (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_sqrt), .io_core_lxcpt_bits_uop_fp_ctrl_wflags (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wflags), .io_core_lxcpt_bits_uop_fp_ctrl_vec (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_vec), .io_core_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), .io_core_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), .io_core_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), .io_core_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), .io_core_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), .io_core_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), .io_core_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), .io_core_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), .io_core_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), .io_core_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), .io_core_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), .io_core_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), .io_core_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), .io_core_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), .io_core_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), .io_core_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), .io_core_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), .io_core_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), .io_core_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), .io_core_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), .io_core_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), .io_core_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), .io_core_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), .io_core_lxcpt_bits_uop_csr_cmd (_lsu_io_core_lxcpt_bits_uop_csr_cmd), .io_core_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), .io_core_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), .io_core_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), .io_core_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), .io_core_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), .io_core_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), .io_core_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), .io_core_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), .io_core_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), .io_core_lxcpt_bits_uop_fcn_dw (_lsu_io_core_lxcpt_bits_uop_fcn_dw), .io_core_lxcpt_bits_uop_fcn_op (_lsu_io_core_lxcpt_bits_uop_fcn_op), .io_core_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), .io_core_lxcpt_bits_uop_fp_rm (_lsu_io_core_lxcpt_bits_uop_fp_rm), .io_core_lxcpt_bits_uop_fp_typ (_lsu_io_core_lxcpt_bits_uop_fp_typ), .io_core_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), .io_core_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), .io_core_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), .io_core_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), .io_core_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), .io_core_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), .io_core_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), .io_core_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), .io_core_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), .io_core_tsc_reg (_core_io_lsu_tsc_reg), // @[tile.scala:158:20] .io_core_status_debug (_core_io_lsu_status_debug), // @[tile.scala:158:20] .io_core_status_cease (_core_io_lsu_status_cease), // @[tile.scala:158:20] .io_core_status_wfi (_core_io_lsu_status_wfi), // @[tile.scala:158:20] .io_core_status_dprv (_core_io_lsu_status_dprv), // @[tile.scala:158:20] .io_core_status_dv (_core_io_lsu_status_dv), // @[tile.scala:158:20] .io_core_status_prv (_core_io_lsu_status_prv), // @[tile.scala:158:20] .io_core_status_v (_core_io_lsu_status_v), // @[tile.scala:158:20] .io_core_status_sd (_core_io_lsu_status_sd), // @[tile.scala:158:20] .io_core_status_mpv (_core_io_lsu_status_mpv), // @[tile.scala:158:20] .io_core_status_gva (_core_io_lsu_status_gva), // @[tile.scala:158:20] .io_core_status_tsr (_core_io_lsu_status_tsr), // @[tile.scala:158:20] .io_core_status_tw (_core_io_lsu_status_tw), // @[tile.scala:158:20] .io_core_status_tvm (_core_io_lsu_status_tvm), // @[tile.scala:158:20] .io_core_status_mxr (_core_io_lsu_status_mxr), // @[tile.scala:158:20] .io_core_status_sum (_core_io_lsu_status_sum), // @[tile.scala:158:20] .io_core_status_mprv (_core_io_lsu_status_mprv), // @[tile.scala:158:20] .io_core_status_fs (_core_io_lsu_status_fs), // @[tile.scala:158:20] .io_core_status_mpp (_core_io_lsu_status_mpp), // @[tile.scala:158:20] .io_core_status_spp (_core_io_lsu_status_spp), // @[tile.scala:158:20] .io_core_status_mpie (_core_io_lsu_status_mpie), // @[tile.scala:158:20] .io_core_status_spie (_core_io_lsu_status_spie), // @[tile.scala:158:20] .io_core_status_mie (_core_io_lsu_status_mie), // @[tile.scala:158:20] .io_core_status_sie (_core_io_lsu_status_sie), // @[tile.scala:158:20] .io_core_perf_acquire (_lsu_io_core_perf_acquire), .io_core_perf_release (_lsu_io_core_perf_release), .io_core_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), .io_dmem_req_ready (_dcache_io_lsu_req_ready), // @[tile.scala:132:54] .io_dmem_req_valid (_lsu_io_dmem_req_valid), .io_dmem_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), .io_dmem_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), .io_dmem_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), .io_dmem_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), .io_dmem_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), .io_dmem_req_bits_0_bits_uop_iq_type_0 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_0), .io_dmem_req_bits_0_bits_uop_iq_type_1 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_1), .io_dmem_req_bits_0_bits_uop_iq_type_2 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_2), .io_dmem_req_bits_0_bits_uop_iq_type_3 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_3), .io_dmem_req_bits_0_bits_uop_fu_code_0 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_0), .io_dmem_req_bits_0_bits_uop_fu_code_1 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_1), .io_dmem_req_bits_0_bits_uop_fu_code_2 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_2), .io_dmem_req_bits_0_bits_uop_fu_code_3 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_3), .io_dmem_req_bits_0_bits_uop_fu_code_4 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_4), .io_dmem_req_bits_0_bits_uop_fu_code_5 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_5), .io_dmem_req_bits_0_bits_uop_fu_code_6 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_6), .io_dmem_req_bits_0_bits_uop_fu_code_7 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_7), .io_dmem_req_bits_0_bits_uop_fu_code_8 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_8), .io_dmem_req_bits_0_bits_uop_fu_code_9 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_9), .io_dmem_req_bits_0_bits_uop_iw_issued (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued), .io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen), .io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen), .io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child), .io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child), .io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint), .io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint), .io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint), .io_dmem_req_bits_0_bits_uop_dis_col_sel (_lsu_io_dmem_req_bits_0_bits_uop_dis_col_sel), .io_dmem_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), .io_dmem_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), .io_dmem_req_bits_0_bits_uop_br_type (_lsu_io_dmem_req_bits_0_bits_uop_br_type), .io_dmem_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), .io_dmem_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), .io_dmem_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), .io_dmem_req_bits_0_bits_uop_is_sfence (_lsu_io_dmem_req_bits_0_bits_uop_is_sfence), .io_dmem_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), .io_dmem_req_bits_0_bits_uop_is_eret (_lsu_io_dmem_req_bits_0_bits_uop_is_eret), .io_dmem_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), .io_dmem_req_bits_0_bits_uop_is_rocc (_lsu_io_dmem_req_bits_0_bits_uop_is_rocc), .io_dmem_req_bits_0_bits_uop_is_mov (_lsu_io_dmem_req_bits_0_bits_uop_is_mov), .io_dmem_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), .io_dmem_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), .io_dmem_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), .io_dmem_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), .io_dmem_req_bits_0_bits_uop_imm_rename (_lsu_io_dmem_req_bits_0_bits_uop_imm_rename), .io_dmem_req_bits_0_bits_uop_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_imm_sel), .io_dmem_req_bits_0_bits_uop_pimm (_lsu_io_dmem_req_bits_0_bits_uop_pimm), .io_dmem_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), .io_dmem_req_bits_0_bits_uop_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_op1_sel), .io_dmem_req_bits_0_bits_uop_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_op2_sel), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst), .io_dmem_req_bits_0_bits_uop_fp_ctrl_wen (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wen), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3), .io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12), .io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23), .io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn), .io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut), .io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint), .io_dmem_req_bits_0_bits_uop_fp_ctrl_toint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_toint), .io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe), .io_dmem_req_bits_0_bits_uop_fp_ctrl_fma (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fma), .io_dmem_req_bits_0_bits_uop_fp_ctrl_div (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_div), .io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt), .io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags), .io_dmem_req_bits_0_bits_uop_fp_ctrl_vec (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_vec), .io_dmem_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), .io_dmem_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), .io_dmem_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), .io_dmem_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), .io_dmem_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), .io_dmem_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), .io_dmem_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), .io_dmem_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), .io_dmem_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), .io_dmem_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), .io_dmem_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), .io_dmem_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), .io_dmem_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), .io_dmem_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), .io_dmem_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), .io_dmem_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), .io_dmem_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), .io_dmem_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), .io_dmem_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), .io_dmem_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), .io_dmem_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), .io_dmem_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), .io_dmem_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), .io_dmem_req_bits_0_bits_uop_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_csr_cmd), .io_dmem_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), .io_dmem_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), .io_dmem_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), .io_dmem_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), .io_dmem_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), .io_dmem_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), .io_dmem_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), .io_dmem_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), .io_dmem_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), .io_dmem_req_bits_0_bits_uop_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_fcn_dw), .io_dmem_req_bits_0_bits_uop_fcn_op (_lsu_io_dmem_req_bits_0_bits_uop_fcn_op), .io_dmem_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), .io_dmem_req_bits_0_bits_uop_fp_rm (_lsu_io_dmem_req_bits_0_bits_uop_fp_rm), .io_dmem_req_bits_0_bits_uop_fp_typ (_lsu_io_dmem_req_bits_0_bits_uop_fp_typ), .io_dmem_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), .io_dmem_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), .io_dmem_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), .io_dmem_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), .io_dmem_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), .io_dmem_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), .io_dmem_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), .io_dmem_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), .io_dmem_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), .io_dmem_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), .io_dmem_s1_kill_0 (_lsu_io_dmem_s1_kill_0), .io_dmem_resp_0_valid (_dcache_io_lsu_resp_0_valid), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_0 (_dcache_io_lsu_resp_0_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_1 (_dcache_io_lsu_resp_0_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_2 (_dcache_io_lsu_resp_0_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_3 (_dcache_io_lsu_resp_0_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_0 (_dcache_io_lsu_resp_0_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_1 (_dcache_io_lsu_resp_0_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_2 (_dcache_io_lsu_resp_0_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_3 (_dcache_io_lsu_resp_0_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_4 (_dcache_io_lsu_resp_0_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_5 (_dcache_io_lsu_resp_0_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_6 (_dcache_io_lsu_resp_0_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_7 (_dcache_io_lsu_resp_0_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_8 (_dcache_io_lsu_resp_0_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_9 (_dcache_io_lsu_resp_0_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_issued (_dcache_io_lsu_resp_0_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_dis_col_sel (_dcache_io_lsu_resp_0_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_br_type (_dcache_io_lsu_resp_0_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_sfence (_dcache_io_lsu_resp_0_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_eret (_dcache_io_lsu_resp_0_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_rocc (_dcache_io_lsu_resp_0_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_mov (_dcache_io_lsu_resp_0_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_imm_rename (_dcache_io_lsu_resp_0_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_imm_sel (_dcache_io_lsu_resp_0_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_pimm (_dcache_io_lsu_resp_0_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_op1_sel (_dcache_io_lsu_resp_0_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_op2_sel (_dcache_io_lsu_resp_0_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fcn_op (_dcache_io_lsu_resp_0_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_rm (_dcache_io_lsu_resp_0_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_typ (_dcache_io_lsu_resp_0_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), // @[tile.scala:132:54] .io_dmem_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), // @[tile.scala:132:54] .io_dmem_store_ack_0_valid (_dcache_io_lsu_store_ack_0_valid), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_inst (_dcache_io_lsu_store_ack_0_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_inst (_dcache_io_lsu_store_ack_0_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_rvc (_dcache_io_lsu_store_ack_0_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_pc (_dcache_io_lsu_store_ack_0_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_0 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_1 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_2 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_3 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_0 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_1 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_2 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_3 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_4 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_5 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_6 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_7 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_8 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_9 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_issued (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_dis_col_sel (_dcache_io_lsu_store_ack_0_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_br_mask (_dcache_io_lsu_store_ack_0_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_br_tag (_dcache_io_lsu_store_ack_0_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_br_type (_dcache_io_lsu_store_ack_0_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_sfb (_dcache_io_lsu_store_ack_0_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_fence (_dcache_io_lsu_store_ack_0_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_fencei (_dcache_io_lsu_store_ack_0_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_sfence (_dcache_io_lsu_store_ack_0_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_amo (_dcache_io_lsu_store_ack_0_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_eret (_dcache_io_lsu_store_ack_0_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_store_ack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_rocc (_dcache_io_lsu_store_ack_0_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_mov (_dcache_io_lsu_store_ack_0_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ftq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_edge_inst (_dcache_io_lsu_store_ack_0_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_pc_lob (_dcache_io_lsu_store_ack_0_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_taken (_dcache_io_lsu_store_ack_0_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_imm_rename (_dcache_io_lsu_store_ack_0_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_imm_sel (_dcache_io_lsu_store_ack_0_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_pimm (_dcache_io_lsu_store_ack_0_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_imm_packed (_dcache_io_lsu_store_ack_0_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_op1_sel (_dcache_io_lsu_store_ack_0_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_op2_sel (_dcache_io_lsu_store_ack_0_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_rob_idx (_dcache_io_lsu_store_ack_0_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ldq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_stq_idx (_dcache_io_lsu_store_ack_0_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_rxq_idx (_dcache_io_lsu_store_ack_0_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_pdst (_dcache_io_lsu_store_ack_0_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs1 (_dcache_io_lsu_store_ack_0_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs2 (_dcache_io_lsu_store_ack_0_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs3 (_dcache_io_lsu_store_ack_0_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ppred (_dcache_io_lsu_store_ack_0_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs1_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs2_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs3_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ppred_busy (_dcache_io_lsu_store_ack_0_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_stale_pdst (_dcache_io_lsu_store_ack_0_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_exception (_dcache_io_lsu_store_ack_0_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_exc_cause (_dcache_io_lsu_store_ack_0_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_mem_cmd (_dcache_io_lsu_store_ack_0_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_mem_size (_dcache_io_lsu_store_ack_0_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_mem_signed (_dcache_io_lsu_store_ack_0_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_uses_ldq (_dcache_io_lsu_store_ack_0_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_uses_stq (_dcache_io_lsu_store_ack_0_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_unique (_dcache_io_lsu_store_ack_0_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_flush_on_commit (_dcache_io_lsu_store_ack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_csr_cmd (_dcache_io_lsu_store_ack_0_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_store_ack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ldst (_dcache_io_lsu_store_ack_0_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs1 (_dcache_io_lsu_store_ack_0_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs2 (_dcache_io_lsu_store_ack_0_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs3 (_dcache_io_lsu_store_ack_0_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_dst_rtype (_dcache_io_lsu_store_ack_0_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_frs3_en (_dcache_io_lsu_store_ack_0_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fcn_dw (_dcache_io_lsu_store_ack_0_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fcn_op (_dcache_io_lsu_store_ack_0_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_val (_dcache_io_lsu_store_ack_0_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_rm (_dcache_io_lsu_store_ack_0_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_typ (_dcache_io_lsu_store_ack_0_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_bp_debug_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_fsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_tsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_addr (_dcache_io_lsu_store_ack_0_bits_addr), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_data (_dcache_io_lsu_store_ack_0_bits_data), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_is_hella (_dcache_io_lsu_store_ack_0_bits_is_hella), // @[tile.scala:132:54] .io_dmem_nack_0_valid (_dcache_io_lsu_nack_0_valid), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_0 (_dcache_io_lsu_nack_0_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_1 (_dcache_io_lsu_nack_0_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_2 (_dcache_io_lsu_nack_0_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_3 (_dcache_io_lsu_nack_0_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_0 (_dcache_io_lsu_nack_0_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_1 (_dcache_io_lsu_nack_0_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_2 (_dcache_io_lsu_nack_0_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_3 (_dcache_io_lsu_nack_0_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_4 (_dcache_io_lsu_nack_0_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_5 (_dcache_io_lsu_nack_0_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_6 (_dcache_io_lsu_nack_0_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_7 (_dcache_io_lsu_nack_0_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_8 (_dcache_io_lsu_nack_0_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_9 (_dcache_io_lsu_nack_0_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_issued (_dcache_io_lsu_nack_0_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_dis_col_sel (_dcache_io_lsu_nack_0_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_br_type (_dcache_io_lsu_nack_0_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_sfence (_dcache_io_lsu_nack_0_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_eret (_dcache_io_lsu_nack_0_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_rocc (_dcache_io_lsu_nack_0_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_mov (_dcache_io_lsu_nack_0_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_imm_rename (_dcache_io_lsu_nack_0_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_imm_sel (_dcache_io_lsu_nack_0_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_pimm (_dcache_io_lsu_nack_0_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_op1_sel (_dcache_io_lsu_nack_0_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_op2_sel (_dcache_io_lsu_nack_0_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fcn_op (_dcache_io_lsu_nack_0_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_rm (_dcache_io_lsu_nack_0_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_typ (_dcache_io_lsu_nack_0_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), // @[tile.scala:132:54] .io_dmem_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), // @[tile.scala:132:54] .io_dmem_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), // @[tile.scala:132:54] .io_dmem_ll_resp_ready (_lsu_io_dmem_ll_resp_ready), .io_dmem_ll_resp_valid (_dcache_io_lsu_ll_resp_valid), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_inst (_dcache_io_lsu_ll_resp_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_inst (_dcache_io_lsu_ll_resp_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_rvc (_dcache_io_lsu_ll_resp_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_pc (_dcache_io_lsu_ll_resp_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_0 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_1 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_2 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_3 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_0 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_1 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_2 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_3 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_4 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_5 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_6 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_7 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_8 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_9 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_issued (_dcache_io_lsu_ll_resp_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_dis_col_sel (_dcache_io_lsu_ll_resp_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_br_mask (_dcache_io_lsu_ll_resp_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_br_tag (_dcache_io_lsu_ll_resp_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_br_type (_dcache_io_lsu_ll_resp_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_sfb (_dcache_io_lsu_ll_resp_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_fence (_dcache_io_lsu_ll_resp_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_fencei (_dcache_io_lsu_ll_resp_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_sfence (_dcache_io_lsu_ll_resp_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_amo (_dcache_io_lsu_ll_resp_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_eret (_dcache_io_lsu_ll_resp_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_sys_pc2epc (_dcache_io_lsu_ll_resp_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_rocc (_dcache_io_lsu_ll_resp_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_mov (_dcache_io_lsu_ll_resp_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ftq_idx (_dcache_io_lsu_ll_resp_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_edge_inst (_dcache_io_lsu_ll_resp_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_pc_lob (_dcache_io_lsu_ll_resp_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_taken (_dcache_io_lsu_ll_resp_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_imm_rename (_dcache_io_lsu_ll_resp_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_imm_sel (_dcache_io_lsu_ll_resp_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_pimm (_dcache_io_lsu_ll_resp_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_imm_packed (_dcache_io_lsu_ll_resp_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_op1_sel (_dcache_io_lsu_ll_resp_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_op2_sel (_dcache_io_lsu_ll_resp_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_wen (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_toint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_fma (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_div (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_vec (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_rob_idx (_dcache_io_lsu_ll_resp_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ldq_idx (_dcache_io_lsu_ll_resp_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_stq_idx (_dcache_io_lsu_ll_resp_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_rxq_idx (_dcache_io_lsu_ll_resp_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_pdst (_dcache_io_lsu_ll_resp_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs1 (_dcache_io_lsu_ll_resp_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs2 (_dcache_io_lsu_ll_resp_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs3 (_dcache_io_lsu_ll_resp_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ppred (_dcache_io_lsu_ll_resp_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs1_busy (_dcache_io_lsu_ll_resp_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs2_busy (_dcache_io_lsu_ll_resp_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs3_busy (_dcache_io_lsu_ll_resp_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ppred_busy (_dcache_io_lsu_ll_resp_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_stale_pdst (_dcache_io_lsu_ll_resp_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_exception (_dcache_io_lsu_ll_resp_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_exc_cause (_dcache_io_lsu_ll_resp_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_mem_cmd (_dcache_io_lsu_ll_resp_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_mem_size (_dcache_io_lsu_ll_resp_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_mem_signed (_dcache_io_lsu_ll_resp_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_uses_ldq (_dcache_io_lsu_ll_resp_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_uses_stq (_dcache_io_lsu_ll_resp_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_unique (_dcache_io_lsu_ll_resp_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_flush_on_commit (_dcache_io_lsu_ll_resp_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_csr_cmd (_dcache_io_lsu_ll_resp_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ldst_is_rs1 (_dcache_io_lsu_ll_resp_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ldst (_dcache_io_lsu_ll_resp_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs1 (_dcache_io_lsu_ll_resp_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs2 (_dcache_io_lsu_ll_resp_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs3 (_dcache_io_lsu_ll_resp_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_dst_rtype (_dcache_io_lsu_ll_resp_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs1_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs2_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_frs3_en (_dcache_io_lsu_ll_resp_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fcn_dw (_dcache_io_lsu_ll_resp_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fcn_op (_dcache_io_lsu_ll_resp_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_val (_dcache_io_lsu_ll_resp_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_rm (_dcache_io_lsu_ll_resp_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_typ (_dcache_io_lsu_ll_resp_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_xcpt_pf_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_xcpt_ae_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_xcpt_ma_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_bp_debug_if (_dcache_io_lsu_ll_resp_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_bp_xcpt_if (_dcache_io_lsu_ll_resp_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_fsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_tsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_data (_dcache_io_lsu_ll_resp_bits_data), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_is_hella (_dcache_io_lsu_ll_resp_bits_is_hella), // @[tile.scala:132:54] .io_dmem_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), .io_dmem_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), .io_dmem_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), .io_dmem_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), .io_dmem_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), .io_dmem_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), .io_dmem_brupdate_b2_uop_iq_type_0 (_lsu_io_dmem_brupdate_b2_uop_iq_type_0), .io_dmem_brupdate_b2_uop_iq_type_1 (_lsu_io_dmem_brupdate_b2_uop_iq_type_1), .io_dmem_brupdate_b2_uop_iq_type_2 (_lsu_io_dmem_brupdate_b2_uop_iq_type_2), .io_dmem_brupdate_b2_uop_iq_type_3 (_lsu_io_dmem_brupdate_b2_uop_iq_type_3), .io_dmem_brupdate_b2_uop_fu_code_0 (_lsu_io_dmem_brupdate_b2_uop_fu_code_0), .io_dmem_brupdate_b2_uop_fu_code_1 (_lsu_io_dmem_brupdate_b2_uop_fu_code_1), .io_dmem_brupdate_b2_uop_fu_code_2 (_lsu_io_dmem_brupdate_b2_uop_fu_code_2), .io_dmem_brupdate_b2_uop_fu_code_3 (_lsu_io_dmem_brupdate_b2_uop_fu_code_3), .io_dmem_brupdate_b2_uop_fu_code_4 (_lsu_io_dmem_brupdate_b2_uop_fu_code_4), .io_dmem_brupdate_b2_uop_fu_code_5 (_lsu_io_dmem_brupdate_b2_uop_fu_code_5), .io_dmem_brupdate_b2_uop_fu_code_6 (_lsu_io_dmem_brupdate_b2_uop_fu_code_6), .io_dmem_brupdate_b2_uop_fu_code_7 (_lsu_io_dmem_brupdate_b2_uop_fu_code_7), .io_dmem_brupdate_b2_uop_fu_code_8 (_lsu_io_dmem_brupdate_b2_uop_fu_code_8), .io_dmem_brupdate_b2_uop_fu_code_9 (_lsu_io_dmem_brupdate_b2_uop_fu_code_9), .io_dmem_brupdate_b2_uop_iw_issued (_lsu_io_dmem_brupdate_b2_uop_iw_issued), .io_dmem_brupdate_b2_uop_iw_issued_partial_agen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_agen), .io_dmem_brupdate_b2_uop_iw_issued_partial_dgen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_dgen), .io_dmem_brupdate_b2_uop_iw_p1_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p1_speculative_child), .io_dmem_brupdate_b2_uop_iw_p2_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p2_speculative_child), .io_dmem_brupdate_b2_uop_iw_p1_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p1_bypass_hint), .io_dmem_brupdate_b2_uop_iw_p2_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p2_bypass_hint), .io_dmem_brupdate_b2_uop_iw_p3_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p3_bypass_hint), .io_dmem_brupdate_b2_uop_dis_col_sel (_lsu_io_dmem_brupdate_b2_uop_dis_col_sel), .io_dmem_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), .io_dmem_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), .io_dmem_brupdate_b2_uop_br_type (_lsu_io_dmem_brupdate_b2_uop_br_type), .io_dmem_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), .io_dmem_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), .io_dmem_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), .io_dmem_brupdate_b2_uop_is_sfence (_lsu_io_dmem_brupdate_b2_uop_is_sfence), .io_dmem_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), .io_dmem_brupdate_b2_uop_is_eret (_lsu_io_dmem_brupdate_b2_uop_is_eret), .io_dmem_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), .io_dmem_brupdate_b2_uop_is_rocc (_lsu_io_dmem_brupdate_b2_uop_is_rocc), .io_dmem_brupdate_b2_uop_is_mov (_lsu_io_dmem_brupdate_b2_uop_is_mov), .io_dmem_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), .io_dmem_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), .io_dmem_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), .io_dmem_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), .io_dmem_brupdate_b2_uop_imm_rename (_lsu_io_dmem_brupdate_b2_uop_imm_rename), .io_dmem_brupdate_b2_uop_imm_sel (_lsu_io_dmem_brupdate_b2_uop_imm_sel), .io_dmem_brupdate_b2_uop_pimm (_lsu_io_dmem_brupdate_b2_uop_pimm), .io_dmem_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), .io_dmem_brupdate_b2_uop_op1_sel (_lsu_io_dmem_brupdate_b2_uop_op1_sel), .io_dmem_brupdate_b2_uop_op2_sel (_lsu_io_dmem_brupdate_b2_uop_op2_sel), .io_dmem_brupdate_b2_uop_fp_ctrl_ldst (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ldst), .io_dmem_brupdate_b2_uop_fp_ctrl_wen (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wen), .io_dmem_brupdate_b2_uop_fp_ctrl_ren1 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren1), .io_dmem_brupdate_b2_uop_fp_ctrl_ren2 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren2), .io_dmem_brupdate_b2_uop_fp_ctrl_ren3 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren3), .io_dmem_brupdate_b2_uop_fp_ctrl_swap12 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap12), .io_dmem_brupdate_b2_uop_fp_ctrl_swap23 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap23), .io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn), .io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut), .io_dmem_brupdate_b2_uop_fp_ctrl_fromint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fromint), .io_dmem_brupdate_b2_uop_fp_ctrl_toint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_toint), .io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe), .io_dmem_brupdate_b2_uop_fp_ctrl_fma (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fma), .io_dmem_brupdate_b2_uop_fp_ctrl_div (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_div), .io_dmem_brupdate_b2_uop_fp_ctrl_sqrt (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_sqrt), .io_dmem_brupdate_b2_uop_fp_ctrl_wflags (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wflags), .io_dmem_brupdate_b2_uop_fp_ctrl_vec (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_vec), .io_dmem_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), .io_dmem_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), .io_dmem_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), .io_dmem_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), .io_dmem_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), .io_dmem_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), .io_dmem_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), .io_dmem_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), .io_dmem_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), .io_dmem_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), .io_dmem_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), .io_dmem_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), .io_dmem_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), .io_dmem_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), .io_dmem_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), .io_dmem_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), .io_dmem_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), .io_dmem_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), .io_dmem_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), .io_dmem_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), .io_dmem_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), .io_dmem_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), .io_dmem_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), .io_dmem_brupdate_b2_uop_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_csr_cmd), .io_dmem_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), .io_dmem_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), .io_dmem_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), .io_dmem_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), .io_dmem_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), .io_dmem_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), .io_dmem_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), .io_dmem_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), .io_dmem_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), .io_dmem_brupdate_b2_uop_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_fcn_dw), .io_dmem_brupdate_b2_uop_fcn_op (_lsu_io_dmem_brupdate_b2_uop_fcn_op), .io_dmem_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), .io_dmem_brupdate_b2_uop_fp_rm (_lsu_io_dmem_brupdate_b2_uop_fp_rm), .io_dmem_brupdate_b2_uop_fp_typ (_lsu_io_dmem_brupdate_b2_uop_fp_typ), .io_dmem_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), .io_dmem_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), .io_dmem_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), .io_dmem_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), .io_dmem_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), .io_dmem_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), .io_dmem_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), .io_dmem_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), .io_dmem_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), .io_dmem_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), .io_dmem_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), .io_dmem_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), .io_dmem_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), .io_dmem_exception (_lsu_io_dmem_exception), .io_dmem_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), .io_dmem_rob_head_idx (_lsu_io_dmem_rob_head_idx), .io_dmem_release_ready (_lsu_io_dmem_release_ready), .io_dmem_release_valid (_dcache_io_lsu_release_valid), // @[tile.scala:132:54] .io_dmem_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), // @[tile.scala:132:54] .io_dmem_release_bits_param (_dcache_io_lsu_release_bits_param), // @[tile.scala:132:54] .io_dmem_release_bits_size (_dcache_io_lsu_release_bits_size), // @[tile.scala:132:54] .io_dmem_release_bits_source (_dcache_io_lsu_release_bits_source), // @[tile.scala:132:54] .io_dmem_release_bits_address (_dcache_io_lsu_release_bits_address), // @[tile.scala:132:54] .io_dmem_release_bits_data (_dcache_io_lsu_release_bits_data), // @[tile.scala:132:54] .io_dmem_force_order (_lsu_io_dmem_force_order), .io_dmem_ordered (_dcache_io_lsu_ordered), // @[tile.scala:132:54] .io_dmem_perf_acquire (_dcache_io_lsu_perf_acquire), // @[tile.scala:132:54] .io_dmem_perf_release (_dcache_io_lsu_perf_release), // @[tile.scala:132:54] .io_hellacache_req_ready (_lsu_io_hellacache_req_ready), .io_hellacache_req_valid (_hellaCacheArb_io_mem_req_valid), // @[tile.scala:242:29] .io_hellacache_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), // @[tile.scala:242:29] .io_hellacache_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), // @[tile.scala:242:29] .io_hellacache_s1_kill (_hellaCacheArb_io_mem_s1_kill), // @[tile.scala:242:29] .io_hellacache_s2_nack (_lsu_io_hellacache_s2_nack), .io_hellacache_resp_valid (_lsu_io_hellacache_resp_valid), .io_hellacache_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), .io_hellacache_resp_bits_dprv (_lsu_io_hellacache_resp_bits_dprv), .io_hellacache_resp_bits_dv (_lsu_io_hellacache_resp_bits_dv), .io_hellacache_resp_bits_data (_lsu_io_hellacache_resp_bits_data), .io_hellacache_resp_bits_data_word_bypass (_lsu_io_hellacache_resp_bits_data_word_bypass), .io_hellacache_resp_bits_data_raw (_lsu_io_hellacache_resp_bits_data_raw), .io_hellacache_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), .io_hellacache_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), .io_hellacache_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), .io_hellacache_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), .io_hellacache_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), .io_hellacache_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), .io_hellacache_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), .io_hellacache_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), .io_hellacache_store_pending (_lsu_io_hellacache_store_pending) ); // @[tile.scala:159:20] PTW ptw ( // @[tile.scala:236:20] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_lsu_io_ptw_req_valid), // @[tile.scala:159:20] .io_requestor_0_req_bits_valid (_lsu_io_ptw_req_bits_valid), // @[tile.scala:159:20] .io_requestor_0_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), // @[tile.scala:159:20] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[tile.scala:137:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[tile.scala:137:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[tile.scala:137:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready), .io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid), .io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), .io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), .io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), .io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), .io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), .io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), .io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), .io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), .io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), .io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), .io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), .io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), .io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), .io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), .io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), .io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), .io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), .io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), .io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), .io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), .io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), .io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), .io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), .io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), .io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), .io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug), .io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease), .io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi), .io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv), .io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv), .io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv), .io_requestor_2_status_v (_ptw_io_requestor_2_status_v), .io_requestor_2_status_sd (_ptw_io_requestor_2_status_sd), .io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv), .io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva), .io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr), .io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw), .io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm), .io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr), .io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum), .io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv), .io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs), .io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp), .io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp), .io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie), .io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie), .io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie), .io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie), .io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), .io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), .io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), .io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), .io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), .io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), .io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), .io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), .io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), .io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), .io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), .io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), .io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), .io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), .io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), .io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), .io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), .io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), .io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), .io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), .io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), .io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), .io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), .io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), .io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), .io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), .io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), .io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), .io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), .io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), .io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), .io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), .io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), .io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), .io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), .io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), .io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), .io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), .io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), .io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), .io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), .io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), .io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), .io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), .io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), .io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), .io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), .io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), .io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), .io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), .io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), .io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), .io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), .io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), .io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), .io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), .io_mem_req_ready (_hellaCacheArb_io_requestor_0_req_ready), // @[tile.scala:242:29] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), // @[tile.scala:242:29] .io_mem_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), // @[tile.scala:242:29] .io_mem_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), // @[tile.scala:242:29] .io_mem_resp_bits_dprv (_hellaCacheArb_io_requestor_0_resp_bits_dprv), // @[tile.scala:242:29] .io_mem_resp_bits_dv (_hellaCacheArb_io_requestor_0_resp_bits_dv), // @[tile.scala:242:29] .io_mem_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), // @[tile.scala:242:29] .io_mem_resp_bits_data_word_bypass (_hellaCacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[tile.scala:242:29] .io_mem_resp_bits_data_raw (_hellaCacheArb_io_requestor_0_resp_bits_data_raw), // @[tile.scala:242:29] .io_mem_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), // @[tile.scala:242:29] .io_mem_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), // @[tile.scala:242:29] .io_mem_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), // @[tile.scala:242:29] .io_mem_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), // @[tile.scala:242:29] .io_mem_store_pending (_hellaCacheArb_io_requestor_0_store_pending), // @[tile.scala:242:29] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[tile.scala:158:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[tile.scala:158:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[tile.scala:158:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[tile.scala:158:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[tile.scala:158:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[tile.scala:158:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[tile.scala:158:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[tile.scala:158:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[tile.scala:158:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[tile.scala:158:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[tile.scala:158:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[tile.scala:158:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[tile.scala:158:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[tile.scala:158:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[tile.scala:158:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[tile.scala:158:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[tile.scala:158:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[tile.scala:158:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[tile.scala:158:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[tile.scala:158:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[tile.scala:158:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[tile.scala:158:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[tile.scala:158:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[tile.scala:158:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[tile.scala:158:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[tile.scala:158:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[tile.scala:158:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[tile.scala:158:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[tile.scala:158:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[tile.scala:158:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[tile.scala:158:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[tile.scala:158:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[tile.scala:158:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[tile.scala:158:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[tile.scala:158:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[tile.scala:158:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[tile.scala:158:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[tile.scala:158:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[tile.scala:158:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[tile.scala:158:20] .io_dpath_perf_l2miss (_ptw_io_dpath_perf_l2miss), .io_dpath_perf_l2hit (_ptw_io_dpath_perf_l2hit), .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[tile.scala:236:20] HellaCacheArbiter hellaCacheArb ( // @[tile.scala:242:29] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_hellaCacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[tile.scala:236:20] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[tile.scala:236:20] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[tile.scala:236:20] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[tile.scala:236:20] .io_requestor_0_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), .io_requestor_0_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_dprv (_hellaCacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_hellaCacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_data_word_bypass (_hellaCacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_hellaCacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), .io_requestor_0_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), .io_requestor_0_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_store_pending (_hellaCacheArb_io_requestor_0_store_pending), .io_mem_req_ready (_lsu_io_hellacache_req_ready), // @[tile.scala:159:20] .io_mem_req_valid (_hellaCacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), .io_mem_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), .io_mem_s1_kill (_hellaCacheArb_io_mem_s1_kill), .io_mem_s2_nack (_lsu_io_hellacache_s2_nack), // @[tile.scala:159:20] .io_mem_resp_valid (_lsu_io_hellacache_resp_valid), // @[tile.scala:159:20] .io_mem_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), // @[tile.scala:159:20] .io_mem_resp_bits_dprv (_lsu_io_hellacache_resp_bits_dprv), // @[tile.scala:159:20] .io_mem_resp_bits_dv (_lsu_io_hellacache_resp_bits_dv), // @[tile.scala:159:20] .io_mem_resp_bits_data (_lsu_io_hellacache_resp_bits_data), // @[tile.scala:159:20] .io_mem_resp_bits_data_word_bypass (_lsu_io_hellacache_resp_bits_data_word_bypass), // @[tile.scala:159:20] .io_mem_resp_bits_data_raw (_lsu_io_hellacache_resp_bits_data_raw), // @[tile.scala:159:20] .io_mem_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), // @[tile.scala:159:20] .io_mem_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), // @[tile.scala:159:20] .io_mem_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), // @[tile.scala:159:20] .io_mem_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), // @[tile.scala:159:20] .io_mem_store_pending (_lsu_io_hellacache_store_pending) // @[tile.scala:159:20] ); // @[tile.scala:242:29] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[tile.scala:154:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[tile.scala:154:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_corrupt = auto_buffer_out_c_bits_corrupt_0; // @[tile.scala:154:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[tile.scala:154:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[tile.scala:154:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[tile.scala:154:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[tile.scala:154:7] assign auto_trace_source_out_custom_rob_empty = auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:154:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_1 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_1 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h14), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h18), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h12), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow	module EgressUnit_1( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module DTLB_5 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) node memIdx = bits(vpn, 1, 0) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4][4], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[1], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<0>, clock reg r_sectored_repl_addr : UInt<2>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<0>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_49 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_5 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_5 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _sector_hits_T_1 = shr(_sector_hits_T, 0) node _sector_hits_T_2 = eq(_sector_hits_T_1, UInt<1>(0h0)) node _sector_hits_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _sector_hits_T_4 = and(_sector_hits_T_2, _sector_hits_T_3) node sector_hits_0 = and(sectored_entries[memIdx][0].valid[0], _sector_hits_T_4) node _sector_hits_T_5 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _sector_hits_T_6 = shr(_sector_hits_T_5, 0) node _sector_hits_T_7 = eq(_sector_hits_T_6, UInt<1>(0h0)) node _sector_hits_T_8 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _sector_hits_T_9 = and(_sector_hits_T_7, _sector_hits_T_8) node sector_hits_1 = and(sectored_entries[memIdx][1].valid[0], _sector_hits_T_9) node _sector_hits_T_10 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _sector_hits_T_11 = shr(_sector_hits_T_10, 0) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _sector_hits_T_14 = and(_sector_hits_T_12, _sector_hits_T_13) node sector_hits_2 = and(sectored_entries[memIdx][2].valid[0], _sector_hits_T_14) node _sector_hits_T_15 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _sector_hits_T_16 = shr(_sector_hits_T_15, 0) node _sector_hits_T_17 = eq(_sector_hits_T_16, UInt<1>(0h0)) node _sector_hits_T_18 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _sector_hits_T_19 = and(_sector_hits_T_17, _sector_hits_T_18) node sector_hits_3 = and(sectored_entries[memIdx][3].valid[0], _sector_hits_T_19) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _hitsVec_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 0) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[memIdx][0].valid[0], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node _hitsVec_T_6 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[memIdx][1].valid[0], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node _hitsVec_T_12 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[memIdx][2].valid[0], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node _hitsVec_T_18 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[memIdx][3].valid[0], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_24 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_25 = bits(_hitsVec_T_24, 26, 18) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = or(hitsVec_ignore, _hitsVec_T_26) node _hitsVec_T_28 = and(hitsVec_tagMatch, _hitsVec_T_27) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_29 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_30 = bits(_hitsVec_T_29, 17, 9) node _hitsVec_T_31 = eq(_hitsVec_T_30, UInt<1>(0h0)) node _hitsVec_T_32 = or(hitsVec_ignore_1, _hitsVec_T_31) node _hitsVec_T_33 = and(_hitsVec_T_28, _hitsVec_T_32) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_34 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_35 = bits(_hitsVec_T_34, 8, 0) node _hitsVec_T_36 = eq(_hitsVec_T_35, UInt<1>(0h0)) node _hitsVec_T_37 = or(hitsVec_ignore_2, _hitsVec_T_36) node _hitsVec_T_38 = and(_hitsVec_T_33, _hitsVec_T_37) node hitsVec_4 = and(vm_enabled, _hitsVec_T_38) node _hitsVec_tagMatch_T_1 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_1 = and(special_entry.valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_39 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_40 = bits(_hitsVec_T_39, 26, 18) node _hitsVec_T_41 = eq(_hitsVec_T_40, UInt<1>(0h0)) node _hitsVec_T_42 = or(hitsVec_ignore_3, _hitsVec_T_41) node _hitsVec_T_43 = and(hitsVec_tagMatch_1, _hitsVec_T_42) node _hitsVec_ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_44 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_45 = bits(_hitsVec_T_44, 17, 9) node _hitsVec_T_46 = eq(_hitsVec_T_45, UInt<1>(0h0)) node _hitsVec_T_47 = or(hitsVec_ignore_4, _hitsVec_T_46) node _hitsVec_T_48 = and(_hitsVec_T_43, _hitsVec_T_47) node _hitsVec_ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h0)) node _hitsVec_T_49 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_50 = bits(_hitsVec_T_49, 8, 0) node _hitsVec_T_51 = eq(_hitsVec_T_50, UInt<1>(0h0)) node _hitsVec_T_52 = or(hitsVec_ignore_5, _hitsVec_T_51) node _hitsVec_T_53 = and(_hitsVec_T_48, _hitsVec_T_52) node hitsVec_5 = and(vm_enabled, _hitsVec_T_53) node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node r_memIdx = bits(r_refill_tag, 1, 0) node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_4 = eq(waddr_1, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_5 : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][0].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][0].tag_v, refill_v connect sectored_entries[r_memIdx][0].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h1) node sectored_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_0_lo_lo_hi = cat(sectored_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_data_0_lo_lo = cat(sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo) node sectored_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_0_lo_hi_lo = cat(sectored_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_data_0_lo_hi_hi = cat(sectored_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_data_0_lo_hi = cat(sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo) node sectored_entries_0_data_0_lo = cat(sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo) node sectored_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_data_0_hi_lo_lo = cat(sectored_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_data_0_hi_lo_hi = cat(sectored_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_data_0_hi_lo = cat(sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo) node sectored_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_data_0_hi_hi_lo = cat(sectored_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_0_hi_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_data_0_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo) node sectored_entries_0_data_0_hi = cat(sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo) node _sectored_entries_0_data_0_T = cat(sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo) connect sectored_entries[r_memIdx][0].data[0], _sectored_entries_0_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) node _T_6 = eq(waddr_1, UInt<1>(0h1)) when _T_6 : node _T_7 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_7 : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][1].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][1].tag_v, refill_v connect sectored_entries[r_memIdx][1].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h1) node sectored_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_0_lo_lo_hi = cat(sectored_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_1_data_0_lo_lo = cat(sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo) node sectored_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_0_lo_hi_lo = cat(sectored_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_1_data_0_lo_hi_hi = cat(sectored_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_1_data_0_lo_hi = cat(sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo) node sectored_entries_1_data_0_lo = cat(sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo) node sectored_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_1_data_0_hi_lo_lo = cat(sectored_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_1_data_0_hi_lo_hi = cat(sectored_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_1_data_0_hi_lo = cat(sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo) node sectored_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_1_data_0_hi_hi_lo = cat(sectored_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_0_hi_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_1_data_0_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo) node sectored_entries_1_data_0_hi = cat(sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo) node _sectored_entries_1_data_0_T = cat(sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo) connect sectored_entries[r_memIdx][1].data[0], _sectored_entries_1_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) node _T_8 = eq(waddr_1, UInt<2>(0h2)) when _T_8 : node _T_9 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_9 : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][2].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][2].tag_v, refill_v connect sectored_entries[r_memIdx][2].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h1) node sectored_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_0_lo_lo_hi = cat(sectored_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_2_data_0_lo_lo = cat(sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo) node sectored_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_0_lo_hi_lo = cat(sectored_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_2_data_0_lo_hi_hi = cat(sectored_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_2_data_0_lo_hi = cat(sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo) node sectored_entries_2_data_0_lo = cat(sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo) node sectored_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_2_data_0_hi_lo_lo = cat(sectored_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_2_data_0_hi_lo_hi = cat(sectored_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_2_data_0_hi_lo = cat(sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo) node sectored_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_2_data_0_hi_hi_lo = cat(sectored_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_0_hi_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_2_data_0_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo) node sectored_entries_2_data_0_hi = cat(sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo) node _sectored_entries_2_data_0_T = cat(sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo) connect sectored_entries[r_memIdx][2].data[0], _sectored_entries_2_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) node _T_10 = eq(waddr_1, UInt<2>(0h3)) when _T_10 : node _T_11 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_11 : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][3].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][3].tag_v, refill_v connect sectored_entries[r_memIdx][3].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h1) node sectored_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_0_lo_lo_hi = cat(sectored_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_3_data_0_lo_lo = cat(sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo) node sectored_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_0_lo_hi_lo = cat(sectored_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_3_data_0_lo_hi_hi = cat(sectored_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_3_data_0_lo_hi = cat(sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo) node sectored_entries_3_data_0_lo = cat(sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo) node sectored_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_3_data_0_hi_lo_lo = cat(sectored_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_3_data_0_hi_lo_hi = cat(sectored_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_3_data_0_hi_lo = cat(sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo) node sectored_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_3_data_0_hi_hi_lo = cat(sectored_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_0_hi_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_3_data_0_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo) node sectored_entries_3_data_0_hi = cat(sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo) node _sectored_entries_3_data_0_T = cat(sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo) connect sectored_entries[r_memIdx][3].data[0], _sectored_entries_3_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[memIdx][0].data[0] node _entries_T = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T node _entries_T_1 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_22 inst entries_barrier of OptimizationBarrier_TLBEntryData_50 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[memIdx][1].data[0] node _entries_T_23 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_45 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_51 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[memIdx][2].data[0] node _entries_T_46 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_68 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_52 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[memIdx][3].data[0] node _entries_T_69 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_91 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_53 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, superpage_entries[0].data[0] node _entries_T_92 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_114 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_54 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, special_entry.data[0] node _entries_T_115 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_137 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_55 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_4.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_4.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_4.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_5.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h0)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_5.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node _ppn_T_17 = bits(vpn, 19, 0) node _ppn_T_18 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_19 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_20 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_21 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_22 = mux(hitsVec_4, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_23 = mux(hitsVec_5, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_24 = mux(_ppn_T, _ppn_T_17, UInt<1>(0h0)) node _ppn_T_25 = or(_ppn_T_18, _ppn_T_19) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_20) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_21) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_22) node _ppn_T_29 = or(_ppn_T_28, _ppn_T_23) node _ppn_T_30 = or(_ppn_T_29, _ppn_T_24) wire ppn : UInt<20> connect ppn, _ppn_T_30 node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<7>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<3>, clock, reset, UInt<3>(0h0) wire _state_vec_WIRE : UInt<3>[4] connect _state_vec_WIRE[0], UInt<3>(0h0) connect _state_vec_WIRE[1], UInt<3>(0h0) connect _state_vec_WIRE[2], UInt<3>(0h0) connect _state_vec_WIRE[3], UInt<3>(0h0) regreset state_vec : UInt<3>[4], clock, reset, _state_vec_WIRE reg state_reg_1 : UInt<0>, clock node _T_12 = and(io.req.valid, vm_enabled) when _T_12 : node _T_13 = or(sector_hits_0, sector_hits_1) node _T_14 = or(_T_13, sector_hits_2) node _T_15 = or(_T_14, sector_hits_3) when _T_15 : node lo = cat(sector_hits_1, sector_hits_0) node hi = cat(sector_hits_3, sector_hits_2) node _T_16 = cat(hi, lo) node hi_1 = bits(_T_16, 3, 2) node lo_1 = bits(_T_16, 1, 0) node _T_17 = orr(hi_1) node _T_18 = or(hi_1, lo_1) node _T_19 = bits(_T_18, 1, 1) node _T_20 = cat(_T_17, _T_19) node state_vec_touch_way_sized = bits(_T_20, 1, 0) node _state_vec_set_left_older_T = bits(state_vec_touch_way_sized, 1, 1) node state_vec_set_left_older = eq(_state_vec_set_left_older_T, UInt<1>(0h0)) node state_vec_left_subtree_state = bits(state_vec[memIdx], 1, 1) node state_vec_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _state_vec_T = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_1 = bits(_state_vec_T, 0, 0) node _state_vec_T_2 = eq(_state_vec_T_1, UInt<1>(0h0)) node _state_vec_T_3 = mux(state_vec_set_left_older, state_vec_left_subtree_state, _state_vec_T_2) node _state_vec_T_4 = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_5 = bits(_state_vec_T_4, 0, 0) node _state_vec_T_6 = eq(_state_vec_T_5, UInt<1>(0h0)) node _state_vec_T_7 = mux(state_vec_set_left_older, _state_vec_T_6, state_vec_right_subtree_state) node state_vec_hi = cat(state_vec_set_left_older, _state_vec_T_3) node _state_vec_T_8 = cat(state_vec_hi, _state_vec_T_7) connect state_vec[memIdx], _state_vec_T_8 when superpage_hits_0 : connect state_reg_1, UInt<1>(0h0) node _multipleHits_T = bits(real_hits, 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits, 5, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_21 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_22 = and(_T_21, io.ptw.req.bits.valid) when _T_22 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_23 = and(io.req.ready, io.req.valid) node _T_24 = and(_T_23, tlb_miss) when _T_24 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node _r_superpage_repl_addr_T = andr(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_1 = not(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_2 = bits(_r_superpage_repl_addr_T_1, 0, 0) node _r_superpage_repl_addr_T_3 = mux(_r_superpage_repl_addr_T, UInt<1>(0h0), UInt<1>(0h0)) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_3 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[memIdx], 2, 2) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[memIdx], 1, 1) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_valids_lo = cat(sectored_entries[memIdx][1].valid[0], sectored_entries[memIdx][0].valid[0]) node r_sectored_repl_addr_valids_hi = cat(sectored_entries[memIdx][3].valid[0], sectored_entries[memIdx][2].valid[0]) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_4 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_5 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_6 = bits(_r_sectored_repl_addr_T_5, 0, 0) node _r_sectored_repl_addr_T_7 = bits(_r_sectored_repl_addr_T_5, 1, 1) node _r_sectored_repl_addr_T_8 = bits(_r_sectored_repl_addr_T_5, 2, 2) node _r_sectored_repl_addr_T_9 = bits(_r_sectored_repl_addr_T_5, 3, 3) node _r_sectored_repl_addr_T_10 = mux(_r_sectored_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_sectored_repl_addr_T_11 = mux(_r_sectored_repl_addr_T_7, UInt<1>(0h1), _r_sectored_repl_addr_T_10) node _r_sectored_repl_addr_T_12 = mux(_r_sectored_repl_addr_T_6, UInt<1>(0h0), _r_sectored_repl_addr_T_11) node _r_sectored_repl_addr_T_13 = mux(_r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_12) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_13 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_2 node r_sectored_hit_bits_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_hi = cat(sector_hits_3, sector_hits_2) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 3, 2) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 1, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node _r_sectored_hit_bits_T_3 = bits(_r_sectored_hit_bits_T_2, 1, 1) node _r_sectored_hit_bits_T_4 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_4 connect r_superpage_hit.valid, superpage_hits_0 connect r_superpage_hit.bits, UInt<1>(0h0) node _T_25 = eq(state, UInt<2>(0h1)) when _T_25 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_26 = eq(state, UInt<2>(0h2)) node _T_27 = and(_T_26, io.sfence.valid) when _T_27 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_28 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_29 = shr(io.sfence.bits.addr, 12) node _T_30 = eq(_T_29, vpn) node _T_31 = or(_T_28, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_31, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_35 = eq(hg, UInt<1>(0h0)) node _T_36 = and(_T_35, io.sfence.bits.rs1) when _T_36 : node _T_37 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_38 = shr(_T_37, 0) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = eq(sectored_entries[0][0].tag_v, hv) node _T_41 = and(_T_39, _T_40) when _T_41 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_42 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_42 node _T_43 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_43 node _T_44 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_44 node _T_45 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_45 node _T_46 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_46 node _T_47 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_47 node _T_48 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_48 node _T_49 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_49 node _T_50 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_50 node _T_51 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_51 node _T_52 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_52 node _T_53 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_53 node _T_54 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_54 node _T_55 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_55 node _T_56 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_56 node _T_57 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_57 node _T_58 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_58 node _T_59 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_59 node _T_60 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_60 node _T_61 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_61 node _T_62 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_62 node _T_63 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_63 node _T_64 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_64 node _T_65 = eq(sectored_entries[0][0].tag_v, hv) node _T_66 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_68 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_69 = shr(_T_68, 18) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[0] node _T_71 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_71 node _T_72 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_72 node _T_73 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_73 node _T_74 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_74 node _T_75 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_75 node _T_76 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_76 node _T_77 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_77 node _T_78 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_78 node _T_79 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_79 node _T_80 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_80 node _T_81 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_81 node _T_82 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_82 node _T_83 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_83 node _T_84 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_84 node _T_85 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_85 node _T_86 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_86 node _T_87 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_87 node _T_88 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_88 node _T_89 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_89 node _T_90 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_90 node _T_91 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_91 node _T_92 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_92 node _T_93 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_93 node _T_94 = eq(sectored_entries[0][0].tag_v, hv) node _T_95 = and(_T_94, _WIRE_2.fragmented_superpage) when _T_95 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_96 = eq(hg, UInt<1>(0h0)) node _T_97 = and(_T_96, io.sfence.bits.rs2) when _T_97 : wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[0] node _T_98 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_98 node _T_99 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_99 node _T_100 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_100 node _T_101 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_101 node _T_102 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_102 node _T_103 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_103 node _T_104 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_104 node _T_105 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_105 node _T_106 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_106 node _T_107 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_107 node _T_108 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_108 node _T_109 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_109 node _T_110 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_110 node _T_111 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_111 node _T_112 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_112 node _T_113 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_113 node _T_114 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_114 node _T_115 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_115 node _T_116 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_116 node _T_117 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_117 node _T_118 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_118 node _T_119 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_119 node _T_120 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_120 node _T_121 = eq(sectored_entries[0][0].tag_v, hv) node _T_122 = eq(_WIRE_4.g, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) when _T_123 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_124 = or(hv, hg) wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[0] node _T_125 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_125 node _T_126 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_126 node _T_127 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_127 node _T_128 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_128 node _T_129 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_129 node _T_130 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_130 node _T_131 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_131 node _T_132 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_132 node _T_133 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_133 node _T_134 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_134 node _T_135 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_135 node _T_136 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_136 node _T_137 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_137 node _T_138 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_138 node _T_139 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_139 node _T_140 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_140 node _T_141 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_141 node _T_142 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_142 node _T_143 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_143 node _T_144 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_144 node _T_145 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_145 node _T_146 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_146 node _T_147 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_147 node _T_148 = eq(sectored_entries[0][0].tag_v, _T_124) when _T_148 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_149 = eq(hg_1, UInt<1>(0h0)) node _T_150 = and(_T_149, io.sfence.bits.rs1) when _T_150 : node _T_151 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_152 = shr(_T_151, 0) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_155 = and(_T_153, _T_154) when _T_155 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][1].data[0] node _T_156 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_156 node _T_157 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_157 node _T_158 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_158 node _T_159 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_159 node _T_160 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_160 node _T_161 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_161 node _T_162 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_162 node _T_163 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_163 node _T_164 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_164 node _T_165 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_165 node _T_166 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_166 node _T_167 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_167 node _T_168 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_168 node _T_169 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_169 node _T_170 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_170 node _T_171 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_171 node _T_172 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_172 node _T_173 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_173 node _T_174 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_174 node _T_175 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_175 node _T_176 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_176 node _T_177 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_177 node _T_178 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_178 node _T_179 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_180 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_181 = and(_T_179, _T_180) when _T_181 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_182 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_183 = shr(_T_182, 18) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][1].data[0] node _T_185 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_185 node _T_186 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_186 node _T_187 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_187 node _T_188 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_188 node _T_189 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_189 node _T_190 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_190 node _T_191 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_191 node _T_192 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_192 node _T_193 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_193 node _T_194 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_194 node _T_195 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_195 node _T_196 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_196 node _T_197 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_197 node _T_198 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_198 node _T_199 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_199 node _T_200 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_200 node _T_201 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_201 node _T_202 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_202 node _T_203 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_203 node _T_204 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_204 node _T_205 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_205 node _T_206 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_206 node _T_207 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_207 node _T_208 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_209 = and(_T_208, _WIRE_10.fragmented_superpage) when _T_209 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_210 = eq(hg_1, UInt<1>(0h0)) node _T_211 = and(_T_210, io.sfence.bits.rs2) when _T_211 : wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][1].data[0] node _T_212 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_212 node _T_213 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_213 node _T_214 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_214 node _T_215 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_215 node _T_216 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_216 node _T_217 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_217 node _T_218 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_218 node _T_219 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_219 node _T_220 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_220 node _T_221 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_221 node _T_222 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_222 node _T_223 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_223 node _T_224 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_224 node _T_225 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_225 node _T_226 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_226 node _T_227 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_227 node _T_228 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_228 node _T_229 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_229 node _T_230 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_230 node _T_231 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_231 node _T_232 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_232 node _T_233 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_233 node _T_234 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_234 node _T_235 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_236 = eq(_WIRE_12.g, UInt<1>(0h0)) node _T_237 = and(_T_235, _T_236) when _T_237 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_238 = or(hv_1, hg_1) wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][1].data[0] node _T_239 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_239 node _T_240 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_240 node _T_241 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_241 node _T_242 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_242 node _T_243 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_243 node _T_244 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_244 node _T_245 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_245 node _T_246 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_246 node _T_247 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_247 node _T_248 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_248 node _T_249 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_249 node _T_250 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_250 node _T_251 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_251 node _T_252 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_252 node _T_253 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_253 node _T_254 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_254 node _T_255 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_255 node _T_256 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_256 node _T_257 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_257 node _T_258 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_258 node _T_259 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_259 node _T_260 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_260 node _T_261 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_261 node _T_262 = eq(sectored_entries[0][1].tag_v, _T_238) when _T_262 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_263 = eq(hg_2, UInt<1>(0h0)) node _T_264 = and(_T_263, io.sfence.bits.rs1) when _T_264 : node _T_265 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_266 = shr(_T_265, 0) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_269 = and(_T_267, _T_268) when _T_269 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][2].data[0] node _T_270 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_270 node _T_271 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_271 node _T_272 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_272 node _T_273 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_273 node _T_274 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_274 node _T_275 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_275 node _T_276 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_276 node _T_277 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_277 node _T_278 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_278 node _T_279 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_279 node _T_280 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_280 node _T_281 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_281 node _T_282 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_282 node _T_283 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_283 node _T_284 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_284 node _T_285 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_285 node _T_286 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_286 node _T_287 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_287 node _T_288 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_288 node _T_289 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_289 node _T_290 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_290 node _T_291 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_291 node _T_292 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_292 node _T_293 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_294 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) when _T_295 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_296 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_297 = shr(_T_296, 18) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][2].data[0] node _T_299 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_299 node _T_300 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_300 node _T_301 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_301 node _T_302 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_302 node _T_303 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_303 node _T_304 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_304 node _T_305 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_305 node _T_306 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_306 node _T_307 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_307 node _T_308 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_308 node _T_309 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_309 node _T_310 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_310 node _T_311 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_311 node _T_312 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_312 node _T_313 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_313 node _T_314 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_314 node _T_315 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_315 node _T_316 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_316 node _T_317 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_317 node _T_318 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_318 node _T_319 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_319 node _T_320 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_320 node _T_321 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_321 node _T_322 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_323 = and(_T_322, _WIRE_18.fragmented_superpage) when _T_323 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_324 = eq(hg_2, UInt<1>(0h0)) node _T_325 = and(_T_324, io.sfence.bits.rs2) when _T_325 : wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][2].data[0] node _T_326 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_326 node _T_327 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_327 node _T_328 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_328 node _T_329 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_329 node _T_330 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_330 node _T_331 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_331 node _T_332 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_332 node _T_333 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_333 node _T_334 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_334 node _T_335 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_335 node _T_336 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_336 node _T_337 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_337 node _T_338 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_338 node _T_339 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_339 node _T_340 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_340 node _T_341 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_341 node _T_342 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_342 node _T_343 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_343 node _T_344 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_344 node _T_345 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_345 node _T_346 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_346 node _T_347 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_347 node _T_348 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_348 node _T_349 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_350 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) when _T_351 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_352 = or(hv_2, hg_2) wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][2].data[0] node _T_353 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_353 node _T_354 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_354 node _T_355 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_355 node _T_356 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_356 node _T_357 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_357 node _T_358 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_358 node _T_359 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_359 node _T_360 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_360 node _T_361 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_361 node _T_362 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_362 node _T_363 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_363 node _T_364 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_364 node _T_365 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_365 node _T_366 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_366 node _T_367 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_367 node _T_368 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_368 node _T_369 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_369 node _T_370 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_370 node _T_371 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_371 node _T_372 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_372 node _T_373 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_373 node _T_374 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_374 node _T_375 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_375 node _T_376 = eq(sectored_entries[0][2].tag_v, _T_352) when _T_376 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_377 = eq(hg_3, UInt<1>(0h0)) node _T_378 = and(_T_377, io.sfence.bits.rs1) when _T_378 : node _T_379 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_380 = shr(_T_379, 0) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_383 = and(_T_381, _T_382) when _T_383 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][3].data[0] node _T_384 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_384 node _T_385 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_385 node _T_386 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_386 node _T_387 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_387 node _T_388 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_388 node _T_389 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_389 node _T_390 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_390 node _T_391 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_391 node _T_392 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_392 node _T_393 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_393 node _T_394 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_394 node _T_395 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_395 node _T_396 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_396 node _T_397 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_397 node _T_398 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_398 node _T_399 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_399 node _T_400 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_400 node _T_401 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_401 node _T_402 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_402 node _T_403 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_403 node _T_404 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_404 node _T_405 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_405 node _T_406 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_406 node _T_407 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_408 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = and(_T_407, _T_408) when _T_409 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_410 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_411 = shr(_T_410, 18) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][3].data[0] node _T_413 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_413 node _T_414 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_414 node _T_415 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_415 node _T_416 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_416 node _T_417 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_417 node _T_418 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_418 node _T_419 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_419 node _T_420 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_420 node _T_421 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_421 node _T_422 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_422 node _T_423 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_423 node _T_424 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_424 node _T_425 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_425 node _T_426 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_426 node _T_427 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_427 node _T_428 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_428 node _T_429 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_429 node _T_430 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_430 node _T_431 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_431 node _T_432 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_432 node _T_433 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_433 node _T_434 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_434 node _T_435 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_435 node _T_436 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_437 = and(_T_436, _WIRE_26.fragmented_superpage) when _T_437 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_438 = eq(hg_3, UInt<1>(0h0)) node _T_439 = and(_T_438, io.sfence.bits.rs2) when _T_439 : wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][3].data[0] node _T_440 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_440 node _T_441 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_441 node _T_442 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_442 node _T_443 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_443 node _T_444 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_444 node _T_445 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_445 node _T_446 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_446 node _T_447 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_447 node _T_448 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_448 node _T_449 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_449 node _T_450 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_450 node _T_451 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_451 node _T_452 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_452 node _T_453 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_453 node _T_454 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_454 node _T_455 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_455 node _T_456 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_456 node _T_457 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_457 node _T_458 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_458 node _T_459 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_459 node _T_460 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_460 node _T_461 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_461 node _T_462 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_462 node _T_463 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_464 = eq(_WIRE_28.g, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) when _T_465 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_466 = or(hv_3, hg_3) wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][3].data[0] node _T_467 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_467 node _T_468 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_468 node _T_469 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_469 node _T_470 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_470 node _T_471 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_471 node _T_472 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_472 node _T_473 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_473 node _T_474 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_474 node _T_475 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_475 node _T_476 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_476 node _T_477 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_477 node _T_478 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_478 node _T_479 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_479 node _T_480 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_480 node _T_481 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_481 node _T_482 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_482 node _T_483 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_483 node _T_484 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_484 node _T_485 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_485 node _T_486 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_486 node _T_487 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_487 node _T_488 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_488 node _T_489 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_489 node _T_490 = eq(sectored_entries[0][3].tag_v, _T_466) when _T_490 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_491 = eq(hg_4, UInt<1>(0h0)) node _T_492 = and(_T_491, io.sfence.bits.rs1) when _T_492 : node _T_493 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_494 = shr(_T_493, 0) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_497 = and(_T_495, _T_496) when _T_497 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[1][0].data[0] node _T_498 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_498 node _T_499 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_499 node _T_500 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_500 node _T_501 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_501 node _T_502 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_502 node _T_503 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_503 node _T_504 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_504 node _T_505 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_505 node _T_506 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_506 node _T_507 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_507 node _T_508 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_508 node _T_509 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_509 node _T_510 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_510 node _T_511 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_511 node _T_512 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_512 node _T_513 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_513 node _T_514 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_514 node _T_515 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_515 node _T_516 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_516 node _T_517 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_517 node _T_518 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_518 node _T_519 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_519 node _T_520 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_520 node _T_521 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = and(_T_521, _T_522) when _T_523 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node _T_524 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_525 = shr(_T_524, 18) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[1][0].data[0] node _T_527 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_527 node _T_528 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_528 node _T_529 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_529 node _T_530 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_530 node _T_531 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_531 node _T_532 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_532 node _T_533 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_533 node _T_534 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_534 node _T_535 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_535 node _T_536 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_536 node _T_537 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_537 node _T_538 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_538 node _T_539 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_539 node _T_540 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_540 node _T_541 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_541 node _T_542 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_542 node _T_543 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_543 node _T_544 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_544 node _T_545 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_545 node _T_546 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_546 node _T_547 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_547 node _T_548 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_548 node _T_549 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_549 node _T_550 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_551 = and(_T_550, _WIRE_34.fragmented_superpage) when _T_551 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_552 = eq(hg_4, UInt<1>(0h0)) node _T_553 = and(_T_552, io.sfence.bits.rs2) when _T_553 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[1][0].data[0] node _T_554 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_554 node _T_555 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_555 node _T_556 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_556 node _T_557 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_557 node _T_558 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_558 node _T_559 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_559 node _T_560 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_560 node _T_561 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_561 node _T_562 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_562 node _T_563 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_563 node _T_564 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_564 node _T_565 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_565 node _T_566 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_566 node _T_567 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_567 node _T_568 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_568 node _T_569 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_569 node _T_570 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_570 node _T_571 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_571 node _T_572 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_572 node _T_573 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_573 node _T_574 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_574 node _T_575 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_575 node _T_576 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_576 node _T_577 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_578 = eq(_WIRE_36.g, UInt<1>(0h0)) node _T_579 = and(_T_577, _T_578) when _T_579 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_580 = or(hv_4, hg_4) wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[1][0].data[0] node _T_581 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_581 node _T_582 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_582 node _T_583 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_583 node _T_584 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_584 node _T_585 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_585 node _T_586 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_586 node _T_587 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_587 node _T_588 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_588 node _T_589 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_589 node _T_590 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_590 node _T_591 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_591 node _T_592 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_592 node _T_593 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_593 node _T_594 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_594 node _T_595 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_595 node _T_596 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_596 node _T_597 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_597 node _T_598 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_598 node _T_599 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_599 node _T_600 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_600 node _T_601 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_601 node _T_602 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_602 node _T_603 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_603 node _T_604 = eq(sectored_entries[1][0].tag_v, _T_580) when _T_604 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_605 = eq(hg_5, UInt<1>(0h0)) node _T_606 = and(_T_605, io.sfence.bits.rs1) when _T_606 : node _T_607 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_608 = shr(_T_607, 0) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_611 = and(_T_609, _T_610) when _T_611 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[1][1].data[0] node _T_612 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_612 node _T_613 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_613 node _T_614 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_614 node _T_615 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_615 node _T_616 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_616 node _T_617 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_617 node _T_618 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_618 node _T_619 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_619 node _T_620 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_620 node _T_621 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_621 node _T_622 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_622 node _T_623 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_623 node _T_624 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_624 node _T_625 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_625 node _T_626 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_626 node _T_627 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_627 node _T_628 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_628 node _T_629 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_629 node _T_630 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_630 node _T_631 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_631 node _T_632 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_632 node _T_633 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_633 node _T_634 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_634 node _T_635 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_636 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = and(_T_635, _T_636) when _T_637 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node _T_638 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_639 = shr(_T_638, 18) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[1][1].data[0] node _T_641 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_641 node _T_642 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_642 node _T_643 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_643 node _T_644 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_644 node _T_645 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_645 node _T_646 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_646 node _T_647 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_647 node _T_648 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_648 node _T_649 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_649 node _T_650 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_650 node _T_651 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_651 node _T_652 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_652 node _T_653 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_653 node _T_654 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_654 node _T_655 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_655 node _T_656 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_656 node _T_657 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_657 node _T_658 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_658 node _T_659 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_659 node _T_660 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_660 node _T_661 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_661 node _T_662 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_662 node _T_663 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_663 node _T_664 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_665 = and(_T_664, _WIRE_42.fragmented_superpage) when _T_665 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_666 = eq(hg_5, UInt<1>(0h0)) node _T_667 = and(_T_666, io.sfence.bits.rs2) when _T_667 : wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[1][1].data[0] node _T_668 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_668 node _T_669 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_669 node _T_670 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_670 node _T_671 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_671 node _T_672 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_672 node _T_673 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_673 node _T_674 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_674 node _T_675 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_675 node _T_676 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_676 node _T_677 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_677 node _T_678 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_678 node _T_679 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_679 node _T_680 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_680 node _T_681 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_681 node _T_682 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_682 node _T_683 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_683 node _T_684 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_684 node _T_685 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_685 node _T_686 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_686 node _T_687 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_687 node _T_688 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_688 node _T_689 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_689 node _T_690 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_690 node _T_691 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_692 = eq(_WIRE_44.g, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) when _T_693 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_694 = or(hv_5, hg_5) wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[1][1].data[0] node _T_695 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_695 node _T_696 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_696 node _T_697 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_697 node _T_698 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_698 node _T_699 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_699 node _T_700 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_700 node _T_701 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_701 node _T_702 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_702 node _T_703 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_703 node _T_704 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_704 node _T_705 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_705 node _T_706 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_706 node _T_707 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_707 node _T_708 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_708 node _T_709 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_709 node _T_710 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_710 node _T_711 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_711 node _T_712 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_712 node _T_713 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_713 node _T_714 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_714 node _T_715 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_715 node _T_716 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_716 node _T_717 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_717 node _T_718 = eq(sectored_entries[1][1].tag_v, _T_694) when _T_718 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_719 = eq(hg_6, UInt<1>(0h0)) node _T_720 = and(_T_719, io.sfence.bits.rs1) when _T_720 : node _T_721 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_722 = shr(_T_721, 0) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_725 = and(_T_723, _T_724) when _T_725 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[1][2].data[0] node _T_726 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_726 node _T_727 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_727 node _T_728 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_728 node _T_729 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_729 node _T_730 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_730 node _T_731 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_731 node _T_732 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_732 node _T_733 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_733 node _T_734 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_734 node _T_735 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_735 node _T_736 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_736 node _T_737 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_737 node _T_738 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_738 node _T_739 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_739 node _T_740 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_740 node _T_741 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_741 node _T_742 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_742 node _T_743 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_743 node _T_744 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_744 node _T_745 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_745 node _T_746 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_746 node _T_747 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_747 node _T_748 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_748 node _T_749 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_750 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = and(_T_749, _T_750) when _T_751 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node _T_752 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_753 = shr(_T_752, 18) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[1][2].data[0] node _T_755 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_755 node _T_756 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_756 node _T_757 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_757 node _T_758 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_758 node _T_759 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_759 node _T_760 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_760 node _T_761 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_761 node _T_762 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_762 node _T_763 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_763 node _T_764 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_764 node _T_765 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_765 node _T_766 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_766 node _T_767 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_767 node _T_768 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_768 node _T_769 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_769 node _T_770 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_770 node _T_771 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_771 node _T_772 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_772 node _T_773 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_773 node _T_774 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_774 node _T_775 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_775 node _T_776 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_776 node _T_777 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_777 node _T_778 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_779 = and(_T_778, _WIRE_50.fragmented_superpage) when _T_779 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_780 = eq(hg_6, UInt<1>(0h0)) node _T_781 = and(_T_780, io.sfence.bits.rs2) when _T_781 : wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[1][2].data[0] node _T_782 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_782 node _T_783 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_783 node _T_784 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_784 node _T_785 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_785 node _T_786 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_786 node _T_787 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_787 node _T_788 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_788 node _T_789 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_789 node _T_790 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_790 node _T_791 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_791 node _T_792 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_792 node _T_793 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_793 node _T_794 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_794 node _T_795 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_795 node _T_796 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_796 node _T_797 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_797 node _T_798 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_798 node _T_799 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_799 node _T_800 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_800 node _T_801 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_801 node _T_802 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_802 node _T_803 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_803 node _T_804 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_804 node _T_805 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_806 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_807 = and(_T_805, _T_806) when _T_807 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_808 = or(hv_6, hg_6) wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[1][2].data[0] node _T_809 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_809 node _T_810 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_810 node _T_811 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_811 node _T_812 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_812 node _T_813 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_813 node _T_814 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_814 node _T_815 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_815 node _T_816 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_816 node _T_817 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_817 node _T_818 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_818 node _T_819 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_819 node _T_820 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_820 node _T_821 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_821 node _T_822 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_822 node _T_823 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_823 node _T_824 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_824 node _T_825 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_825 node _T_826 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_826 node _T_827 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_827 node _T_828 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_828 node _T_829 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_829 node _T_830 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_830 node _T_831 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_831 node _T_832 = eq(sectored_entries[1][2].tag_v, _T_808) when _T_832 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_833 = eq(hg_7, UInt<1>(0h0)) node _T_834 = and(_T_833, io.sfence.bits.rs1) when _T_834 : node _T_835 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_836 = shr(_T_835, 0) node _T_837 = eq(_T_836, UInt<1>(0h0)) node _T_838 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_839 = and(_T_837, _T_838) when _T_839 : wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[1][3].data[0] node _T_840 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_840 node _T_841 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_841 node _T_842 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_842 node _T_843 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_843 node _T_844 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_844 node _T_845 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_845 node _T_846 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_846 node _T_847 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_847 node _T_848 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_848 node _T_849 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_849 node _T_850 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_850 node _T_851 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_851 node _T_852 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_852 node _T_853 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_853 node _T_854 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_854 node _T_855 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_855 node _T_856 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_856 node _T_857 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_857 node _T_858 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_858 node _T_859 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_859 node _T_860 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_860 node _T_861 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_861 node _T_862 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_862 node _T_863 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_864 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_865 = and(_T_863, _T_864) when _T_865 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node _T_866 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_867 = shr(_T_866, 18) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[1][3].data[0] node _T_869 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_869 node _T_870 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_870 node _T_871 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_871 node _T_872 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_872 node _T_873 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_873 node _T_874 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_874 node _T_875 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_875 node _T_876 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_876 node _T_877 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_877 node _T_878 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_878 node _T_879 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_879 node _T_880 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_880 node _T_881 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_881 node _T_882 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_882 node _T_883 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_883 node _T_884 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_884 node _T_885 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_885 node _T_886 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_886 node _T_887 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_887 node _T_888 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_888 node _T_889 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_889 node _T_890 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_890 node _T_891 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_891 node _T_892 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_893 = and(_T_892, _WIRE_58.fragmented_superpage) when _T_893 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_894 = eq(hg_7, UInt<1>(0h0)) node _T_895 = and(_T_894, io.sfence.bits.rs2) when _T_895 : wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[1][3].data[0] node _T_896 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_896 node _T_897 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_897 node _T_898 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_898 node _T_899 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_899 node _T_900 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_900 node _T_901 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_901 node _T_902 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_902 node _T_903 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_903 node _T_904 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_904 node _T_905 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_905 node _T_906 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_906 node _T_907 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_907 node _T_908 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_908 node _T_909 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_909 node _T_910 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_910 node _T_911 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_911 node _T_912 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_912 node _T_913 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_913 node _T_914 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_914 node _T_915 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_915 node _T_916 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_916 node _T_917 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_917 node _T_918 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_918 node _T_919 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_920 = eq(_WIRE_60.g, UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) when _T_921 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_922 = or(hv_7, hg_7) wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[1][3].data[0] node _T_923 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_923 node _T_924 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_924 node _T_925 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_925 node _T_926 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_926 node _T_927 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_927 node _T_928 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_928 node _T_929 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_929 node _T_930 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_930 node _T_931 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_931 node _T_932 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_932 node _T_933 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_933 node _T_934 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_934 node _T_935 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_935 node _T_936 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_936 node _T_937 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_937 node _T_938 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_938 node _T_939 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_939 node _T_940 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_940 node _T_941 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_941 node _T_942 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_942 node _T_943 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_943 node _T_944 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_944 node _T_945 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_945 node _T_946 = eq(sectored_entries[1][3].tag_v, _T_922) when _T_946 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_947 = eq(hg_8, UInt<1>(0h0)) node _T_948 = and(_T_947, io.sfence.bits.rs1) when _T_948 : node _T_949 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_950 = shr(_T_949, 0) node _T_951 = eq(_T_950, UInt<1>(0h0)) node _T_952 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_953 = and(_T_951, _T_952) when _T_953 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[2][0].data[0] node _T_954 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_954 node _T_955 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_955 node _T_956 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_956 node _T_957 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_957 node _T_958 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_958 node _T_959 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_959 node _T_960 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_960 node _T_961 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_961 node _T_962 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_962 node _T_963 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_963 node _T_964 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_964 node _T_965 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_965 node _T_966 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_966 node _T_967 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_967 node _T_968 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_968 node _T_969 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_969 node _T_970 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_970 node _T_971 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_971 node _T_972 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_972 node _T_973 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_973 node _T_974 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_974 node _T_975 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_975 node _T_976 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_976 node _T_977 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_978 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_979 = and(_T_977, _T_978) when _T_979 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node _T_980 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_981 = shr(_T_980, 18) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[2][0].data[0] node _T_983 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_983 node _T_984 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_984 node _T_985 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_985 node _T_986 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_986 node _T_987 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_987 node _T_988 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_988 node _T_989 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_989 node _T_990 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_990 node _T_991 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_991 node _T_992 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_992 node _T_993 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_993 node _T_994 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_994 node _T_995 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_995 node _T_996 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_996 node _T_997 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_997 node _T_998 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_998 node _T_999 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_999 node _T_1000 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_1000 node _T_1001 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_1001 node _T_1002 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_1002 node _T_1003 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_1003 node _T_1004 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_1004 node _T_1005 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_1005 node _T_1006 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1007 = and(_T_1006, _WIRE_66.fragmented_superpage) when _T_1007 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1008 = eq(hg_8, UInt<1>(0h0)) node _T_1009 = and(_T_1008, io.sfence.bits.rs2) when _T_1009 : wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[2][0].data[0] node _T_1010 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_1010 node _T_1011 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_1011 node _T_1012 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_1012 node _T_1013 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_1013 node _T_1014 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_1014 node _T_1015 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_1015 node _T_1016 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_1016 node _T_1017 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_1017 node _T_1018 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_1018 node _T_1019 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_1019 node _T_1020 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_1020 node _T_1021 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_1021 node _T_1022 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_1022 node _T_1023 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_1023 node _T_1024 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_1024 node _T_1025 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_1025 node _T_1026 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_1026 node _T_1027 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_1027 node _T_1028 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_1028 node _T_1029 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_1029 node _T_1030 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_1030 node _T_1031 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_1031 node _T_1032 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_1032 node _T_1033 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1034 = eq(_WIRE_68.g, UInt<1>(0h0)) node _T_1035 = and(_T_1033, _T_1034) when _T_1035 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1036 = or(hv_8, hg_8) wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[2][0].data[0] node _T_1037 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_1037 node _T_1038 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_1038 node _T_1039 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_1039 node _T_1040 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_1040 node _T_1041 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_1041 node _T_1042 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_1042 node _T_1043 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_1043 node _T_1044 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_1044 node _T_1045 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_1045 node _T_1046 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_1046 node _T_1047 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_1047 node _T_1048 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_1048 node _T_1049 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_1049 node _T_1050 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_1050 node _T_1051 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_1051 node _T_1052 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_1052 node _T_1053 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_1053 node _T_1054 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_1054 node _T_1055 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_1055 node _T_1056 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_1056 node _T_1057 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_1057 node _T_1058 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1058 node _T_1059 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1059 node _T_1060 = eq(sectored_entries[2][0].tag_v, _T_1036) when _T_1060 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1061 = eq(hg_9, UInt<1>(0h0)) node _T_1062 = and(_T_1061, io.sfence.bits.rs1) when _T_1062 : node _T_1063 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1064 = shr(_T_1063, 0) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1067 = and(_T_1065, _T_1066) when _T_1067 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[2][1].data[0] node _T_1068 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1068 node _T_1069 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1069 node _T_1070 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1070 node _T_1071 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1071 node _T_1072 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1072 node _T_1073 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1073 node _T_1074 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1074 node _T_1075 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1075 node _T_1076 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1076 node _T_1077 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1077 node _T_1078 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1078 node _T_1079 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1079 node _T_1080 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1080 node _T_1081 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1081 node _T_1082 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1082 node _T_1083 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1083 node _T_1084 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1084 node _T_1085 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1085 node _T_1086 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1086 node _T_1087 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1087 node _T_1088 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1088 node _T_1089 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1089 node _T_1090 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1090 node _T_1091 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1092 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = and(_T_1091, _T_1092) when _T_1093 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node _T_1094 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1095 = shr(_T_1094, 18) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[2][1].data[0] node _T_1097 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1097 node _T_1098 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1098 node _T_1099 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1099 node _T_1100 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1100 node _T_1101 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1101 node _T_1102 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1102 node _T_1103 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1103 node _T_1104 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1104 node _T_1105 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1105 node _T_1106 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1106 node _T_1107 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1107 node _T_1108 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1108 node _T_1109 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1109 node _T_1110 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1110 node _T_1111 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1111 node _T_1112 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1112 node _T_1113 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1113 node _T_1114 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1114 node _T_1115 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1115 node _T_1116 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1116 node _T_1117 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1117 node _T_1118 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1118 node _T_1119 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1119 node _T_1120 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1121 = and(_T_1120, _WIRE_74.fragmented_superpage) when _T_1121 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1122 = eq(hg_9, UInt<1>(0h0)) node _T_1123 = and(_T_1122, io.sfence.bits.rs2) when _T_1123 : wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[2][1].data[0] node _T_1124 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1124 node _T_1125 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1125 node _T_1126 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1126 node _T_1127 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1127 node _T_1128 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1128 node _T_1129 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1129 node _T_1130 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1130 node _T_1131 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1131 node _T_1132 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1132 node _T_1133 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1133 node _T_1134 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1134 node _T_1135 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1135 node _T_1136 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1136 node _T_1137 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1137 node _T_1138 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1138 node _T_1139 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1139 node _T_1140 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1140 node _T_1141 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1141 node _T_1142 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1142 node _T_1143 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1143 node _T_1144 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1144 node _T_1145 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1145 node _T_1146 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1146 node _T_1147 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1148 = eq(_WIRE_76.g, UInt<1>(0h0)) node _T_1149 = and(_T_1147, _T_1148) when _T_1149 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1150 = or(hv_9, hg_9) wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[2][1].data[0] node _T_1151 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1151 node _T_1152 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1152 node _T_1153 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1153 node _T_1154 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1154 node _T_1155 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1155 node _T_1156 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1156 node _T_1157 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1157 node _T_1158 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1158 node _T_1159 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1159 node _T_1160 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1160 node _T_1161 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1161 node _T_1162 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1162 node _T_1163 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1163 node _T_1164 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1164 node _T_1165 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1165 node _T_1166 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1166 node _T_1167 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1167 node _T_1168 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1168 node _T_1169 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1169 node _T_1170 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1170 node _T_1171 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1171 node _T_1172 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1172 node _T_1173 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1173 node _T_1174 = eq(sectored_entries[2][1].tag_v, _T_1150) when _T_1174 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1175 = eq(hg_10, UInt<1>(0h0)) node _T_1176 = and(_T_1175, io.sfence.bits.rs1) when _T_1176 : node _T_1177 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1178 = shr(_T_1177, 0) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1181 = and(_T_1179, _T_1180) when _T_1181 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[2][2].data[0] node _T_1182 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1182 node _T_1183 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1183 node _T_1184 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1184 node _T_1185 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1185 node _T_1186 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1186 node _T_1187 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1187 node _T_1188 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1188 node _T_1189 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1189 node _T_1190 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1190 node _T_1191 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1191 node _T_1192 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1192 node _T_1193 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1193 node _T_1194 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1194 node _T_1195 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1195 node _T_1196 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1196 node _T_1197 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1197 node _T_1198 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1198 node _T_1199 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1199 node _T_1200 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1200 node _T_1201 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1201 node _T_1202 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1202 node _T_1203 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1203 node _T_1204 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1204 node _T_1205 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1206 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node _T_1208 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1209 = shr(_T_1208, 18) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[2][2].data[0] node _T_1211 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1211 node _T_1212 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1212 node _T_1213 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1213 node _T_1214 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1214 node _T_1215 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1215 node _T_1216 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1216 node _T_1217 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1217 node _T_1218 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1218 node _T_1219 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1219 node _T_1220 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1220 node _T_1221 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1221 node _T_1222 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1222 node _T_1223 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1223 node _T_1224 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1224 node _T_1225 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1225 node _T_1226 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1226 node _T_1227 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1227 node _T_1228 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1228 node _T_1229 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1229 node _T_1230 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1230 node _T_1231 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1231 node _T_1232 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1232 node _T_1233 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1233 node _T_1234 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1235 = and(_T_1234, _WIRE_82.fragmented_superpage) when _T_1235 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1236 = eq(hg_10, UInt<1>(0h0)) node _T_1237 = and(_T_1236, io.sfence.bits.rs2) when _T_1237 : wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[2][2].data[0] node _T_1238 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1238 node _T_1239 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1239 node _T_1240 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1240 node _T_1241 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1241 node _T_1242 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1242 node _T_1243 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1243 node _T_1244 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1244 node _T_1245 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1245 node _T_1246 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1246 node _T_1247 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1247 node _T_1248 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1248 node _T_1249 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1249 node _T_1250 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1250 node _T_1251 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1251 node _T_1252 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1252 node _T_1253 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1253 node _T_1254 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1254 node _T_1255 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1255 node _T_1256 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1256 node _T_1257 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1257 node _T_1258 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1258 node _T_1259 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1259 node _T_1260 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1260 node _T_1261 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1262 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1264 = or(hv_10, hg_10) wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[2][2].data[0] node _T_1265 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1265 node _T_1266 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1266 node _T_1267 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1267 node _T_1268 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1268 node _T_1269 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1269 node _T_1270 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1270 node _T_1271 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1271 node _T_1272 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1272 node _T_1273 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1273 node _T_1274 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1274 node _T_1275 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1275 node _T_1276 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1276 node _T_1277 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1277 node _T_1278 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1278 node _T_1279 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1279 node _T_1280 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1280 node _T_1281 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1281 node _T_1282 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1282 node _T_1283 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1283 node _T_1284 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1284 node _T_1285 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1285 node _T_1286 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1286 node _T_1287 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1287 node _T_1288 = eq(sectored_entries[2][2].tag_v, _T_1264) when _T_1288 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1289 = eq(hg_11, UInt<1>(0h0)) node _T_1290 = and(_T_1289, io.sfence.bits.rs1) when _T_1290 : node _T_1291 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1292 = shr(_T_1291, 0) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) node _T_1294 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1295 = and(_T_1293, _T_1294) when _T_1295 : wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[2][3].data[0] node _T_1296 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1296 node _T_1297 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1297 node _T_1298 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1298 node _T_1299 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1299 node _T_1300 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1300 node _T_1301 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1301 node _T_1302 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1302 node _T_1303 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1303 node _T_1304 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1304 node _T_1305 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1305 node _T_1306 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1306 node _T_1307 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1307 node _T_1308 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1308 node _T_1309 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1309 node _T_1310 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1310 node _T_1311 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1311 node _T_1312 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1312 node _T_1313 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1313 node _T_1314 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1314 node _T_1315 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1315 node _T_1316 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1316 node _T_1317 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1317 node _T_1318 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1318 node _T_1319 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1320 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1321 = and(_T_1319, _T_1320) when _T_1321 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node _T_1322 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1323 = shr(_T_1322, 18) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[2][3].data[0] node _T_1325 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1325 node _T_1326 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1326 node _T_1327 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1327 node _T_1328 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1328 node _T_1329 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1329 node _T_1330 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1330 node _T_1331 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1331 node _T_1332 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1332 node _T_1333 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1333 node _T_1334 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1334 node _T_1335 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1335 node _T_1336 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1336 node _T_1337 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1337 node _T_1338 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1338 node _T_1339 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1339 node _T_1340 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1340 node _T_1341 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1341 node _T_1342 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1342 node _T_1343 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1343 node _T_1344 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1344 node _T_1345 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1345 node _T_1346 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1346 node _T_1347 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1347 node _T_1348 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1349 = and(_T_1348, _WIRE_90.fragmented_superpage) when _T_1349 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1350 = eq(hg_11, UInt<1>(0h0)) node _T_1351 = and(_T_1350, io.sfence.bits.rs2) when _T_1351 : wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[2][3].data[0] node _T_1352 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1352 node _T_1353 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1353 node _T_1354 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1354 node _T_1355 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1355 node _T_1356 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1356 node _T_1357 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1357 node _T_1358 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1358 node _T_1359 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1359 node _T_1360 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1360 node _T_1361 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1361 node _T_1362 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1362 node _T_1363 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1363 node _T_1364 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1364 node _T_1365 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1365 node _T_1366 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1366 node _T_1367 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1367 node _T_1368 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1368 node _T_1369 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1369 node _T_1370 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1370 node _T_1371 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1371 node _T_1372 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1372 node _T_1373 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1373 node _T_1374 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1374 node _T_1375 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1376 = eq(_WIRE_92.g, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1378 = or(hv_11, hg_11) wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[2][3].data[0] node _T_1379 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1379 node _T_1380 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1380 node _T_1381 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1381 node _T_1382 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1382 node _T_1383 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1383 node _T_1384 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1384 node _T_1385 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1385 node _T_1386 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1386 node _T_1387 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1387 node _T_1388 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1388 node _T_1389 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1389 node _T_1390 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1390 node _T_1391 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1391 node _T_1392 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1392 node _T_1393 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1393 node _T_1394 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1394 node _T_1395 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1395 node _T_1396 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1396 node _T_1397 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1397 node _T_1398 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1398 node _T_1399 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1399 node _T_1400 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1400 node _T_1401 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1401 node _T_1402 = eq(sectored_entries[2][3].tag_v, _T_1378) when _T_1402 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1403 = eq(hg_12, UInt<1>(0h0)) node _T_1404 = and(_T_1403, io.sfence.bits.rs1) when _T_1404 : node _T_1405 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1406 = shr(_T_1405, 0) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) node _T_1408 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1409 = and(_T_1407, _T_1408) when _T_1409 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[3][0].data[0] node _T_1410 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1410 node _T_1411 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1411 node _T_1412 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1412 node _T_1413 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1413 node _T_1414 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1414 node _T_1415 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1415 node _T_1416 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1416 node _T_1417 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1417 node _T_1418 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1418 node _T_1419 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1419 node _T_1420 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1420 node _T_1421 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1421 node _T_1422 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1422 node _T_1423 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1423 node _T_1424 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1424 node _T_1425 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1425 node _T_1426 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1426 node _T_1427 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1427 node _T_1428 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1428 node _T_1429 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1429 node _T_1430 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1430 node _T_1431 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1431 node _T_1432 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1432 node _T_1433 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1434 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1435 = and(_T_1433, _T_1434) when _T_1435 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node _T_1436 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1437 = shr(_T_1436, 18) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[3][0].data[0] node _T_1439 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1439 node _T_1440 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1440 node _T_1441 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1441 node _T_1442 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1442 node _T_1443 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1443 node _T_1444 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1444 node _T_1445 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1445 node _T_1446 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1446 node _T_1447 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1447 node _T_1448 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1448 node _T_1449 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1449 node _T_1450 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1450 node _T_1451 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1451 node _T_1452 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1452 node _T_1453 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1453 node _T_1454 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1454 node _T_1455 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1455 node _T_1456 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1456 node _T_1457 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1457 node _T_1458 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1458 node _T_1459 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1459 node _T_1460 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1460 node _T_1461 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1461 node _T_1462 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1463 = and(_T_1462, _WIRE_98.fragmented_superpage) when _T_1463 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1464 = eq(hg_12, UInt<1>(0h0)) node _T_1465 = and(_T_1464, io.sfence.bits.rs2) when _T_1465 : wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[3][0].data[0] node _T_1466 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1466 node _T_1467 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1467 node _T_1468 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1468 node _T_1469 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1469 node _T_1470 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1470 node _T_1471 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1471 node _T_1472 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1472 node _T_1473 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1473 node _T_1474 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1474 node _T_1475 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1475 node _T_1476 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1476 node _T_1477 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1477 node _T_1478 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1478 node _T_1479 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1479 node _T_1480 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1480 node _T_1481 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1481 node _T_1482 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1482 node _T_1483 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1483 node _T_1484 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1484 node _T_1485 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1485 node _T_1486 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1486 node _T_1487 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1487 node _T_1488 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1488 node _T_1489 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1490 = eq(_WIRE_100.g, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1492 = or(hv_12, hg_12) wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[3][0].data[0] node _T_1493 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1493 node _T_1494 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1494 node _T_1495 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1495 node _T_1496 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1496 node _T_1497 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1497 node _T_1498 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1498 node _T_1499 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1499 node _T_1500 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1500 node _T_1501 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1501 node _T_1502 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1502 node _T_1503 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1503 node _T_1504 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1504 node _T_1505 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1505 node _T_1506 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1506 node _T_1507 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1507 node _T_1508 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1508 node _T_1509 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1509 node _T_1510 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1510 node _T_1511 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1511 node _T_1512 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1512 node _T_1513 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1513 node _T_1514 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1514 node _T_1515 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1515 node _T_1516 = eq(sectored_entries[3][0].tag_v, _T_1492) when _T_1516 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node hv_13 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_13 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1517 = eq(hg_13, UInt<1>(0h0)) node _T_1518 = and(_T_1517, io.sfence.bits.rs1) when _T_1518 : node _T_1519 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1520 = shr(_T_1519, 0) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1523 = and(_T_1521, _T_1522) when _T_1523 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[3][1].data[0] node _T_1524 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1524 node _T_1525 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1525 node _T_1526 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1526 node _T_1527 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1527 node _T_1528 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1528 node _T_1529 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1529 node _T_1530 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1530 node _T_1531 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1531 node _T_1532 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1532 node _T_1533 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1533 node _T_1534 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1534 node _T_1535 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1535 node _T_1536 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1536 node _T_1537 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1537 node _T_1538 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1538 node _T_1539 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1539 node _T_1540 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1540 node _T_1541 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1541 node _T_1542 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1542 node _T_1543 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1543 node _T_1544 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1544 node _T_1545 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1545 node _T_1546 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1546 node _T_1547 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1548 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1549 = and(_T_1547, _T_1548) when _T_1549 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node _T_1550 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1551 = shr(_T_1550, 18) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[3][1].data[0] node _T_1553 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1553 node _T_1554 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1554 node _T_1555 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1555 node _T_1556 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1556 node _T_1557 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1557 node _T_1558 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1558 node _T_1559 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1559 node _T_1560 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1560 node _T_1561 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1561 node _T_1562 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1562 node _T_1563 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1563 node _T_1564 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1564 node _T_1565 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1565 node _T_1566 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1566 node _T_1567 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1567 node _T_1568 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1568 node _T_1569 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1569 node _T_1570 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1570 node _T_1571 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1571 node _T_1572 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1572 node _T_1573 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1573 node _T_1574 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1574 node _T_1575 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1575 node _T_1576 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1577 = and(_T_1576, _WIRE_106.fragmented_superpage) when _T_1577 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1578 = eq(hg_13, UInt<1>(0h0)) node _T_1579 = and(_T_1578, io.sfence.bits.rs2) when _T_1579 : wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[3][1].data[0] node _T_1580 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1580 node _T_1581 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1581 node _T_1582 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1582 node _T_1583 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1583 node _T_1584 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1584 node _T_1585 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1585 node _T_1586 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1586 node _T_1587 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1587 node _T_1588 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1588 node _T_1589 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1589 node _T_1590 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1590 node _T_1591 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1591 node _T_1592 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1592 node _T_1593 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1593 node _T_1594 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1594 node _T_1595 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1595 node _T_1596 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1596 node _T_1597 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1597 node _T_1598 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1598 node _T_1599 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1599 node _T_1600 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1600 node _T_1601 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1601 node _T_1602 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1602 node _T_1603 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1604 = eq(_WIRE_108.g, UInt<1>(0h0)) node _T_1605 = and(_T_1603, _T_1604) when _T_1605 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1606 = or(hv_13, hg_13) wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[3][1].data[0] node _T_1607 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1607 node _T_1608 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1608 node _T_1609 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1609 node _T_1610 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1610 node _T_1611 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1611 node _T_1612 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1612 node _T_1613 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1613 node _T_1614 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1614 node _T_1615 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1615 node _T_1616 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1616 node _T_1617 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1617 node _T_1618 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1618 node _T_1619 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1619 node _T_1620 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1620 node _T_1621 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1621 node _T_1622 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1622 node _T_1623 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1623 node _T_1624 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1624 node _T_1625 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1625 node _T_1626 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1626 node _T_1627 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1627 node _T_1628 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1628 node _T_1629 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1629 node _T_1630 = eq(sectored_entries[3][1].tag_v, _T_1606) when _T_1630 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node hv_14 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_14 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1631 = eq(hg_14, UInt<1>(0h0)) node _T_1632 = and(_T_1631, io.sfence.bits.rs1) when _T_1632 : node _T_1633 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1634 = shr(_T_1633, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[3][2].data[0] node _T_1638 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1638 node _T_1639 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1639 node _T_1640 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1640 node _T_1641 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1641 node _T_1642 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1642 node _T_1643 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1643 node _T_1644 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1644 node _T_1645 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1645 node _T_1646 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1646 node _T_1647 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1647 node _T_1648 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1648 node _T_1649 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1649 node _T_1650 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1650 node _T_1651 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1651 node _T_1652 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1652 node _T_1653 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1653 node _T_1654 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1654 node _T_1655 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1655 node _T_1656 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1656 node _T_1657 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1657 node _T_1658 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1658 node _T_1659 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1659 node _T_1660 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1660 node _T_1661 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1662 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node _T_1664 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1665 = shr(_T_1664, 18) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[3][2].data[0] node _T_1667 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1667 node _T_1668 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1668 node _T_1669 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1669 node _T_1670 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1670 node _T_1671 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1671 node _T_1672 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1672 node _T_1673 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1673 node _T_1674 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1674 node _T_1675 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1675 node _T_1676 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1676 node _T_1677 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1677 node _T_1678 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1678 node _T_1679 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1679 node _T_1680 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1680 node _T_1681 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1681 node _T_1682 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1682 node _T_1683 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1683 node _T_1684 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1684 node _T_1685 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1685 node _T_1686 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1686 node _T_1687 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1687 node _T_1688 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1688 node _T_1689 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1689 node _T_1690 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1691 = and(_T_1690, _WIRE_114.fragmented_superpage) when _T_1691 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1692 = eq(hg_14, UInt<1>(0h0)) node _T_1693 = and(_T_1692, io.sfence.bits.rs2) when _T_1693 : wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[3][2].data[0] node _T_1694 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1694 node _T_1695 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1695 node _T_1696 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1696 node _T_1697 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1697 node _T_1698 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1698 node _T_1699 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1699 node _T_1700 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1700 node _T_1701 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1701 node _T_1702 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1702 node _T_1703 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1703 node _T_1704 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1704 node _T_1705 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1705 node _T_1706 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1706 node _T_1707 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1707 node _T_1708 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1708 node _T_1709 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1709 node _T_1710 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1710 node _T_1711 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1711 node _T_1712 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1712 node _T_1713 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1713 node _T_1714 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1714 node _T_1715 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1715 node _T_1716 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1716 node _T_1717 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1718 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1719 = and(_T_1717, _T_1718) when _T_1719 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1720 = or(hv_14, hg_14) wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[3][2].data[0] node _T_1721 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1721 node _T_1722 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1722 node _T_1723 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1723 node _T_1724 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1724 node _T_1725 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1725 node _T_1726 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1726 node _T_1727 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1727 node _T_1728 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1728 node _T_1729 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1729 node _T_1730 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1730 node _T_1731 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1731 node _T_1732 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1732 node _T_1733 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1733 node _T_1734 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1734 node _T_1735 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1735 node _T_1736 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1736 node _T_1737 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1737 node _T_1738 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1738 node _T_1739 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1739 node _T_1740 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1740 node _T_1741 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1741 node _T_1742 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1742 node _T_1743 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1743 node _T_1744 = eq(sectored_entries[3][2].tag_v, _T_1720) when _T_1744 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node hv_15 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_15 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_15, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 0) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[3][3].data[0] node _T_1752 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1753 node _T_1754 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1754 node _T_1755 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1755 node _T_1756 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1756 node _T_1757 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1757 node _T_1758 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1758 node _T_1759 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1759 node _T_1760 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1760 node _T_1761 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1761 node _T_1762 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1762 node _T_1763 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1763 node _T_1764 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1764 node _T_1765 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1765 node _T_1766 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1766 node _T_1767 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1767 node _T_1768 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1768 node _T_1769 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1770 node _T_1771 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1772 node _T_1773 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1773 node _T_1774 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1774 node _T_1775 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1776 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1777 = and(_T_1775, _T_1776) when _T_1777 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node _T_1778 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1779 = shr(_T_1778, 18) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[3][3].data[0] node _T_1781 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1781 node _T_1782 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1782 node _T_1783 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1783 node _T_1784 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1784 node _T_1785 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1785 node _T_1786 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1786 node _T_1787 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1787 node _T_1788 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1788 node _T_1789 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1789 node _T_1790 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1790 node _T_1791 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1791 node _T_1792 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1792 node _T_1793 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1793 node _T_1794 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1794 node _T_1795 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1795 node _T_1796 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1796 node _T_1797 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1797 node _T_1798 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1798 node _T_1799 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1799 node _T_1800 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1800 node _T_1801 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1801 node _T_1802 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1802 node _T_1803 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1803 node _T_1804 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1805 = and(_T_1804, _WIRE_122.fragmented_superpage) when _T_1805 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1806 = eq(hg_15, UInt<1>(0h0)) node _T_1807 = and(_T_1806, io.sfence.bits.rs2) when _T_1807 : wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[3][3].data[0] node _T_1808 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1808 node _T_1809 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1809 node _T_1810 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1810 node _T_1811 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1811 node _T_1812 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1812 node _T_1813 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1813 node _T_1814 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1814 node _T_1815 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1815 node _T_1816 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1816 node _T_1817 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1817 node _T_1818 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1818 node _T_1819 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1819 node _T_1820 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1820 node _T_1821 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1821 node _T_1822 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1822 node _T_1823 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1823 node _T_1824 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1824 node _T_1825 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1825 node _T_1826 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1826 node _T_1827 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1827 node _T_1828 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1828 node _T_1829 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1829 node _T_1830 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1830 node _T_1831 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1832 = eq(_WIRE_124.g, UInt<1>(0h0)) node _T_1833 = and(_T_1831, _T_1832) when _T_1833 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1834 = or(hv_15, hg_15) wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[3][3].data[0] node _T_1835 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1835 node _T_1836 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1836 node _T_1837 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1837 node _T_1838 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1838 node _T_1839 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1839 node _T_1840 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1840 node _T_1841 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1841 node _T_1842 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1842 node _T_1843 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1843 node _T_1844 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1844 node _T_1845 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1845 node _T_1846 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1846 node _T_1847 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1847 node _T_1848 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1848 node _T_1849 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1849 node _T_1850 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1850 node _T_1851 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1851 node _T_1852 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1852 node _T_1853 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1853 node _T_1854 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1854 node _T_1855 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1855 node _T_1856 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1856 node _T_1857 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1857 node _T_1858 = eq(sectored_entries[3][3].tag_v, _T_1834) when _T_1858 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node hv_16 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_16 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1859 = eq(hg_16, UInt<1>(0h0)) node _T_1860 = and(_T_1859, io.sfence.bits.rs1) when _T_1860 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_16) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_1861 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1862 = bits(_T_1861, 26, 18) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(ignore, _T_1863) node _T_1865 = and(tagMatch, _T_1864) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_1866 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1867 = bits(_T_1866, 17, 9) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) node _T_1869 = or(ignore_1, _T_1868) node _T_1870 = and(_T_1865, _T_1869) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_1871 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1872 = bits(_T_1871, 8, 0) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) node _T_1874 = or(ignore_2, _T_1873) node _T_1875 = and(_T_1870, _T_1874) when _T_1875 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_1876 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1877 = shr(_T_1876, 18) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, superpage_entries[0].data[0] node _T_1879 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1879 node _T_1880 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1880 node _T_1881 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1881 node _T_1882 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1882 node _T_1883 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1883 node _T_1884 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1884 node _T_1885 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1885 node _T_1886 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1886 node _T_1887 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1887 node _T_1888 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1888 node _T_1889 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1889 node _T_1890 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1890 node _T_1891 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1891 node _T_1892 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1892 node _T_1893 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1893 node _T_1894 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1894 node _T_1895 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1895 node _T_1896 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1896 node _T_1897 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1897 node _T_1898 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1898 node _T_1899 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1899 node _T_1900 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1900 node _T_1901 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1901 node _T_1902 = eq(superpage_entries[0].tag_v, hv_16) node _T_1903 = and(_T_1902, _WIRE_128.fragmented_superpage) when _T_1903 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1904 = eq(hg_16, UInt<1>(0h0)) node _T_1905 = and(_T_1904, io.sfence.bits.rs2) when _T_1905 : wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, superpage_entries[0].data[0] node _T_1906 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1906 node _T_1907 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1907 node _T_1908 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1908 node _T_1909 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1909 node _T_1910 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1910 node _T_1911 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1911 node _T_1912 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1912 node _T_1913 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1913 node _T_1914 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1914 node _T_1915 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1915 node _T_1916 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1916 node _T_1917 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1917 node _T_1918 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1918 node _T_1919 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1919 node _T_1920 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1920 node _T_1921 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1921 node _T_1922 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1922 node _T_1923 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1923 node _T_1924 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1924 node _T_1925 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1925 node _T_1926 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1926 node _T_1927 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1927 node _T_1928 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1928 node _T_1929 = eq(superpage_entries[0].tag_v, hv_16) node _T_1930 = eq(_WIRE_130.g, UInt<1>(0h0)) node _T_1931 = and(_T_1929, _T_1930) when _T_1931 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1932 = or(hv_16, hg_16) wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, superpage_entries[0].data[0] node _T_1933 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1933 node _T_1934 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1934 node _T_1935 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1935 node _T_1936 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1936 node _T_1937 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1937 node _T_1938 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1938 node _T_1939 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1939 node _T_1940 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1940 node _T_1941 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1941 node _T_1942 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1942 node _T_1943 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1943 node _T_1944 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1944 node _T_1945 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1945 node _T_1946 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1946 node _T_1947 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1947 node _T_1948 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1948 node _T_1949 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1949 node _T_1950 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1950 node _T_1951 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1951 node _T_1952 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1952 node _T_1953 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1953 node _T_1954 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1954 node _T_1955 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1955 node _T_1956 = eq(superpage_entries[0].tag_v, _T_1932) when _T_1956 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_17 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_17 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1957 = eq(hg_17, UInt<1>(0h0)) node _T_1958 = and(_T_1957, io.sfence.bits.rs1) when _T_1958 : node _tagMatch_T_1 = eq(special_entry.tag_v, hv_17) node tagMatch_1 = and(special_entry.valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_1959 = xor(special_entry.tag_vpn, vpn) node _T_1960 = bits(_T_1959, 26, 18) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) node _T_1962 = or(ignore_3, _T_1961) node _T_1963 = and(tagMatch_1, _T_1962) node _ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_1964 = xor(special_entry.tag_vpn, vpn) node _T_1965 = bits(_T_1964, 17, 9) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = or(ignore_4, _T_1966) node _T_1968 = and(_T_1963, _T_1967) node _ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h0)) node _T_1969 = xor(special_entry.tag_vpn, vpn) node _T_1970 = bits(_T_1969, 8, 0) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(ignore_5, _T_1971) node _T_1973 = and(_T_1968, _T_1972) when _T_1973 : connect special_entry.valid[0], UInt<1>(0h0) node _T_1974 = xor(special_entry.tag_vpn, vpn) node _T_1975 = shr(_T_1974, 18) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, special_entry.data[0] node _T_1977 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1977 node _T_1978 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1978 node _T_1979 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1979 node _T_1980 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1980 node _T_1981 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1981 node _T_1982 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1982 node _T_1983 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1983 node _T_1984 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1984 node _T_1985 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1985 node _T_1986 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1986 node _T_1987 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1987 node _T_1988 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1988 node _T_1989 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1989 node _T_1990 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1990 node _T_1991 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1991 node _T_1992 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1992 node _T_1993 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1993 node _T_1994 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1994 node _T_1995 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1995 node _T_1996 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1996 node _T_1997 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1997 node _T_1998 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1998 node _T_1999 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1999 node _T_2000 = eq(special_entry.tag_v, hv_17) node _T_2001 = and(_T_2000, _WIRE_134.fragmented_superpage) when _T_2001 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2002 = eq(hg_17, UInt<1>(0h0)) node _T_2003 = and(_T_2002, io.sfence.bits.rs2) when _T_2003 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, special_entry.data[0] node _T_2004 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_2004 node _T_2005 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_2005 node _T_2006 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_2006 node _T_2007 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_2007 node _T_2008 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_2008 node _T_2009 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_2009 node _T_2010 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_2010 node _T_2011 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_2011 node _T_2012 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_2012 node _T_2013 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_2013 node _T_2014 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_2014 node _T_2015 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_2015 node _T_2016 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_2016 node _T_2017 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_2017 node _T_2018 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_2018 node _T_2019 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_2019 node _T_2020 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_2020 node _T_2021 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_2021 node _T_2022 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_2022 node _T_2023 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_2023 node _T_2024 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_2024 node _T_2025 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_2025 node _T_2026 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_2026 node _T_2027 = eq(special_entry.tag_v, hv_17) node _T_2028 = eq(_WIRE_136.g, UInt<1>(0h0)) node _T_2029 = and(_T_2027, _T_2028) when _T_2029 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2030 = or(hv_17, hg_17) wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, special_entry.data[0] node _T_2031 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_2031 node _T_2032 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_2032 node _T_2033 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_2033 node _T_2034 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_2034 node _T_2035 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_2035 node _T_2036 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_2036 node _T_2037 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_2037 node _T_2038 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_2038 node _T_2039 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_2039 node _T_2040 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_2040 node _T_2041 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_2041 node _T_2042 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_2042 node _T_2043 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_2043 node _T_2044 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_2044 node _T_2045 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_2045 node _T_2046 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_2046 node _T_2047 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_2047 node _T_2048 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_2048 node _T_2049 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_2049 node _T_2050 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_2050 node _T_2051 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_2051 node _T_2052 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_2052 node _T_2053 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_2053 node _T_2054 = eq(special_entry.tag_v, _T_2030) when _T_2054 : connect special_entry.valid[0], UInt<1>(0h0) node _T_2055 = and(io.req.ready, io.req.valid) node _T_2056 = and(_T_2055, vsatp_mode_mismatch) when _T_2056 : wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][0].data[0] node _T_2057 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_2057 node _T_2058 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_2058 node _T_2059 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_2059 node _T_2060 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_2060 node _T_2061 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_2061 node _T_2062 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_2062 node _T_2063 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_2063 node _T_2064 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_2064 node _T_2065 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_2065 node _T_2066 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_2066 node _T_2067 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_2067 node _T_2068 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_2068 node _T_2069 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_2069 node _T_2070 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_2070 node _T_2071 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_2071 node _T_2072 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_2072 node _T_2073 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_2073 node _T_2074 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_2074 node _T_2075 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_2075 node _T_2076 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_2076 node _T_2077 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_2077 node _T_2078 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_2078 node _T_2079 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_2079 node _T_2080 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_2080 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][1].data[0] node _T_2081 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_2081 node _T_2082 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_2082 node _T_2083 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_2083 node _T_2084 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_2084 node _T_2085 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_2085 node _T_2086 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_2086 node _T_2087 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_2087 node _T_2088 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_2088 node _T_2089 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_2089 node _T_2090 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_2090 node _T_2091 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_2091 node _T_2092 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_2092 node _T_2093 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_2093 node _T_2094 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_2094 node _T_2095 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_2095 node _T_2096 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_2096 node _T_2097 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_2097 node _T_2098 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_2098 node _T_2099 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_2099 node _T_2100 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_2100 node _T_2101 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_2101 node _T_2102 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_2102 node _T_2103 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_2103 node _T_2104 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_2104 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][2].data[0] node _T_2105 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_2105 node _T_2106 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_2106 node _T_2107 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_2107 node _T_2108 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_2108 node _T_2109 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_2109 node _T_2110 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_2110 node _T_2111 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_2111 node _T_2112 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_2112 node _T_2113 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_2113 node _T_2114 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_2114 node _T_2115 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_2115 node _T_2116 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_2116 node _T_2117 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_2117 node _T_2118 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_2118 node _T_2119 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_2119 node _T_2120 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_2120 node _T_2121 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_2121 node _T_2122 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_2122 node _T_2123 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_2123 node _T_2124 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_2124 node _T_2125 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_2125 node _T_2126 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_2126 node _T_2127 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_2127 node _T_2128 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_2128 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][3].data[0] node _T_2129 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_2129 node _T_2130 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_2130 node _T_2131 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_2131 node _T_2132 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_2132 node _T_2133 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_2133 node _T_2134 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_2134 node _T_2135 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_2135 node _T_2136 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_2136 node _T_2137 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_2137 node _T_2138 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_2138 node _T_2139 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_2139 node _T_2140 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_2140 node _T_2141 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2141 node _T_2142 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2142 node _T_2143 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2143 node _T_2144 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2144 node _T_2145 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2145 node _T_2146 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2146 node _T_2147 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2147 node _T_2148 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2148 node _T_2149 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2149 node _T_2150 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2150 node _T_2151 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2151 node _T_2152 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_2152 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[1][0].data[0] node _T_2153 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2153 node _T_2154 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2154 node _T_2155 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2155 node _T_2156 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2156 node _T_2157 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2157 node _T_2158 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2158 node _T_2159 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2159 node _T_2160 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2160 node _T_2161 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2161 node _T_2162 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2162 node _T_2163 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2163 node _T_2164 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2164 node _T_2165 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2165 node _T_2166 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2166 node _T_2167 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2167 node _T_2168 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2168 node _T_2169 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2169 node _T_2170 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2170 node _T_2171 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2171 node _T_2172 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2172 node _T_2173 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2173 node _T_2174 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2174 node _T_2175 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2175 node _T_2176 = eq(sectored_entries[1][0].tag_v, UInt<1>(0h1)) when _T_2176 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[1][1].data[0] node _T_2177 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2177 node _T_2178 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2178 node _T_2179 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2179 node _T_2180 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2180 node _T_2181 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2181 node _T_2182 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2182 node _T_2183 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2183 node _T_2184 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2184 node _T_2185 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2185 node _T_2186 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2186 node _T_2187 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2187 node _T_2188 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2188 node _T_2189 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2189 node _T_2190 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2190 node _T_2191 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2191 node _T_2192 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2192 node _T_2193 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2193 node _T_2194 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2194 node _T_2195 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2195 node _T_2196 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2196 node _T_2197 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2197 node _T_2198 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2198 node _T_2199 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2199 node _T_2200 = eq(sectored_entries[1][1].tag_v, UInt<1>(0h1)) when _T_2200 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[1][2].data[0] node _T_2201 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2201 node _T_2202 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2202 node _T_2203 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2203 node _T_2204 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2204 node _T_2205 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2205 node _T_2206 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2206 node _T_2207 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2207 node _T_2208 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2208 node _T_2209 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2209 node _T_2210 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2210 node _T_2211 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2211 node _T_2212 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2212 node _T_2213 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2213 node _T_2214 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2214 node _T_2215 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2215 node _T_2216 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2216 node _T_2217 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2217 node _T_2218 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2218 node _T_2219 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2219 node _T_2220 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2220 node _T_2221 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2221 node _T_2222 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2222 node _T_2223 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2223 node _T_2224 = eq(sectored_entries[1][2].tag_v, UInt<1>(0h1)) when _T_2224 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[1][3].data[0] node _T_2225 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2225 node _T_2226 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2226 node _T_2227 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2227 node _T_2228 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2228 node _T_2229 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2229 node _T_2230 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2230 node _T_2231 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2231 node _T_2232 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2232 node _T_2233 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2233 node _T_2234 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2234 node _T_2235 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2235 node _T_2236 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2236 node _T_2237 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2237 node _T_2238 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2238 node _T_2239 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2239 node _T_2240 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2240 node _T_2241 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2241 node _T_2242 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2242 node _T_2243 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2243 node _T_2244 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2244 node _T_2245 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2245 node _T_2246 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2246 node _T_2247 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2247 node _T_2248 = eq(sectored_entries[1][3].tag_v, UInt<1>(0h1)) when _T_2248 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[2][0].data[0] node _T_2249 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2249 node _T_2250 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2250 node _T_2251 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2251 node _T_2252 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2252 node _T_2253 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2253 node _T_2254 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2254 node _T_2255 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2255 node _T_2256 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2256 node _T_2257 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2257 node _T_2258 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2258 node _T_2259 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2259 node _T_2260 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2260 node _T_2261 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2261 node _T_2262 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2262 node _T_2263 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2263 node _T_2264 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2264 node _T_2265 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2265 node _T_2266 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2266 node _T_2267 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2267 node _T_2268 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2268 node _T_2269 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2269 node _T_2270 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2270 node _T_2271 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2271 node _T_2272 = eq(sectored_entries[2][0].tag_v, UInt<1>(0h1)) when _T_2272 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[2][1].data[0] node _T_2273 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2273 node _T_2274 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2274 node _T_2275 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2275 node _T_2276 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2276 node _T_2277 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2277 node _T_2278 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2278 node _T_2279 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2279 node _T_2280 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2280 node _T_2281 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2281 node _T_2282 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2282 node _T_2283 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2283 node _T_2284 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2284 node _T_2285 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2285 node _T_2286 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2286 node _T_2287 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2287 node _T_2288 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2288 node _T_2289 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2289 node _T_2290 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2290 node _T_2291 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2291 node _T_2292 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2292 node _T_2293 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2293 node _T_2294 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2294 node _T_2295 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2295 node _T_2296 = eq(sectored_entries[2][1].tag_v, UInt<1>(0h1)) when _T_2296 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[2][2].data[0] node _T_2297 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2297 node _T_2298 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2298 node _T_2299 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2299 node _T_2300 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2300 node _T_2301 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2301 node _T_2302 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2302 node _T_2303 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2303 node _T_2304 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2304 node _T_2305 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2305 node _T_2306 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2306 node _T_2307 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2307 node _T_2308 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2308 node _T_2309 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2309 node _T_2310 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2310 node _T_2311 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2311 node _T_2312 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2312 node _T_2313 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2313 node _T_2314 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2314 node _T_2315 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2315 node _T_2316 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2316 node _T_2317 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2317 node _T_2318 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2318 node _T_2319 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2319 node _T_2320 = eq(sectored_entries[2][2].tag_v, UInt<1>(0h1)) when _T_2320 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[2][3].data[0] node _T_2321 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2321 node _T_2322 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2322 node _T_2323 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2323 node _T_2324 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2324 node _T_2325 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2325 node _T_2326 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2326 node _T_2327 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2327 node _T_2328 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2328 node _T_2329 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2329 node _T_2330 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2330 node _T_2331 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2331 node _T_2332 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2332 node _T_2333 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2333 node _T_2334 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2334 node _T_2335 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2335 node _T_2336 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2336 node _T_2337 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2337 node _T_2338 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2338 node _T_2339 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2339 node _T_2340 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2340 node _T_2341 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2341 node _T_2342 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2342 node _T_2343 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2343 node _T_2344 = eq(sectored_entries[2][3].tag_v, UInt<1>(0h1)) when _T_2344 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[3][0].data[0] node _T_2345 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2345 node _T_2346 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2346 node _T_2347 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2347 node _T_2348 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2348 node _T_2349 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2349 node _T_2350 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2350 node _T_2351 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2351 node _T_2352 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2352 node _T_2353 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2353 node _T_2354 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2354 node _T_2355 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2355 node _T_2356 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2356 node _T_2357 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2357 node _T_2358 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2358 node _T_2359 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2359 node _T_2360 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2360 node _T_2361 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2361 node _T_2362 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2362 node _T_2363 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2363 node _T_2364 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2364 node _T_2365 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2365 node _T_2366 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2366 node _T_2367 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2367 node _T_2368 = eq(sectored_entries[3][0].tag_v, UInt<1>(0h1)) when _T_2368 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[3][1].data[0] node _T_2369 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2369 node _T_2370 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2370 node _T_2371 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2371 node _T_2372 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2372 node _T_2373 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2373 node _T_2374 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2374 node _T_2375 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2375 node _T_2376 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2376 node _T_2377 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2377 node _T_2378 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2378 node _T_2379 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2379 node _T_2380 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2380 node _T_2381 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2381 node _T_2382 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2382 node _T_2383 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2383 node _T_2384 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2384 node _T_2385 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2385 node _T_2386 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2386 node _T_2387 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2387 node _T_2388 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2388 node _T_2389 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2389 node _T_2390 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2390 node _T_2391 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2391 node _T_2392 = eq(sectored_entries[3][1].tag_v, UInt<1>(0h1)) when _T_2392 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[3][2].data[0] node _T_2393 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2393 node _T_2394 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2394 node _T_2395 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2395 node _T_2396 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2396 node _T_2397 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2397 node _T_2398 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2398 node _T_2399 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2399 node _T_2400 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2400 node _T_2401 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2401 node _T_2402 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2402 node _T_2403 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2403 node _T_2404 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2404 node _T_2405 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2405 node _T_2406 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2406 node _T_2407 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2407 node _T_2408 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2408 node _T_2409 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2409 node _T_2410 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2410 node _T_2411 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2411 node _T_2412 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2412 node _T_2413 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2413 node _T_2414 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2414 node _T_2415 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2415 node _T_2416 = eq(sectored_entries[3][2].tag_v, UInt<1>(0h1)) when _T_2416 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[3][3].data[0] node _T_2417 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2417 node _T_2418 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2418 node _T_2419 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2419 node _T_2420 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2420 node _T_2421 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2421 node _T_2422 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2422 node _T_2423 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2423 node _T_2424 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2424 node _T_2425 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2425 node _T_2426 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2426 node _T_2427 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2427 node _T_2428 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2428 node _T_2429 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2429 node _T_2430 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2430 node _T_2431 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2431 node _T_2432 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2432 node _T_2433 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2433 node _T_2434 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2434 node _T_2435 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2435 node _T_2436 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2436 node _T_2437 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2437 node _T_2438 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2438 node _T_2439 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2439 node _T_2440 = eq(sectored_entries[3][3].tag_v, UInt<1>(0h1)) when _T_2440 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, superpage_entries[0].data[0] node _T_2441 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2441 node _T_2442 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2442 node _T_2443 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2443 node _T_2444 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2444 node _T_2445 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2445 node _T_2446 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2446 node _T_2447 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2447 node _T_2448 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2448 node _T_2449 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2449 node _T_2450 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2450 node _T_2451 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2451 node _T_2452 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2452 node _T_2453 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2453 node _T_2454 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2454 node _T_2455 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2455 node _T_2456 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2456 node _T_2457 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2457 node _T_2458 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2458 node _T_2459 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2459 node _T_2460 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2460 node _T_2461 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2461 node _T_2462 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2462 node _T_2463 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2463 node _T_2464 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_2464 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, special_entry.data[0] node _T_2465 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2465 node _T_2466 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2466 node _T_2467 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2467 node _T_2468 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2468 node _T_2469 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2469 node _T_2470 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2470 node _T_2471 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2471 node _T_2472 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2472 node _T_2473 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2473 node _T_2474 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2474 node _T_2475 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2475 node _T_2476 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2476 node _T_2477 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2477 node _T_2478 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2478 node _T_2479 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2479 node _T_2480 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2480 node _T_2481 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2481 node _T_2482 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2482 node _T_2483 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2483 node _T_2484 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2484 node _T_2485 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2485 node _T_2486 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2486 node _T_2487 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2487 node _T_2488 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_2488 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_2489 = asUInt(reset) node _T_2490 = or(multipleHits, _T_2489) when _T_2490 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[1][0].valid[0], UInt<1>(0h0) connect sectored_entries[1][1].valid[0], UInt<1>(0h0) connect sectored_entries[1][2].valid[0], UInt<1>(0h0) connect sectored_entries[1][3].valid[0], UInt<1>(0h0) connect sectored_entries[2][0].valid[0], UInt<1>(0h0) connect sectored_entries[2][1].valid[0], UInt<1>(0h0) connect sectored_entries[2][2].valid[0], UInt<1>(0h0) connect sectored_entries[2][3].valid[0], UInt<1>(0h0) connect sectored_entries[3][0].valid[0], UInt<1>(0h0) connect sectored_entries[3][1].valid[0], UInt<1>(0h0) connect sectored_entries[3][2].valid[0], UInt<1>(0h0) connect sectored_entries[3][3].valid[0], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_2491 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_2492 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_2493 = and(io.ptw.req.valid, _T_2492) node _T_2494 = eq(state, UInt<2>(0h3)) node _T_2495 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2496 = and(io.sfence.valid, _T_2495) node _T_2497 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2498 = and(_T_2496, _T_2497) node _T_2499 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2500 = and(io.sfence.valid, _T_2499) node _T_2501 = and(_T_2500, io.sfence.bits.rs2) node _T_2502 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2503 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2504 = and(_T_2502, _T_2503) node _T_2505 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2506 = and(_T_2505, io.sfence.bits.rs2)	module DTLB_5( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 \| _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 \| _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 \| _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 \| _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 \| _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 \| _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 \| _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 \| _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 \| _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T \| _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 \| sector_hits_1 \| sector_hits_2 \| sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill \| _GEN_63 \| ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill \| _GEN_63 \| ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill \| _GEN_63 \| ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill \| _GEN_63 \| ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill \| _GEN_63 \| ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill \| _GEN_63 \| ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill \| _GEN_63 \| ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits \| reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_49 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_5 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_5 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_50 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_51 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_52 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_53 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_54 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_55 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_39 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_39 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_39( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_39 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_12 : input clock : Clock input reset : Reset output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst queue of Queue64_TLBundleA_a32d256s5k3z4u_4 connect queue.clock, clock connect queue.reset, reset inst release_ready_cycle_q of Queue64_UInt64_8 connect release_ready_cycle_q.clock, clock connect release_ready_cycle_q.reset, reset node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles) node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1) connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1 connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt connect queue.io.enq.bits.data, io.enq.bits.data connect queue.io.enq.bits.mask, io.enq.bits.mask connect queue.io.enq.bits.address, io.enq.bits.address connect queue.io.enq.bits.source, io.enq.bits.source connect queue.io.enq.bits.size, io.enq.bits.size connect queue.io.enq.bits.param, io.enq.bits.param connect queue.io.enq.bits.opcode, io.enq.bits.opcode connect io.deq.bits, queue.io.deq.bits node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid) connect queue.io.enq.valid, _queue_io_enq_valid_T node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid) connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready) connect io.enq.ready, _io_enq_ready_T node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle) node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T) node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready) connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1 node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid) node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T) connect io.deq.valid, _io_deq_valid_T_1	module LatencyInjectionQueue_12( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14] input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [31:0] io_enq_bits_address, // @[LatencyInjectionQueue.scala:10:14] input [31:0] io_enq_bits_mask, // @[LatencyInjectionQueue.scala:10:14] input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [2:0] io_deq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] output [2:0] io_deq_bits_param, // @[LatencyInjectionQueue.scala:10:14] output [3:0] io_deq_bits_size, // @[LatencyInjectionQueue.scala:10:14] output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [31:0] io_deq_bits_address, // @[LatencyInjectionQueue.scala:10:14] output [31:0] io_deq_bits_mask, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data, // @[LatencyInjectionQueue.scala:10:14] output io_deq_bits_corrupt // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt = 1'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [2:0] io_enq_bits_param = 3'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :16:26, :17:26, :18:21] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :17:26, :18:21, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue64_TLBundleA_a32d256s5k3z4u_4 queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_address (io_enq_bits_address_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_mask (io_enq_bits_mask_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode_0), .io_deq_bits_param (io_deq_bits_param_0), .io_deq_bits_size (io_deq_bits_size_0), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_address (io_deq_bits_address_0), .io_deq_bits_mask (io_deq_bits_mask_0), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt_0) ); // @[LatencyInjectionQueue.scala:18:21] Queue64_UInt64_8 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_251 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_507 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_251( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_507 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_322 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_66 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_322( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_66 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_26 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_26( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x5 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[5], out : { sync : UInt<1>[5]}} wire nodeIn : UInt<1>[5] invalidate nodeIn[0] invalidate nodeIn[1] invalidate nodeIn[2] invalidate nodeIn[3] invalidate nodeIn[4] wire nodeOut : { sync : UInt<1>[5]} invalidate nodeOut.sync[0] invalidate nodeOut.sync[1] invalidate nodeOut.sync[2] invalidate nodeOut.sync[3] invalidate nodeOut.sync[4] connect auto.out, nodeOut connect nodeIn, auto.in node lo = cat(nodeIn[1], nodeIn[0]) node hi_hi = cat(nodeIn[4], nodeIn[3]) node hi = cat(hi_hi, nodeIn[2]) node _T = cat(hi, lo) inst reg of AsyncResetRegVec_w5_i0 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, _T connect reg.io.en, UInt<1>(0h1) node _T_1 = bits(reg.io.q, 0, 0) node _T_2 = bits(reg.io.q, 1, 1) node _T_3 = bits(reg.io.q, 2, 2) node _T_4 = bits(reg.io.q, 3, 3) node _T_5 = bits(reg.io.q, 4, 4) connect nodeOut.sync[0], _T_1 connect nodeOut.sync[1], _T_2 connect nodeOut.sync[2], _T_3 connect nodeOut.sync[3], _T_4 connect nodeOut.sync[4], _T_5	module IntSyncCrossingSource_n1x5( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_2, // @[LazyModuleImp.scala:107:25] output auto_out_sync_3, // @[LazyModuleImp.scala:107:25] output auto_out_sync_4 // @[LazyModuleImp.scala:107:25] ); wire [4:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire [1:0] lo = 2'h0; // @[Crossing.scala:45:36] wire [1:0] hi_hi = 2'h0; // @[Crossing.scala:45:36] wire [2:0] hi = 3'h0; // @[Crossing.scala:45:36] wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_1 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_2 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_3 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_4 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_2 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_3 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_4 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire nodeOut_sync_2; // @[MixedNode.scala:542:17] wire nodeOut_sync_3; // @[MixedNode.scala:542:17] wire nodeOut_sync_4; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] wire auto_out_sync_2_0; // @[Crossing.scala:41:9] wire auto_out_sync_3_0; // @[Crossing.scala:41:9] wire auto_out_sync_4_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign auto_out_sync_2_0 = nodeOut_sync_2; // @[Crossing.scala:41:9] assign auto_out_sync_3_0 = nodeOut_sync_3; // @[Crossing.scala:41:9] assign auto_out_sync_4_0 = nodeOut_sync_4; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_2 = _reg_io_q[2]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_3 = _reg_io_q[3]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_4 = _reg_io_q[4]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w5_i0 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_2 = auto_out_sync_2_0; // @[Crossing.scala:41:9] assign auto_out_sync_3 = auto_out_sync_3_0; // @[Crossing.scala:41:9] assign auto_out_sync_4 = auto_out_sync_4_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a12d64s10k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a12d64s10k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [11:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [11:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [11:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid \| full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN \| full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_125 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_126 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module GenericDeserializer_TLBeatw88_f32_1 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}, busy : UInt<1>} reg data : UInt<32>[2], clock regreset beat : UInt<2>, clock, reset, UInt<2>(0h0) node _io_in_ready_T = neq(beat, UInt<2>(0h2)) node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = eq(beat, UInt<2>(0h2)) node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 node _io_out_bits_T = cat(data[1], data[0]) node _io_out_bits_T_1 = cat(io.in.bits.flit, _io_out_bits_T) wire _io_out_bits_WIRE : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>} wire _io_out_bits_WIRE_1 : UInt<88> connect _io_out_bits_WIRE_1, _io_out_bits_T_1 node _io_out_bits_T_2 = bits(_io_out_bits_WIRE_1, 0, 0) connect _io_out_bits_WIRE.tail, _io_out_bits_T_2 node _io_out_bits_T_3 = bits(_io_out_bits_WIRE_1, 1, 1) connect _io_out_bits_WIRE.head, _io_out_bits_T_3 node _io_out_bits_T_4 = bits(_io_out_bits_WIRE_1, 87, 2) connect _io_out_bits_WIRE.payload, _io_out_bits_T_4 connect io.out.bits, _io_out_bits_WIRE node _T = and(io.in.ready, io.in.valid) when _T : node _beat_T = eq(beat, UInt<2>(0h2)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = neq(beat, UInt<2>(0h2)) when _T_1 : node _T_2 = bits(beat, 0, 0) connect data[_T_2], io.in.bits.flit node _io_busy_T = neq(beat, UInt<1>(0h0)) connect io.busy, _io_busy_T	module GenericDeserializer_TLBeatw88_f32_1( // @[Serdes.scala:37:7] input clock, // @[Serdes.scala:37:7] input reset, // @[Serdes.scala:37:7] output io_in_ready, // @[Serdes.scala:39:14] input io_in_valid, // @[Serdes.scala:39:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:39:14] input io_out_ready, // @[Serdes.scala:39:14] output io_out_valid, // @[Serdes.scala:39:14] output [85:0] io_out_bits_payload, // @[Serdes.scala:39:14] output io_out_bits_head, // @[Serdes.scala:39:14] output io_out_bits_tail, // @[Serdes.scala:39:14] output io_busy // @[Serdes.scala:39:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:37:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:37:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:37:7] wire _io_in_ready_T_1; // @[Serdes.scala:51:31] wire _io_out_valid_T_1; // @[Serdes.scala:52:31] wire [85:0] _io_out_bits_WIRE_payload; // @[Serdes.scala:56:47] wire _io_out_bits_WIRE_head; // @[Serdes.scala:56:47] wire _io_out_bits_WIRE_tail; // @[Serdes.scala:56:47] wire _io_busy_T; // @[Serdes.scala:68:19] wire io_in_ready_0; // @[Serdes.scala:37:7] wire [85:0] io_out_bits_payload_0; // @[Serdes.scala:37:7] wire io_out_bits_head_0; // @[Serdes.scala:37:7] wire io_out_bits_tail_0; // @[Serdes.scala:37:7] wire io_out_valid_0; // @[Serdes.scala:37:7] wire io_busy_0; // @[Serdes.scala:37:7] reg [31:0] data_0; // @[Serdes.scala:48:17] reg [31:0] data_1; // @[Serdes.scala:48:17] reg [1:0] beat; // @[Serdes.scala:49:21] wire _io_in_ready_T = beat != 2'h2; // @[Serdes.scala:49:21, :51:39] assign _io_in_ready_T_1 = io_out_ready_0 \| _io_in_ready_T; // @[Serdes.scala:37:7, :51:{31,39}] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:37:7, :51:31] wire _GEN = beat == 2'h2; // @[Serdes.scala:49:21, :52:39] wire _io_out_valid_T; // @[Serdes.scala:52:39] assign _io_out_valid_T = _GEN; // @[Serdes.scala:52:39] wire _beat_T; // @[Serdes.scala:60:22] assign _beat_T = _GEN; // @[Serdes.scala:52:39, :60:22] assign _io_out_valid_T_1 = io_in_valid_0 & _io_out_valid_T; // @[Serdes.scala:37:7, :52:{31,39}] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:37:7, :52:31] wire [63:0] _io_out_bits_T = {data_1, data_0}; // @[Serdes.scala:48:17, :56:31] wire [95:0] _io_out_bits_T_1 = {io_in_bits_flit_0, _io_out_bits_T}; // @[Serdes.scala:37:7, :56:{8,31}] wire [85:0] _io_out_bits_T_4; // @[Serdes.scala:56:47] assign io_out_bits_payload_0 = _io_out_bits_WIRE_payload; // @[Serdes.scala:37:7, :56:47] wire _io_out_bits_T_3; // @[Serdes.scala:56:47] assign io_out_bits_head_0 = _io_out_bits_WIRE_head; // @[Serdes.scala:37:7, :56:47] wire _io_out_bits_T_2; // @[Serdes.scala:56:47] assign io_out_bits_tail_0 = _io_out_bits_WIRE_tail; // @[Serdes.scala:37:7, :56:47] wire [87:0] _io_out_bits_WIRE_1 = _io_out_bits_T_1[87:0]; // @[Serdes.scala:56:{8,47}] assign _io_out_bits_T_2 = _io_out_bits_WIRE_1[0]; // @[Serdes.scala:56:47] assign _io_out_bits_WIRE_tail = _io_out_bits_T_2; // @[Serdes.scala:56:47] assign _io_out_bits_T_3 = _io_out_bits_WIRE_1[1]; // @[Serdes.scala:56:47] assign _io_out_bits_WIRE_head = _io_out_bits_T_3; // @[Serdes.scala:56:47] assign _io_out_bits_T_4 = _io_out_bits_WIRE_1[87:2]; // @[Serdes.scala:56:47] assign _io_out_bits_WIRE_payload = _io_out_bits_T_4; // @[Serdes.scala:56:47] wire [2:0] _beat_T_1 = {1'h0, beat} + 3'h1; // @[Serdes.scala:49:21, :60:53] wire [1:0] _beat_T_2 = _beat_T_1[1:0]; // @[Serdes.scala:60:53] wire [1:0] _beat_T_3 = _beat_T ? 2'h0 : _beat_T_2; // @[Serdes.scala:60:{16,22,53}] assign _io_busy_T = \|beat; // @[Serdes.scala:49:21, :68:19] assign io_busy_0 = _io_busy_T; // @[Serdes.scala:37:7, :68:19] wire _T = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Serdes.scala:37:7] if (~_T \| _GEN \| beat[0]) begin // @[Decoupled.scala:51:35] end else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47] data_0 <= io_in_bits_flit_0; // @[Serdes.scala:37:7, :48:17] if (~_T \| _GEN \| ~(beat[0])) begin // @[Decoupled.scala:51:35] end else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47] data_1 <= io_in_bits_flit_0; // @[Serdes.scala:37:7, :48:17] if (reset) // @[Serdes.scala:37:7] beat <= 2'h0; // @[Serdes.scala:49:21] else if (_T) // @[Decoupled.scala:51:35] beat <= _beat_T_3; // @[Serdes.scala:49:21, :60:16] always @(posedge) assign io_in_ready = io_in_ready_0; // @[Serdes.scala:37:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:37:7] assign io_out_bits_payload = io_out_bits_payload_0; // @[Serdes.scala:37:7] assign io_out_bits_head = io_out_bits_head_0; // @[Serdes.scala:37:7] assign io_out_bits_tail = io_out_bits_tail_0; // @[Serdes.scala:37:7] assign io_busy = io_busy_0; // @[Serdes.scala:37:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_489 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_233 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_489( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_233 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_49 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_99 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_100 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_212 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_212( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_85 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_24 = shr(io.in.a.bits.source, 2) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_374 = shr(io.in.a.bits.source, 2) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_686 = shr(io.in.a.bits.source, 2) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_783 = shr(io.in.a.bits.source, 2) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_171 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<2>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<2>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<2>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<2>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<2>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<2>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<2>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<2>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<2>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<2>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_172 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<2>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_173 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_174 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_85( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79] wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77] wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain : output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_3 : { sync : UInt<1>[2]}, int_in_clock_xing_out_2 : { sync : UInt<1>[2]}, int_in_clock_xing_out_1 : { sync : UInt<1>[2]}, int_in_clock_xing_out_0 : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} input tick : UInt<1> output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst clint of CLINT connect clint.clock, childClock connect clint.reset, childReset inst intsource of IntSyncCrossingSource_n1x2 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x2_1 connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsource_2 of IntSyncCrossingSource_n1x2_2 connect intsource_2.clock, childClock connect intsource_2.reset, childReset inst intsource_3 of IntSyncCrossingSource_n1x2_3 connect intsource_3.clock, childClock connect intsource_3.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[2]} invalidate intInClockXingOut_1.sync[0] invalidate intInClockXingOut_1.sync[1] wire intInClockXingIn_1 : { sync : UInt<1>[2]} invalidate intInClockXingIn_1.sync[0] invalidate intInClockXingIn_1.sync[1] connect intInClockXingOut_1, intInClockXingIn_1 wire intInClockXingOut_2 : { sync : UInt<1>[2]} invalidate intInClockXingOut_2.sync[0] invalidate intInClockXingOut_2.sync[1] wire intInClockXingIn_2 : { sync : UInt<1>[2]} invalidate intInClockXingIn_2.sync[0] invalidate intInClockXingIn_2.sync[1] connect intInClockXingOut_2, intInClockXingIn_2 wire intInClockXingOut_3 : { sync : UInt<1>[2]} invalidate intInClockXingOut_3.sync[0] invalidate intInClockXingOut_3.sync[1] wire intInClockXingIn_3 : { sync : UInt<1>[2]} invalidate intInClockXingIn_3.sync[0] invalidate intInClockXingIn_3.sync[1] connect intInClockXingOut_3, intInClockXingIn_3 connect intsource.auto.in[0], clint.auto.int_out_0[0] connect intsource.auto.in[1], clint.auto.int_out_0[1] connect intsource_1.auto.in[0], clint.auto.int_out_1[0] connect intsource_1.auto.in[1], clint.auto.int_out_1[1] connect intsource_2.auto.in[0], clint.auto.int_out_2[0] connect intsource_2.auto.in[1], clint.auto.int_out_2[1] connect intsource_3.auto.in[0], clint.auto.int_out_3[0] connect intsource_3.auto.in[1], clint.auto.int_out_3[1] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect intInClockXingIn_2, intsource_2.auto.out connect intInClockXingIn_3, intsource_3.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect auto.int_in_clock_xing_out_2, intInClockXingOut_2 connect auto.int_in_clock_xing_out_3, intInClockXingOut_3 connect clint.auto.in, auto.clint_in connect clint.io.rtcTick, tick connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_114 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_115 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_3_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_2_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input tick, // @[CLINT.scala:115:20] output clock, // @[ClockDomain.scala:21:19] output reset // @[ClockDomain.scala:22:19] ); wire _clint_auto_int_out_3_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_3_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_2_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_2_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_0_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_0_1; // @[CLINT.scala:112:48] wire auto_clint_in_a_valid_0 = auto_clint_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_a_bits_opcode_0 = auto_clint_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_a_bits_param_0 = auto_clint_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_a_bits_size_0 = auto_clint_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_clint_in_a_bits_source_0 = auto_clint_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_clint_in_a_bits_address_0 = auto_clint_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_clint_in_a_bits_mask_0 = auto_clint_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_clint_in_a_bits_data_0 = auto_clint_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_clint_in_a_bits_corrupt_0 = auto_clint_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_ready_0 = auto_clint_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire intInClockXingOut_3_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_3_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_2_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_1_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_3_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_3_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_2_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_2_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_1_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_1_0 = intInClockXingOut_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_1_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_1_0 = intInClockXingOut_1_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_1_sync_1 = intInClockXingIn_1_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_2_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_2_sync_0_0 = intInClockXingOut_2_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_2_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_2_sync_1_0 = intInClockXingOut_2_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_2_sync_1 = intInClockXingIn_2_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_3_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_3_sync_0_0 = intInClockXingOut_3_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_3_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_3_sync_1_0 = intInClockXingOut_3_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_3_sync_0 = intInClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_3_sync_1 = intInClockXingIn_3_sync_1; // @[MixedNode.scala:542:17, :551:17] CLINT clint ( // @[CLINT.scala:112:48] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_out_3_0 (_clint_auto_int_out_3_0), .auto_int_out_3_1 (_clint_auto_int_out_3_1), .auto_int_out_2_0 (_clint_auto_int_out_2_0), .auto_int_out_2_1 (_clint_auto_int_out_2_1), .auto_int_out_1_0 (_clint_auto_int_out_1_0), .auto_int_out_1_1 (_clint_auto_int_out_1_1), .auto_int_out_0_0 (_clint_auto_int_out_0_0), .auto_int_out_0_1 (_clint_auto_int_out_0_1), .auto_in_a_ready (auto_clint_in_a_ready_0), .auto_in_a_valid (auto_clint_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_clint_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_clint_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_clint_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_clint_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_clint_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_clint_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_clint_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_clint_in_d_valid_0), .auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_clint_in_d_bits_size_0), .auto_in_d_bits_source (auto_clint_in_d_bits_source_0), .auto_in_d_bits_data (auto_clint_in_d_bits_data_0), .io_rtcTick (tick) ); // @[CLINT.scala:112:48] IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_0_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_0_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_sync_0), .auto_out_sync_1 (intInClockXingIn_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_1 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_1_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_1_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_1_sync_0), .auto_out_sync_1 (intInClockXingIn_1_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_2 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_2_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_2_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_2_sync_0), .auto_out_sync_1 (intInClockXingIn_2_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_3 intsource_3 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_3_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_3_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_3_sync_0), .auto_out_sync_1 (intInClockXingIn_3_sync_1) ); // @[Crossing.scala:29:31] assign auto_clint_in_a_ready = auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_valid = auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_opcode = auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_size = auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_source = auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_data = auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_3_sync_0 = auto_int_in_clock_xing_out_3_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_3_sync_1 = auto_int_in_clock_xing_out_3_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_2_sync_0 = auto_int_in_clock_xing_out_2_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_2_sync_1 = auto_int_in_clock_xing_out_2_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_1 = auto_int_in_clock_xing_out_1_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_1 = auto_int_in_clock_xing_out_0_sync_1_0; // @[ClockDomain.scala:14:9] assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9] assign reset = clockNodeIn_reset; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_94 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_95 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SourceB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset remain : UInt<1>, clock, reset, UInt<1>(0h0) wire remain_set : UInt<1> connect remain_set, UInt<1>(0h0) wire remain_clr : UInt<1> connect remain_clr, UInt<1>(0h0) node _remain_T = or(remain, remain_set) node _remain_T_1 = not(remain_clr) node _remain_T_2 = and(_remain_T, _remain_T_1) connect remain, _remain_T_2 node busy = orr(remain) node todo = mux(busy, remain, io.req.bits.clients) node _next_T = bits(todo, 0, 0) node _next_T_1 = shl(_next_T, 1) node _next_T_2 = not(_next_T_1) node next = and(_next_T_2, todo) node _T = eq(io.req.valid, UInt<1>(0h0)) node _T_1 = neq(io.req.bits.clients, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect remain_set, io.req.bits.clients wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect io.b, b node _b_valid_T = or(busy, io.req.valid) connect b.valid, _b_valid_T node _T_7 = and(b.ready, b.valid) when _T_7 : connect remain_clr, next node _T_8 = eq(b.ready, UInt<1>(0h0)) node _T_9 = and(b.valid, _T_8) node _tag_T = eq(busy, UInt<1>(0h0)) node _tag_T_1 = and(io.req.ready, io.req.valid) reg tag_r : UInt<13>, clock when _tag_T_1 : connect tag_r, io.req.bits.tag node tag = mux(_tag_T, io.req.bits.tag, tag_r) node _set_T = eq(busy, UInt<1>(0h0)) node _set_T_1 = and(io.req.ready, io.req.valid) reg set_r : UInt<10>, clock when _set_T_1 : connect set_r, io.req.bits.set node set = mux(_set_T, io.req.bits.set, set_r) node _param_T = eq(busy, UInt<1>(0h0)) node _param_T_1 = and(io.req.ready, io.req.valid) reg param_r : UInt<3>, clock when _param_T_1 : connect param_r, io.req.bits.param node param = mux(_param_T, io.req.bits.param, param_r) connect b.bits.opcode, UInt<3>(0h6) connect b.bits.param, param connect b.bits.size, UInt<3>(0h6) node _b_bits_source_T = bits(next, 0, 0) connect b.bits.source, UInt<6>(0h21) node b_bits_address_base_y = or(tag, UInt<13>(0h0)) node _b_bits_address_base_T = shr(b_bits_address_base_y, 13) node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0)) node _b_bits_address_base_T_2 = asUInt(reset) node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0)) when _b_bits_address_base_T_3 : node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0)) when _b_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 12, 0) node b_bits_address_base_y_1 = or(set, UInt<10>(0h0)) node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10) node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0)) node _b_bits_address_base_T_8 = asUInt(reset) node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0)) when _b_bits_address_base_T_9 : node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0)) when _b_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1 assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1 node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0) node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6) node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0)) node _b_bits_address_base_T_14 = asUInt(reset) node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0)) when _b_bits_address_base_T_15 : node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0)) when _b_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2 assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2 node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0) node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11) node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17) node _b_bits_address_T = bits(b_bits_address_base, 0, 0) node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1) node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2) node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3) node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4) node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5) node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6) node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7) node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8) node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9) node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10) node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11) node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12) node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13) node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14) node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15) node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16) node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17) node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18) node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19) node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20) node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21) node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22) node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23) node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24) node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25) node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26) node _b_bits_address_T_27 = bits(b_bits_address_base, 27, 27) node _b_bits_address_T_28 = bits(b_bits_address_base, 28, 28) node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T) node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2) node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo) node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4) node b_bits_address_lo_lo_hi_hi = cat(_b_bits_address_T_7, _b_bits_address_T_6) node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo) node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo) node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_9, _b_bits_address_T_8) node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_11, _b_bits_address_T_10) node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo) node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_13, _b_bits_address_T_12) node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_15, _b_bits_address_T_14) node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo) node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo) node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo) node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_17, _b_bits_address_T_16) node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_19, _b_bits_address_T_18) node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo) node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_21, _b_bits_address_T_20) node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_23, _b_bits_address_T_22) node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo) node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo) node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_25, _b_bits_address_T_24) node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_27, _b_bits_address_T_26) node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo) node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_28, UInt<1>(0h0)) node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo) node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo) node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo) node _b_bits_address_T_29 = cat(b_bits_address_hi, b_bits_address_lo) connect b.bits.address, _b_bits_address_T_29 node _b_bits_mask_T = not(UInt<8>(0h0)) connect b.bits.mask, _b_bits_mask_T connect b.bits.data, UInt<1>(0h0) connect b.bits.corrupt, UInt<1>(0h0)	module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h21; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h21; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_mask = 8'hFF; // @[SourceB.scala:33:7] wire [7:0] b_bits_mask = 8'hFF; // @[SourceB.scala:65:17] wire [7:0] _b_bits_mask_T = 8'hFF; // @[SourceB.scala:81:23] wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7] wire [63:0] b_bits_data = 64'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_UInt2_4 : output auto : { out_3 : UInt<2>, out_2 : UInt<2>, out_1 : UInt<2>, out_0 : UInt<2>} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeOut : UInt<2> invalidate nodeOut wire x1_nodeOut : UInt<2> invalidate x1_nodeOut wire x1_nodeOut_1 : UInt<2> invalidate x1_nodeOut_1 wire x1_nodeOut_2 : UInt<2> invalidate x1_nodeOut_2 connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 node outputs_0 = or(UInt<2>(0h0), UInt<2>(0h0)) node outputs_1 = or(UInt<2>(0h0), UInt<2>(0h1)) node outputs_2 = or(UInt<2>(0h0), UInt<2>(0h2)) node outputs_3 = or(UInt<2>(0h0), UInt<2>(0h3)) connect nodeOut, outputs_0 connect x1_nodeOut, outputs_1 connect x1_nodeOut_1, outputs_2 connect x1_nodeOut_2, outputs_3	module BundleBridgeNexus_UInt2_4( // @[BundleBridgeNexus.scala:20:9] output [1:0] auto_out_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire [1:0] outputs_0 = 2'h0; // @[HasTiles.scala:78:32] wire [1:0] outputs_1 = 2'h1; // @[HasTiles.scala:78:32] wire [1:0] outputs_2 = 2'h2; // @[HasTiles.scala:78:32] wire [1:0] outputs_3 = 2'h3; // @[HasTiles.scala:78:32] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire [1:0] nodeOut; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_1; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_2; // @[MixedNode.scala:542:17] assign nodeOut = outputs_0; // @[HasTiles.scala:78:32] assign x1_nodeOut = outputs_1; // @[HasTiles.scala:78:32] assign x1_nodeOut_1 = outputs_2; // @[HasTiles.scala:78:32] assign x1_nodeOut_2 = outputs_3; // @[HasTiles.scala:78:32] assign auto_out_3 = x1_nodeOut_2; // @[MixedNode.scala:542:17] assign auto_out_2 = x1_nodeOut_1; // @[MixedNode.scala:542:17] assign auto_out_1 = x1_nodeOut; // @[MixedNode.scala:542:17] assign auto_out_0 = nodeOut; // @[MixedNode.scala:542:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<2>(0h3)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<2>(0h2)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 4) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<4>(0h9)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<2>(0h3)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<9>(0hc0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_17 = shr(io.in.a.bits.source, 4) node _T_18 = eq(_T_17, UInt<2>(0h2)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<9>(0hc0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_30 = shr(io.in.a.bits.source, 4) node _T_31 = eq(_T_30, UInt<1>(0h1)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<9>(0hc0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_43 = shr(io.in.a.bits.source, 4) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<9>(0hc0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_66 = shr(io.in.a.bits.source, 4) node _T_67 = eq(_T_66, UInt<2>(0h3)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_72 = shr(io.in.a.bits.source, 4) node _T_73 = eq(_T_72, UInt<2>(0h2)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_78 = shr(io.in.a.bits.source, 4) node _T_79 = eq(_T_78, UInt<1>(0h1)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_84 = shr(io.in.a.bits.source, 4) node _T_85 = eq(_T_84, UInt<1>(0h0)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = and(_T_95, _T_100) node _T_102 = or(UInt<1>(0h0), _T_101) node _T_103 = and(_T_94, _T_102) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_103, UInt<1>(0h1), "") : assert_2 node _T_107 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_108 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_109 = and(_T_107, _T_108) node _T_110 = or(UInt<1>(0h0), _T_109) node _T_111 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = and(_T_110, _T_115) node _T_117 = or(UInt<1>(0h0), _T_116) node _T_118 = and(UInt<1>(0h0), _T_117) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_118, UInt<1>(0h1), "") : assert_3 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(source_ok, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_125 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_125, UInt<1>(0h1), "") : assert_5 node _T_129 = asUInt(reset) node _T_130 = eq(_T_129, UInt<1>(0h0)) when _T_130 : node _T_131 = eq(is_aligned, UInt<1>(0h0)) when _T_131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_132 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_132, UInt<1>(0h1), "") : assert_7 node _T_136 = not(io.in.a.bits.mask) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_137, UInt<1>(0h1), "") : assert_8 node _T_141 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_141, UInt<1>(0h1), "") : assert_9 node _T_145 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_145 : node _T_146 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_147 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_149 = shr(io.in.a.bits.source, 4) node _T_150 = eq(_T_149, UInt<2>(0h3)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_8) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_155 = shr(io.in.a.bits.source, 4) node _T_156 = eq(_T_155, UInt<2>(0h2)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_9) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_161 = shr(io.in.a.bits.source, 4) node _T_162 = eq(_T_161, UInt<1>(0h1)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_10) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_166 = and(_T_164, _T_165) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_167 = shr(io.in.a.bits.source, 4) node _T_168 = eq(_T_167, UInt<1>(0h0)) node _T_169 = leq(UInt<1>(0h0), uncommonBits_11) node _T_170 = and(_T_168, _T_169) node _T_171 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_172 = and(_T_170, _T_171) node _T_173 = or(_T_154, _T_160) node _T_174 = or(_T_173, _T_166) node _T_175 = or(_T_174, _T_172) node _T_176 = and(_T_148, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_179 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<17>(0h10000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = and(_T_178, _T_183) node _T_185 = or(UInt<1>(0h0), _T_184) node _T_186 = and(_T_177, _T_185) node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_T_186, UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_186, UInt<1>(0h1), "") : assert_10 node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<17>(0h10000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = and(_T_193, _T_198) node _T_200 = or(UInt<1>(0h0), _T_199) node _T_201 = and(UInt<1>(0h0), _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_201, UInt<1>(0h1), "") : assert_11 node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(source_ok, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_208 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = asUInt(reset) node _T_210 = eq(_T_209, UInt<1>(0h0)) when _T_210 : node _T_211 = eq(_T_208, UInt<1>(0h0)) when _T_211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_208, UInt<1>(0h1), "") : assert_13 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(is_aligned, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_215 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_215, UInt<1>(0h1), "") : assert_15 node _T_219 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_219, UInt<1>(0h1), "") : assert_16 node _T_223 = not(io.in.a.bits.mask) node _T_224 = eq(_T_223, UInt<1>(0h0)) node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(_T_224, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_224, UInt<1>(0h1), "") : assert_17 node _T_228 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_228, UInt<1>(0h1), "") : assert_18 node _T_232 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_232 : node _T_233 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_234 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_236 = shr(io.in.a.bits.source, 4) node _T_237 = eq(_T_236, UInt<2>(0h3)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_242 = shr(io.in.a.bits.source, 4) node _T_243 = eq(_T_242, UInt<2>(0h2)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<4>(0h9)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_248 = shr(io.in.a.bits.source, 4) node _T_249 = eq(_T_248, UInt<1>(0h1)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<4>(0h9)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_254 = shr(io.in.a.bits.source, 4) node _T_255 = eq(_T_254, UInt<1>(0h0)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<4>(0h9)) node _T_259 = and(_T_257, _T_258) node _T_260 = or(_T_241, _T_247) node _T_261 = or(_T_260, _T_253) node _T_262 = or(_T_261, _T_259) node _T_263 = and(_T_235, _T_262) node _T_264 = or(UInt<1>(0h0), _T_263) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_264, UInt<1>(0h1), "") : assert_19 node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_270 = and(_T_268, _T_269) node _T_271 = or(UInt<1>(0h0), _T_270) node _T_272 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_278, UInt<1>(0h1), "") : assert_20 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_288 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_288, UInt<1>(0h1), "") : assert_23 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_292, UInt<1>(0h1), "") : assert_24 node _T_296 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_296, UInt<1>(0h1), "") : assert_25 node _T_300 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_300 : node _T_301 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_302 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_303 = and(_T_301, _T_302) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_304 = shr(io.in.a.bits.source, 4) node _T_305 = eq(_T_304, UInt<2>(0h3)) node _T_306 = leq(UInt<1>(0h0), uncommonBits_16) node _T_307 = and(_T_305, _T_306) node _T_308 = leq(uncommonBits_16, UInt<4>(0h9)) node _T_309 = and(_T_307, _T_308) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_310 = shr(io.in.a.bits.source, 4) node _T_311 = eq(_T_310, UInt<2>(0h2)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_17) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_17, UInt<4>(0h9)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 3, 0) node _T_316 = shr(io.in.a.bits.source, 4) node _T_317 = eq(_T_316, UInt<1>(0h1)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_18) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_18, UInt<4>(0h9)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 3, 0) node _T_322 = shr(io.in.a.bits.source, 4) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_19) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_19, UInt<4>(0h9)) node _T_327 = and(_T_325, _T_326) node _T_328 = or(_T_309, _T_315) node _T_329 = or(_T_328, _T_321) node _T_330 = or(_T_329, _T_327) node _T_331 = and(_T_303, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_334 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_335 = and(_T_333, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = and(_T_336, _T_341) node _T_343 = or(UInt<1>(0h0), _T_342) node _T_344 = and(_T_332, _T_343) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_344, UInt<1>(0h1), "") : assert_26 node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(source_ok, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(is_aligned, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_354 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_354, UInt<1>(0h1), "") : assert_29 node _T_358 = eq(io.in.a.bits.mask, mask) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_358, UInt<1>(0h1), "") : assert_30 node _T_362 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_362 : node _T_363 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_364 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 3, 0) node _T_366 = shr(io.in.a.bits.source, 4) node _T_367 = eq(_T_366, UInt<2>(0h3)) node _T_368 = leq(UInt<1>(0h0), uncommonBits_20) node _T_369 = and(_T_367, _T_368) node _T_370 = leq(uncommonBits_20, UInt<4>(0h9)) node _T_371 = and(_T_369, _T_370) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 3, 0) node _T_372 = shr(io.in.a.bits.source, 4) node _T_373 = eq(_T_372, UInt<2>(0h2)) node _T_374 = leq(UInt<1>(0h0), uncommonBits_21) node _T_375 = and(_T_373, _T_374) node _T_376 = leq(uncommonBits_21, UInt<4>(0h9)) node _T_377 = and(_T_375, _T_376) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_378 = shr(io.in.a.bits.source, 4) node _T_379 = eq(_T_378, UInt<1>(0h1)) node _T_380 = leq(UInt<1>(0h0), uncommonBits_22) node _T_381 = and(_T_379, _T_380) node _T_382 = leq(uncommonBits_22, UInt<4>(0h9)) node _T_383 = and(_T_381, _T_382) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_384 = shr(io.in.a.bits.source, 4) node _T_385 = eq(_T_384, UInt<1>(0h0)) node _T_386 = leq(UInt<1>(0h0), uncommonBits_23) node _T_387 = and(_T_385, _T_386) node _T_388 = leq(uncommonBits_23, UInt<4>(0h9)) node _T_389 = and(_T_387, _T_388) node _T_390 = or(_T_371, _T_377) node _T_391 = or(_T_390, _T_383) node _T_392 = or(_T_391, _T_389) node _T_393 = and(_T_365, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<17>(0h10000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = and(_T_398, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = and(_T_394, _T_405) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_406, UInt<1>(0h1), "") : assert_31 node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(source_ok, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(is_aligned, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_416 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_416, UInt<1>(0h1), "") : assert_34 node _T_420 = not(mask) node _T_421 = and(io.in.a.bits.mask, _T_420) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_422, UInt<1>(0h1), "") : assert_35 node _T_426 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_426 : node _T_427 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_428 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 3, 0) node _T_430 = shr(io.in.a.bits.source, 4) node _T_431 = eq(_T_430, UInt<2>(0h3)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_24) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_24, UInt<4>(0h9)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 3, 0) node _T_436 = shr(io.in.a.bits.source, 4) node _T_437 = eq(_T_436, UInt<2>(0h2)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_25) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_25, UInt<4>(0h9)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 3, 0) node _T_442 = shr(io.in.a.bits.source, 4) node _T_443 = eq(_T_442, UInt<1>(0h1)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_26) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_26, UInt<4>(0h9)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 3, 0) node _T_448 = shr(io.in.a.bits.source, 4) node _T_449 = eq(_T_448, UInt<1>(0h0)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_27) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_27, UInt<4>(0h9)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(_T_435, _T_441) node _T_455 = or(_T_454, _T_447) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_429, _T_456) node _T_458 = or(UInt<1>(0h0), _T_457) node _T_459 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<17>(0h10000))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = and(_T_459, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = and(_T_458, _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_467, UInt<1>(0h1), "") : assert_36 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(source_ok, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(is_aligned, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_477 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_477, UInt<1>(0h1), "") : assert_39 node _T_481 = eq(io.in.a.bits.mask, mask) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_481, UInt<1>(0h1), "") : assert_40 node _T_485 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_485 : node _T_486 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_487 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_489 = shr(io.in.a.bits.source, 4) node _T_490 = eq(_T_489, UInt<2>(0h3)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_28) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_28, UInt<4>(0h9)) node _T_494 = and(_T_492, _T_493) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_495 = shr(io.in.a.bits.source, 4) node _T_496 = eq(_T_495, UInt<2>(0h2)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_29) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_29, UInt<4>(0h9)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 3, 0) node _T_501 = shr(io.in.a.bits.source, 4) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_30) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_30, UInt<4>(0h9)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 3, 0) node _T_507 = shr(io.in.a.bits.source, 4) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_31) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_31, UInt<4>(0h9)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(_T_494, _T_500) node _T_514 = or(_T_513, _T_506) node _T_515 = or(_T_514, _T_512) node _T_516 = and(_T_488, _T_515) node _T_517 = or(UInt<1>(0h0), _T_516) node _T_518 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = or(UInt<1>(0h0), _T_524) node _T_526 = and(_T_517, _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_526, UInt<1>(0h1), "") : assert_41 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_536 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_536, UInt<1>(0h1), "") : assert_44 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_540, UInt<1>(0h1), "") : assert_45 node _T_544 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_544 : node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_547 = and(_T_545, _T_546) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 3, 0) node _T_548 = shr(io.in.a.bits.source, 4) node _T_549 = eq(_T_548, UInt<2>(0h3)) node _T_550 = leq(UInt<1>(0h0), uncommonBits_32) node _T_551 = and(_T_549, _T_550) node _T_552 = leq(uncommonBits_32, UInt<4>(0h9)) node _T_553 = and(_T_551, _T_552) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 3, 0) node _T_554 = shr(io.in.a.bits.source, 4) node _T_555 = eq(_T_554, UInt<2>(0h2)) node _T_556 = leq(UInt<1>(0h0), uncommonBits_33) node _T_557 = and(_T_555, _T_556) node _T_558 = leq(uncommonBits_33, UInt<4>(0h9)) node _T_559 = and(_T_557, _T_558) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_560 = shr(io.in.a.bits.source, 4) node _T_561 = eq(_T_560, UInt<1>(0h1)) node _T_562 = leq(UInt<1>(0h0), uncommonBits_34) node _T_563 = and(_T_561, _T_562) node _T_564 = leq(uncommonBits_34, UInt<4>(0h9)) node _T_565 = and(_T_563, _T_564) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_566 = shr(io.in.a.bits.source, 4) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = leq(UInt<1>(0h0), uncommonBits_35) node _T_569 = and(_T_567, _T_568) node _T_570 = leq(uncommonBits_35, UInt<4>(0h9)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(_T_553, _T_559) node _T_573 = or(_T_572, _T_565) node _T_574 = or(_T_573, _T_571) node _T_575 = and(_T_547, _T_574) node _T_576 = or(UInt<1>(0h0), _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_583) node _T_585 = and(_T_576, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_585, UInt<1>(0h1), "") : assert_46 node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(source_ok, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(is_aligned, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_595 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_595, UInt<1>(0h1), "") : assert_49 node _T_599 = eq(io.in.a.bits.mask, mask) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_599, UInt<1>(0h1), "") : assert_50 node _T_603 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_603, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_607 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_607, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 4) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<2>(0h3)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<4>(0h9)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 4) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<2>(0h2)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<4>(0h9)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 3, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 4) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<1>(0h1)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<4>(0h9)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 3, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 4) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<4>(0h9)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_611 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_611 : node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(source_ok_1, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_615 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(_T_615, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_615, UInt<1>(0h1), "") : assert_54 node _T_619 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_619, UInt<1>(0h1), "") : assert_55 node _T_623 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_623, UInt<1>(0h1), "") : assert_56 node _T_627 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_T_627, UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_627, UInt<1>(0h1), "") : assert_57 node _T_631 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_631 : node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok_1, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(sink_ok, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_638, UInt<1>(0h1), "") : assert_60 node _T_642 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_642, UInt<1>(0h1), "") : assert_61 node _T_646 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_646, UInt<1>(0h1), "") : assert_62 node _T_650 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_650, UInt<1>(0h1), "") : assert_63 node _T_654 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_655, UInt<1>(0h1), "") : assert_64 node _T_659 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_659 : node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(source_ok_1, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(sink_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_666 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_666, UInt<1>(0h1), "") : assert_67 node _T_670 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_670, UInt<1>(0h1), "") : assert_68 node _T_674 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_674, UInt<1>(0h1), "") : assert_69 node _T_678 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_679 = or(_T_678, io.in.d.bits.corrupt) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_679, UInt<1>(0h1), "") : assert_70 node _T_683 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_684, UInt<1>(0h1), "") : assert_71 node _T_688 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_688 : node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(source_ok_1, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_692 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_692, UInt<1>(0h1), "") : assert_73 node _T_696 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_696, UInt<1>(0h1), "") : assert_74 node _T_700 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_701 = or(UInt<1>(0h0), _T_700) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_701, UInt<1>(0h1), "") : assert_75 node _T_705 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_705 : node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(source_ok_1, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_709 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_709, UInt<1>(0h1), "") : assert_77 node _T_713 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_714 = or(_T_713, io.in.d.bits.corrupt) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_714, UInt<1>(0h1), "") : assert_78 node _T_718 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_719, UInt<1>(0h1), "") : assert_79 node _T_723 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(source_ok_1, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_727 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_727, UInt<1>(0h1), "") : assert_81 node _T_731 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_731, UInt<1>(0h1), "") : assert_82 node _T_735 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_736, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_740 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_740, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_744 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_744, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_748 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_748, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_752 = eq(a_first, UInt<1>(0h0)) node _T_753 = and(io.in.a.valid, _T_752) when _T_753 : node _T_754 = eq(io.in.a.bits.opcode, opcode) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_754, UInt<1>(0h1), "") : assert_87 node _T_758 = eq(io.in.a.bits.param, param) node _T_759 = asUInt(reset) node _T_760 = eq(_T_759, UInt<1>(0h0)) when _T_760 : node _T_761 = eq(_T_758, UInt<1>(0h0)) when _T_761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_758, UInt<1>(0h1), "") : assert_88 node _T_762 = eq(io.in.a.bits.size, size) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_762, UInt<1>(0h1), "") : assert_89 node _T_766 = eq(io.in.a.bits.source, source) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_766, UInt<1>(0h1), "") : assert_90 node _T_770 = eq(io.in.a.bits.address, address) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_770, UInt<1>(0h1), "") : assert_91 node _T_774 = and(io.in.a.ready, io.in.a.valid) node _T_775 = and(_T_774, a_first) when _T_775 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_776 = eq(d_first, UInt<1>(0h0)) node _T_777 = and(io.in.d.valid, _T_776) when _T_777 : node _T_778 = eq(io.in.d.bits.opcode, opcode_1) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_778, UInt<1>(0h1), "") : assert_92 node _T_782 = eq(io.in.d.bits.param, param_1) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_782, UInt<1>(0h1), "") : assert_93 node _T_786 = eq(io.in.d.bits.size, size_1) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_786, UInt<1>(0h1), "") : assert_94 node _T_790 = eq(io.in.d.bits.source, source_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_790, UInt<1>(0h1), "") : assert_95 node _T_794 = eq(io.in.d.bits.sink, sink) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_794, UInt<1>(0h1), "") : assert_96 node _T_798 = eq(io.in.d.bits.denied, denied) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_798, UInt<1>(0h1), "") : assert_97 node _T_802 = and(io.in.d.ready, io.in.d.valid) node _T_803 = and(_T_802, d_first) when _T_803 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<58>, clock, reset, UInt<58>(0h0) regreset inflight_opcodes : UInt<232>, clock, reset, UInt<232>(0h0) regreset inflight_sizes : UInt<232>, clock, reset, UInt<232>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<58> connect a_set, UInt<58>(0h0) wire a_set_wo_ready : UInt<58> connect a_set_wo_ready, UInt<58>(0h0) wire a_opcodes_set : UInt<232> connect a_opcodes_set, UInt<232>(0h0) wire a_sizes_set : UInt<232> connect a_sizes_set, UInt<232>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_804 = and(io.in.a.valid, a_first_1) node _T_805 = and(_T_804, UInt<1>(0h1)) when _T_805 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_806 = and(io.in.a.ready, io.in.a.valid) node _T_807 = and(_T_806, a_first_1) node _T_808 = and(_T_807, UInt<1>(0h1)) when _T_808 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_809 = dshr(inflight, io.in.a.bits.source) node _T_810 = bits(_T_809, 0, 0) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_811, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<58> connect d_clr, UInt<58>(0h0) wire d_clr_wo_ready : UInt<58> connect d_clr_wo_ready, UInt<58>(0h0) wire d_opcodes_clr : UInt<232> connect d_opcodes_clr, UInt<232>(0h0) wire d_sizes_clr : UInt<232> connect d_sizes_clr, UInt<232>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_815 = and(io.in.d.valid, d_first_1) node _T_816 = and(_T_815, UInt<1>(0h1)) node _T_817 = eq(d_release_ack, UInt<1>(0h0)) node _T_818 = and(_T_816, _T_817) when _T_818 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_819 = and(io.in.d.ready, io.in.d.valid) node _T_820 = and(_T_819, d_first_1) node _T_821 = and(_T_820, UInt<1>(0h1)) node _T_822 = eq(d_release_ack, UInt<1>(0h0)) node _T_823 = and(_T_821, _T_822) when _T_823 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_824 = and(io.in.d.valid, d_first_1) node _T_825 = and(_T_824, UInt<1>(0h1)) node _T_826 = eq(d_release_ack, UInt<1>(0h0)) node _T_827 = and(_T_825, _T_826) when _T_827 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_828 = dshr(inflight, io.in.d.bits.source) node _T_829 = bits(_T_828, 0, 0) node _T_830 = or(_T_829, same_cycle_resp) node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_T_830, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_830, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_834 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_835 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_836 = or(_T_834, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_836, UInt<1>(0h1), "") : assert_100 node _T_840 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_840, UInt<1>(0h1), "") : assert_101 else : node _T_844 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_845 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_846 = or(_T_844, _T_845) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_846, UInt<1>(0h1), "") : assert_102 node _T_850 = eq(io.in.d.bits.size, a_size_lookup) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_850, UInt<1>(0h1), "") : assert_103 node _T_854 = and(io.in.d.valid, d_first_1) node _T_855 = and(_T_854, a_first_1) node _T_856 = and(_T_855, io.in.a.valid) node _T_857 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(d_release_ack, UInt<1>(0h0)) node _T_860 = and(_T_858, _T_859) when _T_860 : node _T_861 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_862 = or(_T_861, io.in.a.ready) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_862, UInt<1>(0h1), "") : assert_104 node _T_866 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_867 = orr(a_set_wo_ready) node _T_868 = eq(_T_867, UInt<1>(0h0)) node _T_869 = or(_T_866, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_869, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_106 node _T_873 = orr(inflight) node _T_874 = eq(_T_873, UInt<1>(0h0)) node _T_875 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_876 = or(_T_874, _T_875) node _T_877 = lt(watchdog, plusarg_reader.out) node _T_878 = or(_T_876, _T_877) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_878, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_882 = and(io.in.a.ready, io.in.a.valid) node _T_883 = and(io.in.d.ready, io.in.d.valid) node _T_884 = or(_T_882, _T_883) when _T_884 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<58>, clock, reset, UInt<58>(0h0) regreset inflight_opcodes_1 : UInt<232>, clock, reset, UInt<232>(0h0) regreset inflight_sizes_1 : UInt<232>, clock, reset, UInt<232>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<58> connect c_set, UInt<58>(0h0) wire c_set_wo_ready : UInt<58> connect c_set_wo_ready, UInt<58>(0h0) wire c_opcodes_set : UInt<232> connect c_opcodes_set, UInt<232>(0h0) wire c_sizes_set : UInt<232> connect c_sizes_set, UInt<232>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_885 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_886 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_887 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_888 = and(_T_886, _T_887) node _T_889 = and(_T_885, _T_888) when _T_889 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_890 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_891 = and(_T_890, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_892 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_893 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_894 = and(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) when _T_895 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_896 = dshr(inflight_1, _WIRE_15.bits.source) node _T_897 = bits(_T_896, 0, 0) node _T_898 = eq(_T_897, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_898, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<58> connect d_clr_1, UInt<58>(0h0) wire d_clr_wo_ready_1 : UInt<58> connect d_clr_wo_ready_1, UInt<58>(0h0) wire d_opcodes_clr_1 : UInt<232> connect d_opcodes_clr_1, UInt<232>(0h0) wire d_sizes_clr_1 : UInt<232> connect d_sizes_clr_1, UInt<232>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_902 = and(io.in.d.valid, d_first_2) node _T_903 = and(_T_902, UInt<1>(0h1)) node _T_904 = and(_T_903, d_release_ack_1) when _T_904 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_905 = and(io.in.d.ready, io.in.d.valid) node _T_906 = and(_T_905, d_first_2) node _T_907 = and(_T_906, UInt<1>(0h1)) node _T_908 = and(_T_907, d_release_ack_1) when _T_908 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_909 = and(io.in.d.valid, d_first_2) node _T_910 = and(_T_909, UInt<1>(0h1)) node _T_911 = and(_T_910, d_release_ack_1) when _T_911 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_912 = dshr(inflight_1, io.in.d.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = or(_T_913, same_cycle_resp_1) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_914, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_918 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_918, UInt<1>(0h1), "") : assert_109 else : node _T_922 = eq(io.in.d.bits.size, c_size_lookup) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_922, UInt<1>(0h1), "") : assert_110 node _T_926 = and(io.in.d.valid, d_first_2) node _T_927 = and(_T_926, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_928 = and(_T_927, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_929 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_930 = and(_T_928, _T_929) node _T_931 = and(_T_930, d_release_ack_1) node _T_932 = eq(c_probe_ack, UInt<1>(0h0)) node _T_933 = and(_T_931, _T_932) when _T_933 : node _T_934 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_935 = or(_T_934, _WIRE_23.ready) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_935, UInt<1>(0h1), "") : assert_111 node _T_939 = orr(c_set_wo_ready) when _T_939 : node _T_940 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_940, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_107 node _T_944 = orr(inflight_1) node _T_945 = eq(_T_944, UInt<1>(0h0)) node _T_946 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_947 = or(_T_945, _T_946) node _T_948 = lt(watchdog_1, plusarg_reader_1.out) node _T_949 = or(_T_947, _T_948) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_949, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_953 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_954 = and(io.in.d.ready, io.in.d.valid) node _T_955 = or(_T_953, _T_954) when _T_955 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [57:0] inflight; // @[Monitor.scala:614:27] reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [231:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [57:0] inflight_1; // @[Monitor.scala:726:35] reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PTW : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[3], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) wire l2_refill_wire : UInt<1> inst arb of Arbiter3_Valid_PTWReq connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req connect arb.io.in[1], io.requestor[1].req connect arb.io.in[2], io.requestor[2].req node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) connect arb.io.out.ready, _arb_io_out_ready_T_2 wire _resp_valid_WIRE : UInt<1>[3] connect _resp_valid_WIRE[0], UInt<1>(0h0) connect _resp_valid_WIRE[1], UInt<1>(0h0) connect _resp_valid_WIRE[2], UInt<1>(0h0) reg resp_valid : UInt<1>[3], clock connect resp_valid, _resp_valid_WIRE node _clock_en_T = neq(state, UInt<3>(0h0)) node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[2].value, 0, 0) node clock_en = or(_clock_en_T_3, _clock_en_T_4) node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en) connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T reg invalidated : UInt<1>, clock reg count : UInt<2>, clock reg resp_ae_ptw : UInt<1>, clock reg resp_ae_final : UInt<1>, clock reg resp_pf : UInt<1>, clock reg resp_gf : UInt<1>, clock reg resp_hr : UInt<1>, clock reg resp_hw : UInt<1>, clock reg resp_hx : UInt<1>, clock reg resp_fragmented_superpage : UInt<1>, clock reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock reg r_req_dest : UInt, clock reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg aux_count : UInt<2>, clock reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg gpa_pgoff : UInt<12>, clock reg stage2 : UInt<1>, clock reg stage2_final : UInt<1>, clock node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0)) node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1) node do_both_stages = and(r_req.vstage1, r_req.stage2) node _max_count_T = lt(count, aux_count) node max_count = mux(_max_count_T, aux_count, count) node _vpn_T = and(r_req.vstage1, stage2) node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) reg mem_resp_valid : UInt<1>, clock connect mem_resp_valid, io.mem.resp.valid reg mem_resp_data : UInt, clock connect mem_resp_data, io.mem.resp.bits.data wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} wire _tmp_WIRE : UInt<64> connect _tmp_WIRE, mem_resp_data node _tmp_T = bits(_tmp_WIRE, 0, 0) connect tmp.v, _tmp_T node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) connect tmp.r, _tmp_T_1 node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) connect tmp.w, _tmp_T_2 node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) connect tmp.x, _tmp_T_3 node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) connect tmp.u, _tmp_T_4 node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) connect tmp.g, _tmp_T_5 node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) connect tmp.a, _tmp_T_6 node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) connect tmp.d, _tmp_T_7 node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) connect tmp.reserved_for_software, _tmp_T_8 node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) connect tmp.ppn, _tmp_T_9 node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) connect tmp.reserved_for_future, _tmp_T_10 wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect pte, tmp node _res_ppn_T = eq(stage2, UInt<1>(0h0)) node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) node _res_ppn_T_2 = bits(tmp.ppn, 26, 0) node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) connect pte.ppn, _res_ppn_T_4 node _T = or(tmp.r, tmp.w) node _T_1 = or(_T, tmp.x) when _T_1 : node _T_2 = leq(count, UInt<1>(0h0)) node _T_3 = bits(tmp.ppn, 17, 9) node _T_4 = neq(_T_3, UInt<1>(0h0)) node _T_5 = and(_T_2, _T_4) when _T_5 : connect pte.v, UInt<1>(0h0) node _T_6 = leq(count, UInt<1>(0h1)) node _T_7 = bits(tmp.ppn, 8, 0) node _T_8 = neq(_T_7, UInt<1>(0h0)) node _T_9 = and(_T_6, _T_8) when _T_9 : connect pte.v, UInt<1>(0h0) node _T_10 = eq(stage2, UInt<1>(0h0)) node _T_11 = and(do_both_stages, _T_10) node _T_12 = shr(tmp.ppn, 27) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = shr(tmp.ppn, 20) node _T_15 = neq(_T_14, UInt<1>(0h0)) node invalid_paddr = mux(_T_11, _T_13, _T_15) node _T_16 = eq(stage2, UInt<1>(0h0)) node _T_17 = and(do_both_stages, _T_16) node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = sub(_count_T_1, UInt<1>(0h0)) node count_1 = tail(_count_T_2, 1) node idxs_0 = shr(tmp.ppn, 29) wire _WIRE : UInt<15>[1] connect _WIRE[0], idxs_0 node _T_18 = or(count_1, UInt<0>(0h0)) node _T_19 = neq(_WIRE[0], UInt<1>(0h0)) node invalid_gpa = and(_T_17, _T_19) node _traverse_T = eq(pte.r, UInt<1>(0h0)) node _traverse_T_1 = and(pte.v, _traverse_T) node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) node _traverse_T_18 = lt(count, UInt<2>(0h2)) node traverse = and(_traverse_T_17, _traverse_T_18) node _pte_addr_vpn_idxs_T = shr(vpn, 18) node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0) node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9) node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0) node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0) node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0) node _pte_addr_mask_T = eq(count, r_hgatp_initial_count) node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T) node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff)) node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1)) node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0) node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2)) node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1) node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3)) node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3) node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask) node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9) node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx) node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3) node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0) reg pte_hit : UInt<1>, clock connect pte_hit, UInt<1>(0h0) connect io.dpath.perf.pte_miss, UInt<1>(0h0) node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 node _T_20 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) node _T_21 = and(io.dpath.perf.l2hit, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)),\n") : printf assert(clock, _T_22, UInt<1>(0h1), "") : assert reg l2_refill : UInt<1>, clock connect l2_refill, UInt<1>(0h0) connect l2_refill_wire, l2_refill connect io.dpath.perf.l2miss, UInt<1>(0h0) connect io.dpath.perf.l2hit, UInt<1>(0h0) reg state_reg : UInt<0>, clock reg state_vec : UInt<0>[512], clock smem l2_tlb_ram : UInt<45>[1] [512] reg g : UInt<512>[1], clock wire _valid_WIRE : UInt<512>[1] connect _valid_WIRE[0], UInt<512>(0h0) regreset valid : UInt<512>[1], clock, reset, _valid_WIRE node _T_26 = bits(r_req.addr, 26, 0) node _T_27 = cat(r_req.vstage1, _T_26) node r_tag = bits(_T_27, 27, 9) node r_idx = bits(_T_27, 8, 0) node _r_valid_vec_T = dshr(valid[0], r_idx) node r_valid_vec = bits(_r_valid_vec_T, 0, 0) reg r_valid_vec_q : UInt<1>, clock reg r_l2_plru_way : UInt<0>, clock connect r_valid_vec_q, r_valid_vec connect r_l2_plru_way, UInt<1>(0h0) node _T_28 = eq(invalidated, UInt<1>(0h0)) node _T_29 = and(l2_refill, _T_28) when _T_29 : wire entry : { tag : UInt<18>, ppn : UInt<20>, d : UInt<1>, a : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} connect entry.ppn, r_pte.ppn connect entry.d, r_pte.d connect entry.a, r_pte.a connect entry.u, r_pte.u connect entry.x, r_pte.x connect entry.w, r_pte.w connect entry.r, r_pte.r connect entry.tag, r_tag node lo_lo = cat(entry.w, entry.r) node lo_hi = cat(entry.u, entry.x) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(entry.d, entry.a) node hi_hi = cat(entry.tag, entry.ppn) node hi = cat(hi_hi, hi_lo) node _T_30 = cat(hi, lo) node _T_31 = xorr(_T_30) node _T_32 = xor(_T_31, UInt<1>(0h0)) node _T_33 = cat(_T_32, _T_30) wire _WIRE_1 : UInt<45>[1] connect _WIRE_1[0], _T_33 write mport MPORT = l2_tlb_ram[r_idx], clock when UInt<1>(0h1) : connect MPORT[0], _WIRE_1[0] node mask = dshl(UInt<1>(0h1), r_idx) when UInt<1>(0h1) : node _valid_0_T = or(valid[0], mask) connect valid[0], _valid_0_T node _g_0_T = or(g[0], mask) node _g_0_T_1 = not(mask) node _g_0_T_2 = and(g[0], _g_0_T_1) node _g_0_T_3 = mux(r_pte.g, _g_0_T, _g_0_T_2) connect g[0], _g_0_T_3 when io.dpath.sfence.valid : node hg = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _valid_0_T_1 = eq(hg, UInt<1>(0h0)) node _valid_0_T_2 = and(_valid_0_T_1, io.dpath.sfence.bits.rs1) node _valid_0_T_3 = bits(io.dpath.sfence.bits.addr, 20, 12) node _valid_0_T_4 = dshl(UInt<1>(0h1), _valid_0_T_3) node _valid_0_T_5 = not(_valid_0_T_4) node _valid_0_T_6 = and(valid[0], _valid_0_T_5) node _valid_0_T_7 = eq(hg, UInt<1>(0h0)) node _valid_0_T_8 = and(_valid_0_T_7, io.dpath.sfence.bits.rs2) node _valid_0_T_9 = and(valid[0], g[0]) node _valid_0_T_10 = mux(_valid_0_T_8, _valid_0_T_9, UInt<1>(0h0)) node _valid_0_T_11 = mux(_valid_0_T_2, _valid_0_T_6, _valid_0_T_10) connect valid[0], _valid_0_T_11 node _s0_valid_T = eq(l2_refill, UInt<1>(0h0)) node _s0_valid_T_1 = and(arb.io.out.ready, arb.io.out.valid) node s0_valid = and(_s0_valid_T, _s0_valid_T_1) node _s0_suitable_T = eq(arb.io.out.bits.bits.vstage1, arb.io.out.bits.bits.stage2) node _s0_suitable_T_1 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node s0_suitable = and(_s0_suitable_T, _s0_suitable_T_1) node _s1_valid_T = and(s0_valid, s0_suitable) node _s1_valid_T_1 = and(_s1_valid_T, arb.io.out.bits.valid) reg s1_valid : UInt<1>, clock connect s1_valid, _s1_valid_T_1 reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid node _s1_rdata_T = bits(arb.io.out.bits.bits.addr, 8, 0) wire _s1_rdata_WIRE : UInt<9> invalidate _s1_rdata_WIRE when s0_valid : connect _s1_rdata_WIRE, _s1_rdata_T read mport s1_rdata = l2_tlb_ram[_s1_rdata_WIRE], clock reg r : UInt<45>, clock when s1_valid : connect r, s1_rdata[0] node uncorrected = bits(r, 43, 0) node uncorrectable = xorr(r) reg s2_valid_vec : UInt<1>, clock when s1_valid : connect s2_valid_vec, r_valid_vec node _s2_g_vec_T = dshr(g[0], r_idx) node _s2_g_vec_T_1 = bits(_s2_g_vec_T, 0, 0) wire _s2_g_vec_WIRE : UInt<1>[1] connect _s2_g_vec_WIRE[0], _s2_g_vec_T_1 reg s2_g_vec : UInt<1>[1], clock when s1_valid : connect s2_g_vec, _s2_g_vec_WIRE node _s2_error_T = bits(s2_valid_vec, 0, 0) node _s2_error_T_1 = or(UInt<1>(0h0), uncorrectable) node l2_error = and(_s2_error_T, _s2_error_T_1) node _T_34 = and(s2_valid, l2_error) when _T_34 : connect valid[0], UInt<1>(0h0) wire s2_entry_vec_0 : { tag : UInt<18>, ppn : UInt<20>, d : UInt<1>, a : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _s2_entry_vec_WIRE : UInt<44> connect _s2_entry_vec_WIRE, uncorrected node _s2_entry_vec_T = bits(_s2_entry_vec_WIRE, 0, 0) connect s2_entry_vec_0.r, _s2_entry_vec_T node _s2_entry_vec_T_1 = bits(_s2_entry_vec_WIRE, 1, 1) connect s2_entry_vec_0.w, _s2_entry_vec_T_1 node _s2_entry_vec_T_2 = bits(_s2_entry_vec_WIRE, 2, 2) connect s2_entry_vec_0.x, _s2_entry_vec_T_2 node _s2_entry_vec_T_3 = bits(_s2_entry_vec_WIRE, 3, 3) connect s2_entry_vec_0.u, _s2_entry_vec_T_3 node _s2_entry_vec_T_4 = bits(_s2_entry_vec_WIRE, 4, 4) connect s2_entry_vec_0.a, _s2_entry_vec_T_4 node _s2_entry_vec_T_5 = bits(_s2_entry_vec_WIRE, 5, 5) connect s2_entry_vec_0.d, _s2_entry_vec_T_5 node _s2_entry_vec_T_6 = bits(_s2_entry_vec_WIRE, 25, 6) connect s2_entry_vec_0.ppn, _s2_entry_vec_T_6 node _s2_entry_vec_T_7 = bits(_s2_entry_vec_WIRE, 43, 26) connect s2_entry_vec_0.tag, _s2_entry_vec_T_7 node _s2_hit_vec_T = bits(s2_valid_vec, 0, 0) node _s2_hit_vec_T_1 = eq(r_tag, s2_entry_vec_0.tag) node s2_hit_vec_0 = and(_s2_hit_vec_T, _s2_hit_vec_T_1) node l2_hit = and(s2_valid, s2_hit_vec_0) node _io_dpath_perf_l2miss_T = eq(s2_hit_vec_0, UInt<1>(0h0)) node _io_dpath_perf_l2miss_T_1 = and(s2_valid, _io_dpath_perf_l2miss_T) connect io.dpath.perf.l2miss, _io_dpath_perf_l2miss_T_1 connect io.dpath.perf.l2hit, l2_hit when l2_hit : connect state_vec[r_idx], UInt<1>(0h0) node _T_35 = eq(s2_hit_vec_0, UInt<1>(0h1)) node _T_36 = or(_T_35, l2_error) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed: L2 TLB multi-hit\n at PTW.scala:486 assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, \"L2 TLB multi-hit\")\n") : printf_1 assert(clock, _T_36, UInt<1>(0h1), "") : assert_1 wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect l2_pte.ppn, s2_entry_vec_0.ppn connect l2_pte.d, s2_entry_vec_0.d connect l2_pte.a, s2_entry_vec_0.a connect l2_pte.g, s2_g_vec[0] connect l2_pte.u, s2_entry_vec_0.u connect l2_pte.x, s2_entry_vec_0.x connect l2_pte.w, s2_entry_vec_0.w connect l2_pte.r, s2_entry_vec_0.r connect l2_pte.v, UInt<1>(0h1) connect l2_pte.reserved_for_future, UInt<1>(0h0) connect l2_pte.reserved_for_software, UInt<1>(0h0) node _T_40 = and(l2_hit, s2_hit_vec_0) node _invalidated_T = neq(state, UInt<3>(0h0)) node _invalidated_T_1 = and(invalidated, _invalidated_T) node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) connect invalidated, _invalidated_T_2 connect io.mem.keep_clock_enabled, UInt<1>(0h0) node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) connect io.mem.req.valid, _io_mem_req_valid_T_2 connect io.mem.req.bits.phys, UInt<1>(0h1) connect io.mem.req.bits.cmd, UInt<1>(0h0) connect io.mem.req.bits.size, UInt<2>(0h3) connect io.mem.req.bits.signed, UInt<1>(0h0) connect io.mem.req.bits.addr, pte_addr connect io.mem.req.bits.dprv, UInt<1>(0h1) node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 invalidate io.mem.req.bits.tag connect io.mem.req.bits.no_resp, UInt<1>(0h0) invalidate io.mem.req.bits.no_alloc invalidate io.mem.req.bits.no_xcpt invalidate io.mem.req.bits.data invalidate io.mem.req.bits.mask node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) node _io_mem_s1_kill_T_1 = or(l2_hit, _io_mem_s1_kill_T) node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) connect io.mem.s1_kill, _io_mem_s1_kill_T_2 invalidate io.mem.s1_data.mask invalidate io.mem.s1_data.data connect io.mem.s2_kill, UInt<1>(0h0) node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8) node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10) node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13) node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15) node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12) node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17) node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21) node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23) node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25) node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32) node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38) node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000))) node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40) node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43) node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45) node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48) node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50) node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000)) node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53) node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000))) node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55) node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000)) node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58) node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60) node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000)) node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63) node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65) node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68) node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70) node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73) node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75) node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000)) node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78) node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80) node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83) node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85) node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42) node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47) node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52) node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57) node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62) node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67) node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72) node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77) node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82) node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87) node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98) node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100) node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102) node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105) node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107) node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110) node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112) node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115) node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117) node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120) node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122) node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125) node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000))) node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127) node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109) node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114) node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119) node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124) node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129) node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135) node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000))) node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137) node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140) node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142) node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139) node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144) node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147) node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149) node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151) node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154) node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156) node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158) node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0)) node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0)) node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3) node _pmpHomogeneous_T = shl(r_pte.ppn, 12) wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T) node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4) node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6) node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2) node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3)) node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4) node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5) node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30) node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0)) node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9) node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3)) node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11) node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12) node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21) node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0)) node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16) node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3)) node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18) node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19) node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12) node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0)) node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8) node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24) node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26) node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28) node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0) node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T) node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2) node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3) node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T) node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2) node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3) node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1) node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3) node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1) node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3) node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5) node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1) node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3) node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5) node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper) node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper) node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33) node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34) node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35) node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36) node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8) node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12) node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14) node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39) node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3)) node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41) node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42) node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30) node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0)) node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46) node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3)) node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48) node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49) node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21) node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0)) node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53) node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3)) node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55) node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56) node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12) node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0)) node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45) node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61) node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63) node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65) node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0) node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5) node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7) node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8) node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5) node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7) node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8) node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6) node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8) node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7) node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9) node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11) node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7) node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9) node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11) node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1) node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1) node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70) node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71) node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72) node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73) node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16) node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20) node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22) node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76) node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3)) node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78) node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79) node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30) node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0)) node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83) node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3)) node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85) node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86) node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21) node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0)) node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90) node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3)) node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92) node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93) node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12) node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0)) node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82) node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98) node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100) node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102) node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0) node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10) node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12) node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13) node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10) node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12) node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13) node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11) node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13) node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13) node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15) node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17) node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13) node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15) node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17) node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2) node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2) node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107) node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108) node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109) node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110) node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24) node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28) node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30) node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113) node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3)) node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115) node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116) node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30) node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0)) node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120) node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3)) node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122) node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123) node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21) node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0)) node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127) node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3)) node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129) node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130) node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12) node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0)) node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119) node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135) node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137) node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139) node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0) node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15) node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17) node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18) node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15) node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17) node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18) node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16) node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18) node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19) node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21) node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23) node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19) node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21) node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23) node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3) node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3) node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144) node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145) node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146) node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147) node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32) node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36) node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38) node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150) node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3)) node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152) node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153) node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30) node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0)) node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157) node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3)) node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159) node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160) node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21) node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0)) node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164) node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3)) node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166) node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167) node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12) node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0)) node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156) node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172) node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174) node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176) node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0) node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20) node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22) node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23) node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20) node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22) node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23) node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21) node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23) node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25) node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27) node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29) node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25) node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27) node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29) node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4) node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4) node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181) node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182) node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183) node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184) node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40) node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44) node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46) node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187) node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3)) node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189) node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190) node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30) node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0)) node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194) node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3)) node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196) node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197) node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21) node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0)) node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201) node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3)) node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203) node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204) node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12) node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0)) node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193) node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209) node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211) node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213) node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0) node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25) node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27) node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28) node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25) node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27) node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28) node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26) node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28) node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31) node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33) node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35) node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31) node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33) node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35) node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5) node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5) node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218) node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219) node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220) node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221) node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48) node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52) node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54) node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224) node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3)) node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226) node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227) node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30) node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0)) node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231) node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3)) node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233) node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234) node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21) node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0)) node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238) node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3)) node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240) node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241) node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12) node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0)) node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230) node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246) node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248) node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250) node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0) node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30) node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32) node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33) node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30) node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32) node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33) node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31) node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33) node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37) node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39) node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41) node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37) node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39) node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41) node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6) node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6) node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255) node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256) node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257) node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258) node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56) node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60) node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62) node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261) node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3)) node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263) node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264) node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30) node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0)) node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268) node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3)) node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270) node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271) node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21) node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0)) node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275) node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3)) node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277) node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278) node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12) node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0)) node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267) node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283) node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285) node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287) node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0) node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35) node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37) node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38) node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35) node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37) node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38) node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36) node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38) node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43) node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45) node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47) node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43) node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45) node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47) node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7) node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7) node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292) node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293) node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294) node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295) node homogeneous = and(pmaHomogeneous, pmpHomogeneous) connect io.requestor[0].resp.valid, resp_valid[0] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[0].resp.bits.ae_final, resp_ae_final connect io.requestor[0].resp.bits.pf, resp_pf connect io.requestor[0].resp.bits.gf, resp_gf connect io.requestor[0].resp.bits.hr, resp_hr connect io.requestor[0].resp.bits.hw, resp_hw connect io.requestor[0].resp.bits.hx, resp_hx connect io.requestor[0].resp.bits.pte, r_pte connect io.requestor[0].resp.bits.level, max_count node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3) node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6) node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9) node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7) node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12) node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14 node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T connect io.requestor[0].ptbr, io.dpath.ptbr connect io.requestor[0].hgatp, io.dpath.hgatp connect io.requestor[0].vsatp, io.dpath.vsatp connect io.requestor[0].customCSRs, io.dpath.customCSRs connect io.requestor[0].status, io.dpath.status connect io.requestor[0].hstatus, io.dpath.hstatus connect io.requestor[0].gstatus, io.dpath.gstatus connect io.requestor[0].pmp, io.dpath.pmp connect io.requestor[1].resp.valid, resp_valid[1] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[1].resp.bits.ae_final, resp_ae_final connect io.requestor[1].resp.bits.pf, resp_pf connect io.requestor[1].resp.bits.gf, resp_gf connect io.requestor[1].resp.bits.hr, resp_hr connect io.requestor[1].resp.bits.hw, resp_hw connect io.requestor[1].resp.bits.hx, resp_hx connect io.requestor[1].resp.bits.pte, r_pte connect io.requestor[1].resp.bits.level, max_count node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3) node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6) node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9) node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7) node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12) node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14 node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T connect io.requestor[1].ptbr, io.dpath.ptbr connect io.requestor[1].hgatp, io.dpath.hgatp connect io.requestor[1].vsatp, io.dpath.vsatp connect io.requestor[1].customCSRs, io.dpath.customCSRs connect io.requestor[1].status, io.dpath.status connect io.requestor[1].hstatus, io.dpath.hstatus connect io.requestor[1].gstatus, io.dpath.gstatus connect io.requestor[1].pmp, io.dpath.pmp connect io.requestor[2].resp.valid, resp_valid[2] connect io.requestor[2].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[2].resp.bits.ae_final, resp_ae_final connect io.requestor[2].resp.bits.pf, resp_pf connect io.requestor[2].resp.bits.gf, resp_gf connect io.requestor[2].resp.bits.hr, resp_hr connect io.requestor[2].resp.bits.hw, resp_hw connect io.requestor[2].resp.bits.hx, resp_hx connect io.requestor[2].resp.bits.pte, r_pte connect io.requestor[2].resp.bits.level, max_count node _io_requestor_2_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[2].resp.bits.homogeneous, _io_requestor_2_resp_bits_homogeneous_T node _io_requestor_2_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[2].resp.bits.fragmented_superpage, _io_requestor_2_resp_bits_fragmented_superpage_T connect io.requestor[2].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_2_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_2_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_2_resp_bits_gpa_bits_T_2 = or(_io_requestor_2_resp_bits_gpa_bits_T, _io_requestor_2_resp_bits_gpa_bits_T_1) node _io_requestor_2_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_2_resp_bits_gpa_bits_T_4 = or(_io_requestor_2_resp_bits_gpa_bits_T_2, _io_requestor_2_resp_bits_gpa_bits_T_3) node _io_requestor_2_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_2_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_2_resp_bits_gpa_bits_T_7 = cat(_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6) node _io_requestor_2_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_2_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_2_resp_bits_gpa_bits_T_10 = cat(_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9) node _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_2_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_2_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_2_resp_bits_gpa_bits_T_11 = eq(io_requestor_2_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_2_resp_bits_gpa_bits_T_12 = mux(_io_requestor_2_resp_bits_gpa_bits_T_11, _io_requestor_2_resp_bits_gpa_bits_T_10, _io_requestor_2_resp_bits_gpa_bits_T_7) node _io_requestor_2_resp_bits_gpa_bits_T_13 = mux(_io_requestor_2_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_2_resp_bits_gpa_bits_T_12) node _io_requestor_2_resp_bits_gpa_bits_T_14 = cat(_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[2].resp.bits.gpa.bits, _io_requestor_2_resp_bits_gpa_bits_T_14 node _io_requestor_2_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[2].resp.bits.gpa_is_pte, _io_requestor_2_resp_bits_gpa_is_pte_T connect io.requestor[2].ptbr, io.dpath.ptbr connect io.requestor[2].hgatp, io.dpath.hgatp connect io.requestor[2].vsatp, io.dpath.vsatp connect io.requestor[2].customCSRs, io.dpath.customCSRs connect io.requestor[2].status, io.dpath.status connect io.requestor[2].hstatus, io.dpath.hstatus connect io.requestor[2].gstatus, io.dpath.gstatus connect io.requestor[2].pmp, io.dpath.pmp wire next_state : UInt connect next_state, state inst state_barrier of OptimizationBarrier_UInt connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state connect state, state_barrier.io.y wire do_switch : UInt<1> connect do_switch, UInt<1>(0h0) node _T_41 = eq(UInt<3>(0h0), state) when _T_41 : node _T_42 = and(arb.io.out.ready, arb.io.out.valid) when _T_42 : node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0)) node satp_initial_count = tail(_satp_initial_count_T_2, 1) node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0)) node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1) node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0)) node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1) node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) connect r_req, arb.io.out.bits.bits connect r_req_dest, arb.io.chosen node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) connect next_state, _next_state_T connect stage2, arb.io.out.bits.bits.stage2 node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) connect stage2_final, _stage2_final_T_1 node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) connect count, _count_T_3 node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) connect aux_count, _aux_count_T connect aux_pte.ppn, aux_ppn connect aux_pte.reserved_for_future, UInt<1>(0h0) connect resp_ae_ptw, UInt<1>(0h0) connect resp_ae_final, UInt<1>(0h0) connect resp_pf, UInt<1>(0h0) node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0)) node resp_gf_count = tail(_resp_gf_count_T_2, 1) node resp_gf_idxs_0 = shr(aux_ppn, 29) wire _resp_gf_WIRE : UInt<15>[1] connect _resp_gf_WIRE[0], resp_gf_idxs_0 node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0)) node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0)) node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2) connect resp_gf, _resp_gf_T_2 connect resp_hr, UInt<1>(0h1) connect resp_hw, UInt<1>(0h1) connect resp_hx, UInt<1>(0h1) connect resp_fragmented_superpage, UInt<1>(0h0) connect r_hgatp, io.dpath.hgatp node _T_43 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node _T_44 = or(_T_43, arb.io.out.bits.bits.stage2) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2)\n") : printf_2 assert(clock, _T_44, UInt<1>(0h1), "") : assert_2 else : node _T_48 = eq(UInt<3>(0h1), state) when _T_48 : node _T_49 = eq(count, r_hgatp_initial_count) node _T_50 = and(stage2, _T_49) when _T_50 : node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2)) node _gpa_pgoff_T_1 = shl(r_req.addr, 3) node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) connect gpa_pgoff, _gpa_pgoff_T_2 when UInt<1>(0h0) : node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) node _aux_count_T_2 = tail(_aux_count_T_1, 1) connect aux_count, _aux_count_T_2 connect aux_pte.ppn, UInt<1>(0h0) connect aux_pte.reserved_for_future, UInt<1>(0h0) connect pte_hit, UInt<1>(0h1) else : when UInt<1>(0h0) : node _count_T_4 = add(count, UInt<1>(0h1)) node _count_T_5 = tail(_count_T_4, 1) connect count, _count_T_5 connect pte_hit, UInt<1>(0h1) else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) connect next_state, _next_state_T_1 when resp_gf : connect next_state, UInt<3>(0h0) node _T_51 = or(r_req_dest, UInt<2>(0h0)) node _T_52 = bits(_T_51, 1, 0) connect resp_valid[_T_52], UInt<1>(0h1) else : node _T_53 = eq(UInt<3>(0h2), state) when _T_53 : node _next_state_T_2 = mux(l2_hit, UInt<3>(0h1), UInt<3>(0h4)) connect next_state, _next_state_T_2 else : node _T_54 = eq(UInt<3>(0h4), state) when _T_54 : connect next_state, UInt<3>(0h5) node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2)) connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T when io.mem.s2_xcpt.ae.ld : connect resp_ae_ptw, UInt<1>(0h1) connect next_state, UInt<3>(0h0) node _T_55 = or(r_req_dest, UInt<2>(0h0)) node _T_56 = bits(_T_55, 1, 0) connect resp_valid[_T_56], UInt<1>(0h1) else : node _T_57 = eq(UInt<3>(0h7), state) when _T_57 : connect next_state, UInt<3>(0h0) node _T_58 = or(r_req_dest, UInt<2>(0h0)) node _T_59 = bits(_T_58, 1, 0) connect resp_valid[_T_59], UInt<1>(0h1) node _T_60 = eq(homogeneous, UInt<1>(0h0)) when _T_60 : connect count, UInt<2>(0h2) connect resp_fragmented_superpage, UInt<1>(0h1) when do_both_stages : connect resp_fragmented_superpage, UInt<1>(0h1) node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000)) node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2) node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18) node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0) node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9) node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0) node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1) node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect merged_pte, aux_pte connect merged_pte.ppn, _merged_pte_T node _r_pte_T = eq(l2_error, UInt<1>(0h0)) node _r_pte_T_1 = and(l2_hit, _r_pte_T) node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) node _r_pte_T_4 = eq(state, UInt<3>(0h1)) node _r_pte_T_5 = and(_r_pte_T_4, UInt<1>(0h0)) node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0)) node r_pte_count = tail(_r_pte_count_T_2, 1) node r_pte_idxs_0 = shr(UInt<1>(0h0), 27) wire r_pte_lsbs : UInt<2> connect r_pte_lsbs, r_pte_idxs_0 wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte, l2_pte node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 node _r_pte_T_6 = eq(state, UInt<3>(0h1)) node _r_pte_T_7 = and(_r_pte_T_6, UInt<1>(0h0)) wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_1, l2_pte connect r_pte_pte_1.ppn, UInt<1>(0h0) node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1) node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0)) node r_pte_count_1 = tail(_r_pte_count_T_5, 1) node r_pte_idxs_0_1 = shr(pte.ppn, 27) wire r_pte_lsbs_1 : UInt<2> connect r_pte_lsbs_1, r_pte_idxs_0_1 wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_2, r_pte node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) node _r_pte_T_10 = and(_r_pte_T_9, stage2) node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) node _r_pte_T_12 = eq(state, UInt<3>(0h7)) node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) node _r_pte_T_15 = neq(count, UInt<2>(0h2)) node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) node _r_pte_T_17 = shr(r_pte.ppn, 18) node _r_pte_T_18 = bits(r_req.addr, 17, 0) node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) node _r_pte_T_20 = shr(r_pte.ppn, 9) node _r_pte_T_21 = bits(r_req.addr, 8, 0) node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) node _r_pte_truncIdx_T = or(count, UInt<1>(0h0)) node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0) node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1)) node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19) wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_3, r_pte connect r_pte_pte_3.ppn, _r_pte_T_24 node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid) node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1) node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0)) node r_pte_count_2 = tail(_r_pte_count_T_8, 1) node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27) wire r_pte_lsbs_2 : UInt<2> connect r_pte_lsbs_2, r_pte_idxs_0_2 wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_4, r_pte node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_5, r_pte connect r_pte_pte_5.ppn, satp.ppn node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte) node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27) node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28) node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29) node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30) node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31) node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32) inst r_pte_barrier of OptimizationBarrier_PTE connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_33.v connect r_pte_barrier.io.x.r, _r_pte_T_33.r connect r_pte_barrier.io.x.w, _r_pte_T_33.w connect r_pte_barrier.io.x.x, _r_pte_T_33.x connect r_pte_barrier.io.x.u, _r_pte_T_33.u connect r_pte_barrier.io.x.g, _r_pte_T_33.g connect r_pte_barrier.io.x.a, _r_pte_T_33.a connect r_pte_barrier.io.x.d, _r_pte_T_33.d connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future connect r_pte, r_pte_barrier.io.y node _T_61 = eq(l2_error, UInt<1>(0h0)) node _T_62 = and(l2_hit, _T_61) node _T_63 = eq(resp_gf, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) when _T_64 : node _T_65 = eq(state, UInt<3>(0h1)) node _T_66 = eq(state, UInt<3>(0h2)) node _T_67 = or(_T_65, _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req \|\| state === s_wait1)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 connect next_state, UInt<3>(0h0) node _T_71 = or(r_req_dest, UInt<2>(0h0)) node _T_72 = bits(_T_71, 1, 0) connect resp_valid[_T_72], UInt<1>(0h1) connect count, UInt<2>(0h2) when mem_resp_valid : node _T_73 = eq(state, UInt<3>(0h5)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_4 assert(clock, _T_73, UInt<1>(0h1), "") : assert_4 connect next_state, UInt<3>(0h1) when traverse : node _T_77 = eq(stage2, UInt<1>(0h0)) node _T_78 = and(do_both_stages, _T_77) when _T_78 : connect do_switch, UInt<1>(0h1) node _count_T_6 = add(count, UInt<1>(0h1)) node _count_T_7 = tail(_count_T_6, 1) connect count, _count_T_7 else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) node _gf_T_1 = and(stage2, _gf_T) node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) node _gf_T_3 = and(pte.x, _gf_T_2) node _gf_T_4 = or(pte.r, _gf_T_3) node _gf_T_5 = and(pte.v, _gf_T_4) node _gf_T_6 = and(_gf_T_5, pte.a) node _gf_T_7 = and(_gf_T_6, pte.r) node _gf_T_8 = and(_gf_T_7, pte.u) node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) node _gf_T_10 = and(_gf_T_1, _gf_T_9) node _gf_T_11 = eq(pte.w, UInt<1>(0h0)) node _gf_T_12 = and(pte.x, _gf_T_11) node _gf_T_13 = or(pte.r, _gf_T_12) node _gf_T_14 = and(pte.v, _gf_T_13) node _gf_T_15 = and(_gf_T_14, pte.a) node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _gf_T_17 = and(_gf_T_15, _gf_T_16) node _gf_T_18 = and(_gf_T_17, invalid_gpa) node gf = or(_gf_T_10, _gf_T_18) node ae = and(pte.v, invalid_paddr) node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) node pf = and(pte.v, _pf_T) node _success_T = eq(ae, UInt<1>(0h0)) node _success_T_1 = and(pte.v, _success_T) node _success_T_2 = eq(pf, UInt<1>(0h0)) node _success_T_3 = and(_success_T_1, _success_T_2) node _success_T_4 = eq(gf, UInt<1>(0h0)) node success = and(_success_T_3, _success_T_4) node _T_79 = eq(stage2_final, UInt<1>(0h0)) node _T_80 = and(do_both_stages, _T_79) node _T_81 = and(_T_80, success) when _T_81 : when stage2 : connect stage2, UInt<1>(0h0) connect count, aux_count else : connect stage2_final, UInt<1>(0h1) connect do_switch, UInt<1>(0h1) else : node _l2_refill_T = eq(count, UInt<2>(0h2)) node _l2_refill_T_1 = and(success, _l2_refill_T) node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2)) node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) connect l2_refill, _l2_refill_T_27 connect count, max_count node _T_82 = eq(count, UInt<2>(0h2)) node _T_83 = eq(do_both_stages, UInt<1>(0h0)) node _T_84 = eq(aux_count, UInt<2>(0h2)) node _T_85 = or(_T_83, _T_84) node _T_86 = and(_T_82, _T_85) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = and(UInt<1>(0h0), _T_87) when _T_88 : connect next_state, UInt<3>(0h7) else : connect next_state, UInt<3>(0h0) node _T_89 = or(r_req_dest, UInt<2>(0h0)) node _T_90 = bits(_T_89, 1, 0) connect resp_valid[_T_90], UInt<1>(0h1) node _resp_ae_ptw_T = lt(count, UInt<2>(0h2)) node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T) node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0)) node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2) node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4) node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0)) node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6) node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0)) node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8) node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0)) node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10) node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0)) node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12) node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14) node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15) connect resp_ae_ptw, _resp_ae_ptw_T_16 node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) connect resp_ae_final, _resp_ae_final_T_5 node _resp_pf_T = eq(stage2, UInt<1>(0h0)) node _resp_pf_T_1 = and(pf, _resp_pf_T) connect resp_pf, _resp_pf_T_1 node _resp_gf_T_3 = and(pf, stage2) node _resp_gf_T_4 = or(gf, _resp_gf_T_3) connect resp_gf, _resp_gf_T_4 node _resp_hr_T = eq(stage2, UInt<1>(0h0)) node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) connect resp_hr, _resp_hr_T_12 node _resp_hw_T = eq(stage2, UInt<1>(0h0)) node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) connect resp_hw, _resp_hw_T_13 node _resp_hx_T = eq(stage2, UInt<1>(0h0)) node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) connect resp_hx, _resp_hx_T_12 when io.mem.s2_nack : node _T_91 = eq(state, UInt<3>(0h4)) node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : node _T_94 = eq(_T_91, UInt<1>(0h0)) when _T_94 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_5 assert(clock, _T_91, UInt<1>(0h1), "") : assert_5 connect next_state, UInt<3>(0h1) when do_switch : node _aux_count_T_3 = add(count, UInt<1>(0h1)) node _aux_count_T_4 = tail(_aux_count_T_3, 1) node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) connect aux_count, _aux_count_T_5 connect count, r_hgatp_initial_count node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18) node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0) node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9) node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0) node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) node _aux_pte_T = eq(count, UInt<1>(0h1)) node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1) node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect aux_pte_pte, pte connect aux_pte_pte.ppn, _aux_pte_T_5 node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) connect aux_pte, _aux_pte_T_6 connect stage2, UInt<1>(0h1) node _leaf_T = eq(traverse, UInt<1>(0h0)) node _leaf_T_1 = and(mem_resp_valid, _leaf_T) node _leaf_T_2 = eq(count, UInt<1>(0h0)) node leaf = and(_leaf_T_1, _leaf_T_2) node _T_95 = and(leaf, pte.v) node _T_96 = eq(invalid_paddr, UInt<1>(0h0)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(invalid_gpa, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = and(leaf, pte.v) node _T_103 = and(_T_102, invalid_paddr) node _T_104 = and(leaf, pte.v) node _T_105 = and(_T_104, invalid_gpa) node _T_106 = and(leaf, pte.v) node _T_107 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = bits(mem_resp_data, 0, 0) node _T_110 = eq(_T_109, UInt<1>(0h0)) node _T_111 = and(leaf, _T_110) node _T_112 = eq(pte.v, UInt<1>(0h0)) node _T_113 = and(leaf, _T_112) node _T_114 = bits(mem_resp_data, 0, 0) node _T_115 = and(_T_113, _T_114) node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) node _leaf_T_5 = eq(count, UInt<1>(0h1)) node leaf_1 = and(_leaf_T_4, _leaf_T_5) node _T_116 = and(leaf_1, pte.v) node _T_117 = eq(invalid_paddr, UInt<1>(0h0)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(invalid_gpa, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = and(leaf_1, pte.v) node _T_124 = and(_T_123, invalid_paddr) node _T_125 = and(leaf_1, pte.v) node _T_126 = and(_T_125, invalid_gpa) node _T_127 = and(leaf_1, pte.v) node _T_128 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = bits(mem_resp_data, 0, 0) node _T_131 = eq(_T_130, UInt<1>(0h0)) node _T_132 = and(leaf_1, _T_131) node _T_133 = eq(pte.v, UInt<1>(0h0)) node _T_134 = and(leaf_1, _T_133) node _T_135 = bits(mem_resp_data, 0, 0) node _T_136 = and(_T_134, _T_135) node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) node _leaf_T_8 = eq(count, UInt<2>(0h2)) node leaf_2 = and(_leaf_T_7, _leaf_T_8) node _T_137 = and(leaf_2, pte.v) node _T_138 = eq(invalid_paddr, UInt<1>(0h0)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(invalid_gpa, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = and(leaf_2, pte.v) node _T_145 = and(_T_144, invalid_paddr) node _T_146 = and(leaf_2, pte.v) node _T_147 = and(_T_146, invalid_gpa) node _T_148 = and(leaf_2, pte.v) node _T_149 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = bits(mem_resp_data, 0, 0) node _T_152 = eq(_T_151, UInt<1>(0h0)) node _T_153 = and(leaf_2, _T_152) node _T_154 = eq(count, UInt<2>(0h2)) node _T_155 = and(mem_resp_valid, _T_154) node _T_156 = eq(pte.r, UInt<1>(0h0)) node _T_157 = and(pte.v, _T_156) node _T_158 = eq(pte.w, UInt<1>(0h0)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(pte.x, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(pte.d, UInt<1>(0h0)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(pte.a, UInt<1>(0h0)) node _T_165 = and(_T_163, _T_164) node _T_166 = eq(pte.u, UInt<1>(0h0)) node _T_167 = and(_T_165, _T_166) node _T_168 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_169 = and(_T_167, _T_168) node _T_170 = and(_T_155, _T_169) node _T_171 = eq(state, UInt<3>(0h4)) node _T_172 = and(_T_171, io.mem.s2_xcpt.ae.ld)	module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input io_requestor_0_req_bits_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_sd, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_sd, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_2_req_ready, // @[PTW.scala:220:14] output io_requestor_2_resp_valid, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_2_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_2_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_2_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_2_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_2_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_2_status_debug, // @[PTW.scala:220:14] output io_requestor_2_status_cease, // @[PTW.scala:220:14] output io_requestor_2_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_dprv, // @[PTW.scala:220:14] output io_requestor_2_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_prv, // @[PTW.scala:220:14] output io_requestor_2_status_v, // @[PTW.scala:220:14] output io_requestor_2_status_sd, // @[PTW.scala:220:14] output io_requestor_2_status_mpv, // @[PTW.scala:220:14] output io_requestor_2_status_gva, // @[PTW.scala:220:14] output io_requestor_2_status_tsr, // @[PTW.scala:220:14] output io_requestor_2_status_tw, // @[PTW.scala:220:14] output io_requestor_2_status_tvm, // @[PTW.scala:220:14] output io_requestor_2_status_mxr, // @[PTW.scala:220:14] output io_requestor_2_status_sum, // @[PTW.scala:220:14] output io_requestor_2_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_mpp, // @[PTW.scala:220:14] output io_requestor_2_status_spp, // @[PTW.scala:220:14] output io_requestor_2_status_mpie, // @[PTW.scala:220:14] output io_requestor_2_status_spie, // @[PTW.scala:220:14] output io_requestor_2_status_mie, // @[PTW.scala:220:14] output io_requestor_2_status_sie, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_7_mask, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14] input io_mem_resp_bits_dv, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_gf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_gf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_sd, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_l2miss, // @[PTW.scala:220:14] output io_dpath_perf_l2hit, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire s2_entry_vec_0_w; // @[PTW.scala:479:59] wire s2_entry_vec_0_x; // @[PTW.scala:479:59] wire s2_entry_vec_0_u; // @[PTW.scala:479:59] wire s2_entry_vec_0_a; // @[PTW.scala:479:59] wire s2_entry_vec_0_d; // @[PTW.scala:479:59] wire writeEnable; // @[PTW.scala:433:21] wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire [44:0] _l2_tlb_ram_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire [1:0] _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid_0 = io_requestor_0_req_bits_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [31:0] io_requestor_0_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_uncached = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay = 1'h0; // @[PTW.scala:219:7] wire io_mem_replay_next = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_ordered = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_acquire = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_release = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_grant = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_blocked = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_2 = 1'h0; // @[PTW.scala:242:35] wire _clock_en_T_4 = 1'h0; // @[CustomCSRs.scala:43:61] wire _io_dpath_perf_pte_hit_T_1 = 1'h0; // @[PTW.scala:394:36] wire _io_dpath_perf_pte_hit_T_3 = 1'h0; // @[PTW.scala:394:57] wire hg = 1'h0; // @[PTW.scala:458:34] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_2_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire _r_pte_T_7 = 1'h0; // @[PTW.scala:674:25] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42] wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58] wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:489:22] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45] wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61] wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46] wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62] wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46] wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62] wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27] wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27] wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44] wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40] wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44] wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [6:0] io_mem_resp_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_2_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size = 2'h3; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] r_pte_pte_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_1 = 44'h0; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_1_ppn = 44'h0; // @[PTW.scala:771:26] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire [41:0] _r_pte_pte_ppn_T = 42'h0; // @[PTW.scala:781:30] wire [41:0] _r_pte_pte_ppn_T_2 = 42'h0; // @[PTW.scala:781:30] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire io_requestor_1_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire _valid_0_T_1 = 1'h1; // @[PTW.scala:461:15] wire _valid_0_T_7 = 1'h1; // @[PTW.scala:462:15] wire _s0_suitable_T = 1'h1; // @[PTW.scala:468:52] wire l2_pte_v = 1'h1; // @[PTW.scala:489:22] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire r_pte_pte_v = 1'h1; // @[PTW.scala:780:26] wire r_pte_pte_1_v = 1'h1; // @[PTW.scala:771:26] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_2_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_2_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [26:0] io_requestor_2_req_bits_bits_addr = 27'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[PTW.scala:219:7] wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58] wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42] wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58] wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45] wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61] wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46] wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46] wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:489:22] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [511:0] _valid_WIRE_0 = 512'h0; // @[PTW.scala:422:32] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire _valid_0_T_2 = io_dpath_sfence_bits_rs1_0; // @[PTW.scala:219:7, :461:19] wire _valid_0_T_8 = io_dpath_sfence_bits_rs2_0; // @[PTW.scala:219:7, :462:19] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_2_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_l2miss_T_1; // @[PTW.scala:482:38] wire l2_hit; // @[PTW.scala:481:27] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_2_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_2_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_2_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_valid_0; // @[PTW.scala:219:7] wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(\|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] reg resp_valid_2; // @[PTW.scala:242:27] assign io_requestor_2_resp_valid_0 = resp_valid_2; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = \|state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T \| l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 \| _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 \| io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire clock_en = _clock_en_T_3; // @[PTW.scala:244:{74,99}] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_2_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_2_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_2_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_2_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_2_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_2_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_2_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [26:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_2_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg [1:0] r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire entry_d = r_pte_d; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire entry_a = r_pte_a; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire entry_u = r_pte_u; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire entry_x = r_pte_x; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire entry_w = r_pte_w; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire entry_r = r_pte_r; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [1:0] aux_count; // @[PTW.scala:278:22] wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_2_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r \| tmp_w \| tmp_x) & (~(count[1]) & (\|(tmp_ppn[8:0])) \| count == 2'h0 & (\|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (\|(tmp_ppn[43:27])) : (\|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (\|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(\|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire _pte_addr_mask_T = ~(\|count); // @[PTW.scala:259:18, :324:40] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _GEN = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _GEN; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_23; // @[package.scala:39:86] assign _pmpHomogeneous_T_23 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_60; // @[package.scala:39:86] assign _pmpHomogeneous_T_60 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_97; // @[package.scala:39:86] assign _pmpHomogeneous_T_97 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_134; // @[package.scala:39:86] assign _pmpHomogeneous_T_134 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_171; // @[package.scala:39:86] assign _pmpHomogeneous_T_171 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_245; // @[package.scala:39:86] assign _pmpHomogeneous_T_245 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_282; // @[package.scala:39:86] assign _pmpHomogeneous_T_282 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _GEN; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _GEN; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _GEN; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _GEN; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_154 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_154; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_T_25 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_62; // @[package.scala:39:86] assign _pmpHomogeneous_T_62 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_99; // @[package.scala:39:86] assign _pmpHomogeneous_T_99 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_136; // @[package.scala:39:86] assign _pmpHomogeneous_T_136 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_173; // @[package.scala:39:86] assign _pmpHomogeneous_T_173 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_210; // @[package.scala:39:86] assign _pmpHomogeneous_T_210 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_247; // @[package.scala:39:86] assign _pmpHomogeneous_T_247 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_284; // @[package.scala:39:86] assign _pmpHomogeneous_T_284 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_154; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_154; // @[package.scala:39:86] wire _l2_refill_T; // @[PTW.scala:713:39] assign _l2_refill_T = _T_154; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_154; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_154; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] \| pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] wire _T_65 = state == 3'h1; // @[PTW.scala:233:22, :394:46] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_65; // @[PTW.scala:394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_65; // @[PTW.scala:394:46, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_65; // @[PTW.scala:394:46, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_65; // @[PTW.scala:394:46, :674:15] wire _io_dpath_perf_pte_hit_T_2 = ~io_dpath_perf_l2hit_0; // @[PTW.scala:219:7, :394:60] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire [8:0] r_idx; // @[package.scala:163:13] wire [8:0] _s1_rdata_WIRE; // @[PTW.scala:472:28] wire s0_valid; // @[PTW.scala:467:31] reg [511:0] g_0; // @[PTW.scala:421:16] reg [511:0] valid_0; // @[PTW.scala:422:24] wire [18:0] r_tag = {r_req_vstage1, r_req_addr[26:9]}; // @[package.scala:163:13] assign r_idx = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_2_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[package.scala:163:13] wire [511:0] _GEN_0 = {503'h0, r_idx}; // @[package.scala:163:13] wire [511:0] _r_valid_vec_T = valid_0 >> _GEN_0; // @[PTW.scala:422:24, :426:34] wire r_valid_vec = _r_valid_vec_T[0]; // @[PTW.scala:426:34] reg r_valid_vec_q; // @[PTW.scala:427:28] assign writeEnable = l2_refill & ~invalidated; // @[PTW.scala:251:24, :398:26, :433:{21,24}] wire [17:0] entry_tag; // @[PTW.scala:434:23] wire [19:0] entry_ppn; // @[PTW.scala:434:23] assign entry_ppn = r_pte_ppn[19:0]; // @[PTW.scala:275:18, :434:23, :435:17] assign entry_tag = r_tag[17:0]; // @[package.scala:163:13] wire [1:0] lo_lo = {entry_w, entry_r}; // @[PTW.scala:434:23, :446:82] wire [1:0] lo_hi = {entry_u, entry_x}; // @[PTW.scala:434:23, :446:82] wire [3:0] lo = {lo_hi, lo_lo}; // @[PTW.scala:446:82] wire [1:0] hi_lo = {entry_d, entry_a}; // @[PTW.scala:434:23, :446:82] wire [37:0] hi_hi = {entry_tag, entry_ppn}; // @[PTW.scala:434:23, :446:82] wire [39:0] hi = {hi_hi, hi_lo}; // @[PTW.scala:446:82] wire [511:0] mask = 512'h1 << _GEN_0; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T = valid_0 \| mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T = g_0 \| mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_1 = ~mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_2 = g_0 & _g_0_T_1; // @[PTW.scala:421:16, :452:{56,58}] wire [511:0] _g_0_T_3 = r_pte_g ? _g_0_T : _g_0_T_2; // @[PTW.scala:275:18, :452:{24,41,56}] wire [8:0] _valid_0_T_3 = io_dpath_sfence_bits_addr_0[20:12]; // @[PTW.scala:219:7, :461:96] wire [511:0] _valid_0_T_4 = 512'h1 << _valid_0_T_3; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_5 = ~_valid_0_T_4; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_6 = valid_0 & _valid_0_T_5; // @[PTW.scala:422:24, :461:{59,61}] wire [511:0] _valid_0_T_9 = valid_0 & g_0; // @[PTW.scala:421:16, :422:24, :462:59] wire [511:0] _valid_0_T_10 = _valid_0_T_8 ? _valid_0_T_9 : 512'h0; // @[PTW.scala:462:{14,19,59}] wire [511:0] _valid_0_T_11 = _valid_0_T_2 ? _valid_0_T_6 : _valid_0_T_10; // @[PTW.scala:461:{14,19,59}, :462:14] wire _s0_valid_T = ~l2_refill; // @[PTW.scala:398:26, :467:20] wire _T_42 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _s0_valid_T_1; // @[Decoupled.scala:51:35] assign _s0_valid_T_1 = _T_42; // @[Decoupled.scala:51:35] wire _r_pte_T_25; // @[Decoupled.scala:51:35] assign _r_pte_T_25 = _T_42; // @[Decoupled.scala:51:35] assign s0_valid = _s0_valid_T & _s0_valid_T_1; // @[Decoupled.scala:51:35] wire _s0_suitable_T_1 = ~_arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19, :468:87] wire s0_suitable = _s0_suitable_T_1; // @[PTW.scala:468:{84,87}] wire _s1_valid_T = s0_valid & s0_suitable; // @[PTW.scala:467:31, :468:84, :469:37] wire _s1_valid_T_1 = _s1_valid_T & _arb_io_out_bits_valid; // @[PTW.scala:236:19, :469:{37,52}] reg s1_valid; // @[PTW.scala:469:27] reg s2_valid; // @[PTW.scala:470:27] wire [8:0] _s1_rdata_T = _arb_io_out_bits_bits_addr[8:0]; // @[PTW.scala:236:19, :472:54] assign _s1_rdata_WIRE = _s1_rdata_T; // @[PTW.scala:472:{28,54}] reg [44:0] r; // @[PTW.scala:473:66] wire [43:0] uncorrected = r[43:0]; // @[ECC.scala:75:24] wire [43:0] _s2_entry_vec_WIRE = uncorrected; // @[ECC.scala:75:24] wire uncorrectable = ^r; // @[ECC.scala:78:27] wire _s2_error_T_1 = uncorrectable; // @[ECC.scala:15:27, :78:27] reg s2_valid_vec; // @[PTW.scala:474:33] wire _s2_error_T = s2_valid_vec; // @[PTW.scala:474:33, :476:75] wire _s2_hit_vec_T = s2_valid_vec; // @[PTW.scala:474:33, :480:77] wire [511:0] _s2_g_vec_T = g_0 >> _GEN_0; // @[PTW.scala:421:16, :426:34, :475:45] wire _s2_g_vec_T_1 = _s2_g_vec_T[0]; // @[PTW.scala:475:45] wire _s2_g_vec_WIRE_0 = _s2_g_vec_T_1; // @[PTW.scala:475:{37,45}] reg s2_g_vec_0; // @[PTW.scala:475:29] wire l2_pte_g = s2_g_vec_0; // @[PTW.scala:475:29, :489:22] wire l2_error = _s2_error_T & _s2_error_T_1; // @[ECC.scala:15:27] wire [17:0] _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire [19:0] _s2_entry_vec_T_6; // @[PTW.scala:479:59] wire _s2_entry_vec_T_5; // @[PTW.scala:479:59] wire _s2_entry_vec_T_4; // @[PTW.scala:479:59] wire l2_pte_d = s2_entry_vec_0_d; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_3; // @[PTW.scala:479:59] wire l2_pte_a = s2_entry_vec_0_a; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_2; // @[PTW.scala:479:59] wire l2_pte_u = s2_entry_vec_0_u; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_1; // @[PTW.scala:479:59] wire l2_pte_x = s2_entry_vec_0_x; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T; // @[PTW.scala:479:59] wire l2_pte_w = s2_entry_vec_0_w; // @[PTW.scala:479:59, :489:22] wire [17:0] s2_entry_vec_0_tag; // @[PTW.scala:479:59] wire [19:0] s2_entry_vec_0_ppn; // @[PTW.scala:479:59] wire s2_entry_vec_0_r; // @[PTW.scala:479:59] wire l2_pte_r = s2_entry_vec_0_r; // @[PTW.scala:479:59, :489:22] assign _s2_entry_vec_T = _s2_entry_vec_WIRE[0]; // @[PTW.scala:479:59] assign s2_entry_vec_0_r = _s2_entry_vec_T; // @[PTW.scala:479:59] assign _s2_entry_vec_T_1 = _s2_entry_vec_WIRE[1]; // @[PTW.scala:479:59] assign s2_entry_vec_0_w = _s2_entry_vec_T_1; // @[PTW.scala:479:59] assign _s2_entry_vec_T_2 = _s2_entry_vec_WIRE[2]; // @[PTW.scala:479:59] assign s2_entry_vec_0_x = _s2_entry_vec_T_2; // @[PTW.scala:479:59] assign _s2_entry_vec_T_3 = _s2_entry_vec_WIRE[3]; // @[PTW.scala:479:59] assign s2_entry_vec_0_u = _s2_entry_vec_T_3; // @[PTW.scala:479:59] assign _s2_entry_vec_T_4 = _s2_entry_vec_WIRE[4]; // @[PTW.scala:479:59] assign s2_entry_vec_0_a = _s2_entry_vec_T_4; // @[PTW.scala:479:59] assign _s2_entry_vec_T_5 = _s2_entry_vec_WIRE[5]; // @[PTW.scala:479:59] assign s2_entry_vec_0_d = _s2_entry_vec_T_5; // @[PTW.scala:479:59] assign _s2_entry_vec_T_6 = _s2_entry_vec_WIRE[25:6]; // @[PTW.scala:479:59] assign s2_entry_vec_0_ppn = _s2_entry_vec_T_6; // @[PTW.scala:479:59] assign _s2_entry_vec_T_7 = _s2_entry_vec_WIRE[43:26]; // @[PTW.scala:479:59] assign s2_entry_vec_0_tag = _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire _s2_hit_vec_T_1 = r_tag == {1'h0, s2_entry_vec_0_tag}; // @[package.scala:163:13] wire s2_hit_vec_0 = _s2_hit_vec_T & _s2_hit_vec_T_1; // @[PTW.scala:480:{77,83,93}] assign l2_hit = s2_valid & s2_hit_vec_0; // @[PTW.scala:470:27, :480:83, :481:27] assign io_dpath_perf_l2hit_0 = l2_hit; // @[PTW.scala:219:7, :481:27] wire _io_dpath_perf_l2miss_T = ~s2_hit_vec_0; // @[PTW.scala:480:83, :482:41] assign _io_dpath_perf_l2miss_T_1 = s2_valid & _io_dpath_perf_l2miss_T; // @[PTW.scala:470:27, :482:{38,41}] assign io_dpath_perf_l2miss_0 = _io_dpath_perf_l2miss_T_1; // @[PTW.scala:219:7, :482:38] wire r_pte_pte_d = l2_pte_d; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_d = l2_pte_d; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_a = l2_pte_a; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_a = l2_pte_a; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_g = l2_pte_g; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_g = l2_pte_g; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_u = l2_pte_u; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_u = l2_pte_u; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_x = l2_pte_x; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_x = l2_pte_x; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_w = l2_pte_w; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_w = l2_pte_w; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_r = l2_pte_r; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_r = l2_pte_r; // @[PTW.scala:489:22, :771:26] wire [43:0] l2_pte_ppn; // @[PTW.scala:489:22] assign l2_pte_ppn = {24'h0, s2_entry_vec_0_ppn}; // @[PTW.scala:479:59, :489:22, :491:16] wire _invalidated_T = \|state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 \| _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T \| _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = l2_hit \| _io_mem_s1_kill_T; // @[PTW.scala:481:27, :531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 \| resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN_1 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_37 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN_1; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 \| _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_43 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_48 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_98 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_115 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_68 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_120 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_135 = _GEN_4; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_5 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_83 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_125 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_140 = _GEN_5; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 \| _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 \| _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 \| _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 \| _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 \| _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 \| _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 \| _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 \| _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 \| _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 \| _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 \| _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 \| _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 \| _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 \| _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_6 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = \|_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = \|_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = \|_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous \| _pmpHomogeneous_T_28; // @[package.scala:39:76] wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_7; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_7; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 \| _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 \| _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_8 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_39 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_45 = \|_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = \|_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = \|_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 \| _pmpHomogeneous_T_65; // @[package.scala:39:76] wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_9; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_9; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 \| pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 \| _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 \| _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_10 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_76 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_83 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_82 = \|_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_89 = \|_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = \|_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 \| _pmpHomogeneous_T_102; // @[package.scala:39:76] wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_11; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_11; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 \| pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 \| _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 \| _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_12 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_113 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_120 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_127 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_119 = \|_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_126 = \|_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_133 = \|_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 \| _pmpHomogeneous_T_139; // @[package.scala:39:76] wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_13; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_13; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 \| pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 \| _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 \| _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_14 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_150 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_157 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_164 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_156 = \|_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_163 = \|_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_170 = \|_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 \| _pmpHomogeneous_T_176; // @[package.scala:39:76] wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_15; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_15; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 \| pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 \| _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 \| _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_16 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_187 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_194 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_201 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_193 = \|_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_200 = \|_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_207 = \|_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 \| _pmpHomogeneous_T_213; // @[package.scala:39:76] wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_17; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_17; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 \| pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 \| _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 \| _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_18 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_224 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_231 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_238 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_230 = \|_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_237 = \|_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_244 = \|_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 \| _pmpHomogeneous_T_250; // @[package.scala:39:76] wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_19; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_19; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 \| pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 \| _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 \| _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_20 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_261 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_268 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_275 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_267 = \|_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_274 = \|_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_281 = \|_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 \| _pmpHomogeneous_T_287; // @[package.scala:39:76] wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_21 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_21; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_21; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 \| pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 \| _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 \| _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_2_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T \| _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _T_84 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_2_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _gpa_pgoff_T; // @[PTW.scala:615:36] assign _gpa_pgoff_T = _T_84; // @[PTW.scala:566:60, :615:36] wire _l2_refill_T_7; // @[PTW.scala:715:40] assign _l2_refill_T_7 = _T_84; // @[PTW.scala:566:60, :715:40] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 \| _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_2_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_2_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_2_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T \| _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 \| _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_2_resp_bits_homogeneous_0 = _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_2_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_2_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_2_resp_bits_gpa_bits_T_2 = _io_requestor_2_resp_bits_gpa_bits_T \| _io_requestor_2_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_2_resp_bits_gpa_bits_T_4 = _io_requestor_2_resp_bits_gpa_bits_T_2 \| _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_7 = {_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_10 = {_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_2_resp_bits_gpa_bits_truncIdx = _io_requestor_2_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_2_resp_bits_gpa_bits_T_11 = io_requestor_2_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_12 = _io_requestor_2_resp_bits_gpa_bits_T_11 ? _io_requestor_2_resp_bits_gpa_bits_T_10 : _io_requestor_2_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_13 = _io_requestor_2_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_2_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_2_resp_bits_gpa_bits_T_14 = {_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_2_resp_bits_gpa_bits_0 = _io_requestor_2_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_2_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_2_resp_bits_gpa_is_pte_0 = _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _GEN_22 = ~(\|state) & _T_42; // @[Decoupled.scala:51:35] wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40] wire _resp_gf_T_1 = \|_resp_gf_WIRE_0; // @[package.scala:43:40] wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_23 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24] wire [2:0] _count_T_4; // @[PTW.scala:624:24] assign _count_T_4 = _GEN_23; // @[PTW.scala:624:24] wire [2:0] _count_T_6; // @[PTW.scala:696:22] assign _count_T_6 = _GEN_23; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_23; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_53 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire [2:0] _next_state_T_2 = l2_hit ? 3'h1 : 3'h4; // @[PTW.scala:481:27, :636:24] wire _T_54 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39] assign io_dpath_perf_pte_miss_0 = ~(~(\|state) \| _T_65 \| _T_53) & _T_54 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :394:46, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T = ~l2_error; // @[PTW.scala:476:81, :670:19] wire _r_pte_T_1 = l2_hit & _r_pte_T; // @[PTW.scala:481:27, :670:{16,19}] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire _r_pte_T_3 = _r_pte_T_1 & _r_pte_T_2; // @[PTW.scala:670:{16,29,32}] wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {42'h0, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:19] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76] wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:8, :676:8] wire [43:0] _r_pte_T_31_ppn = _r_pte_T_30_ppn; // @[PTW.scala:674:8, :676:8] wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_d = _r_pte_T_30_d; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_a = _r_pte_T_30_a; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_g = _r_pte_T_30_g; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_u = _r_pte_T_30_u; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_x = _r_pte_T_30_x; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_w = _r_pte_T_30_w; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_r = _r_pte_T_30_r; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_v = _r_pte_T_30_v; // @[PTW.scala:674:8, :676:8] wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_3 ? 10'h0 : _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:{8,29}, :672:8] wire [43:0] _r_pte_T_33_ppn = _r_pte_T_3 ? l2_pte_ppn : _r_pte_T_32_ppn; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_3 ? 2'h0 : _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:{8,29}, :672:8] wire _r_pte_T_33_d = _r_pte_T_3 ? l2_pte_d : _r_pte_T_32_d; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_a = _r_pte_T_3 ? l2_pte_a : _r_pte_T_32_a; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_g = _r_pte_T_3 ? l2_pte_g : _r_pte_T_32_g; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_u = _r_pte_T_3 ? l2_pte_u : _r_pte_T_32_u; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_x = _r_pte_T_3 ? l2_pte_x : _r_pte_T_32_x; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_w = _r_pte_T_3 ? l2_pte_w : _r_pte_T_32_w; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_r = _r_pte_T_3 ? l2_pte_r : _r_pte_T_32_r; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_v = _r_pte_T_3 \| _r_pte_T_32_v; // @[PTW.scala:670:{8,29}, :672:8] wire _T_64 = l2_hit & ~l2_error & ~resp_gf; // @[PTW.scala:263:20, :476:81, :481:27, :670:{19,32}, :685:{16,29}] wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r \| _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r \| _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(\|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 \| _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = \|pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_81 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :566:15, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_81 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r \| _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r \| _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 \| _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_24 = traverse \| _T_81; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(\|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r \| _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_4 = gf \| _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r \| _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T \| _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r \| _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T \| _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r \| _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T \| _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveACDToNoC_2 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAFromNoC_2 connect a.clock, clock connect a.reset, reset inst c of TLCFromNoC_2 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_2 connect d.clock, clock connect d.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect a.io.flit, io.flits.a connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready	module TLSlaveACDToNoC_2( // @[Tilelink.scala:161:7] input clock, // @[Tilelink.scala:161:7] input reset, // @[Tilelink.scala:161:7] input io_tilelink_a_ready, // @[Tilelink.scala:168:14] output io_tilelink_a_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:168:14] output [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:168:14] output [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:168:14] output [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:168:14] input io_tilelink_c_ready, // @[Tilelink.scala:168:14] output io_tilelink_c_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:168:14] output [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:168:14] output [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:168:14] output io_tilelink_d_ready, // @[Tilelink.scala:168:14] input io_tilelink_d_valid, // @[Tilelink.scala:168:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:168:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:168:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:168:14] input [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:168:14] input [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:168:14] input [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:168:14] output io_flits_a_ready, // @[Tilelink.scala:168:14] input io_flits_a_valid, // @[Tilelink.scala:168:14] input io_flits_a_bits_head, // @[Tilelink.scala:168:14] input io_flits_a_bits_tail, // @[Tilelink.scala:168:14] input [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:168:14] output io_flits_c_ready, // @[Tilelink.scala:168:14] input io_flits_c_valid, // @[Tilelink.scala:168:14] input io_flits_c_bits_head, // @[Tilelink.scala:168:14] input io_flits_c_bits_tail, // @[Tilelink.scala:168:14] input [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:168:14] input io_flits_d_ready, // @[Tilelink.scala:168:14] output io_flits_d_valid, // @[Tilelink.scala:168:14] output io_flits_d_bits_head, // @[Tilelink.scala:168:14] output io_flits_d_bits_tail, // @[Tilelink.scala:168:14] output [144:0] io_flits_d_bits_payload, // @[Tilelink.scala:168:14] output [3:0] io_flits_d_bits_egress_id // @[Tilelink.scala:168:14] ); wire [128:0] _d_io_flit_bits_payload; // @[Tilelink.scala:179:17] TLAFromNoC a ( // @[Tilelink.scala:177:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:177:17] TLCFromNoC_1 c ( // @[Tilelink.scala:178:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[128:0]) // @[Tilelink.scala:185:14] ); // @[Tilelink.scala:178:17] TLDToNoC_2 d ( // @[Tilelink.scala:179:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:179:17] assign io_flits_d_bits_payload = {16'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:161:7, :179:17, :186:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCXbar : input clock : Clock input reset : Reset output auto : { flip in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}}, out_4 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_3 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_2 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_1 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_0 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}} wire nodeIn : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}} invalidate nodeIn.resp.bits.data invalidate nodeIn.resp.bits.manager_id invalidate nodeIn.resp.bits.client_id invalidate nodeIn.resp.bits.opcode invalidate nodeIn.resp.valid invalidate nodeIn.resp.ready invalidate nodeIn.req.bits.data invalidate nodeIn.req.bits.manager_id invalidate nodeIn.req.bits.client_id invalidate nodeIn.req.bits.opcode invalidate nodeIn.req.valid invalidate nodeIn.req.ready wire nodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate nodeOut.resp.bits.data invalidate nodeOut.resp.bits.manager_id invalidate nodeOut.resp.bits.client_id invalidate nodeOut.resp.bits.opcode invalidate nodeOut.resp.valid invalidate nodeOut.resp.ready invalidate nodeOut.req.bits.data invalidate nodeOut.req.bits.manager_id invalidate nodeOut.req.bits.client_id invalidate nodeOut.req.bits.opcode invalidate nodeOut.req.valid invalidate nodeOut.req.ready wire x1_nodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut.resp.bits.data invalidate x1_nodeOut.resp.bits.manager_id invalidate x1_nodeOut.resp.bits.client_id invalidate x1_nodeOut.resp.bits.opcode invalidate x1_nodeOut.resp.valid invalidate x1_nodeOut.resp.ready invalidate x1_nodeOut.req.bits.data invalidate x1_nodeOut.req.bits.manager_id invalidate x1_nodeOut.req.bits.client_id invalidate x1_nodeOut.req.bits.opcode invalidate x1_nodeOut.req.valid invalidate x1_nodeOut.req.ready wire x1_nodeOut_1 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut_1.resp.bits.data invalidate x1_nodeOut_1.resp.bits.manager_id invalidate x1_nodeOut_1.resp.bits.client_id invalidate x1_nodeOut_1.resp.bits.opcode invalidate x1_nodeOut_1.resp.valid invalidate x1_nodeOut_1.resp.ready invalidate x1_nodeOut_1.req.bits.data invalidate x1_nodeOut_1.req.bits.manager_id invalidate x1_nodeOut_1.req.bits.client_id invalidate x1_nodeOut_1.req.bits.opcode invalidate x1_nodeOut_1.req.valid invalidate x1_nodeOut_1.req.ready wire x1_nodeOut_2 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut_2.resp.bits.data invalidate x1_nodeOut_2.resp.bits.manager_id invalidate x1_nodeOut_2.resp.bits.client_id invalidate x1_nodeOut_2.resp.bits.opcode invalidate x1_nodeOut_2.resp.valid invalidate x1_nodeOut_2.resp.ready invalidate x1_nodeOut_2.req.bits.data invalidate x1_nodeOut_2.req.bits.manager_id invalidate x1_nodeOut_2.req.bits.client_id invalidate x1_nodeOut_2.req.bits.opcode invalidate x1_nodeOut_2.req.valid invalidate x1_nodeOut_2.req.ready wire x1_nodeOut_3 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut_3.resp.bits.data invalidate x1_nodeOut_3.resp.bits.manager_id invalidate x1_nodeOut_3.resp.bits.client_id invalidate x1_nodeOut_3.resp.bits.opcode invalidate x1_nodeOut_3.resp.valid invalidate x1_nodeOut_3.resp.ready invalidate x1_nodeOut_3.req.bits.data invalidate x1_nodeOut_3.req.bits.manager_id invalidate x1_nodeOut_3.req.bits.client_id invalidate x1_nodeOut_3.req.bits.opcode invalidate x1_nodeOut_3.req.valid invalidate x1_nodeOut_3.req.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 connect auto.out_4, x1_nodeOut_3 connect nodeIn, auto.in connect nodeIn.req.ready, UInt<1>(0h0) inst out_arb of ReRoCCMsgArbiter_6 connect out_arb.clock, clock connect out_arb.reset, reset node sel = eq(UInt<1>(0h0), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T = and(nodeIn.req.valid, sel) connect out_arb.io.in[0].valid, _out_arb_io_in_0_valid_T connect out_arb.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T when sel : connect nodeIn.req.ready, out_arb.io.in[0].ready connect nodeOut.req.bits, out_arb.io.out.bits connect nodeOut.req.valid, out_arb.io.out.valid connect out_arb.io.out.ready, nodeOut.req.ready inst out_arb_1 of ReRoCCMsgArbiter_7 connect out_arb_1.clock, clock connect out_arb_1.reset, reset node sel_1 = eq(UInt<1>(0h1), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_1 = and(nodeIn.req.valid, sel_1) connect out_arb_1.io.in[0].valid, _out_arb_io_in_0_valid_T_1 connect out_arb_1.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_1.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_1.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_1.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_1.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_1 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_1.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_1 when sel_1 : connect nodeIn.req.ready, out_arb_1.io.in[0].ready connect x1_nodeOut.req.bits, out_arb_1.io.out.bits connect x1_nodeOut.req.valid, out_arb_1.io.out.valid connect out_arb_1.io.out.ready, x1_nodeOut.req.ready inst out_arb_2 of ReRoCCMsgArbiter_8 connect out_arb_2.clock, clock connect out_arb_2.reset, reset node sel_2 = eq(UInt<2>(0h2), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_2 = and(nodeIn.req.valid, sel_2) connect out_arb_2.io.in[0].valid, _out_arb_io_in_0_valid_T_2 connect out_arb_2.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_2.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_2.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_2.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_2.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_2 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_2.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_2 when sel_2 : connect nodeIn.req.ready, out_arb_2.io.in[0].ready connect x1_nodeOut_1.req.bits, out_arb_2.io.out.bits connect x1_nodeOut_1.req.valid, out_arb_2.io.out.valid connect out_arb_2.io.out.ready, x1_nodeOut_1.req.ready inst out_arb_3 of ReRoCCMsgArbiter_9 connect out_arb_3.clock, clock connect out_arb_3.reset, reset node sel_3 = eq(UInt<2>(0h3), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_3 = and(nodeIn.req.valid, sel_3) connect out_arb_3.io.in[0].valid, _out_arb_io_in_0_valid_T_3 connect out_arb_3.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_3.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_3.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_3.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_3.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_3 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_3.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_3 when sel_3 : connect nodeIn.req.ready, out_arb_3.io.in[0].ready connect x1_nodeOut_2.req.bits, out_arb_3.io.out.bits connect x1_nodeOut_2.req.valid, out_arb_3.io.out.valid connect out_arb_3.io.out.ready, x1_nodeOut_2.req.ready inst out_arb_4 of ReRoCCMsgArbiter_10 connect out_arb_4.clock, clock connect out_arb_4.reset, reset node sel_4 = eq(UInt<3>(0h4), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_4 = and(nodeIn.req.valid, sel_4) connect out_arb_4.io.in[0].valid, _out_arb_io_in_0_valid_T_4 connect out_arb_4.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_4.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_4.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_4.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_4.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_4 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_4.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_4 when sel_4 : connect nodeIn.req.ready, out_arb_4.io.in[0].ready connect x1_nodeOut_3.req.bits, out_arb_4.io.out.bits connect x1_nodeOut_3.req.valid, out_arb_4.io.out.valid connect out_arb_4.io.out.ready, x1_nodeOut_3.req.ready connect nodeOut.resp.ready, UInt<1>(0h0) connect x1_nodeOut.resp.ready, UInt<1>(0h0) connect x1_nodeOut_1.resp.ready, UInt<1>(0h0) connect x1_nodeOut_2.resp.ready, UInt<1>(0h0) connect x1_nodeOut_3.resp.ready, UInt<1>(0h0) inst in_arb of ReRoCCMsgArbiter_11 connect in_arb.clock, clock connect in_arb.reset, reset node _sel_T = leq(UInt<1>(0h0), nodeOut.resp.bits.client_id) node _sel_T_1 = gt(UInt<5>(0h10), nodeOut.resp.bits.client_id) node sel_5 = and(_sel_T, _sel_T_1) node _in_arb_io_in_0_valid_T = and(nodeOut.resp.valid, sel_5) connect in_arb.io.in[0].valid, _in_arb_io_in_0_valid_T connect in_arb.io.in[0].bits.data, nodeOut.resp.bits.data connect in_arb.io.in[0].bits.manager_id, nodeOut.resp.bits.manager_id connect in_arb.io.in[0].bits.client_id, nodeOut.resp.bits.client_id connect in_arb.io.in[0].bits.opcode, nodeOut.resp.bits.opcode node _in_arb_io_in_0_bits_client_id_T = sub(nodeOut.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_0_bits_client_id_T_1 = tail(_in_arb_io_in_0_bits_client_id_T, 1) connect in_arb.io.in[0].bits.client_id, _in_arb_io_in_0_bits_client_id_T_1 connect in_arb.io.in[0].bits.manager_id, nodeOut.resp.bits.manager_id when sel_5 : connect nodeOut.resp.ready, in_arb.io.in[0].ready node _sel_T_2 = leq(UInt<1>(0h0), x1_nodeOut.resp.bits.client_id) node _sel_T_3 = gt(UInt<5>(0h10), x1_nodeOut.resp.bits.client_id) node sel_6 = and(_sel_T_2, _sel_T_3) node _in_arb_io_in_1_valid_T = and(x1_nodeOut.resp.valid, sel_6) connect in_arb.io.in[1].valid, _in_arb_io_in_1_valid_T connect in_arb.io.in[1].bits.data, x1_nodeOut.resp.bits.data connect in_arb.io.in[1].bits.manager_id, x1_nodeOut.resp.bits.manager_id connect in_arb.io.in[1].bits.client_id, x1_nodeOut.resp.bits.client_id connect in_arb.io.in[1].bits.opcode, x1_nodeOut.resp.bits.opcode node _in_arb_io_in_1_bits_client_id_T = sub(x1_nodeOut.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_1_bits_client_id_T_1 = tail(_in_arb_io_in_1_bits_client_id_T, 1) connect in_arb.io.in[1].bits.client_id, _in_arb_io_in_1_bits_client_id_T_1 connect in_arb.io.in[1].bits.manager_id, x1_nodeOut.resp.bits.manager_id when sel_6 : connect x1_nodeOut.resp.ready, in_arb.io.in[1].ready node _sel_T_4 = leq(UInt<1>(0h0), x1_nodeOut_1.resp.bits.client_id) node _sel_T_5 = gt(UInt<5>(0h10), x1_nodeOut_1.resp.bits.client_id) node sel_7 = and(_sel_T_4, _sel_T_5) node _in_arb_io_in_2_valid_T = and(x1_nodeOut_1.resp.valid, sel_7) connect in_arb.io.in[2].valid, _in_arb_io_in_2_valid_T connect in_arb.io.in[2].bits.data, x1_nodeOut_1.resp.bits.data connect in_arb.io.in[2].bits.manager_id, x1_nodeOut_1.resp.bits.manager_id connect in_arb.io.in[2].bits.client_id, x1_nodeOut_1.resp.bits.client_id connect in_arb.io.in[2].bits.opcode, x1_nodeOut_1.resp.bits.opcode node _in_arb_io_in_2_bits_client_id_T = sub(x1_nodeOut_1.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_2_bits_client_id_T_1 = tail(_in_arb_io_in_2_bits_client_id_T, 1) connect in_arb.io.in[2].bits.client_id, _in_arb_io_in_2_bits_client_id_T_1 connect in_arb.io.in[2].bits.manager_id, x1_nodeOut_1.resp.bits.manager_id when sel_7 : connect x1_nodeOut_1.resp.ready, in_arb.io.in[2].ready node _sel_T_6 = leq(UInt<1>(0h0), x1_nodeOut_2.resp.bits.client_id) node _sel_T_7 = gt(UInt<5>(0h10), x1_nodeOut_2.resp.bits.client_id) node sel_8 = and(_sel_T_6, _sel_T_7) node _in_arb_io_in_3_valid_T = and(x1_nodeOut_2.resp.valid, sel_8) connect in_arb.io.in[3].valid, _in_arb_io_in_3_valid_T connect in_arb.io.in[3].bits.data, x1_nodeOut_2.resp.bits.data connect in_arb.io.in[3].bits.manager_id, x1_nodeOut_2.resp.bits.manager_id connect in_arb.io.in[3].bits.client_id, x1_nodeOut_2.resp.bits.client_id connect in_arb.io.in[3].bits.opcode, x1_nodeOut_2.resp.bits.opcode node _in_arb_io_in_3_bits_client_id_T = sub(x1_nodeOut_2.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_3_bits_client_id_T_1 = tail(_in_arb_io_in_3_bits_client_id_T, 1) connect in_arb.io.in[3].bits.client_id, _in_arb_io_in_3_bits_client_id_T_1 connect in_arb.io.in[3].bits.manager_id, x1_nodeOut_2.resp.bits.manager_id when sel_8 : connect x1_nodeOut_2.resp.ready, in_arb.io.in[3].ready node _sel_T_8 = leq(UInt<1>(0h0), x1_nodeOut_3.resp.bits.client_id) node _sel_T_9 = gt(UInt<5>(0h10), x1_nodeOut_3.resp.bits.client_id) node sel_9 = and(_sel_T_8, _sel_T_9) node _in_arb_io_in_4_valid_T = and(x1_nodeOut_3.resp.valid, sel_9) connect in_arb.io.in[4].valid, _in_arb_io_in_4_valid_T connect in_arb.io.in[4].bits.data, x1_nodeOut_3.resp.bits.data connect in_arb.io.in[4].bits.manager_id, x1_nodeOut_3.resp.bits.manager_id connect in_arb.io.in[4].bits.client_id, x1_nodeOut_3.resp.bits.client_id connect in_arb.io.in[4].bits.opcode, x1_nodeOut_3.resp.bits.opcode node _in_arb_io_in_4_bits_client_id_T = sub(x1_nodeOut_3.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_4_bits_client_id_T_1 = tail(_in_arb_io_in_4_bits_client_id_T, 1) connect in_arb.io.in[4].bits.client_id, _in_arb_io_in_4_bits_client_id_T_1 connect in_arb.io.in[4].bits.manager_id, x1_nodeOut_3.resp.bits.manager_id when sel_9 : connect x1_nodeOut_3.resp.ready, in_arb.io.in[4].ready connect nodeIn.resp.bits, in_arb.io.out.bits connect nodeIn.resp.valid, in_arb.io.out.valid connect in_arb.io.out.ready, nodeIn.resp.ready	module ReRoCCXbar( // @[Xbar.scala:34:25] input clock, // @[Xbar.scala:34:25] input reset, // @[Xbar.scala:34:25] output auto_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_4_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_4_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_4_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_4_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_4_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_4_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_4_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_4_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_4_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_4_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_4_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_4_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_3_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_3_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_3_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_3_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_3_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_3_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_3_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_3_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_3_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_3_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_2_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_2_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_2_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_2_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_2_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_2_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_2_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_2_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_2_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_2_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_1_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_1_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_0_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_0_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_resp_bits_data // @[LazyModuleImp.scala:107:25] ); wire _out_arb_4_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_4_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_3_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_3_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_2_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_2_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_1_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_1_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire auto_in_req_valid_0 = auto_in_req_valid; // @[Xbar.scala:34:25] wire [2:0] auto_in_req_bits_opcode_0 = auto_in_req_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_in_req_bits_client_id_0 = auto_in_req_bits_client_id; // @[Xbar.scala:34:25] wire [2:0] auto_in_req_bits_manager_id_0 = auto_in_req_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_in_req_bits_data_0 = auto_in_req_bits_data; // @[Xbar.scala:34:25] wire auto_in_resp_ready_0 = auto_in_resp_ready; // @[Xbar.scala:34:25] wire auto_out_4_req_ready_0 = auto_out_4_req_ready; // @[Xbar.scala:34:25] wire auto_out_4_resp_valid_0 = auto_out_4_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_4_resp_bits_opcode_0 = auto_out_4_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_4_resp_bits_client_id_0 = auto_out_4_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_4_resp_bits_manager_id_0 = auto_out_4_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_4_resp_bits_data_0 = auto_out_4_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_3_req_ready_0 = auto_out_3_req_ready; // @[Xbar.scala:34:25] wire auto_out_3_resp_valid_0 = auto_out_3_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_3_resp_bits_opcode_0 = auto_out_3_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_3_resp_bits_client_id_0 = auto_out_3_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_3_resp_bits_manager_id_0 = auto_out_3_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_3_resp_bits_data_0 = auto_out_3_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_2_req_ready_0 = auto_out_2_req_ready; // @[Xbar.scala:34:25] wire auto_out_2_resp_valid_0 = auto_out_2_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_2_resp_bits_opcode_0 = auto_out_2_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_2_resp_bits_client_id_0 = auto_out_2_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_2_resp_bits_manager_id_0 = auto_out_2_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_2_resp_bits_data_0 = auto_out_2_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_1_req_ready_0 = auto_out_1_req_ready; // @[Xbar.scala:34:25] wire auto_out_1_resp_valid_0 = auto_out_1_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_1_resp_bits_opcode_0 = auto_out_1_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_1_resp_bits_client_id_0 = auto_out_1_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_1_resp_bits_manager_id_0 = auto_out_1_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_1_resp_bits_data_0 = auto_out_1_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_0_req_ready_0 = auto_out_0_req_ready; // @[Xbar.scala:34:25] wire auto_out_0_resp_valid_0 = auto_out_0_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_0_resp_bits_opcode_0 = auto_out_0_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_0_resp_bits_client_id_0 = auto_out_0_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_0_resp_bits_manager_id_0 = auto_out_0_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_0_resp_bits_data_0 = auto_out_0_resp_bits_data; // @[Xbar.scala:34:25] wire nodeIn_req_ready; // @[MixedNode.scala:551:17] wire _sel_T = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_1 = 1'h1; // @[Xbar.scala:26:77] wire sel_5 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_2 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_3 = 1'h1; // @[Xbar.scala:26:77] wire sel_6 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_4 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_5 = 1'h1; // @[Xbar.scala:26:77] wire sel_7 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_6 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_7 = 1'h1; // @[Xbar.scala:26:77] wire sel_8 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_8 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_9 = 1'h1; // @[Xbar.scala:26:77] wire sel_9 = 1'h1; // @[Xbar.scala:26:46] wire nodeIn_req_valid = auto_in_req_valid_0; // @[Xbar.scala:34:25] wire [2:0] nodeIn_req_bits_opcode = auto_in_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] nodeIn_req_bits_client_id = auto_in_req_bits_client_id_0; // @[Xbar.scala:34:25] wire [2:0] nodeIn_req_bits_manager_id = auto_in_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] nodeIn_req_bits_data = auto_in_req_bits_data_0; // @[Xbar.scala:34:25] wire nodeIn_resp_ready = auto_in_resp_ready_0; // @[Xbar.scala:34:25] wire nodeIn_resp_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_resp_bits_data; // @[MixedNode.scala:551:17] wire x1_nodeOut_3_req_ready = auto_out_4_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_3_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_3_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_3_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_3_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_resp_valid = auto_out_4_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_3_resp_bits_opcode = auto_out_4_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_3_resp_bits_client_id = auto_out_4_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_3_resp_bits_manager_id = auto_out_4_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_3_resp_bits_data = auto_out_4_resp_bits_data_0; // @[Xbar.scala:34:25] wire x1_nodeOut_2_req_ready = auto_out_3_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_2_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_2_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_2_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_2_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_resp_valid = auto_out_3_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_2_resp_bits_opcode = auto_out_3_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_2_resp_bits_client_id = auto_out_3_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_2_resp_bits_manager_id = auto_out_3_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_2_resp_bits_data = auto_out_3_resp_bits_data_0; // @[Xbar.scala:34:25] wire x1_nodeOut_1_req_ready = auto_out_2_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_1_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_1_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_1_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_1_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_resp_valid = auto_out_2_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_1_resp_bits_opcode = auto_out_2_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_1_resp_bits_client_id = auto_out_2_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_1_resp_bits_manager_id = auto_out_2_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_1_resp_bits_data = auto_out_2_resp_bits_data_0; // @[Xbar.scala:34:25] wire x1_nodeOut_req_ready = auto_out_1_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_resp_valid = auto_out_1_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_resp_bits_opcode = auto_out_1_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_resp_bits_client_id = auto_out_1_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_resp_bits_manager_id = auto_out_1_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_resp_bits_data = auto_out_1_resp_bits_data_0; // @[Xbar.scala:34:25] wire nodeOut_req_ready = auto_out_0_req_ready_0; // @[Xbar.scala:34:25] wire nodeOut_req_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_req_bits_client_id; // @[MixedNode.scala:542:17] wire nodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_req_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_resp_ready; // @[MixedNode.scala:542:17] wire nodeOut_resp_valid = auto_out_0_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] nodeOut_resp_bits_opcode = auto_out_0_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] nodeOut_resp_bits_client_id = auto_out_0_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire nodeOut_resp_bits_manager_id = auto_out_0_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] nodeOut_resp_bits_data = auto_out_0_resp_bits_data_0; // @[Xbar.scala:34:25] wire auto_in_req_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_in_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_in_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire [2:0] auto_in_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_in_resp_bits_data_0; // @[Xbar.scala:34:25] wire auto_in_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_4_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_4_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_4_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_4_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_4_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_4_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_3_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_3_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_3_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_3_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_3_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_3_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_2_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_2_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_2_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_2_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_2_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_2_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_1_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_1_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_1_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_1_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_1_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_1_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_0_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_0_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_0_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_0_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_0_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_0_resp_ready_0; // @[Xbar.scala:34:25] assign auto_in_req_ready_0 = nodeIn_req_ready; // @[Xbar.scala:34:25] assign auto_in_resp_valid_0 = nodeIn_resp_valid; // @[Xbar.scala:34:25] assign auto_in_resp_bits_opcode_0 = nodeIn_resp_bits_opcode; // @[Xbar.scala:34:25] assign auto_in_resp_bits_client_id_0 = nodeIn_resp_bits_client_id; // @[Xbar.scala:34:25] assign auto_in_resp_bits_manager_id_0 = nodeIn_resp_bits_manager_id; // @[Xbar.scala:34:25] assign auto_in_resp_bits_data_0 = nodeIn_resp_bits_data; // @[Xbar.scala:34:25] assign auto_out_0_req_valid_0 = nodeOut_req_valid; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_opcode_0 = nodeOut_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_client_id_0 = nodeOut_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_manager_id_0 = nodeOut_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_data_0 = nodeOut_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_0_resp_ready_0 = nodeOut_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_0_valid_T = nodeOut_resp_valid; // @[Xbar.scala:69:42] assign auto_out_1_req_valid_0 = x1_nodeOut_req_valid; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_opcode_0 = x1_nodeOut_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_client_id_0 = x1_nodeOut_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_manager_id_0 = x1_nodeOut_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_data_0 = x1_nodeOut_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_1_resp_ready_0 = x1_nodeOut_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_1_valid_T = x1_nodeOut_resp_valid; // @[Xbar.scala:69:42] assign auto_out_2_req_valid_0 = x1_nodeOut_1_req_valid; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_opcode_0 = x1_nodeOut_1_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_client_id_0 = x1_nodeOut_1_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_manager_id_0 = x1_nodeOut_1_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_data_0 = x1_nodeOut_1_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_2_resp_ready_0 = x1_nodeOut_1_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_2_valid_T = x1_nodeOut_1_resp_valid; // @[Xbar.scala:69:42] assign auto_out_3_req_valid_0 = x1_nodeOut_2_req_valid; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_opcode_0 = x1_nodeOut_2_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_client_id_0 = x1_nodeOut_2_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_manager_id_0 = x1_nodeOut_2_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_data_0 = x1_nodeOut_2_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_3_resp_ready_0 = x1_nodeOut_2_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_3_valid_T = x1_nodeOut_2_resp_valid; // @[Xbar.scala:69:42] assign auto_out_4_req_valid_0 = x1_nodeOut_3_req_valid; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_opcode_0 = x1_nodeOut_3_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_client_id_0 = x1_nodeOut_3_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_manager_id_0 = x1_nodeOut_3_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_data_0 = x1_nodeOut_3_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_4_resp_ready_0 = x1_nodeOut_3_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_4_valid_T = x1_nodeOut_3_resp_valid; // @[Xbar.scala:69:42] wire sel = nodeIn_req_bits_manager_id == 3'h0; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T = nodeIn_req_valid & sel; // @[Xbar.scala:49:67, :50:40] wire [4:0] _GEN = {1'h0, nodeIn_req_bits_client_id}; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_1; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_1 = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_2; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_2 = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_3; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_3 = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_4; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_4 = _GEN; // @[Xbar.scala:28:87] assign nodeOut_req_bits_manager_id = _out_arb_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_1 = nodeIn_req_bits_manager_id == 3'h1; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_1 = nodeIn_req_valid & sel_1; // @[Xbar.scala:49:67, :50:40] assign x1_nodeOut_req_bits_manager_id = _out_arb_1_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_2 = nodeIn_req_bits_manager_id == 3'h2; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_2 = nodeIn_req_valid & sel_2; // @[Xbar.scala:49:67, :50:40] assign x1_nodeOut_1_req_bits_manager_id = _out_arb_2_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_3 = nodeIn_req_bits_manager_id == 3'h3; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_3 = nodeIn_req_valid & sel_3; // @[Xbar.scala:49:67, :50:40] assign x1_nodeOut_2_req_bits_manager_id = _out_arb_3_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_4 = nodeIn_req_bits_manager_id == 3'h4; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_4 = nodeIn_req_valid & sel_4; // @[Xbar.scala:49:67, :50:40] assign nodeIn_req_ready = sel_4 ? _out_arb_4_io_in_0_ready : sel_3 ? _out_arb_3_io_in_0_ready : sel_2 ? _out_arb_2_io_in_0_ready : sel_1 ? _out_arb_1_io_in_0_ready : sel & _out_arb_io_in_0_ready; // @[Xbar.scala:42:31, :47:27, :49:67, :54:20, :55:31] assign x1_nodeOut_3_req_bits_manager_id = _out_arb_4_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire [4:0] _in_arb_io_in_0_bits_client_id_T = {1'h0, nodeOut_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_0_bits_client_id_T_1 = _in_arb_io_in_0_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_1_bits_client_id_T = {1'h0, x1_nodeOut_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_1_bits_client_id_T_1 = _in_arb_io_in_1_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_2_bits_client_id_T = {1'h0, x1_nodeOut_1_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_2_bits_client_id_T_1 = _in_arb_io_in_2_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_3_bits_client_id_T = {1'h0, x1_nodeOut_2_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_3_bits_client_id_T_1 = _in_arb_io_in_3_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_4_bits_client_id_T = {1'h0, x1_nodeOut_3_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_4_bits_client_id_T_1 = _in_arb_io_in_4_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] ReRoCCMsgArbiter_6 out_arb ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (nodeOut_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (nodeOut_req_valid), .io_out_bits_opcode (nodeOut_req_bits_opcode), .io_out_bits_client_id (nodeOut_req_bits_client_id), .io_out_bits_manager_id (_out_arb_io_out_bits_manager_id), .io_out_bits_data (nodeOut_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_7 out_arb_1 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_1_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_1), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_1[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_req_valid), .io_out_bits_opcode (x1_nodeOut_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_req_bits_client_id), .io_out_bits_manager_id (_out_arb_1_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_8 out_arb_2 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_2_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_2), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_2[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_1_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_1_req_valid), .io_out_bits_opcode (x1_nodeOut_1_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_1_req_bits_client_id), .io_out_bits_manager_id (_out_arb_2_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_1_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_9 out_arb_3 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_3_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_3), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_3[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_2_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_2_req_valid), .io_out_bits_opcode (x1_nodeOut_2_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_2_req_bits_client_id), .io_out_bits_manager_id (_out_arb_3_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_2_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_10 out_arb_4 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_4_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_4), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_4[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_3_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_3_req_valid), .io_out_bits_opcode (x1_nodeOut_3_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_3_req_bits_client_id), .io_out_bits_manager_id (_out_arb_4_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_3_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_11 in_arb ( // @[Xbar.scala:64:26] .clock (clock), .reset (reset), .io_in_0_ready (nodeOut_resp_ready), .io_in_0_valid (_in_arb_io_in_0_valid_T), // @[Xbar.scala:69:42] .io_in_0_bits_opcode (nodeOut_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_0_bits_client_id (_in_arb_io_in_0_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_0_bits_manager_id ({2'h0, nodeOut_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_0_bits_data (nodeOut_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_1_ready (x1_nodeOut_resp_ready), .io_in_1_valid (_in_arb_io_in_1_valid_T), // @[Xbar.scala:69:42] .io_in_1_bits_opcode (x1_nodeOut_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_1_bits_client_id (_in_arb_io_in_1_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_1_bits_manager_id ({2'h0, x1_nodeOut_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_1_bits_data (x1_nodeOut_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_2_ready (x1_nodeOut_1_resp_ready), .io_in_2_valid (_in_arb_io_in_2_valid_T), // @[Xbar.scala:69:42] .io_in_2_bits_opcode (x1_nodeOut_1_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_2_bits_client_id (_in_arb_io_in_2_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_2_bits_manager_id ({2'h0, x1_nodeOut_1_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_2_bits_data (x1_nodeOut_1_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_3_ready (x1_nodeOut_2_resp_ready), .io_in_3_valid (_in_arb_io_in_3_valid_T), // @[Xbar.scala:69:42] .io_in_3_bits_opcode (x1_nodeOut_2_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_3_bits_client_id (_in_arb_io_in_3_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_3_bits_manager_id ({2'h0, x1_nodeOut_2_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_3_bits_data (x1_nodeOut_2_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_4_ready (x1_nodeOut_3_resp_ready), .io_in_4_valid (_in_arb_io_in_4_valid_T), // @[Xbar.scala:69:42] .io_in_4_bits_opcode (x1_nodeOut_3_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_4_bits_client_id (_in_arb_io_in_4_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_4_bits_manager_id ({2'h0, x1_nodeOut_3_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_4_bits_data (x1_nodeOut_3_resp_bits_data), // @[MixedNode.scala:542:17] .io_out_ready (nodeIn_resp_ready), // @[MixedNode.scala:551:17] .io_out_valid (nodeIn_resp_valid), .io_out_bits_opcode (nodeIn_resp_bits_opcode), .io_out_bits_client_id (nodeIn_resp_bits_client_id), .io_out_bits_manager_id (nodeIn_resp_bits_manager_id), .io_out_bits_data (nodeIn_resp_bits_data) ); // @[Xbar.scala:64:26] assign auto_in_req_ready = auto_in_req_ready_0; // @[Xbar.scala:34:25] assign auto_in_resp_valid = auto_in_resp_valid_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_opcode = auto_in_resp_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_client_id = auto_in_resp_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_manager_id = auto_in_resp_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_data = auto_in_resp_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_4_req_valid = auto_out_4_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_opcode = auto_out_4_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_client_id = auto_out_4_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_manager_id = auto_out_4_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_data = auto_out_4_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_4_resp_ready = auto_out_4_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_3_req_valid = auto_out_3_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_opcode = auto_out_3_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_client_id = auto_out_3_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_manager_id = auto_out_3_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_data = auto_out_3_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_3_resp_ready = auto_out_3_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_2_req_valid = auto_out_2_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_opcode = auto_out_2_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_client_id = auto_out_2_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_manager_id = auto_out_2_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_data = auto_out_2_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_2_resp_ready = auto_out_2_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_1_req_valid = auto_out_1_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_opcode = auto_out_1_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_client_id = auto_out_1_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_manager_id = auto_out_1_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_data = auto_out_1_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_1_resp_ready = auto_out_1_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_0_req_valid = auto_out_0_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_opcode = auto_out_0_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_client_id = auto_out_0_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_manager_id = auto_out_0_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_data = auto_out_0_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_0_resp_ready = auto_out_0_resp_ready_0; // @[Xbar.scala:34:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FullyPortedRF_2 : input clock : Clock input reset : Reset output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<6>}[6], rrd_read_resps : UInt<64>[6], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<64>}}[5]} node _T = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr) node _T_4 = or(_T_2, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _T_8 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_9 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_10 = or(_T_8, _T_9) node _T_11 = neq(io.write_ports[0].bits.addr, io.write_ports[2].bits.addr) node _T_12 = or(_T_10, _T_11) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_1 assert(clock, _T_12, UInt<1>(0h1), "") : assert_1 node _T_16 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_17 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_18 = or(_T_16, _T_17) node _T_19 = neq(io.write_ports[0].bits.addr, io.write_ports[3].bits.addr) node _T_20 = or(_T_18, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 node _T_24 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_25 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_26 = or(_T_24, _T_25) node _T_27 = neq(io.write_ports[0].bits.addr, io.write_ports[4].bits.addr) node _T_28 = or(_T_26, _T_27) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_3 assert(clock, _T_28, UInt<1>(0h1), "") : assert_3 node _T_32 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_33 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_34 = or(_T_32, _T_33) node _T_35 = neq(io.write_ports[1].bits.addr, io.write_ports[2].bits.addr) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_4 assert(clock, _T_36, UInt<1>(0h1), "") : assert_4 node _T_40 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_41 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = neq(io.write_ports[1].bits.addr, io.write_ports[3].bits.addr) node _T_44 = or(_T_42, _T_43) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_5 assert(clock, _T_44, UInt<1>(0h1), "") : assert_5 node _T_48 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_49 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_50 = or(_T_48, _T_49) node _T_51 = neq(io.write_ports[1].bits.addr, io.write_ports[4].bits.addr) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_6 assert(clock, _T_52, UInt<1>(0h1), "") : assert_6 node _T_56 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_57 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_58 = or(_T_56, _T_57) node _T_59 = neq(io.write_ports[2].bits.addr, io.write_ports[3].bits.addr) node _T_60 = or(_T_58, _T_59) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_7 assert(clock, _T_60, UInt<1>(0h1), "") : assert_7 node _T_64 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_65 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_66 = or(_T_64, _T_65) node _T_67 = neq(io.write_ports[2].bits.addr, io.write_ports[4].bits.addr) node _T_68 = or(_T_66, _T_67) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_8 assert(clock, _T_68, UInt<1>(0h1), "") : assert_8 node _T_72 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_73 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_74 = or(_T_72, _T_73) node _T_75 = neq(io.write_ports[3].bits.addr, io.write_ports[4].bits.addr) node _T_76 = or(_T_74, _T_75) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid \|\|\n") : printf_9 assert(clock, _T_76, UInt<1>(0h1), "") : assert_9 connect io.arb_read_reqs[0].ready, UInt<1>(0h1) connect io.arb_read_reqs[1].ready, UInt<1>(0h1) connect io.arb_read_reqs[2].ready, UInt<1>(0h1) connect io.arb_read_reqs[3].ready, UInt<1>(0h1) connect io.arb_read_reqs[4].ready, UInt<1>(0h1) connect io.arb_read_reqs[5].ready, UInt<1>(0h1) cmem regfile : UInt<64> [50] reg io_rrd_read_resps_0_REG : UInt, clock connect io_rrd_read_resps_0_REG, io.arb_read_reqs[0].bits node _io_rrd_read_resps_0_T = or(io_rrd_read_resps_0_REG, UInt<6>(0h0)) node _io_rrd_read_resps_0_T_1 = bits(_io_rrd_read_resps_0_T, 5, 0) infer mport io_rrd_read_resps_0_MPORT = regfile[_io_rrd_read_resps_0_T_1], clock connect io.rrd_read_resps[0], io_rrd_read_resps_0_MPORT reg io_rrd_read_resps_1_REG : UInt, clock connect io_rrd_read_resps_1_REG, io.arb_read_reqs[1].bits node _io_rrd_read_resps_1_T = or(io_rrd_read_resps_1_REG, UInt<6>(0h0)) node _io_rrd_read_resps_1_T_1 = bits(_io_rrd_read_resps_1_T, 5, 0) infer mport io_rrd_read_resps_1_MPORT = regfile[_io_rrd_read_resps_1_T_1], clock connect io.rrd_read_resps[1], io_rrd_read_resps_1_MPORT reg io_rrd_read_resps_2_REG : UInt, clock connect io_rrd_read_resps_2_REG, io.arb_read_reqs[2].bits node _io_rrd_read_resps_2_T = or(io_rrd_read_resps_2_REG, UInt<6>(0h0)) node _io_rrd_read_resps_2_T_1 = bits(_io_rrd_read_resps_2_T, 5, 0) infer mport io_rrd_read_resps_2_MPORT = regfile[_io_rrd_read_resps_2_T_1], clock connect io.rrd_read_resps[2], io_rrd_read_resps_2_MPORT reg io_rrd_read_resps_3_REG : UInt, clock connect io_rrd_read_resps_3_REG, io.arb_read_reqs[3].bits node _io_rrd_read_resps_3_T = or(io_rrd_read_resps_3_REG, UInt<6>(0h0)) node _io_rrd_read_resps_3_T_1 = bits(_io_rrd_read_resps_3_T, 5, 0) infer mport io_rrd_read_resps_3_MPORT = regfile[_io_rrd_read_resps_3_T_1], clock connect io.rrd_read_resps[3], io_rrd_read_resps_3_MPORT reg io_rrd_read_resps_4_REG : UInt, clock connect io_rrd_read_resps_4_REG, io.arb_read_reqs[4].bits node _io_rrd_read_resps_4_T = or(io_rrd_read_resps_4_REG, UInt<6>(0h0)) node _io_rrd_read_resps_4_T_1 = bits(_io_rrd_read_resps_4_T, 5, 0) infer mport io_rrd_read_resps_4_MPORT = regfile[_io_rrd_read_resps_4_T_1], clock connect io.rrd_read_resps[4], io_rrd_read_resps_4_MPORT reg io_rrd_read_resps_5_REG : UInt, clock connect io_rrd_read_resps_5_REG, io.arb_read_reqs[5].bits node _io_rrd_read_resps_5_T = or(io_rrd_read_resps_5_REG, UInt<6>(0h0)) node _io_rrd_read_resps_5_T_1 = bits(_io_rrd_read_resps_5_T, 5, 0) infer mport io_rrd_read_resps_5_MPORT = regfile[_io_rrd_read_resps_5_T_1], clock connect io.rrd_read_resps[5], io_rrd_read_resps_5_MPORT when io.write_ports[0].valid : node _T_80 = bits(io.write_ports[0].bits.addr, 5, 0) infer mport MPORT = regfile[_T_80], clock connect MPORT, io.write_ports[0].bits.data when io.write_ports[1].valid : node _T_81 = bits(io.write_ports[1].bits.addr, 5, 0) infer mport MPORT_1 = regfile[_T_81], clock connect MPORT_1, io.write_ports[1].bits.data when io.write_ports[2].valid : node _T_82 = bits(io.write_ports[2].bits.addr, 5, 0) infer mport MPORT_2 = regfile[_T_82], clock connect MPORT_2, io.write_ports[2].bits.data when io.write_ports[3].valid : node _T_83 = bits(io.write_ports[3].bits.addr, 5, 0) infer mport MPORT_3 = regfile[_T_83], clock connect MPORT_3, io.write_ports[3].bits.data when io.write_ports[4].valid : node _T_84 = bits(io.write_ports[4].bits.addr, 5, 0) infer mport MPORT_4 = regfile[_T_84], clock connect MPORT_4, io.write_ports[4].bits.data	module FullyPortedRF_2( // @[regfile.scala:186:7] input clock, // @[regfile.scala:186:7] input reset, // @[regfile.scala:186:7] input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_3_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_3_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_4_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_4_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_5_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_5_bits, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_0, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_1, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_2, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_3, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_4, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_5, // @[regfile.scala:31:14] input io_write_ports_0_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14] input io_write_ports_1_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_1_bits_data, // @[regfile.scala:31:14] input io_write_ports_2_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_2_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_2_bits_data, // @[regfile.scala:31:14] input io_write_ports_3_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_3_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_3_bits_data, // @[regfile.scala:31:14] input io_write_ports_4_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_4_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_4_bits_data // @[regfile.scala:31:14] ); wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_3_valid_0 = io_arb_read_reqs_3_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_3_bits_0 = io_arb_read_reqs_3_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_4_valid_0 = io_arb_read_reqs_4_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_4_bits_0 = io_arb_read_reqs_4_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_5_valid_0 = io_arb_read_reqs_5_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_5_bits_0 = io_arb_read_reqs_5_bits; // @[regfile.scala:186:7] wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:186:7] wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:186:7] wire io_write_ports_2_valid_0 = io_write_ports_2_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_2_bits_addr_0 = io_write_ports_2_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_2_bits_data_0 = io_write_ports_2_bits_data; // @[regfile.scala:186:7] wire io_write_ports_3_valid_0 = io_write_ports_3_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_3_bits_addr_0 = io_write_ports_3_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_3_bits_data_0 = io_write_ports_3_bits_data; // @[regfile.scala:186:7] wire io_write_ports_4_valid_0 = io_write_ports_4_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_4_bits_addr_0 = io_write_ports_4_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_4_bits_data_0 = io_write_ports_4_bits_data; // @[regfile.scala:186:7] wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_3_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_4_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_5_ready = 1'h1; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_0_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_1_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_2_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_3_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_4_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_5_0; // @[regfile.scala:186:7]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_37 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_51 = and(io.pred_wakeup_port.valid, _T_50) when _T_51 : connect ppred, UInt<1>(0h1) node _T_52 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_59 = and(io.spec_ld_wakeup[0].valid, _T_58) node _T_60 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) when _T_61 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_62 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_62, UInt<1>(0h1), "") : assert_4 node _T_66 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_67 = and(io.spec_ld_wakeup[0].valid, _T_66) node _T_68 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_69 = and(_T_67, _T_68) when _T_69 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_70 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_74 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_75 = neq(_T_74, UInt<1>(0h0)) when _T_75 : connect next_state, UInt<2>(0h0) node _T_76 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_76 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_77 = eq(state, UInt<2>(0h1)) when _T_77 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_78 = eq(state, UInt<2>(0h2)) when _T_78 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_79 = eq(state, UInt<2>(0h2)) when _T_79 : node _T_80 = and(p1, p2) node _T_81 = and(_T_80, ppred) when _T_81 : skip else : node _T_82 = and(p1, ppred) when _T_82 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_83 = and(p2, ppred) when _T_83 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_37( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module TagMan : input clock : Clock input reset : Reset output io : { available : UInt<1>, tagOut : UInt<3>, flip take : UInt<1>, flip put : UInt<1>, flip tagIn : UInt<3>} regreset inUse_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_5 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_6 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_7 : UInt<1>, clock, reset, UInt<1>(0h0) regreset nextTag : UInt<3>, clock, reset, UInt<3>(0h0) connect io.tagOut, nextTag node _io_available_T = eq(UInt<1>(0h1), nextTag) node _io_available_T_1 = mux(_io_available_T, inUse_1, inUse_0) node _io_available_T_2 = eq(UInt<2>(0h2), nextTag) node _io_available_T_3 = mux(_io_available_T_2, inUse_2, _io_available_T_1) node _io_available_T_4 = eq(UInt<2>(0h3), nextTag) node _io_available_T_5 = mux(_io_available_T_4, inUse_3, _io_available_T_3) node _io_available_T_6 = eq(UInt<3>(0h4), nextTag) node _io_available_T_7 = mux(_io_available_T_6, inUse_4, _io_available_T_5) node _io_available_T_8 = eq(UInt<3>(0h5), nextTag) node _io_available_T_9 = mux(_io_available_T_8, inUse_5, _io_available_T_7) node _io_available_T_10 = eq(UInt<3>(0h6), nextTag) node _io_available_T_11 = mux(_io_available_T_10, inUse_6, _io_available_T_9) node _io_available_T_12 = eq(UInt<3>(0h7), nextTag) node _io_available_T_13 = mux(_io_available_T_12, inUse_7, _io_available_T_11) node _io_available_T_14 = not(_io_available_T_13) connect io.available, _io_available_T_14 when io.take : node _T = eq(UInt<1>(0h0), nextTag) when _T : connect inUse_0, UInt<1>(0h1) node _T_1 = eq(UInt<1>(0h1), nextTag) when _T_1 : connect inUse_1, UInt<1>(0h1) node _T_2 = eq(UInt<2>(0h2), nextTag) when _T_2 : connect inUse_2, UInt<1>(0h1) node _T_3 = eq(UInt<2>(0h3), nextTag) when _T_3 : connect inUse_3, UInt<1>(0h1) node _T_4 = eq(UInt<3>(0h4), nextTag) when _T_4 : connect inUse_4, UInt<1>(0h1) node _T_5 = eq(UInt<3>(0h5), nextTag) when _T_5 : connect inUse_5, UInt<1>(0h1) node _T_6 = eq(UInt<3>(0h6), nextTag) when _T_6 : connect inUse_6, UInt<1>(0h1) node _T_7 = eq(UInt<3>(0h7), nextTag) when _T_7 : connect inUse_7, UInt<1>(0h1) node _nextTag_T = add(nextTag, UInt<1>(0h1)) node _nextTag_T_1 = tail(_nextTag_T, 1) connect nextTag, _nextTag_T_1 when io.put : node _T_8 = eq(UInt<1>(0h0), io.tagIn) when _T_8 : connect inUse_0, UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h1), io.tagIn) when _T_9 : connect inUse_1, UInt<1>(0h0) node _T_10 = eq(UInt<2>(0h2), io.tagIn) when _T_10 : connect inUse_2, UInt<1>(0h0) node _T_11 = eq(UInt<2>(0h3), io.tagIn) when _T_11 : connect inUse_3, UInt<1>(0h0) node _T_12 = eq(UInt<3>(0h4), io.tagIn) when _T_12 : connect inUse_4, UInt<1>(0h0) node _T_13 = eq(UInt<3>(0h5), io.tagIn) when _T_13 : connect inUse_5, UInt<1>(0h0) node _T_14 = eq(UInt<3>(0h6), io.tagIn) when _T_14 : connect inUse_6, UInt<1>(0h0) node _T_15 = eq(UInt<3>(0h7), io.tagIn) when _T_15 : connect inUse_7, UInt<1>(0h0)	module TagMan( // @[TraceGen.scala:162:7] input clock, // @[TraceGen.scala:162:7] input reset, // @[TraceGen.scala:162:7] output io_available, // @[TraceGen.scala:163:14] output [2:0] io_tagOut, // @[TraceGen.scala:163:14] input io_take, // @[TraceGen.scala:163:14] input io_put, // @[TraceGen.scala:163:14] input [2:0] io_tagIn // @[TraceGen.scala:163:14] ); wire io_take_0 = io_take; // @[TraceGen.scala:162:7] wire io_put_0 = io_put; // @[TraceGen.scala:162:7] wire [2:0] io_tagIn_0 = io_tagIn; // @[TraceGen.scala:162:7] wire _io_available_T_14; // @[TraceGen.scala:190:19] wire io_available_0; // @[TraceGen.scala:162:7] wire [2:0] io_tagOut_0; // @[TraceGen.scala:162:7] reg inUse_0; // @[TraceGen.scala:180:41] reg inUse_1; // @[TraceGen.scala:180:41] reg inUse_2; // @[TraceGen.scala:180:41] reg inUse_3; // @[TraceGen.scala:180:41] reg inUse_4; // @[TraceGen.scala:180:41] reg inUse_5; // @[TraceGen.scala:180:41] reg inUse_6; // @[TraceGen.scala:180:41] reg inUse_7; // @[TraceGen.scala:180:41] reg [2:0] nextTag; // @[TraceGen.scala:186:24] assign io_tagOut_0 = nextTag; // @[TraceGen.scala:162:7, :186:24] wire _io_available_T = nextTag == 3'h1; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_1 = _io_available_T ? inUse_1 : inUse_0; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_2 = nextTag == 3'h2; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_3 = _io_available_T_2 ? inUse_2 : _io_available_T_1; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_4 = nextTag == 3'h3; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_5 = _io_available_T_4 ? inUse_3 : _io_available_T_3; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_6 = nextTag == 3'h4; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_7 = _io_available_T_6 ? inUse_4 : _io_available_T_5; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_8 = nextTag == 3'h5; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_9 = _io_available_T_8 ? inUse_5 : _io_available_T_7; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_10 = nextTag == 3'h6; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_11 = _io_available_T_10 ? inUse_6 : _io_available_T_9; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_12 = &nextTag; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_13 = _io_available_T_12 ? inUse_7 : _io_available_T_11; // @[TraceGen.scala:180:41, :190:46] assign _io_available_T_14 = ~_io_available_T_13; // @[TraceGen.scala:190:{19,46}] assign io_available_0 = _io_available_T_14; // @[TraceGen.scala:162:7, :190:19] wire [3:0] _nextTag_T = {1'h0, nextTag} + 4'h1; // @[TraceGen.scala:186:24, :197:24] wire [2:0] _nextTag_T_1 = _nextTag_T[2:0]; // @[TraceGen.scala:197:24] always @(posedge clock) begin // @[TraceGen.scala:162:7] if (reset) begin // @[TraceGen.scala:162:7] inUse_0 <= 1'h0; // @[TraceGen.scala:180:41] inUse_1 <= 1'h0; // @[TraceGen.scala:180:41] inUse_2 <= 1'h0; // @[TraceGen.scala:180:41] inUse_3 <= 1'h0; // @[TraceGen.scala:180:41] inUse_4 <= 1'h0; // @[TraceGen.scala:180:41] inUse_5 <= 1'h0; // @[TraceGen.scala:180:41] inUse_6 <= 1'h0; // @[TraceGen.scala:180:41] inUse_7 <= 1'h0; // @[TraceGen.scala:180:41] nextTag <= 3'h0; // @[TraceGen.scala:186:24] end else begin // @[TraceGen.scala:162:7] inUse_0 <= ~(io_put_0 & io_tagIn_0 == 3'h0) & (io_take_0 & nextTag == 3'h0 \| inUse_0); // @[TraceGen.scala:162:7, :180:41, :186:24, :193:18, :195:{15,28,32}, :201:17, :203:{15,29,33}] inUse_1 <= ~(io_put_0 & io_tagIn_0 == 3'h1) & (io_take_0 & _io_available_T \| inUse_1); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_2 <= ~(io_put_0 & io_tagIn_0 == 3'h2) & (io_take_0 & _io_available_T_2 \| inUse_2); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_3 <= ~(io_put_0 & io_tagIn_0 == 3'h3) & (io_take_0 & _io_available_T_4 \| inUse_3); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_4 <= ~(io_put_0 & io_tagIn_0 == 3'h4) & (io_take_0 & _io_available_T_6 \| inUse_4); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_5 <= ~(io_put_0 & io_tagIn_0 == 3'h5) & (io_take_0 & _io_available_T_8 \| inUse_5); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_6 <= ~(io_put_0 & io_tagIn_0 == 3'h6) & (io_take_0 & _io_available_T_10 \| inUse_6); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_7 <= ~(io_put_0 & (&io_tagIn_0)) & (io_take_0 & (&nextTag) \| inUse_7); // @[TraceGen.scala:162:7, :180:41, :186:24, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] if (io_take_0) // @[TraceGen.scala:162:7] nextTag <= _nextTag_T_1; // @[TraceGen.scala:186:24, :197:24] end always @(posedge) assign io_available = io_available_0; // @[TraceGen.scala:162:7] assign io_tagOut = io_tagOut_0; // @[TraceGen.scala:162:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_124 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_134 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_124( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_134 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_3 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_3( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 \| io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_17 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<20> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_12, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_14_1, decoded_andMatrixOutputs_andMatrixInput_15) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_12_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_8_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_14_2) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_13_3, decoded_andMatrixOutputs_andMatrixInput_14_3) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_11_3, decoded_andMatrixOutputs_andMatrixInput_12_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_14_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_15_2, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_5, decoded_andMatrixOutputs_andMatrixInput_14_5) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_2) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_14_6, decoded_andMatrixOutputs_andMatrixInput_15_3) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_lo_lo_lo_3) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_12_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_14_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_14_8, decoded_andMatrixOutputs_andMatrixInput_15_4) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_12_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_4) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_12_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_14_9) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_15_5, decoded_andMatrixOutputs_andMatrixInput_16_2) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_13_10, decoded_andMatrixOutputs_andMatrixInput_14_10) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_lo_lo_lo_5) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_11_10, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_12_11, decoded_andMatrixOutputs_andMatrixInput_13_11) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_14_11) node decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_10_11, decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_lo_hi_lo_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_11) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_11, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_15_6, decoded_andMatrixOutputs_andMatrixInput_16_3) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_13_12, decoded_andMatrixOutputs_andMatrixInput_14_12) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_lo_lo_lo_6) node decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_11_12, decoded_andMatrixOutputs_andMatrixInput_12_12) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_lo_hi_lo_12) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_hi_lo_lo_12) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_14_13, decoded_andMatrixOutputs_andMatrixInput_15_7) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_12_13, decoded_andMatrixOutputs_andMatrixInput_13_13) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_lo_lo_lo_7) node decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_10_13, decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_8_13, decoded_andMatrixOutputs_andMatrixInput_9_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_lo_hi_lo_13) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_hi_lo_lo_13) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_12_14, decoded_andMatrixOutputs_andMatrixInput_13_14) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_14_14) node decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_10_14, decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_8_14, decoded_andMatrixOutputs_andMatrixInput_9_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_lo_hi_lo_14) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_hi_lo_lo_14) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_14_15, decoded_andMatrixOutputs_andMatrixInput_15_8) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_12_15, decoded_andMatrixOutputs_andMatrixInput_13_15) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_lo_lo_lo_8) node decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_10_15, decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_8_15, decoded_andMatrixOutputs_andMatrixInput_9_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_lo_hi_lo_15) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_4_15, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_hi_lo_lo_15) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_12_16, decoded_andMatrixOutputs_andMatrixInput_13_16) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_14_16) node decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_8_16, decoded_andMatrixOutputs_andMatrixInput_9_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_16) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_hi_lo_lo_16) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_16, decoded_andMatrixOutputs_andMatrixInput_3_16) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_15_9, decoded_andMatrixOutputs_andMatrixInput_16_4) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_13_17, decoded_andMatrixOutputs_andMatrixInput_14_17) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_lo_lo_lo_9) node decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_11_17, decoded_andMatrixOutputs_andMatrixInput_12_17) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_lo_hi_lo_17) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_7_17, decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_hi_lo_lo_17) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_12_18, decoded_andMatrixOutputs_andMatrixInput_13_18) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_14_18) node decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_10_18, decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_8_18, decoded_andMatrixOutputs_andMatrixInput_9_18) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_lo_hi_lo_18) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_hi_lo_lo_18) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_15_10, decoded_andMatrixOutputs_andMatrixInput_16_5) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_13_19, decoded_andMatrixOutputs_andMatrixInput_14_19) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_lo_lo_lo_10) node decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_11_19, decoded_andMatrixOutputs_andMatrixInput_12_19) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_lo_hi_lo_19) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_19, decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_5_19, decoded_andMatrixOutputs_andMatrixInput_6_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_hi_lo_lo_19) node decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_19) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_14_20, decoded_andMatrixOutputs_andMatrixInput_15_11) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_12_20, decoded_andMatrixOutputs_andMatrixInput_13_20) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_lo_lo_lo_11) node decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_10_20, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_8_20, decoded_andMatrixOutputs_andMatrixInput_9_20) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_lo_hi_lo_20) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_4_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_hi_lo_lo_20) node decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_20) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_hi_hi_lo_20) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_8 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_6 = cat(decoded_orMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_20_2) node decoded_orMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_15_2, decoded_andMatrixOutputs_10_2) node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_7_2) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_6) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_7, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_7, decoded_orMatrixOutputs_hi_lo) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_7) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_8 = cat(decoded_orMatrixOutputs_lo_hi_8, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_8, decoded_orMatrixOutputs_hi_lo_1) node _decoded_orMatrixOutputs_T_16 = cat(decoded_orMatrixOutputs_hi_8, decoded_orMatrixOutputs_lo_8) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_9 = cat(decoded_orMatrixOutputs_lo_hi_9, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_9, decoded_orMatrixOutputs_hi_lo_2) node _decoded_orMatrixOutputs_T_18 = cat(decoded_orMatrixOutputs_hi_9, decoded_orMatrixOutputs_lo_9) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_10 = cat(decoded_orMatrixOutputs_lo_hi_10, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_10, decoded_orMatrixOutputs_hi_lo_3) node _decoded_orMatrixOutputs_T_20 = cat(decoded_orMatrixOutputs_hi_10, decoded_orMatrixOutputs_lo_10) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_11 = cat(decoded_orMatrixOutputs_lo_hi_11, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_11, decoded_orMatrixOutputs_hi_lo_4) node _decoded_orMatrixOutputs_T_22 = cat(decoded_orMatrixOutputs_hi_11, decoded_orMatrixOutputs_lo_11) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_12 = cat(decoded_orMatrixOutputs_lo_hi_12, decoded_orMatrixOutputs_lo_lo_5) node decoded_orMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_12, decoded_orMatrixOutputs_hi_lo_5) node _decoded_orMatrixOutputs_T_24 = cat(decoded_orMatrixOutputs_hi_12, decoded_orMatrixOutputs_lo_12) node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_13 = cat(decoded_orMatrixOutputs_lo_hi_13, decoded_orMatrixOutputs_lo_lo_6) node decoded_orMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_13, decoded_orMatrixOutputs_hi_lo_6) node _decoded_orMatrixOutputs_T_26 = cat(decoded_orMatrixOutputs_hi_13, decoded_orMatrixOutputs_lo_13) node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_lo_7 = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_decoded_orMatrixOutputs_T_15, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_lo_hi_14 = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo_14 = cat(decoded_orMatrixOutputs_lo_hi_14, decoded_orMatrixOutputs_lo_lo_7) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_25) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_7 = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_hi_7, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_14, decoded_orMatrixOutputs_hi_lo_7) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_14, decoded_orMatrixOutputs_lo_14) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo) node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_20, _decoded_invMatrixOutputs_T_19) node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, _decoded_invMatrixOutputs_T_21) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 15, 0) node _decoded_T_1 = shl(UInt<8>(0hff), 8) node _decoded_T_2 = xor(UInt<16>(0hffff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 8) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 7, 0) node _decoded_T_6 = shl(_decoded_T_5, 8) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 11, 0) node _decoded_T_11 = shl(_decoded_T_10, 4) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 4) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 11, 0) node _decoded_T_16 = shl(_decoded_T_15, 4) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 13, 0) node _decoded_T_21 = shl(_decoded_T_20, 2) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 2) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 13, 0) node _decoded_T_26 = shl(_decoded_T_25, 2) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(_decoded_T_22, 14, 0) node _decoded_T_31 = shl(_decoded_T_30, 1) node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31) node _decoded_T_33 = shr(_decoded_T_29, 1) node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32) node _decoded_T_35 = bits(_decoded_T_29, 14, 0) node _decoded_T_36 = shl(_decoded_T_35, 1) node _decoded_T_37 = not(_decoded_T_32) node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38) node _decoded_T_40 = bits(decoded_plaOutput, 23, 16) node _decoded_T_41 = shl(UInt<4>(0hf), 4) node _decoded_T_42 = xor(UInt<8>(0hff), _decoded_T_41) node _decoded_T_43 = shr(_decoded_T_40, 4) node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42) node _decoded_T_45 = bits(_decoded_T_40, 3, 0) node _decoded_T_46 = shl(_decoded_T_45, 4) node _decoded_T_47 = not(_decoded_T_42) node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47) node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48) node _decoded_T_50 = bits(_decoded_T_42, 5, 0) node _decoded_T_51 = shl(_decoded_T_50, 2) node _decoded_T_52 = xor(_decoded_T_42, _decoded_T_51) node _decoded_T_53 = shr(_decoded_T_49, 2) node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52) node _decoded_T_55 = bits(_decoded_T_49, 5, 0) node _decoded_T_56 = shl(_decoded_T_55, 2) node _decoded_T_57 = not(_decoded_T_52) node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57) node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58) node _decoded_T_60 = bits(_decoded_T_52, 6, 0) node _decoded_T_61 = shl(_decoded_T_60, 1) node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61) node _decoded_T_63 = shr(_decoded_T_59, 1) node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62) node _decoded_T_65 = bits(_decoded_T_59, 6, 0) node _decoded_T_66 = shl(_decoded_T_65, 1) node _decoded_T_67 = not(_decoded_T_62) node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67) node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68) node decoded = cat(_decoded_T_39, _decoded_T_69) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_1_3_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T node _io_resp_0_vc_sel_1_4_T = bits(decoded, 12, 12) connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T node _io_resp_0_vc_sel_1_5_T = bits(decoded, 13, 13) connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T node _io_resp_0_vc_sel_1_6_T = bits(decoded, 14, 14) connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T node _io_resp_0_vc_sel_1_7_T = bits(decoded, 15, 15) connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 16, 16) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 17, 17) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 18, 18) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_2_3_T = bits(decoded, 19, 19) connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T node _io_resp_0_vc_sel_2_4_T = bits(decoded, 20, 20) connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T node _io_resp_0_vc_sel_2_5_T = bits(decoded, 21, 21) connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T node _io_resp_0_vc_sel_2_6_T = bits(decoded, 22, 22) connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T node _io_resp_0_vc_sel_2_7_T = bits(decoded, 23, 23) connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<20> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_21) node _decoded_orMatrixOutputs_T_28 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_29 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_30 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_31 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_8 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_15 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_15 = cat(decoded_orMatrixOutputs_lo_hi_15, decoded_orMatrixOutputs_lo_lo_8) node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_29, _decoded_orMatrixOutputs_T_28) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_8 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_31) node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, _decoded_orMatrixOutputs_T_30) node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_hi_8, decoded_orMatrixOutputs_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_15, decoded_orMatrixOutputs_hi_lo_8) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_15, decoded_orMatrixOutputs_lo_15) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_1, 11, 11) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_1, 12, 12) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_1, 13, 13) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_1, 14, 14) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_1, 15, 15) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 16, 16) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 17, 17) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 18, 18) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 19, 19) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 20, 20) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 21, 21) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 22, 22) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, _decoded_invMatrixOutputs_T_42) node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_70 = bits(decoded_plaOutput_1, 15, 0) node _decoded_T_71 = shl(UInt<8>(0hff), 8) node _decoded_T_72 = xor(UInt<16>(0hffff), _decoded_T_71) node _decoded_T_73 = shr(_decoded_T_70, 8) node _decoded_T_74 = and(_decoded_T_73, _decoded_T_72) node _decoded_T_75 = bits(_decoded_T_70, 7, 0) node _decoded_T_76 = shl(_decoded_T_75, 8) node _decoded_T_77 = not(_decoded_T_72) node _decoded_T_78 = and(_decoded_T_76, _decoded_T_77) node _decoded_T_79 = or(_decoded_T_74, _decoded_T_78) node _decoded_T_80 = bits(_decoded_T_72, 11, 0) node _decoded_T_81 = shl(_decoded_T_80, 4) node _decoded_T_82 = xor(_decoded_T_72, _decoded_T_81) node _decoded_T_83 = shr(_decoded_T_79, 4) node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82) node _decoded_T_85 = bits(_decoded_T_79, 11, 0) node _decoded_T_86 = shl(_decoded_T_85, 4) node _decoded_T_87 = not(_decoded_T_82) node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87) node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88) node _decoded_T_90 = bits(_decoded_T_82, 13, 0) node _decoded_T_91 = shl(_decoded_T_90, 2) node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91) node _decoded_T_93 = shr(_decoded_T_89, 2) node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92) node _decoded_T_95 = bits(_decoded_T_89, 13, 0) node _decoded_T_96 = shl(_decoded_T_95, 2) node _decoded_T_97 = not(_decoded_T_92) node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97) node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98) node _decoded_T_100 = bits(_decoded_T_92, 14, 0) node _decoded_T_101 = shl(_decoded_T_100, 1) node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101) node _decoded_T_103 = shr(_decoded_T_99, 1) node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102) node _decoded_T_105 = bits(_decoded_T_99, 14, 0) node _decoded_T_106 = shl(_decoded_T_105, 1) node _decoded_T_107 = not(_decoded_T_102) node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107) node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108) node _decoded_T_110 = bits(decoded_plaOutput_1, 23, 16) node _decoded_T_111 = shl(UInt<4>(0hf), 4) node _decoded_T_112 = xor(UInt<8>(0hff), _decoded_T_111) node _decoded_T_113 = shr(_decoded_T_110, 4) node _decoded_T_114 = and(_decoded_T_113, _decoded_T_112) node _decoded_T_115 = bits(_decoded_T_110, 3, 0) node _decoded_T_116 = shl(_decoded_T_115, 4) node _decoded_T_117 = not(_decoded_T_112) node _decoded_T_118 = and(_decoded_T_116, _decoded_T_117) node _decoded_T_119 = or(_decoded_T_114, _decoded_T_118) node _decoded_T_120 = bits(_decoded_T_112, 5, 0) node _decoded_T_121 = shl(_decoded_T_120, 2) node _decoded_T_122 = xor(_decoded_T_112, _decoded_T_121) node _decoded_T_123 = shr(_decoded_T_119, 2) node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122) node _decoded_T_125 = bits(_decoded_T_119, 5, 0) node _decoded_T_126 = shl(_decoded_T_125, 2) node _decoded_T_127 = not(_decoded_T_122) node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127) node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128) node _decoded_T_130 = bits(_decoded_T_122, 6, 0) node _decoded_T_131 = shl(_decoded_T_130, 1) node _decoded_T_132 = xor(_decoded_T_122, _decoded_T_131) node _decoded_T_133 = shr(_decoded_T_129, 1) node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132) node _decoded_T_135 = bits(_decoded_T_129, 6, 0) node _decoded_T_136 = shl(_decoded_T_135, 1) node _decoded_T_137 = not(_decoded_T_132) node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137) node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138) node decoded_1 = cat(_decoded_T_109, _decoded_T_139) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 12, 12) connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 13, 13) connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 14, 14) connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 15, 15) connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 16, 16) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 17, 17) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 18, 18) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 19, 19) connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 20, 20) connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 21, 21) connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 22, 22) connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 23, 23) connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<20> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_22) node _decoded_orMatrixOutputs_T_32 = orr(decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_33 = orr(decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_34 = orr(decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_35 = orr(decoded_andMatrixOutputs_0_2_2) node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_9 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_16 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_orMatrixOutputs_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_16 = cat(decoded_orMatrixOutputs_lo_hi_16, decoded_orMatrixOutputs_lo_lo_9) node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_33, _decoded_orMatrixOutputs_T_32) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_9 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_35) node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, _decoded_orMatrixOutputs_T_34) node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_16 = cat(decoded_orMatrixOutputs_hi_hi_hi_9, decoded_orMatrixOutputs_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_16 = cat(decoded_orMatrixOutputs_hi_hi_16, decoded_orMatrixOutputs_hi_lo_9) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_16, decoded_orMatrixOutputs_lo_16) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_2, 11, 11) node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_2, 12, 12) node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_2, 13, 13) node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_2, 14, 14) node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_2, 15, 15) node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_2, 16, 16) node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_2, 17, 17) node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_2, 18, 18) node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_2, 19, 19) node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_2, 20, 20) node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_2, 21, 21) node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_2, 22, 22) node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_2, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_50, _decoded_invMatrixOutputs_T_49) node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, _decoded_invMatrixOutputs_T_51) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55) node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, _decoded_invMatrixOutputs_T_57) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_62, _decoded_invMatrixOutputs_T_61) node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, _decoded_invMatrixOutputs_T_60) node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_65, _decoded_invMatrixOutputs_T_64) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, _decoded_invMatrixOutputs_T_63) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_68, _decoded_invMatrixOutputs_T_67) node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, _decoded_invMatrixOutputs_T_66) node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_71, _decoded_invMatrixOutputs_T_70) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, _decoded_invMatrixOutputs_T_69) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_140 = bits(decoded_plaOutput_2, 15, 0) node _decoded_T_141 = shl(UInt<8>(0hff), 8) node _decoded_T_142 = xor(UInt<16>(0hffff), _decoded_T_141) node _decoded_T_143 = shr(_decoded_T_140, 8) node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142) node _decoded_T_145 = bits(_decoded_T_140, 7, 0) node _decoded_T_146 = shl(_decoded_T_145, 8) node _decoded_T_147 = not(_decoded_T_142) node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147) node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148) node _decoded_T_150 = bits(_decoded_T_142, 11, 0) node _decoded_T_151 = shl(_decoded_T_150, 4) node _decoded_T_152 = xor(_decoded_T_142, _decoded_T_151) node _decoded_T_153 = shr(_decoded_T_149, 4) node _decoded_T_154 = and(_decoded_T_153, _decoded_T_152) node _decoded_T_155 = bits(_decoded_T_149, 11, 0) node _decoded_T_156 = shl(_decoded_T_155, 4) node _decoded_T_157 = not(_decoded_T_152) node _decoded_T_158 = and(_decoded_T_156, _decoded_T_157) node _decoded_T_159 = or(_decoded_T_154, _decoded_T_158) node _decoded_T_160 = bits(_decoded_T_152, 13, 0) node _decoded_T_161 = shl(_decoded_T_160, 2) node _decoded_T_162 = xor(_decoded_T_152, _decoded_T_161) node _decoded_T_163 = shr(_decoded_T_159, 2) node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162) node _decoded_T_165 = bits(_decoded_T_159, 13, 0) node _decoded_T_166 = shl(_decoded_T_165, 2) node _decoded_T_167 = not(_decoded_T_162) node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_162, 14, 0) node _decoded_T_171 = shl(_decoded_T_170, 1) node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171) node _decoded_T_173 = shr(_decoded_T_169, 1) node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172) node _decoded_T_175 = bits(_decoded_T_169, 14, 0) node _decoded_T_176 = shl(_decoded_T_175, 1) node _decoded_T_177 = not(_decoded_T_172) node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177) node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178) node _decoded_T_180 = bits(decoded_plaOutput_2, 23, 16) node _decoded_T_181 = shl(UInt<4>(0hf), 4) node _decoded_T_182 = xor(UInt<8>(0hff), _decoded_T_181) node _decoded_T_183 = shr(_decoded_T_180, 4) node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182) node _decoded_T_185 = bits(_decoded_T_180, 3, 0) node _decoded_T_186 = shl(_decoded_T_185, 4) node _decoded_T_187 = not(_decoded_T_182) node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187) node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188) node _decoded_T_190 = bits(_decoded_T_182, 5, 0) node _decoded_T_191 = shl(_decoded_T_190, 2) node _decoded_T_192 = xor(_decoded_T_182, _decoded_T_191) node _decoded_T_193 = shr(_decoded_T_189, 2) node _decoded_T_194 = and(_decoded_T_193, _decoded_T_192) node _decoded_T_195 = bits(_decoded_T_189, 5, 0) node _decoded_T_196 = shl(_decoded_T_195, 2) node _decoded_T_197 = not(_decoded_T_192) node _decoded_T_198 = and(_decoded_T_196, _decoded_T_197) node _decoded_T_199 = or(_decoded_T_194, _decoded_T_198) node _decoded_T_200 = bits(_decoded_T_192, 6, 0) node _decoded_T_201 = shl(_decoded_T_200, 1) node _decoded_T_202 = xor(_decoded_T_192, _decoded_T_201) node _decoded_T_203 = shr(_decoded_T_199, 1) node _decoded_T_204 = and(_decoded_T_203, _decoded_T_202) node _decoded_T_205 = bits(_decoded_T_199, 6, 0) node _decoded_T_206 = shl(_decoded_T_205, 1) node _decoded_T_207 = not(_decoded_T_202) node _decoded_T_208 = and(_decoded_T_206, _decoded_T_207) node _decoded_T_209 = or(_decoded_T_204, _decoded_T_208) node decoded_2 = cat(_decoded_T_179, _decoded_T_209) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 12, 12) connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 13, 13) connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 14, 14) connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 15, 15) connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 16, 16) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 17, 17) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 18, 18) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 19, 19) connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 20, 20) connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 21, 21) connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 22, 22) connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 23, 23) connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T extmodule plusarg_reader_35 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_17( // @[RouteComputer.scala:29:7] input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14] ); wire [15:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id[1]}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_1 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_2 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_4 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_6 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_7 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_8 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_9 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_11 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_13 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_14 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_15 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_16 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_18 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_20 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_1 = ~io_req_1_bits_flow_egress_node_id; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_21 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_2 = ~io_req_2_bits_flow_egress_node_id; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_22 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_2_vc_sel_0_4 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_0_5 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_0_6 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_0_7 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_4 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_5 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_6 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_7 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_2_1 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_1 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_2 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_3 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_4 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_5 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_6 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_7 = \|{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w32_16 : input clock : Clock input reset : Reset output io : { flip d : UInt<32>, q : UInt<32>, flip en : UInt<1>} reg cdc_reg : UInt<32>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg	module ClockCrossingReg_w32_16( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_32 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_288 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_32( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_288 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_SerialRAM : input clock : Clock input reset : Reset output auto : { flip manager_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire managerNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate managerNodeIn.d.bits.corrupt invalidate managerNodeIn.d.bits.data invalidate managerNodeIn.d.bits.denied invalidate managerNodeIn.d.bits.sink invalidate managerNodeIn.d.bits.source invalidate managerNodeIn.d.bits.size invalidate managerNodeIn.d.bits.param invalidate managerNodeIn.d.bits.opcode invalidate managerNodeIn.d.valid invalidate managerNodeIn.d.ready invalidate managerNodeIn.a.bits.corrupt invalidate managerNodeIn.a.bits.data invalidate managerNodeIn.a.bits.mask invalidate managerNodeIn.a.bits.address invalidate managerNodeIn.a.bits.source invalidate managerNodeIn.a.bits.size invalidate managerNodeIn.a.bits.param invalidate managerNodeIn.a.bits.opcode invalidate managerNodeIn.a.valid invalidate managerNodeIn.a.ready inst monitor of TLMonitor_74 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, managerNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, managerNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, managerNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, managerNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, managerNodeIn.d.bits.source connect monitor.io.in.d.bits.size, managerNodeIn.d.bits.size connect monitor.io.in.d.bits.param, managerNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, managerNodeIn.d.bits.opcode connect monitor.io.in.d.valid, managerNodeIn.d.valid connect monitor.io.in.d.ready, managerNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, managerNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, managerNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, managerNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, managerNodeIn.a.bits.address connect monitor.io.in.a.bits.source, managerNodeIn.a.bits.source connect monitor.io.in.a.bits.size, managerNodeIn.a.bits.size connect monitor.io.in.a.bits.param, managerNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, managerNodeIn.a.bits.opcode connect monitor.io.in.a.valid, managerNodeIn.a.valid connect monitor.io.in.a.ready, managerNodeIn.a.ready connect managerNodeIn, auto.manager_in wire client_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect client_tl.e.bits.sink, UInt<8>(0h0) connect client_tl.e.valid, UInt<1>(0h0) connect client_tl.e.ready, UInt<1>(0h0) connect client_tl.d.bits.corrupt, UInt<1>(0h0) connect client_tl.d.bits.data, UInt<64>(0h0) connect client_tl.d.bits.denied, UInt<1>(0h0) connect client_tl.d.bits.sink, UInt<8>(0h0) connect client_tl.d.bits.source, UInt<8>(0h0) connect client_tl.d.bits.size, UInt<8>(0h0) connect client_tl.d.bits.param, UInt<2>(0h0) connect client_tl.d.bits.opcode, UInt<3>(0h0) connect client_tl.d.valid, UInt<1>(0h0) connect client_tl.d.ready, UInt<1>(0h0) connect client_tl.c.bits.corrupt, UInt<1>(0h0) connect client_tl.c.bits.data, UInt<64>(0h0) connect client_tl.c.bits.address, UInt<64>(0h0) connect client_tl.c.bits.source, UInt<8>(0h0) connect client_tl.c.bits.size, UInt<8>(0h0) connect client_tl.c.bits.param, UInt<3>(0h0) connect client_tl.c.bits.opcode, UInt<3>(0h0) connect client_tl.c.valid, UInt<1>(0h0) connect client_tl.c.ready, UInt<1>(0h0) connect client_tl.b.bits.corrupt, UInt<1>(0h0) connect client_tl.b.bits.data, UInt<64>(0h0) connect client_tl.b.bits.mask, UInt<8>(0h0) connect client_tl.b.bits.address, UInt<64>(0h0) connect client_tl.b.bits.source, UInt<8>(0h0) connect client_tl.b.bits.size, UInt<8>(0h0) connect client_tl.b.bits.param, UInt<2>(0h0) connect client_tl.b.bits.opcode, UInt<3>(0h0) connect client_tl.b.valid, UInt<1>(0h0) connect client_tl.b.ready, UInt<1>(0h0) connect client_tl.a.bits.corrupt, UInt<1>(0h0) connect client_tl.a.bits.data, UInt<64>(0h0) connect client_tl.a.bits.mask, UInt<8>(0h0) connect client_tl.a.bits.address, UInt<64>(0h0) connect client_tl.a.bits.source, UInt<8>(0h0) connect client_tl.a.bits.size, UInt<8>(0h0) connect client_tl.a.bits.param, UInt<3>(0h0) connect client_tl.a.bits.opcode, UInt<3>(0h0) connect client_tl.a.valid, UInt<1>(0h0) connect client_tl.a.ready, UInt<1>(0h0) wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _out_channels_WIRE.bits.sink, UInt<4>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect out_channels_0_1.bits, _out_channels_WIRE.bits connect out_channels_0_1.valid, _out_channels_WIRE.valid connect out_channels_0_1.ready, _out_channels_WIRE.ready inst out_channels_0_2 of TLEToBeat_SerialRAM_a64d64s8k8z8c connect out_channels_0_2.clock, clock connect out_channels_0_2.reset, reset wire _out_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _out_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _out_channels_WIRE_1.bits.source, UInt<1>(0h0) connect _out_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _out_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _out_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE_1.valid, UInt<1>(0h0) connect _out_channels_WIRE_1.ready, UInt<1>(0h0) wire out_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_2_1.bits, _out_channels_WIRE_1.bits connect out_channels_2_1.valid, _out_channels_WIRE_1.valid connect out_channels_2_1.ready, _out_channels_WIRE_1.ready inst out_channels_2_2 of TLCToBeat_SerialRAM_a64d64s8k8z8c connect out_channels_2_2.clock, clock connect out_channels_2_2.reset, reset inst out_channels_4_2 of TLAToBeat_SerialRAM_a64d64s8k8z8c connect out_channels_4_2.clock, clock connect out_channels_4_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_0_2.io.protocol, out_channels_0_1 inst ser_0 of GenericSerializer_TLBeatw10_f32 connect ser_0.clock, clock connect ser_0.reset, reset connect ser_0.io.in, out_channels_0_2.io.beat connect io.ser[0].out.bits, ser_0.io.out.bits connect io.ser[0].out.valid, ser_0.io.out.valid connect ser_0.io.out.ready, io.ser[0].out.ready connect out_channels_2_2.io.protocol, out_channels_2_1 inst ser_2 of GenericSerializer_TLBeatw88_f32 connect ser_2.clock, clock connect ser_2.reset, reset connect ser_2.io.in, out_channels_2_2.io.beat connect io.ser[2].out.bits, ser_2.io.out.bits connect io.ser[2].out.valid, ser_2.io.out.valid connect ser_2.io.out.ready, io.ser[2].out.ready connect out_channels_4_2.io.protocol, managerNodeIn.a inst ser_4 of GenericSerializer_TLBeatw88_f32_1 connect ser_4.clock, clock connect ser_4.reset, reset connect ser_4.io.in, out_channels_4_2.io.beat connect io.ser[4].out.bits, ser_4.io.out.bits connect io.ser[4].out.valid, ser_4.io.out.valid connect ser_4.io.out.ready, io.ser[4].out.ready node _io_debug_ser_busy_T = or(ser_0.io.busy, ser_2.io.busy) node _io_debug_ser_busy_T_1 = or(_io_debug_ser_busy_T, ser_4.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T_1 inst in_channels_0_2 of TLEFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset inst in_channels_2_2 of TLCFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE.bits.data, UInt<64>(0h0) connect _in_channels_WIRE.bits.mask, UInt<8>(0h0) connect _in_channels_WIRE.bits.address, UInt<32>(0h0) connect _in_channels_WIRE.bits.source, UInt<1>(0h0) connect _in_channels_WIRE.bits.size, UInt<4>(0h0) connect _in_channels_WIRE.bits.param, UInt<2>(0h0) connect _in_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_3_1.bits, _in_channels_WIRE.bits connect in_channels_3_1.valid, _in_channels_WIRE.valid connect in_channels_3_1.ready, _in_channels_WIRE.ready inst in_channels_3_2 of TLBFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect client_tl.e.bits.sink, in_channels_0_2.io.protocol.bits.sink connect client_tl.e.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, client_tl.e.ready inst des_0 of GenericDeserializer_TLBeatw10_f32_1 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect managerNodeIn.d.bits, in_channels_1_2.io.protocol.bits connect managerNodeIn.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, managerNodeIn.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32_1 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect client_tl.c.bits.corrupt, in_channels_2_2.io.protocol.bits.corrupt connect client_tl.c.bits.data, in_channels_2_2.io.protocol.bits.data connect client_tl.c.bits.address, in_channels_2_2.io.protocol.bits.address connect client_tl.c.bits.source, in_channels_2_2.io.protocol.bits.source connect client_tl.c.bits.size, in_channels_2_2.io.protocol.bits.size connect client_tl.c.bits.param, in_channels_2_2.io.protocol.bits.param connect client_tl.c.bits.opcode, in_channels_2_2.io.protocol.bits.opcode connect client_tl.c.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, client_tl.c.ready inst des_2 of GenericDeserializer_TLBeatw88_f32_2 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect in_channels_3_1.bits, in_channels_3_2.io.protocol.bits connect in_channels_3_1.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, in_channels_3_1.ready inst des_3 of GenericDeserializer_TLBeatw87_f32_1 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect client_tl.a.bits.corrupt, in_channels_4_2.io.protocol.bits.corrupt connect client_tl.a.bits.data, in_channels_4_2.io.protocol.bits.data connect client_tl.a.bits.mask, in_channels_4_2.io.protocol.bits.mask connect client_tl.a.bits.address, in_channels_4_2.io.protocol.bits.address connect client_tl.a.bits.source, in_channels_4_2.io.protocol.bits.source connect client_tl.a.bits.size, in_channels_4_2.io.protocol.bits.size connect client_tl.a.bits.param, in_channels_4_2.io.protocol.bits.param connect client_tl.a.bits.opcode, in_channels_4_2.io.protocol.bits.opcode connect client_tl.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, client_tl.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_3 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3	module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_0_out_ready, // @[TLSerdes.scala:40:16] output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_2_out_ready, // @[TLSerdes.scala:40:16] output io_ser_2_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_4_out_ready, // @[TLSerdes.scala:40:16] output io_ser_4_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28] wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_4_io_busy; // @[TLSerdes.scala:69:23] wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50] wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50] wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50] wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50] wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9] wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9] wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74] wire [3:0] out_channels_0_1_bits_sink = 4'h0; // @[Bundles.scala:267:61] wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17] wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61] wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire _io_debug_ser_busy_T_1; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy; // @[TLSerdes.scala:39:9] wire io_debug_des_busy; // @[TLSerdes.scala:39:9] assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_a_valid; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_c_valid; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71] wire client_tl_e_valid; // @[TLSerdes.scala:45:71] wire _io_debug_ser_busy_T; // @[package.scala:81:59] assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T \| _ser_4_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9] wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61] wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61] wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61] wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61] wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61] wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61] wire in_channels_3_1_valid; // @[Bundles.scala:264:61] assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T \| _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 \| _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 \| _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLMonitor_74 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_0_2_io_beat_bits_head) ); // @[TLSerdes.scala:59:50] TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_2_2_io_beat_bits_head) ); // @[TLSerdes.scala:61:50] TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_a_ready), .io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21] .io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_4_2_io_beat_valid), .io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_4_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail) ); // @[TLSerdes.scala:63:50] GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_0_io_in_ready), .io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50] .io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_bits_flit (io_ser_0_out_bits_flit_0) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_2_io_in_ready), .io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50] .io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_2_out_valid_0), .io_out_bits_flit (io_ser_2_out_bits_flit_0), .io_busy (_io_debug_ser_busy_T) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_4_io_in_ready), .io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50] .io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50] .io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50] .io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50] .io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_4_out_valid_0), .io_out_bits_flit (io_ser_4_out_bits_flit_0), .io_busy (_ser_4_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_e_valid), .io_protocol_bits_sink (client_tl_e_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_protocol_valid (managerNodeIn_d_valid), .io_protocol_bits_opcode (managerNodeIn_d_bits_opcode), .io_protocol_bits_param (managerNodeIn_d_bits_param), .io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source), .io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink), .io_protocol_bits_denied (managerNodeIn_d_bits_denied), .io_protocol_bits_data (managerNodeIn_d_bits_data), .io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_c_valid), .io_protocol_bits_opcode (client_tl_c_bits_opcode), .io_protocol_bits_param (client_tl_c_bits_param), .io_protocol_bits_size (client_tl_c_bits_size), .io_protocol_bits_source (client_tl_c_bits_source), .io_protocol_bits_address (client_tl_c_bits_address), .io_protocol_bits_data (client_tl_c_bits_data), .io_protocol_bits_corrupt (client_tl_c_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_3_1_valid), .io_protocol_bits_opcode (in_channels_3_1_bits_opcode), .io_protocol_bits_param (in_channels_3_1_bits_param), .io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address), .io_protocol_bits_mask (in_channels_3_1_bits_mask), .io_protocol_bits_data (in_channels_3_1_bits_data), .io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_a_valid), .io_protocol_bits_opcode (client_tl_a_bits_opcode), .io_protocol_bits_param (client_tl_a_bits_param), .io_protocol_bits_size (client_tl_a_bits_size), .io_protocol_bits_source (client_tl_a_bits_source), .io_protocol_bits_address (client_tl_a_bits_address), .io_protocol_bits_mask (client_tl_a_bits_mask), .io_protocol_bits_data (client_tl_a_bits_data), .io_protocol_bits_corrupt (client_tl_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_14 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_14( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_34 node _source_ok_T_35 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[2]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[3]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[4]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[5]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[6]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[7]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_42, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_102 = eq(_T_101, UInt<1>(0h0)) node _T_103 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_104 = cvt(_T_103) node _T_105 = and(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = asSInt(_T_105) node _T_107 = eq(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = or(_T_102, _T_107) node _T_109 = and(_T_11, _T_24) node _T_110 = and(_T_109, _T_37) node _T_111 = and(_T_110, _T_50) node _T_112 = and(_T_111, _T_63) node _T_113 = and(_T_112, _T_76) node _T_114 = and(_T_113, _T_84) node _T_115 = and(_T_114, _T_92) node _T_116 = and(_T_115, _T_100) node _T_117 = and(_T_116, _T_108) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_117, UInt<1>(0h1), "") : assert_1 node _T_121 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_121 : node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<1>(0h0)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_5) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_132 = shr(io.in.a.bits.source, 2) node _T_133 = eq(_T_132, UInt<1>(0h1)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_6) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_137 = and(_T_135, _T_136) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_138 = shr(io.in.a.bits.source, 2) node _T_139 = eq(_T_138, UInt<2>(0h2)) node _T_140 = leq(UInt<1>(0h0), uncommonBits_7) node _T_141 = and(_T_139, _T_140) node _T_142 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_143 = and(_T_141, _T_142) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_144 = shr(io.in.a.bits.source, 2) node _T_145 = eq(_T_144, UInt<2>(0h3)) node _T_146 = leq(UInt<1>(0h0), uncommonBits_8) node _T_147 = and(_T_145, _T_146) node _T_148 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_149 = and(_T_147, _T_148) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_150 = shr(io.in.a.bits.source, 3) node _T_151 = eq(_T_150, UInt<3>(0h4)) node _T_152 = leq(UInt<1>(0h0), uncommonBits_9) node _T_153 = and(_T_151, _T_152) node _T_154 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_157 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_158 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_159 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_160 = or(_T_125, _T_131) node _T_161 = or(_T_160, _T_137) node _T_162 = or(_T_161, _T_143) node _T_163 = or(_T_162, _T_149) node _T_164 = or(_T_163, _T_155) node _T_165 = or(_T_164, _T_156) node _T_166 = or(_T_165, _T_157) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_159) node _T_169 = and(_T_124, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_172 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<27>(0h4000000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = and(_T_171, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = and(_T_170, _T_178) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_179, UInt<1>(0h1), "") : assert_2 node _T_183 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_184 = shr(io.in.a.bits.source, 2) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_10) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_189 = and(_T_187, _T_188) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_190 = shr(io.in.a.bits.source, 2) node _T_191 = eq(_T_190, UInt<1>(0h1)) node _T_192 = leq(UInt<1>(0h0), uncommonBits_11) node _T_193 = and(_T_191, _T_192) node _T_194 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_195 = and(_T_193, _T_194) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<2>(0h2)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_12) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<2>(0h3)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_13) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_208 = shr(io.in.a.bits.source, 3) node _T_209 = eq(_T_208, UInt<3>(0h4)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_14) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_215 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_217 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_183 connect _WIRE[1], _T_189 connect _WIRE[2], _T_195 connect _WIRE[3], _T_201 connect _WIRE[4], _T_207 connect _WIRE[5], _T_213 connect _WIRE[6], _T_214 connect _WIRE[7], _T_215 connect _WIRE[8], _T_216 connect _WIRE[9], _T_217 node _T_218 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_219 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_220 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_221 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_222 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_223 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_224 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_225 = mux(_WIRE[6], _T_218, UInt<1>(0h0)) node _T_226 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_227 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_228 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_229 = or(_T_219, _T_220) node _T_230 = or(_T_229, _T_221) node _T_231 = or(_T_230, _T_222) node _T_232 = or(_T_231, _T_223) node _T_233 = or(_T_232, _T_224) node _T_234 = or(_T_233, _T_225) node _T_235 = or(_T_234, _T_226) node _T_236 = or(_T_235, _T_227) node _T_237 = or(_T_236, _T_228) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_237 node _T_238 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_239 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_240 = and(_T_238, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<27>(0h4000000))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = and(_T_241, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = and(_WIRE_1, _T_248) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_249, UInt<1>(0h1), "") : assert_3 node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(source_ok, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_256 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_T_256, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_256, UInt<1>(0h1), "") : assert_5 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_263 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_263, UInt<1>(0h1), "") : assert_7 node _T_267 = not(io.in.a.bits.mask) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_268, UInt<1>(0h1), "") : assert_8 node _T_272 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_272, UInt<1>(0h1), "") : assert_9 node _T_276 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_276 : node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_281 = shr(io.in.a.bits.source, 2) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_15) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_287 = shr(io.in.a.bits.source, 2) node _T_288 = eq(_T_287, UInt<1>(0h1)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_16) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_293 = shr(io.in.a.bits.source, 2) node _T_294 = eq(_T_293, UInt<2>(0h2)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_17) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_298 = and(_T_296, _T_297) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_299 = shr(io.in.a.bits.source, 2) node _T_300 = eq(_T_299, UInt<2>(0h3)) node _T_301 = leq(UInt<1>(0h0), uncommonBits_18) node _T_302 = and(_T_300, _T_301) node _T_303 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_304 = and(_T_302, _T_303) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_305 = shr(io.in.a.bits.source, 3) node _T_306 = eq(_T_305, UInt<3>(0h4)) node _T_307 = leq(UInt<1>(0h0), uncommonBits_19) node _T_308 = and(_T_306, _T_307) node _T_309 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_314 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_315 = or(_T_280, _T_286) node _T_316 = or(_T_315, _T_292) node _T_317 = or(_T_316, _T_298) node _T_318 = or(_T_317, _T_304) node _T_319 = or(_T_318, _T_310) node _T_320 = or(_T_319, _T_311) node _T_321 = or(_T_320, _T_312) node _T_322 = or(_T_321, _T_313) node _T_323 = or(_T_322, _T_314) node _T_324 = and(_T_279, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_327 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<27>(0h4000000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = and(_T_326, _T_331) node _T_333 = or(UInt<1>(0h0), _T_332) node _T_334 = and(_T_325, _T_333) node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_T_334, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_334, UInt<1>(0h1), "") : assert_10 node _T_338 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<1>(0h0)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_20) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<1>(0h1)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_21) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_351 = shr(io.in.a.bits.source, 2) node _T_352 = eq(_T_351, UInt<2>(0h2)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_22) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_356 = and(_T_354, _T_355) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_357 = shr(io.in.a.bits.source, 2) node _T_358 = eq(_T_357, UInt<2>(0h3)) node _T_359 = leq(UInt<1>(0h0), uncommonBits_23) node _T_360 = and(_T_358, _T_359) node _T_361 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_362 = and(_T_360, _T_361) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_363 = shr(io.in.a.bits.source, 3) node _T_364 = eq(_T_363, UInt<3>(0h4)) node _T_365 = leq(UInt<1>(0h0), uncommonBits_24) node _T_366 = and(_T_364, _T_365) node _T_367 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_370 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_371 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_372 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_338 connect _WIRE_2[1], _T_344 connect _WIRE_2[2], _T_350 connect _WIRE_2[3], _T_356 connect _WIRE_2[4], _T_362 connect _WIRE_2[5], _T_368 connect _WIRE_2[6], _T_369 connect _WIRE_2[7], _T_370 connect _WIRE_2[8], _T_371 connect _WIRE_2[9], _T_372 node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_374 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_375 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE_2[6], _T_373, UInt<1>(0h0)) node _T_381 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_384 = or(_T_374, _T_375) node _T_385 = or(_T_384, _T_376) node _T_386 = or(_T_385, _T_377) node _T_387 = or(_T_386, _T_378) node _T_388 = or(_T_387, _T_379) node _T_389 = or(_T_388, _T_380) node _T_390 = or(_T_389, _T_381) node _T_391 = or(_T_390, _T_382) node _T_392 = or(_T_391, _T_383) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_392 node _T_393 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_394 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = and(_T_396, _T_401) node _T_403 = or(UInt<1>(0h0), _T_402) node _T_404 = and(_WIRE_3, _T_403) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_404, UInt<1>(0h1), "") : assert_11 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(source_ok, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_411 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_411, UInt<1>(0h1), "") : assert_13 node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(is_aligned, UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_418 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_418, UInt<1>(0h1), "") : assert_15 node _T_422 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_422, UInt<1>(0h1), "") : assert_16 node _T_426 = not(io.in.a.bits.mask) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_427, UInt<1>(0h1), "") : assert_17 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_431, UInt<1>(0h1), "") : assert_18 node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_25) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<1>(0h1)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_26) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_452 = shr(io.in.a.bits.source, 2) node _T_453 = eq(_T_452, UInt<2>(0h2)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_27) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<2>(0h3)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_28) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_464 = shr(io.in.a.bits.source, 3) node _T_465 = eq(_T_464, UInt<3>(0h4)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_29) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_473 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_474 = or(_T_439, _T_445) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_457) node _T_477 = or(_T_476, _T_463) node _T_478 = or(_T_477, _T_469) node _T_479 = or(_T_478, _T_470) node _T_480 = or(_T_479, _T_471) node _T_481 = or(_T_480, _T_472) node _T_482 = or(_T_481, _T_473) node _T_483 = and(_T_438, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_484, UInt<1>(0h1), "") : assert_19 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<27>(0h4000000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_498, UInt<1>(0h1), "") : assert_20 node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(source_ok, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(is_aligned, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_508 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_508, UInt<1>(0h1), "") : assert_23 node _T_512 = eq(io.in.a.bits.mask, mask) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_512, UInt<1>(0h1), "") : assert_24 node _T_516 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_516, UInt<1>(0h1), "") : assert_25 node _T_520 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_520 : node _T_521 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_522 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_523 = and(_T_521, _T_522) node _T_524 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<1>(0h0)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_30) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_531 = shr(io.in.a.bits.source, 2) node _T_532 = eq(_T_531, UInt<1>(0h1)) node _T_533 = leq(UInt<1>(0h0), uncommonBits_31) node _T_534 = and(_T_532, _T_533) node _T_535 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_537 = shr(io.in.a.bits.source, 2) node _T_538 = eq(_T_537, UInt<2>(0h2)) node _T_539 = leq(UInt<1>(0h0), uncommonBits_32) node _T_540 = and(_T_538, _T_539) node _T_541 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_542 = and(_T_540, _T_541) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_543 = shr(io.in.a.bits.source, 2) node _T_544 = eq(_T_543, UInt<2>(0h3)) node _T_545 = leq(UInt<1>(0h0), uncommonBits_33) node _T_546 = and(_T_544, _T_545) node _T_547 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_548 = and(_T_546, _T_547) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_549 = shr(io.in.a.bits.source, 3) node _T_550 = eq(_T_549, UInt<3>(0h4)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_34) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_559 = or(_T_524, _T_530) node _T_560 = or(_T_559, _T_536) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_548) node _T_563 = or(_T_562, _T_554) node _T_564 = or(_T_563, _T_555) node _T_565 = or(_T_564, _T_556) node _T_566 = or(_T_565, _T_557) node _T_567 = or(_T_566, _T_558) node _T_568 = and(_T_523, _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<27>(0h4000000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = and(_T_573, _T_578) node _T_580 = or(UInt<1>(0h0), _T_579) node _T_581 = and(_T_569, _T_580) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_581, UInt<1>(0h1), "") : assert_26 node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(source_ok, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(is_aligned, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_591 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_591, UInt<1>(0h1), "") : assert_29 node _T_595 = eq(io.in.a.bits.mask, mask) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_595, UInt<1>(0h1), "") : assert_30 node _T_599 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_599 : node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_602 = and(_T_600, _T_601) node _T_603 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<1>(0h0)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_35) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_610 = shr(io.in.a.bits.source, 2) node _T_611 = eq(_T_610, UInt<1>(0h1)) node _T_612 = leq(UInt<1>(0h0), uncommonBits_36) node _T_613 = and(_T_611, _T_612) node _T_614 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_615 = and(_T_613, _T_614) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_616 = shr(io.in.a.bits.source, 2) node _T_617 = eq(_T_616, UInt<2>(0h2)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_37) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_622 = shr(io.in.a.bits.source, 2) node _T_623 = eq(_T_622, UInt<2>(0h3)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_38) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_628 = shr(io.in.a.bits.source, 3) node _T_629 = eq(_T_628, UInt<3>(0h4)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_39) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_633 = and(_T_631, _T_632) node _T_634 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_635 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_636 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_637 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_638 = or(_T_603, _T_609) node _T_639 = or(_T_638, _T_615) node _T_640 = or(_T_639, _T_621) node _T_641 = or(_T_640, _T_627) node _T_642 = or(_T_641, _T_633) node _T_643 = or(_T_642, _T_634) node _T_644 = or(_T_643, _T_635) node _T_645 = or(_T_644, _T_636) node _T_646 = or(_T_645, _T_637) node _T_647 = and(_T_602, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = and(_T_648, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_660, UInt<1>(0h1), "") : assert_31 node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(source_ok, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(is_aligned, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_670 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_670, UInt<1>(0h1), "") : assert_34 node _T_674 = not(mask) node _T_675 = and(io.in.a.bits.mask, _T_674) node _T_676 = eq(_T_675, UInt<1>(0h0)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_676, UInt<1>(0h1), "") : assert_35 node _T_680 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_680 : node _T_681 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_682 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h0)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_40) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<1>(0h1)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_41) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h2)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_42) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<2>(0h3)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_43) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_709 = shr(io.in.a.bits.source, 3) node _T_710 = eq(_T_709, UInt<3>(0h4)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_44) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_718 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_719 = or(_T_684, _T_690) node _T_720 = or(_T_719, _T_696) node _T_721 = or(_T_720, _T_702) node _T_722 = or(_T_721, _T_708) node _T_723 = or(_T_722, _T_714) node _T_724 = or(_T_723, _T_715) node _T_725 = or(_T_724, _T_716) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_718) node _T_728 = and(_T_683, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<27>(0h4000000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = and(_T_730, _T_735) node _T_737 = or(UInt<1>(0h0), _T_736) node _T_738 = and(_T_729, _T_737) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_738, UInt<1>(0h1), "") : assert_36 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(source_ok, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(is_aligned, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_748 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_748, UInt<1>(0h1), "") : assert_39 node _T_752 = eq(io.in.a.bits.mask, mask) node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(_T_752, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_752, UInt<1>(0h1), "") : assert_40 node _T_756 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_756 : node _T_757 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_758 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_759 = and(_T_757, _T_758) node _T_760 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_761 = shr(io.in.a.bits.source, 2) node _T_762 = eq(_T_761, UInt<1>(0h0)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_45) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_767 = shr(io.in.a.bits.source, 2) node _T_768 = eq(_T_767, UInt<1>(0h1)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_46) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_773 = shr(io.in.a.bits.source, 2) node _T_774 = eq(_T_773, UInt<2>(0h2)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_47) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_779 = shr(io.in.a.bits.source, 2) node _T_780 = eq(_T_779, UInt<2>(0h3)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_48) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_785 = shr(io.in.a.bits.source, 3) node _T_786 = eq(_T_785, UInt<3>(0h4)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_49) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_790 = and(_T_788, _T_789) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_792 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_793 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_794 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_795 = or(_T_760, _T_766) node _T_796 = or(_T_795, _T_772) node _T_797 = or(_T_796, _T_778) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_790) node _T_800 = or(_T_799, _T_791) node _T_801 = or(_T_800, _T_792) node _T_802 = or(_T_801, _T_793) node _T_803 = or(_T_802, _T_794) node _T_804 = and(_T_759, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_807 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_808 = cvt(_T_807) node _T_809 = and(_T_808, asSInt(UInt<27>(0h4000000))) node _T_810 = asSInt(_T_809) node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0))) node _T_812 = and(_T_806, _T_811) node _T_813 = or(UInt<1>(0h0), _T_812) node _T_814 = and(_T_805, _T_813) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_814, UInt<1>(0h1), "") : assert_41 node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(source_ok, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(is_aligned, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_824 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_824, UInt<1>(0h1), "") : assert_44 node _T_828 = eq(io.in.a.bits.mask, mask) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_828, UInt<1>(0h1), "") : assert_45 node _T_832 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_832 : node _T_833 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_834 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_835 = and(_T_833, _T_834) node _T_836 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_837 = shr(io.in.a.bits.source, 2) node _T_838 = eq(_T_837, UInt<1>(0h0)) node _T_839 = leq(UInt<1>(0h0), uncommonBits_50) node _T_840 = and(_T_838, _T_839) node _T_841 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_842 = and(_T_840, _T_841) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_843 = shr(io.in.a.bits.source, 2) node _T_844 = eq(_T_843, UInt<1>(0h1)) node _T_845 = leq(UInt<1>(0h0), uncommonBits_51) node _T_846 = and(_T_844, _T_845) node _T_847 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_848 = and(_T_846, _T_847) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_849 = shr(io.in.a.bits.source, 2) node _T_850 = eq(_T_849, UInt<2>(0h2)) node _T_851 = leq(UInt<1>(0h0), uncommonBits_52) node _T_852 = and(_T_850, _T_851) node _T_853 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_854 = and(_T_852, _T_853) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_855 = shr(io.in.a.bits.source, 2) node _T_856 = eq(_T_855, UInt<2>(0h3)) node _T_857 = leq(UInt<1>(0h0), uncommonBits_53) node _T_858 = and(_T_856, _T_857) node _T_859 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_860 = and(_T_858, _T_859) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_861 = shr(io.in.a.bits.source, 3) node _T_862 = eq(_T_861, UInt<3>(0h4)) node _T_863 = leq(UInt<1>(0h0), uncommonBits_54) node _T_864 = and(_T_862, _T_863) node _T_865 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_866 = and(_T_864, _T_865) node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_871 = or(_T_836, _T_842) node _T_872 = or(_T_871, _T_848) node _T_873 = or(_T_872, _T_854) node _T_874 = or(_T_873, _T_860) node _T_875 = or(_T_874, _T_866) node _T_876 = or(_T_875, _T_867) node _T_877 = or(_T_876, _T_868) node _T_878 = or(_T_877, _T_869) node _T_879 = or(_T_878, _T_870) node _T_880 = and(_T_835, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_883 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<27>(0h4000000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = and(_T_882, _T_887) node _T_889 = or(UInt<1>(0h0), _T_888) node _T_890 = and(_T_881, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_890, UInt<1>(0h1), "") : assert_46 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_900 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_900, UInt<1>(0h1), "") : assert_49 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_904, UInt<1>(0h1), "") : assert_50 node _T_908 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_908, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_912 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_912, UInt<1>(0h1), "") : assert_52 node _source_ok_T_43 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_50 = shr(io.in.d.bits.source, 2) node _source_ok_T_51 = eq(_source_ok_T_50, UInt<1>(0h1)) node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_T_54 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<2>(0h2)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<2>(0h3)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 3) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<3>(0h4)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_77 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_43 connect _source_ok_WIRE_1[1], _source_ok_T_49 connect _source_ok_WIRE_1[2], _source_ok_T_55 connect _source_ok_WIRE_1[3], _source_ok_T_61 connect _source_ok_WIRE_1[4], _source_ok_T_67 connect _source_ok_WIRE_1[5], _source_ok_T_73 connect _source_ok_WIRE_1[6], _source_ok_T_74 connect _source_ok_WIRE_1[7], _source_ok_T_75 connect _source_ok_WIRE_1[8], _source_ok_T_76 connect _source_ok_WIRE_1[9], _source_ok_T_77 node _source_ok_T_78 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[2]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[3]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[4]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[5]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[6]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[7]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_85, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_916 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_916 : node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(source_ok_1, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_920 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_920, UInt<1>(0h1), "") : assert_54 node _T_924 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_924, UInt<1>(0h1), "") : assert_55 node _T_928 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_928, UInt<1>(0h1), "") : assert_56 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_932, UInt<1>(0h1), "") : assert_57 node _T_936 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_936 : node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(source_ok_1, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(sink_ok, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_943 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_943, UInt<1>(0h1), "") : assert_60 node _T_947 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_947, UInt<1>(0h1), "") : assert_61 node _T_951 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_951, UInt<1>(0h1), "") : assert_62 node _T_955 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_955, UInt<1>(0h1), "") : assert_63 node _T_959 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_960 = or(UInt<1>(0h0), _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_960, UInt<1>(0h1), "") : assert_64 node _T_964 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_964 : node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(source_ok_1, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(sink_ok, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_971 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_971, UInt<1>(0h1), "") : assert_67 node _T_975 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_975, UInt<1>(0h1), "") : assert_68 node _T_979 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(_T_979, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_979, UInt<1>(0h1), "") : assert_69 node _T_983 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_984 = or(_T_983, io.in.d.bits.corrupt) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_984, UInt<1>(0h1), "") : assert_70 node _T_988 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_989 = or(UInt<1>(0h0), _T_988) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_989, UInt<1>(0h1), "") : assert_71 node _T_993 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_993 : node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(source_ok_1, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_997 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_997, UInt<1>(0h1), "") : assert_73 node _T_1001 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_74 node _T_1005 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_75 node _T_1010 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1010 : node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok_1, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1014 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_77 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_78 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h0), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_79 node _T_1028 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok_1, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_81 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_82 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h0), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1045 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1049 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1053 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1057 = eq(a_first, UInt<1>(0h0)) node _T_1058 = and(io.in.a.valid, _T_1057) when _T_1058 : node _T_1059 = eq(io.in.a.bits.opcode, opcode) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_87 node _T_1063 = eq(io.in.a.bits.param, param) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_88 node _T_1067 = eq(io.in.a.bits.size, size) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_89 node _T_1071 = eq(io.in.a.bits.source, source) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_90 node _T_1075 = eq(io.in.a.bits.address, address) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_91 node _T_1079 = and(io.in.a.ready, io.in.a.valid) node _T_1080 = and(_T_1079, a_first) when _T_1080 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1081 = eq(d_first, UInt<1>(0h0)) node _T_1082 = and(io.in.d.valid, _T_1081) when _T_1082 : node _T_1083 = eq(io.in.d.bits.opcode, opcode_1) node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(_T_1083, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1083, UInt<1>(0h1), "") : assert_92 node _T_1087 = eq(io.in.d.bits.param, param_1) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_93 node _T_1091 = eq(io.in.d.bits.size, size_1) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_94 node _T_1095 = eq(io.in.d.bits.source, source_1) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_95 node _T_1099 = eq(io.in.d.bits.sink, sink) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_96 node _T_1103 = eq(io.in.d.bits.denied, denied) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_97 node _T_1107 = and(io.in.d.ready, io.in.d.valid) node _T_1108 = and(_T_1107, d_first) when _T_1108 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1109 = and(io.in.a.valid, a_first_1) node _T_1110 = and(_T_1109, UInt<1>(0h1)) when _T_1110 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1111 = and(io.in.a.ready, io.in.a.valid) node _T_1112 = and(_T_1111, a_first_1) node _T_1113 = and(_T_1112, UInt<1>(0h1)) when _T_1113 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1114 = dshr(inflight, io.in.a.bits.source) node _T_1115 = bits(_T_1114, 0, 0) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1120 = and(io.in.d.valid, d_first_1) node _T_1121 = and(_T_1120, UInt<1>(0h1)) node _T_1122 = eq(d_release_ack, UInt<1>(0h0)) node _T_1123 = and(_T_1121, _T_1122) when _T_1123 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_1) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = eq(d_release_ack, UInt<1>(0h0)) node _T_1128 = and(_T_1126, _T_1127) when _T_1128 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1133 = dshr(inflight, io.in.d.bits.source) node _T_1134 = bits(_T_1133, 0, 0) node _T_1135 = or(_T_1134, same_cycle_resp) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1139 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1140 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1141 = or(_T_1139, _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_100 node _T_1145 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_101 else : node _T_1149 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1150 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1151 = or(_T_1149, _T_1150) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_102 node _T_1155 = eq(io.in.d.bits.size, a_size_lookup) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_103 node _T_1159 = and(io.in.d.valid, d_first_1) node _T_1160 = and(_T_1159, a_first_1) node _T_1161 = and(_T_1160, io.in.a.valid) node _T_1162 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(d_release_ack, UInt<1>(0h0)) node _T_1165 = and(_T_1163, _T_1164) when _T_1165 : node _T_1166 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1167 = or(_T_1166, io.in.a.ready) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_104 node _T_1171 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1172 = orr(a_set_wo_ready) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = or(_T_1171, _T_1173) node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(_T_1174, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1174, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_54 node _T_1178 = orr(inflight) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1181 = or(_T_1179, _T_1180) node _T_1182 = lt(watchdog, plusarg_reader.out) node _T_1183 = or(_T_1181, _T_1182) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1187 = and(io.in.a.ready, io.in.a.valid) node _T_1188 = and(io.in.d.ready, io.in.d.valid) node _T_1189 = or(_T_1187, _T_1188) when _T_1189 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1190 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1191 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1192 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = and(_T_1190, _T_1193) when _T_1194 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1195 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1196 = and(_T_1195, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1197 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1198 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = and(_T_1196, _T_1199) when _T_1200 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1201 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1202 = bits(_T_1201, 0, 0) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1207 = and(io.in.d.valid, d_first_2) node _T_1208 = and(_T_1207, UInt<1>(0h1)) node _T_1209 = and(_T_1208, d_release_ack_1) when _T_1209 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = and(_T_1210, d_first_2) node _T_1212 = and(_T_1211, UInt<1>(0h1)) node _T_1213 = and(_T_1212, d_release_ack_1) when _T_1213 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1214 = and(io.in.d.valid, d_first_2) node _T_1215 = and(_T_1214, UInt<1>(0h1)) node _T_1216 = and(_T_1215, d_release_ack_1) when _T_1216 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1217 = dshr(inflight_1, io.in.d.bits.source) node _T_1218 = bits(_T_1217, 0, 0) node _T_1219 = or(_T_1218, same_cycle_resp_1) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1223 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_109 else : node _T_1227 = eq(io.in.d.bits.size, c_size_lookup) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_110 node _T_1231 = and(io.in.d.valid, d_first_2) node _T_1232 = and(_T_1231, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1233 = and(_T_1232, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1234 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1235 = and(_T_1233, _T_1234) node _T_1236 = and(_T_1235, d_release_ack_1) node _T_1237 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1238 = and(_T_1236, _T_1237) when _T_1238 : node _T_1239 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1240 = or(_T_1239, _WIRE_27.ready) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_111 node _T_1244 = orr(c_set_wo_ready) when _T_1244 : node _T_1245 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_55 node _T_1249 = orr(inflight_1) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) node _T_1251 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1252 = or(_T_1250, _T_1251) node _T_1253 = lt(watchdog_1, plusarg_reader_1.out) node _T_1254 = or(_T_1252, _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1258 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1259 = and(io.in.d.ready, io.in.d.valid) node _T_1260 = or(_T_1258, _T_1259) when _T_1260 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_42 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_43 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_44 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_50 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_56 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_62 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_45 = _source_ok_T_44 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = _source_ok_T_50 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_69 = _source_ok_T_68 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire _source_ok_T_77 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire _source_ok_T_78 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_84 = _source_ok_T_83 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_85 = _source_ok_T_84 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_85 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1187 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1187; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1187; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1260 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1260; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1260; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1260; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1113 = _T_1187 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1113 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1113 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1113 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1113 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1113 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1159 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1159 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1128 = _T_1260 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1128 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1128 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1128 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1231 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1231 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1213 = _T_1260 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1213 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1213 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1213 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_184 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_184( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate : input clock : Clock input reset : Reset output io : { flip chainIn : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, chainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, capture : { flip bits : { addr : UInt<7>, data : UInt<32>, resp : UInt<2>}, capture : UInt<1>}, update : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}} connect io.chainOut.shift, io.chainIn.shift connect io.chainOut.capture, io.chainIn.capture connect io.chainOut.update, io.chainIn.update reg regs_0 : UInt<1>, clock reg regs_1 : UInt<1>, clock reg regs_2 : UInt<1>, clock reg regs_3 : UInt<1>, clock reg regs_4 : UInt<1>, clock reg regs_5 : UInt<1>, clock reg regs_6 : UInt<1>, clock reg regs_7 : UInt<1>, clock reg regs_8 : UInt<1>, clock reg regs_9 : UInt<1>, clock reg regs_10 : UInt<1>, clock reg regs_11 : UInt<1>, clock reg regs_12 : UInt<1>, clock reg regs_13 : UInt<1>, clock reg regs_14 : UInt<1>, clock reg regs_15 : UInt<1>, clock reg regs_16 : UInt<1>, clock reg regs_17 : UInt<1>, clock reg regs_18 : UInt<1>, clock reg regs_19 : UInt<1>, clock reg regs_20 : UInt<1>, clock reg regs_21 : UInt<1>, clock reg regs_22 : UInt<1>, clock reg regs_23 : UInt<1>, clock reg regs_24 : UInt<1>, clock reg regs_25 : UInt<1>, clock reg regs_26 : UInt<1>, clock reg regs_27 : UInt<1>, clock reg regs_28 : UInt<1>, clock reg regs_29 : UInt<1>, clock reg regs_30 : UInt<1>, clock reg regs_31 : UInt<1>, clock reg regs_32 : UInt<1>, clock reg regs_33 : UInt<1>, clock reg regs_34 : UInt<1>, clock reg regs_35 : UInt<1>, clock reg regs_36 : UInt<1>, clock reg regs_37 : UInt<1>, clock reg regs_38 : UInt<1>, clock reg regs_39 : UInt<1>, clock reg regs_40 : UInt<1>, clock connect io.chainOut.data, regs_0 node updateBits_lo_lo_lo_lo = cat(regs_1, regs_0) node updateBits_lo_lo_lo_hi_hi = cat(regs_4, regs_3) node updateBits_lo_lo_lo_hi = cat(updateBits_lo_lo_lo_hi_hi, regs_2) node updateBits_lo_lo_lo = cat(updateBits_lo_lo_lo_hi, updateBits_lo_lo_lo_lo) node updateBits_lo_lo_hi_lo = cat(regs_6, regs_5) node updateBits_lo_lo_hi_hi_hi = cat(regs_9, regs_8) node updateBits_lo_lo_hi_hi = cat(updateBits_lo_lo_hi_hi_hi, regs_7) node updateBits_lo_lo_hi = cat(updateBits_lo_lo_hi_hi, updateBits_lo_lo_hi_lo) node updateBits_lo_lo = cat(updateBits_lo_lo_hi, updateBits_lo_lo_lo) node updateBits_lo_hi_lo_lo = cat(regs_11, regs_10) node updateBits_lo_hi_lo_hi_hi = cat(regs_14, regs_13) node updateBits_lo_hi_lo_hi = cat(updateBits_lo_hi_lo_hi_hi, regs_12) node updateBits_lo_hi_lo = cat(updateBits_lo_hi_lo_hi, updateBits_lo_hi_lo_lo) node updateBits_lo_hi_hi_lo = cat(regs_16, regs_15) node updateBits_lo_hi_hi_hi_hi = cat(regs_19, regs_18) node updateBits_lo_hi_hi_hi = cat(updateBits_lo_hi_hi_hi_hi, regs_17) node updateBits_lo_hi_hi = cat(updateBits_lo_hi_hi_hi, updateBits_lo_hi_hi_lo) node updateBits_lo_hi = cat(updateBits_lo_hi_hi, updateBits_lo_hi_lo) node updateBits_lo = cat(updateBits_lo_hi, updateBits_lo_lo) node updateBits_hi_lo_lo_lo = cat(regs_21, regs_20) node updateBits_hi_lo_lo_hi_hi = cat(regs_24, regs_23) node updateBits_hi_lo_lo_hi = cat(updateBits_hi_lo_lo_hi_hi, regs_22) node updateBits_hi_lo_lo = cat(updateBits_hi_lo_lo_hi, updateBits_hi_lo_lo_lo) node updateBits_hi_lo_hi_lo = cat(regs_26, regs_25) node updateBits_hi_lo_hi_hi_hi = cat(regs_29, regs_28) node updateBits_hi_lo_hi_hi = cat(updateBits_hi_lo_hi_hi_hi, regs_27) node updateBits_hi_lo_hi = cat(updateBits_hi_lo_hi_hi, updateBits_hi_lo_hi_lo) node updateBits_hi_lo = cat(updateBits_hi_lo_hi, updateBits_hi_lo_lo) node updateBits_hi_hi_lo_lo = cat(regs_31, regs_30) node updateBits_hi_hi_lo_hi_hi = cat(regs_34, regs_33) node updateBits_hi_hi_lo_hi = cat(updateBits_hi_hi_lo_hi_hi, regs_32) node updateBits_hi_hi_lo = cat(updateBits_hi_hi_lo_hi, updateBits_hi_hi_lo_lo) node updateBits_hi_hi_hi_lo_hi = cat(regs_37, regs_36) node updateBits_hi_hi_hi_lo = cat(updateBits_hi_hi_hi_lo_hi, regs_35) node updateBits_hi_hi_hi_hi_hi = cat(regs_40, regs_39) node updateBits_hi_hi_hi_hi = cat(updateBits_hi_hi_hi_hi_hi, regs_38) node updateBits_hi_hi_hi = cat(updateBits_hi_hi_hi_hi, updateBits_hi_hi_hi_lo) node updateBits_hi_hi = cat(updateBits_hi_hi_hi, updateBits_hi_hi_lo) node updateBits_hi = cat(updateBits_hi_hi, updateBits_hi_lo) node _updateBits_T = cat(updateBits_hi, updateBits_lo) node updateBits = bits(_updateBits_T, 40, 0) wire _io_update_bits_WIRE : { addr : UInt<7>, data : UInt<32>, op : UInt<2>} wire _io_update_bits_WIRE_1 : UInt<41> connect _io_update_bits_WIRE_1, updateBits node _io_update_bits_T = bits(_io_update_bits_WIRE_1, 1, 0) connect _io_update_bits_WIRE.op, _io_update_bits_T node _io_update_bits_T_1 = bits(_io_update_bits_WIRE_1, 33, 2) connect _io_update_bits_WIRE.data, _io_update_bits_T_1 node _io_update_bits_T_2 = bits(_io_update_bits_WIRE_1, 40, 34) connect _io_update_bits_WIRE.addr, _io_update_bits_T_2 connect io.update.bits, _io_update_bits_WIRE node captureBits_hi = cat(io.capture.bits.addr, io.capture.bits.data) node captureBits = cat(captureBits_hi, io.capture.bits.resp) when io.chainIn.capture : node _regs_0_T = bits(captureBits, 0, 0) connect regs_0, _regs_0_T node _regs_1_T = bits(captureBits, 1, 1) connect regs_1, _regs_1_T node _regs_2_T = bits(captureBits, 2, 2) connect regs_2, _regs_2_T node _regs_3_T = bits(captureBits, 3, 3) connect regs_3, _regs_3_T node _regs_4_T = bits(captureBits, 4, 4) connect regs_4, _regs_4_T node _regs_5_T = bits(captureBits, 5, 5) connect regs_5, _regs_5_T node _regs_6_T = bits(captureBits, 6, 6) connect regs_6, _regs_6_T node _regs_7_T = bits(captureBits, 7, 7) connect regs_7, _regs_7_T node _regs_8_T = bits(captureBits, 8, 8) connect regs_8, _regs_8_T node _regs_9_T = bits(captureBits, 9, 9) connect regs_9, _regs_9_T node _regs_10_T = bits(captureBits, 10, 10) connect regs_10, _regs_10_T node _regs_11_T = bits(captureBits, 11, 11) connect regs_11, _regs_11_T node _regs_12_T = bits(captureBits, 12, 12) connect regs_12, _regs_12_T node _regs_13_T = bits(captureBits, 13, 13) connect regs_13, _regs_13_T node _regs_14_T = bits(captureBits, 14, 14) connect regs_14, _regs_14_T node _regs_15_T = bits(captureBits, 15, 15) connect regs_15, _regs_15_T node _regs_16_T = bits(captureBits, 16, 16) connect regs_16, _regs_16_T node _regs_17_T = bits(captureBits, 17, 17) connect regs_17, _regs_17_T node _regs_18_T = bits(captureBits, 18, 18) connect regs_18, _regs_18_T node _regs_19_T = bits(captureBits, 19, 19) connect regs_19, _regs_19_T node _regs_20_T = bits(captureBits, 20, 20) connect regs_20, _regs_20_T node _regs_21_T = bits(captureBits, 21, 21) connect regs_21, _regs_21_T node _regs_22_T = bits(captureBits, 22, 22) connect regs_22, _regs_22_T node _regs_23_T = bits(captureBits, 23, 23) connect regs_23, _regs_23_T node _regs_24_T = bits(captureBits, 24, 24) connect regs_24, _regs_24_T node _regs_25_T = bits(captureBits, 25, 25) connect regs_25, _regs_25_T node _regs_26_T = bits(captureBits, 26, 26) connect regs_26, _regs_26_T node _regs_27_T = bits(captureBits, 27, 27) connect regs_27, _regs_27_T node _regs_28_T = bits(captureBits, 28, 28) connect regs_28, _regs_28_T node _regs_29_T = bits(captureBits, 29, 29) connect regs_29, _regs_29_T node _regs_30_T = bits(captureBits, 30, 30) connect regs_30, _regs_30_T node _regs_31_T = bits(captureBits, 31, 31) connect regs_31, _regs_31_T node _regs_32_T = bits(captureBits, 32, 32) connect regs_32, _regs_32_T node _regs_33_T = bits(captureBits, 33, 33) connect regs_33, _regs_33_T node _regs_34_T = bits(captureBits, 34, 34) connect regs_34, _regs_34_T node _regs_35_T = bits(captureBits, 35, 35) connect regs_35, _regs_35_T node _regs_36_T = bits(captureBits, 36, 36) connect regs_36, _regs_36_T node _regs_37_T = bits(captureBits, 37, 37) connect regs_37, _regs_37_T node _regs_38_T = bits(captureBits, 38, 38) connect regs_38, _regs_38_T node _regs_39_T = bits(captureBits, 39, 39) connect regs_39, _regs_39_T node _regs_40_T = bits(captureBits, 40, 40) connect regs_40, _regs_40_T connect io.capture.capture, UInt<1>(0h1) connect io.update.valid, UInt<1>(0h0) else : when io.chainIn.update : connect io.capture.capture, UInt<1>(0h0) connect io.update.valid, UInt<1>(0h1) else : when io.chainIn.shift : connect regs_40, io.chainIn.data connect regs_0, regs_1 connect regs_1, regs_2 connect regs_2, regs_3 connect regs_3, regs_4 connect regs_4, regs_5 connect regs_5, regs_6 connect regs_6, regs_7 connect regs_7, regs_8 connect regs_8, regs_9 connect regs_9, regs_10 connect regs_10, regs_11 connect regs_11, regs_12 connect regs_12, regs_13 connect regs_13, regs_14 connect regs_14, regs_15 connect regs_15, regs_16 connect regs_16, regs_17 connect regs_17, regs_18 connect regs_18, regs_19 connect regs_19, regs_20 connect regs_20, regs_21 connect regs_21, regs_22 connect regs_22, regs_23 connect regs_23, regs_24 connect regs_24, regs_25 connect regs_25, regs_26 connect regs_26, regs_27 connect regs_27, regs_28 connect regs_28, regs_29 connect regs_29, regs_30 connect regs_30, regs_31 connect regs_31, regs_32 connect regs_32, regs_33 connect regs_33, regs_34 connect regs_34, regs_35 connect regs_35, regs_36 connect regs_36, regs_37 connect regs_37, regs_38 connect regs_38, regs_39 connect regs_39, regs_40 connect io.capture.capture, UInt<1>(0h0) connect io.update.valid, UInt<1>(0h0) else : connect io.capture.capture, UInt<1>(0h0) connect io.update.valid, UInt<1>(0h0) node _T = and(io.chainIn.capture, io.chainIn.update) node _T_1 = eq(_T, UInt<1>(0h0)) node _T_2 = and(io.chainIn.capture, io.chainIn.shift) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = and(_T_1, _T_3) node _T_5 = and(io.chainIn.update, io.chainIn.shift) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = and(_T_4, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at JtagShifter.scala:185 assert(!(io.chainIn.capture && io.chainIn.update)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert	module CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate( // @[JtagShifter.scala:137:7] input clock, // @[JtagShifter.scala:137:7] input reset, // @[JtagShifter.scala:137:7] input io_chainIn_shift, // @[JtagShifter.scala:143:14] input io_chainIn_data, // @[JtagShifter.scala:143:14] input io_chainIn_capture, // @[JtagShifter.scala:143:14] input io_chainIn_update, // @[JtagShifter.scala:143:14] output io_chainOut_data, // @[JtagShifter.scala:143:14] input [6:0] io_capture_bits_addr, // @[JtagShifter.scala:143:14] input [31:0] io_capture_bits_data, // @[JtagShifter.scala:143:14] input [1:0] io_capture_bits_resp, // @[JtagShifter.scala:143:14] output io_capture_capture, // @[JtagShifter.scala:143:14] output io_update_valid, // @[JtagShifter.scala:143:14] output [6:0] io_update_bits_addr, // @[JtagShifter.scala:143:14] output [31:0] io_update_bits_data, // @[JtagShifter.scala:143:14] output [1:0] io_update_bits_op // @[JtagShifter.scala:143:14] ); reg regs_0; // @[JtagShifter.scala:156:39] reg regs_1; // @[JtagShifter.scala:156:39] reg regs_2; // @[JtagShifter.scala:156:39] reg regs_3; // @[JtagShifter.scala:156:39] reg regs_4; // @[JtagShifter.scala:156:39] reg regs_5; // @[JtagShifter.scala:156:39] reg regs_6; // @[JtagShifter.scala:156:39] reg regs_7; // @[JtagShifter.scala:156:39] reg regs_8; // @[JtagShifter.scala:156:39] reg regs_9; // @[JtagShifter.scala:156:39] reg regs_10; // @[JtagShifter.scala:156:39] reg regs_11; // @[JtagShifter.scala:156:39] reg regs_12; // @[JtagShifter.scala:156:39] reg regs_13; // @[JtagShifter.scala:156:39] reg regs_14; // @[JtagShifter.scala:156:39] reg regs_15; // @[JtagShifter.scala:156:39] reg regs_16; // @[JtagShifter.scala:156:39] reg regs_17; // @[JtagShifter.scala:156:39] reg regs_18; // @[JtagShifter.scala:156:39] reg regs_19; // @[JtagShifter.scala:156:39] reg regs_20; // @[JtagShifter.scala:156:39] reg regs_21; // @[JtagShifter.scala:156:39] reg regs_22; // @[JtagShifter.scala:156:39] reg regs_23; // @[JtagShifter.scala:156:39] reg regs_24; // @[JtagShifter.scala:156:39] reg regs_25; // @[JtagShifter.scala:156:39] reg regs_26; // @[JtagShifter.scala:156:39] reg regs_27; // @[JtagShifter.scala:156:39] reg regs_28; // @[JtagShifter.scala:156:39] reg regs_29; // @[JtagShifter.scala:156:39] reg regs_30; // @[JtagShifter.scala:156:39] reg regs_31; // @[JtagShifter.scala:156:39] reg regs_32; // @[JtagShifter.scala:156:39] reg regs_33; // @[JtagShifter.scala:156:39] reg regs_34; // @[JtagShifter.scala:156:39] reg regs_35; // @[JtagShifter.scala:156:39] reg regs_36; // @[JtagShifter.scala:156:39] reg regs_37; // @[JtagShifter.scala:156:39] reg regs_38; // @[JtagShifter.scala:156:39] reg regs_39; // @[JtagShifter.scala:156:39] reg regs_40; // @[JtagShifter.scala:156:39]
Generate the Verilog code corresponding to this FIRRTL code module PE_488 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_232 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_488( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_232 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<17>(0h10000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_50 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_51 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_189 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_199 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_189( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_199 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_9 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x	module PMPChecker_s3_9( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T \| _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T \| _res_hit_T_5; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess \| _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 \| _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = \|_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 \| res_aligned_lsbMask; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = \|_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound \| res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 \| _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 \| _res_hit_T_18; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 \| _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 \| _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = \|_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 \| res_aligned_lsbMask_1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = \|_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 \| res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 \| _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 \| _res_hit_T_31; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 \| _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 \| _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = \|_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 \| res_aligned_lsbMask_2; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = \|_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 \| res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 \| _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 \| _res_hit_T_44; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 \| _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 \| _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = \|_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 \| res_aligned_lsbMask_3; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = \|_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 \| res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 \| _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 \| _res_hit_T_57; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 \| _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 \| _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = \|_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 \| res_aligned_lsbMask_4; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = \|_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 \| res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 \| _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 \| _res_hit_T_70; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 \| _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 \| _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = \|_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 \| res_aligned_lsbMask_5; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = \|_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 \| res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 \| _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 \| _res_hit_T_83; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 \| _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 \| _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = \|_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 \| res_aligned_lsbMask_6; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = \|_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 \| res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 \| _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 \| _res_hit_T_96; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 \| _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 \| res_aligned_lsbMask_7; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = \|_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_156 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_177 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_156( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_177 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_52 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_5 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_109 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_52 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_5 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleD_a32d64s1k3z4u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleD_a32d64s1k3z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_sink, // @[Repeater.scala:13:14] input io_enq_bits_denied, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_sink, // @[Repeater.scala:13:14] output io_deq_bits_denied, // @[Repeater.scala:13:14] output [63:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [1:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [2:0] saved_sink; // @[Repeater.scala:21:18] reg saved_denied; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid \| full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN \| full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_sink <= io_enq_bits_sink; // @[Repeater.scala:21:18] saved_denied <= io_enq_bits_denied; // @[Repeater.scala:21:18] saved_data <= io_enq_bits_data; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_25 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_25( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PlusArgTimeout_2 : input clock : Clock input reset : Reset output io : { flip count : UInt<32>} inst plusarg_reader of plusarg_reader_104 node _T = gt(plusarg_reader.out, UInt<1>(0h0)) when _T : node _T_1 = lt(io.count, plusarg_reader.out) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert	module PlusArgTimeout_2( // @[PlusArg.scala:58:7] input clock, // @[PlusArg.scala:58:7] input reset, // @[PlusArg.scala:58:7] input [31:0] io_count // @[PlusArg.scala:59:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19] wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_36 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<17>(0h10000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = or(_T_156, _T_161) node _T_163 = and(_T_151, _T_162) node _T_164 = or(UInt<1>(0h0), _T_163) node _T_165 = and(_T_149, _T_164) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_165, UInt<1>(0h1), "") : assert_2 node _T_169 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_170 = shr(io.in.a.bits.source, 2) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = leq(UInt<1>(0h0), uncommonBits_8) node _T_173 = and(_T_171, _T_172) node _T_174 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_176 = shr(io.in.a.bits.source, 2) node _T_177 = eq(_T_176, UInt<1>(0h1)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_9) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_181 = and(_T_179, _T_180) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_182 = shr(io.in.a.bits.source, 2) node _T_183 = eq(_T_182, UInt<2>(0h2)) node _T_184 = leq(UInt<1>(0h0), uncommonBits_10) node _T_185 = and(_T_183, _T_184) node _T_186 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_187 = and(_T_185, _T_186) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_188 = shr(io.in.a.bits.source, 2) node _T_189 = eq(_T_188, UInt<2>(0h3)) node _T_190 = leq(UInt<1>(0h0), uncommonBits_11) node _T_191 = and(_T_189, _T_190) node _T_192 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_193 = and(_T_191, _T_192) node _T_194 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_195 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_196 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_197 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_169 connect _WIRE[1], _T_175 connect _WIRE[2], _T_181 connect _WIRE[3], _T_187 connect _WIRE[4], _T_193 connect _WIRE[5], _T_194 connect _WIRE[6], _T_195 connect _WIRE[7], _T_196 connect _WIRE[8], _T_197 node _T_198 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_199 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_200 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_202 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[5], _T_198, UInt<1>(0h0)) node _T_206 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[7], _T_199, UInt<1>(0h0)) node _T_208 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = or(_T_200, _T_201) node _T_210 = or(_T_209, _T_202) node _T_211 = or(_T_210, _T_203) node _T_212 = or(_T_211, _T_204) node _T_213 = or(_T_212, _T_205) node _T_214 = or(_T_213, _T_206) node _T_215 = or(_T_214, _T_207) node _T_216 = or(_T_215, _T_208) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h10000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h10000000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_12) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_13) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_14) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_15) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_294 = or(_T_265, _T_271) node _T_295 = or(_T_294, _T_277) node _T_296 = or(_T_295, _T_283) node _T_297 = or(_T_296, _T_289) node _T_298 = or(_T_297, _T_290) node _T_299 = or(_T_298, _T_291) node _T_300 = or(_T_299, _T_292) node _T_301 = or(_T_300, _T_293) node _T_302 = and(_T_264, _T_301) node _T_303 = or(UInt<1>(0h0), _T_302) node _T_304 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<29>(0h10000000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = or(_T_310, _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = and(_T_303, _T_318) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_319, UInt<1>(0h1), "") : assert_10 node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_16) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_17) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_18) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_19) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_349 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_323 connect _WIRE_2[1], _T_329 connect _WIRE_2[2], _T_335 connect _WIRE_2[3], _T_341 connect _WIRE_2[4], _T_347 connect _WIRE_2[5], _T_348 connect _WIRE_2[6], _T_349 connect _WIRE_2[7], _T_350 connect _WIRE_2[8], _T_351 node _T_352 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_353 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_354 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[5], _T_352, UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[7], _T_353, UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = or(_T_354, _T_355) node _T_364 = or(_T_363, _T_356) node _T_365 = or(_T_364, _T_357) node _T_366 = or(_T_365, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_370 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<17>(0h10000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<29>(0h10000000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = or(_T_379, _T_384) node _T_386 = and(_T_374, _T_385) node _T_387 = or(UInt<1>(0h0), _T_386) node _T_388 = and(_WIRE_3, _T_387) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_388, UInt<1>(0h1), "") : assert_11 node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(source_ok, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_395 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_395, UInt<1>(0h1), "") : assert_13 node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(is_aligned, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_402 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_402, UInt<1>(0h1), "") : assert_15 node _T_406 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_406, UInt<1>(0h1), "") : assert_16 node _T_410 = not(io.in.a.bits.mask) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_411, UInt<1>(0h1), "") : assert_17 node _T_415 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_415, UInt<1>(0h1), "") : assert_18 node _T_419 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_419 : node _T_420 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_421 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_422 = and(_T_420, _T_421) node _T_423 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_424 = shr(io.in.a.bits.source, 2) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_20) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_430 = shr(io.in.a.bits.source, 2) node _T_431 = eq(_T_430, UInt<1>(0h1)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_21) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<2>(0h2)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_22) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_442 = shr(io.in.a.bits.source, 2) node _T_443 = eq(_T_442, UInt<2>(0h3)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_23) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_452 = or(_T_423, _T_429) node _T_453 = or(_T_452, _T_435) node _T_454 = or(_T_453, _T_441) node _T_455 = or(_T_454, _T_447) node _T_456 = or(_T_455, _T_448) node _T_457 = or(_T_456, _T_449) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = and(_T_422, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_461, UInt<1>(0h1), "") : assert_19 node _T_465 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_466 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_467 = and(_T_465, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<29>(0h10000000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = or(_T_473, _T_478) node _T_480 = and(_T_468, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_481, UInt<1>(0h1), "") : assert_20 node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(source_ok, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(is_aligned, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_491 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_491, UInt<1>(0h1), "") : assert_23 node _T_495 = eq(io.in.a.bits.mask, mask) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_495, UInt<1>(0h1), "") : assert_24 node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_499, UInt<1>(0h1), "") : assert_25 node _T_503 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_503 : node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_508 = shr(io.in.a.bits.source, 2) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = leq(UInt<1>(0h0), uncommonBits_24) node _T_511 = and(_T_509, _T_510) node _T_512 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_513 = and(_T_511, _T_512) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_514 = shr(io.in.a.bits.source, 2) node _T_515 = eq(_T_514, UInt<1>(0h1)) node _T_516 = leq(UInt<1>(0h0), uncommonBits_25) node _T_517 = and(_T_515, _T_516) node _T_518 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_519 = and(_T_517, _T_518) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_520 = shr(io.in.a.bits.source, 2) node _T_521 = eq(_T_520, UInt<2>(0h2)) node _T_522 = leq(UInt<1>(0h0), uncommonBits_26) node _T_523 = and(_T_521, _T_522) node _T_524 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_525 = and(_T_523, _T_524) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<2>(0h3)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_27) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_536 = or(_T_507, _T_513) node _T_537 = or(_T_536, _T_519) node _T_538 = or(_T_537, _T_525) node _T_539 = or(_T_538, _T_531) node _T_540 = or(_T_539, _T_532) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = and(_T_506, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_547 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_548 = and(_T_546, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_551 = cvt(_T_550) node _T_552 = and(_T_551, asSInt(UInt<17>(0h10000))) node _T_553 = asSInt(_T_552) node _T_554 = eq(_T_553, asSInt(UInt<1>(0h0))) node _T_555 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<29>(0h10000000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = or(_T_554, _T_559) node _T_561 = and(_T_549, _T_560) node _T_562 = or(UInt<1>(0h0), _T_561) node _T_563 = and(_T_545, _T_562) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_563, UInt<1>(0h1), "") : assert_26 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(source_ok, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(is_aligned, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_573 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_573, UInt<1>(0h1), "") : assert_29 node _T_577 = eq(io.in.a.bits.mask, mask) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_577, UInt<1>(0h1), "") : assert_30 node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_581 : node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_584 = and(_T_582, _T_583) node _T_585 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h0)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_28) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<1>(0h1)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_29) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h2)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_30) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<2>(0h3)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_31) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_613 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_614 = or(_T_585, _T_591) node _T_615 = or(_T_614, _T_597) node _T_616 = or(_T_615, _T_603) node _T_617 = or(_T_616, _T_609) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_584, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<17>(0h10000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<29>(0h10000000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = or(_T_632, _T_637) node _T_639 = and(_T_627, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_623, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_641, UInt<1>(0h1), "") : assert_31 node _T_645 = asUInt(reset) node _T_646 = eq(_T_645, UInt<1>(0h0)) when _T_646 : node _T_647 = eq(source_ok, UInt<1>(0h0)) when _T_647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(is_aligned, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_651 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_651, UInt<1>(0h1), "") : assert_34 node _T_655 = not(mask) node _T_656 = and(io.in.a.bits.mask, _T_655) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(_T_657, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_657, UInt<1>(0h1), "") : assert_35 node _T_661 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_661 : node _T_662 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_663 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h0)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_32) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<1>(0h1)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_33) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h2)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_34) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<2>(0h3)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_35) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = or(_T_665, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = or(_T_700, _T_693) node _T_702 = and(_T_664, _T_701) node _T_703 = or(UInt<1>(0h0), _T_702) node _T_704 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_705 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<17>(0h10000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<29>(0h10000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = or(_T_712, _T_717) node _T_719 = and(_T_707, _T_718) node _T_720 = or(UInt<1>(0h0), _T_719) node _T_721 = and(_T_703, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_721, UInt<1>(0h1), "") : assert_36 node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(source_ok, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(is_aligned, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_731 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_731, UInt<1>(0h1), "") : assert_39 node _T_735 = eq(io.in.a.bits.mask, mask) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_735, UInt<1>(0h1), "") : assert_40 node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_739 : node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<1>(0h0)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_36) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_750 = shr(io.in.a.bits.source, 2) node _T_751 = eq(_T_750, UInt<1>(0h1)) node _T_752 = leq(UInt<1>(0h0), uncommonBits_37) node _T_753 = and(_T_751, _T_752) node _T_754 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_755 = and(_T_753, _T_754) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_756 = shr(io.in.a.bits.source, 2) node _T_757 = eq(_T_756, UInt<2>(0h2)) node _T_758 = leq(UInt<1>(0h0), uncommonBits_38) node _T_759 = and(_T_757, _T_758) node _T_760 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_762 = shr(io.in.a.bits.source, 2) node _T_763 = eq(_T_762, UInt<2>(0h3)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_39) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_772 = or(_T_743, _T_749) node _T_773 = or(_T_772, _T_755) node _T_774 = or(_T_773, _T_761) node _T_775 = or(_T_774, _T_767) node _T_776 = or(_T_775, _T_768) node _T_777 = or(_T_776, _T_769) node _T_778 = or(_T_777, _T_770) node _T_779 = or(_T_778, _T_771) node _T_780 = and(_T_742, _T_779) node _T_781 = or(UInt<1>(0h0), _T_780) node _T_782 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_783 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_784 = and(_T_782, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_792 = cvt(_T_791) node _T_793 = and(_T_792, asSInt(UInt<29>(0h10000000))) node _T_794 = asSInt(_T_793) node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0))) node _T_796 = or(_T_790, _T_795) node _T_797 = and(_T_785, _T_796) node _T_798 = or(UInt<1>(0h0), _T_797) node _T_799 = and(_T_781, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_799, UInt<1>(0h1), "") : assert_41 node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(source_ok, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(is_aligned, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_809 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_809, UInt<1>(0h1), "") : assert_44 node _T_813 = eq(io.in.a.bits.mask, mask) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_813, UInt<1>(0h1), "") : assert_45 node _T_817 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_817 : node _T_818 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_819 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_820 = and(_T_818, _T_819) node _T_821 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_822 = shr(io.in.a.bits.source, 2) node _T_823 = eq(_T_822, UInt<1>(0h0)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_40) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_828 = shr(io.in.a.bits.source, 2) node _T_829 = eq(_T_828, UInt<1>(0h1)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_41) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_833 = and(_T_831, _T_832) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_834 = shr(io.in.a.bits.source, 2) node _T_835 = eq(_T_834, UInt<2>(0h2)) node _T_836 = leq(UInt<1>(0h0), uncommonBits_42) node _T_837 = and(_T_835, _T_836) node _T_838 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_839 = and(_T_837, _T_838) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_840 = shr(io.in.a.bits.source, 2) node _T_841 = eq(_T_840, UInt<2>(0h3)) node _T_842 = leq(UInt<1>(0h0), uncommonBits_43) node _T_843 = and(_T_841, _T_842) node _T_844 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_845 = and(_T_843, _T_844) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_850 = or(_T_821, _T_827) node _T_851 = or(_T_850, _T_833) node _T_852 = or(_T_851, _T_839) node _T_853 = or(_T_852, _T_845) node _T_854 = or(_T_853, _T_846) node _T_855 = or(_T_854, _T_847) node _T_856 = or(_T_855, _T_848) node _T_857 = or(_T_856, _T_849) node _T_858 = and(_T_820, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_861 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_862 = and(_T_860, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<17>(0h10000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<29>(0h10000000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = or(_T_868, _T_873) node _T_875 = and(_T_863, _T_874) node _T_876 = or(UInt<1>(0h0), _T_875) node _T_877 = and(_T_859, _T_876) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_877, UInt<1>(0h1), "") : assert_46 node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(source_ok, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(is_aligned, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_887 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_887, UInt<1>(0h1), "") : assert_49 node _T_891 = eq(io.in.a.bits.mask, mask) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_891, UInt<1>(0h1), "") : assert_50 node _T_895 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_895, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_899 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_899, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_903 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_903 : node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(source_ok_1, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_907 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_907, UInt<1>(0h1), "") : assert_54 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_911, UInt<1>(0h1), "") : assert_55 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_915, UInt<1>(0h1), "") : assert_56 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_919, UInt<1>(0h1), "") : assert_57 node _T_923 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_923 : node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(source_ok_1, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(sink_ok, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_930, UInt<1>(0h1), "") : assert_60 node _T_934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_934, UInt<1>(0h1), "") : assert_61 node _T_938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_938, UInt<1>(0h1), "") : assert_62 node _T_942 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_942, UInt<1>(0h1), "") : assert_63 node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_947 = or(UInt<1>(0h1), _T_946) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_947, UInt<1>(0h1), "") : assert_64 node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(source_ok_1, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(sink_ok, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_958 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_958, UInt<1>(0h1), "") : assert_67 node _T_962 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_962, UInt<1>(0h1), "") : assert_68 node _T_966 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_966, UInt<1>(0h1), "") : assert_69 node _T_970 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_971 = or(_T_970, io.in.d.bits.corrupt) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_971, UInt<1>(0h1), "") : assert_70 node _T_975 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_976 = or(UInt<1>(0h1), _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_976, UInt<1>(0h1), "") : assert_71 node _T_980 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_980 : node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(source_ok_1, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_984 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_984, UInt<1>(0h1), "") : assert_73 node _T_988 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_988, UInt<1>(0h1), "") : assert_74 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(UInt<1>(0h1), _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_993, UInt<1>(0h1), "") : assert_75 node _T_997 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_997 : node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(source_ok_1, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_77 node _T_1005 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1006 = or(_T_1005, io.in.d.bits.corrupt) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_78 node _T_1010 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1011 = or(UInt<1>(0h1), _T_1010) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_79 node _T_1015 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1015 : node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(source_ok_1, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_81 node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_82 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(UInt<1>(0h1), _T_1027) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1032 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_84 node _T_1036 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) node _T_1038 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<1>(0h0))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1044 = shr(io.in.b.bits.source, 2) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) node _T_1046 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) node _T_1051 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = or(_T_1050, _T_1055) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1057 = shr(io.in.b.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<1>(0h1)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) node _T_1064 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1065 = cvt(_T_1064) node _T_1066 = and(_T_1065, asSInt(UInt<1>(0h0))) node _T_1067 = asSInt(_T_1066) node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0))) node _T_1069 = or(_T_1063, _T_1068) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1070 = shr(io.in.b.bits.source, 2) node _T_1071 = eq(_T_1070, UInt<2>(0h2)) node _T_1072 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1073 = and(_T_1071, _T_1072) node _T_1074 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) node _T_1077 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<1>(0h0))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1083 = shr(io.in.b.bits.source, 2) node _T_1084 = eq(_T_1083, UInt<2>(0h3)) node _T_1085 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) node _T_1090 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1091 = cvt(_T_1090) node _T_1092 = and(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = asSInt(_T_1092) node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0))) node _T_1095 = or(_T_1089, _T_1094) node _T_1096 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1099 = cvt(_T_1098) node _T_1100 = and(_T_1099, asSInt(UInt<1>(0h0))) node _T_1101 = asSInt(_T_1100) node _T_1102 = eq(_T_1101, asSInt(UInt<1>(0h0))) node _T_1103 = or(_T_1097, _T_1102) node _T_1104 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) node _T_1106 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<1>(0h0))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = or(_T_1105, _T_1110) node _T_1112 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) node _T_1114 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = or(_T_1113, _T_1118) node _T_1120 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) node _T_1122 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = or(_T_1121, _T_1126) node _T_1128 = and(_T_1043, _T_1056) node _T_1129 = and(_T_1128, _T_1069) node _T_1130 = and(_T_1129, _T_1082) node _T_1131 = and(_T_1130, _T_1095) node _T_1132 = and(_T_1131, _T_1103) node _T_1133 = and(_T_1132, _T_1111) node _T_1134 = and(_T_1133, _T_1119) node _T_1135 = and(_T_1134, _T_1127) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[9] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 node _legal_source_T_29 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_30 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_31 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_32 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_33 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[5], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[6], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[7], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[8], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_38 = or(_legal_source_T_29, _legal_source_T_30) node _legal_source_T_39 = or(_legal_source_T_38, _legal_source_T_31) node _legal_source_T_40 = or(_legal_source_T_39, _legal_source_T_32) node _legal_source_T_41 = or(_legal_source_T_40, _legal_source_T_33) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_34) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_35) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_36) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_37) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_45 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1139 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1139 : node _T_1140 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1141 = shr(io.in.b.bits.source, 2) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) node _T_1143 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1146 = and(_T_1144, _T_1145) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1147 = shr(io.in.b.bits.source, 2) node _T_1148 = eq(_T_1147, UInt<1>(0h1)) node _T_1149 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1152 = and(_T_1150, _T_1151) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1153 = shr(io.in.b.bits.source, 2) node _T_1154 = eq(_T_1153, UInt<2>(0h2)) node _T_1155 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1158 = and(_T_1156, _T_1157) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<2>(0h3)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _T_1165 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1166 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1167 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1168 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[9] connect _WIRE_4[0], _T_1140 connect _WIRE_4[1], _T_1146 connect _WIRE_4[2], _T_1152 connect _WIRE_4[3], _T_1158 connect _WIRE_4[4], _T_1164 connect _WIRE_4[5], _T_1165 connect _WIRE_4[6], _T_1166 connect _WIRE_4[7], _T_1167 connect _WIRE_4[8], _T_1168 node _T_1169 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1170 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1171 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1172 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1173 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1174 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1175 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1176 = mux(_WIRE_4[5], _T_1169, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[7], _T_1170, UInt<1>(0h0)) node _T_1179 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1180 = or(_T_1171, _T_1172) node _T_1181 = or(_T_1180, _T_1173) node _T_1182 = or(_T_1181, _T_1174) node _T_1183 = or(_T_1182, _T_1175) node _T_1184 = or(_T_1183, _T_1176) node _T_1185 = or(_T_1184, _T_1177) node _T_1186 = or(_T_1185, _T_1178) node _T_1187 = or(_T_1186, _T_1179) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1187 node _T_1188 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1189 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = or(UInt<1>(0h0), _T_1190) node _T_1192 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1193 = cvt(_T_1192) node _T_1194 = and(_T_1193, asSInt(UInt<17>(0h10000))) node _T_1195 = asSInt(_T_1194) node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0))) node _T_1197 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1198 = cvt(_T_1197) node _T_1199 = and(_T_1198, asSInt(UInt<29>(0h10000000))) node _T_1200 = asSInt(_T_1199) node _T_1201 = eq(_T_1200, asSInt(UInt<1>(0h0))) node _T_1202 = or(_T_1196, _T_1201) node _T_1203 = and(_T_1191, _T_1202) node _T_1204 = or(UInt<1>(0h0), _T_1203) node _T_1205 = and(_WIRE_5, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_86 node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(address_ok, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(legal_source, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1218 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_90 node _T_1222 = eq(io.in.b.bits.mask, mask_1) node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(_T_1222, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1222, UInt<1>(0h1), "") : assert_91 node _T_1226 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_92 node _T_1230 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1230 : node _T_1231 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1232 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1233) node _T_1235 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<17>(0h10000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<29>(0h10000000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = or(_T_1239, _T_1244) node _T_1246 = and(_T_1234, _T_1245) node _T_1247 = or(UInt<1>(0h0), _T_1246) node _T_1248 = and(UInt<1>(0h0), _T_1247) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_93 node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(address_ok, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(legal_source, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1261 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_97 node _T_1265 = eq(io.in.b.bits.mask, mask_1) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_98 node _T_1269 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_99 node _T_1273 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1273 : node _T_1274 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1275 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = or(UInt<1>(0h0), _T_1276) node _T_1278 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1284 = cvt(_T_1283) node _T_1285 = and(_T_1284, asSInt(UInt<29>(0h10000000))) node _T_1286 = asSInt(_T_1285) node _T_1287 = eq(_T_1286, asSInt(UInt<1>(0h0))) node _T_1288 = or(_T_1282, _T_1287) node _T_1289 = and(_T_1277, _T_1288) node _T_1290 = or(UInt<1>(0h0), _T_1289) node _T_1291 = and(UInt<1>(0h0), _T_1290) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_100 node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(address_ok, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(legal_source, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1304 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_104 node _T_1308 = eq(io.in.b.bits.mask, mask_1) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_105 node _T_1312 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1312 : node _T_1313 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1314 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1315 = and(_T_1313, _T_1314) node _T_1316 = or(UInt<1>(0h0), _T_1315) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<29>(0h10000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = or(_T_1321, _T_1326) node _T_1328 = and(_T_1316, _T_1327) node _T_1329 = or(UInt<1>(0h0), _T_1328) node _T_1330 = and(UInt<1>(0h0), _T_1329) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_106 node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(address_ok, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(legal_source, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1343 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_110 node _T_1347 = not(mask_1) node _T_1348 = and(io.in.b.bits.mask, _T_1347) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_111 node _T_1353 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1353 : node _T_1354 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1355 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1356 = and(_T_1354, _T_1355) node _T_1357 = or(UInt<1>(0h0), _T_1356) node _T_1358 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1359 = cvt(_T_1358) node _T_1360 = and(_T_1359, asSInt(UInt<17>(0h10000))) node _T_1361 = asSInt(_T_1360) node _T_1362 = eq(_T_1361, asSInt(UInt<1>(0h0))) node _T_1363 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1364 = cvt(_T_1363) node _T_1365 = and(_T_1364, asSInt(UInt<29>(0h10000000))) node _T_1366 = asSInt(_T_1365) node _T_1367 = eq(_T_1366, asSInt(UInt<1>(0h0))) node _T_1368 = or(_T_1362, _T_1367) node _T_1369 = and(_T_1357, _T_1368) node _T_1370 = or(UInt<1>(0h0), _T_1369) node _T_1371 = and(UInt<1>(0h0), _T_1370) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_112 node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(address_ok, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(legal_source, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1384 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_116 node _T_1388 = eq(io.in.b.bits.mask, mask_1) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_117 node _T_1392 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1392 : node _T_1393 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1394 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = or(UInt<1>(0h0), _T_1395) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<29>(0h10000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = or(_T_1401, _T_1406) node _T_1408 = and(_T_1396, _T_1407) node _T_1409 = or(UInt<1>(0h0), _T_1408) node _T_1410 = and(UInt<1>(0h0), _T_1409) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_118 node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(address_ok, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(legal_source, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1423 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_122 node _T_1427 = eq(io.in.b.bits.mask, mask_1) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_123 node _T_1431 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1431 : node _T_1432 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1433 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<17>(0h10000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<29>(0h10000000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = or(_T_1440, _T_1445) node _T_1447 = and(_T_1435, _T_1446) node _T_1448 = or(UInt<1>(0h0), _T_1447) node _T_1449 = and(UInt<1>(0h0), _T_1448) node _T_1450 = asUInt(reset) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) when _T_1451 : node _T_1452 = eq(_T_1449, UInt<1>(0h0)) when _T_1452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1449, UInt<1>(0h1), "") : assert_124 node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(address_ok, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(legal_source, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1462 = eq(io.in.b.bits.mask, mask_1) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_128 node _T_1466 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1470 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_130 node _source_ok_T_72 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_73 = shr(io.in.c.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<1>(0h0)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h1)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<2>(0h2)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h3)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_98 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_99 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_100 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[9] connect _source_ok_WIRE_2[0], _source_ok_T_72 connect _source_ok_WIRE_2[1], _source_ok_T_78 connect _source_ok_WIRE_2[2], _source_ok_T_84 connect _source_ok_WIRE_2[3], _source_ok_T_90 connect _source_ok_WIRE_2[4], _source_ok_T_96 connect _source_ok_WIRE_2[5], _source_ok_T_97 connect _source_ok_WIRE_2[6], _source_ok_T_98 connect _source_ok_WIRE_2[7], _source_ok_T_99 connect _source_ok_WIRE_2[8], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_2[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_2[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_2[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_2[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_2[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_2[7]) node source_ok_2 = or(_source_ok_T_107, _source_ok_WIRE_2[8]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1474 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) node _T_1476 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = or(_T_1475, _T_1480) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1482 = shr(io.in.c.bits.source, 2) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) node _T_1484 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1485 = and(_T_1483, _T_1484) node _T_1486 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) node _T_1489 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = or(_T_1488, _T_1493) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1495 = shr(io.in.c.bits.source, 2) node _T_1496 = eq(_T_1495, UInt<1>(0h1)) node _T_1497 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1500 = and(_T_1498, _T_1499) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) node _T_1502 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1503 = cvt(_T_1502) node _T_1504 = and(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = asSInt(_T_1504) node _T_1506 = eq(_T_1505, asSInt(UInt<1>(0h0))) node _T_1507 = or(_T_1501, _T_1506) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1508 = shr(io.in.c.bits.source, 2) node _T_1509 = eq(_T_1508, UInt<2>(0h2)) node _T_1510 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1511 = and(_T_1509, _T_1510) node _T_1512 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1513 = and(_T_1511, _T_1512) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) node _T_1515 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1516 = cvt(_T_1515) node _T_1517 = and(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = asSInt(_T_1517) node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0))) node _T_1520 = or(_T_1514, _T_1519) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1521 = shr(io.in.c.bits.source, 2) node _T_1522 = eq(_T_1521, UInt<2>(0h3)) node _T_1523 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1524 = and(_T_1522, _T_1523) node _T_1525 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1526 = and(_T_1524, _T_1525) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) node _T_1528 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<1>(0h0))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = or(_T_1527, _T_1532) node _T_1534 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) node _T_1536 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = or(_T_1535, _T_1540) node _T_1542 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) node _T_1544 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<1>(0h0))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = or(_T_1543, _T_1548) node _T_1550 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) node _T_1552 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1553 = cvt(_T_1552) node _T_1554 = and(_T_1553, asSInt(UInt<1>(0h0))) node _T_1555 = asSInt(_T_1554) node _T_1556 = eq(_T_1555, asSInt(UInt<1>(0h0))) node _T_1557 = or(_T_1551, _T_1556) node _T_1558 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = and(_T_1481, _T_1494) node _T_1567 = and(_T_1566, _T_1507) node _T_1568 = and(_T_1567, _T_1520) node _T_1569 = and(_T_1568, _T_1533) node _T_1570 = and(_T_1569, _T_1541) node _T_1571 = and(_T_1570, _T_1549) node _T_1572 = and(_T_1571, _T_1557) node _T_1573 = and(_T_1572, _T_1565) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_131 node _T_1577 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1577 : node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(address_ok_1, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(source_ok_2, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1584 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_134 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1591 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_136 node _T_1595 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_137 node _T_1599 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1599 : node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(address_ok_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(source_ok_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1606 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_140 node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1613 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(_T_1613, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1613, UInt<1>(0h1), "") : assert_142 node _T_1617 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1617 : node _T_1618 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1619 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1620 = and(_T_1618, _T_1619) node _T_1621 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1622 = shr(io.in.c.bits.source, 2) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) node _T_1624 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1627 = and(_T_1625, _T_1626) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1628 = shr(io.in.c.bits.source, 2) node _T_1629 = eq(_T_1628, UInt<1>(0h1)) node _T_1630 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1631 = and(_T_1629, _T_1630) node _T_1632 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1633 = and(_T_1631, _T_1632) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1634 = shr(io.in.c.bits.source, 2) node _T_1635 = eq(_T_1634, UInt<2>(0h2)) node _T_1636 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1637 = and(_T_1635, _T_1636) node _T_1638 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1639 = and(_T_1637, _T_1638) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1640 = shr(io.in.c.bits.source, 2) node _T_1641 = eq(_T_1640, UInt<2>(0h3)) node _T_1642 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1643 = and(_T_1641, _T_1642) node _T_1644 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1645 = and(_T_1643, _T_1644) node _T_1646 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1647 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1648 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1649 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1650 = or(_T_1621, _T_1627) node _T_1651 = or(_T_1650, _T_1633) node _T_1652 = or(_T_1651, _T_1639) node _T_1653 = or(_T_1652, _T_1645) node _T_1654 = or(_T_1653, _T_1646) node _T_1655 = or(_T_1654, _T_1647) node _T_1656 = or(_T_1655, _T_1648) node _T_1657 = or(_T_1656, _T_1649) node _T_1658 = and(_T_1620, _T_1657) node _T_1659 = or(UInt<1>(0h0), _T_1658) node _T_1660 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1661 = or(UInt<1>(0h0), _T_1660) node _T_1662 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1663 = cvt(_T_1662) node _T_1664 = and(_T_1663, asSInt(UInt<17>(0h10000))) node _T_1665 = asSInt(_T_1664) node _T_1666 = eq(_T_1665, asSInt(UInt<1>(0h0))) node _T_1667 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<29>(0h10000000))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = or(_T_1666, _T_1671) node _T_1673 = and(_T_1661, _T_1672) node _T_1674 = or(UInt<1>(0h0), _T_1673) node _T_1675 = and(_T_1659, _T_1674) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_143 node _T_1679 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1680 = shr(io.in.c.bits.source, 2) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) node _T_1682 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1685 = and(_T_1683, _T_1684) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1686 = shr(io.in.c.bits.source, 2) node _T_1687 = eq(_T_1686, UInt<1>(0h1)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1691 = and(_T_1689, _T_1690) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1692 = shr(io.in.c.bits.source, 2) node _T_1693 = eq(_T_1692, UInt<2>(0h2)) node _T_1694 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1697 = and(_T_1695, _T_1696) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<2>(0h3)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1705 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1706 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1707 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[9] connect _WIRE_6[0], _T_1679 connect _WIRE_6[1], _T_1685 connect _WIRE_6[2], _T_1691 connect _WIRE_6[3], _T_1697 connect _WIRE_6[4], _T_1703 connect _WIRE_6[5], _T_1704 connect _WIRE_6[6], _T_1705 connect _WIRE_6[7], _T_1706 connect _WIRE_6[8], _T_1707 node _T_1708 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1709 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1710 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1711 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1712 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1713 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1714 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1715 = mux(_WIRE_6[5], _T_1708, UInt<1>(0h0)) node _T_1716 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1717 = mux(_WIRE_6[7], _T_1709, UInt<1>(0h0)) node _T_1718 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1719 = or(_T_1710, _T_1711) node _T_1720 = or(_T_1719, _T_1712) node _T_1721 = or(_T_1720, _T_1713) node _T_1722 = or(_T_1721, _T_1714) node _T_1723 = or(_T_1722, _T_1715) node _T_1724 = or(_T_1723, _T_1716) node _T_1725 = or(_T_1724, _T_1717) node _T_1726 = or(_T_1725, _T_1718) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1726 node _T_1727 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1728 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1729 = and(_T_1727, _T_1728) node _T_1730 = or(UInt<1>(0h0), _T_1729) node _T_1731 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1732 = cvt(_T_1731) node _T_1733 = and(_T_1732, asSInt(UInt<17>(0h10000))) node _T_1734 = asSInt(_T_1733) node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0))) node _T_1736 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1737 = cvt(_T_1736) node _T_1738 = and(_T_1737, asSInt(UInt<29>(0h10000000))) node _T_1739 = asSInt(_T_1738) node _T_1740 = eq(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = or(_T_1735, _T_1740) node _T_1742 = and(_T_1730, _T_1741) node _T_1743 = or(UInt<1>(0h0), _T_1742) node _T_1744 = and(_WIRE_7, _T_1743) node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(_T_1744, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1744, UInt<1>(0h1), "") : assert_144 node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(source_ok_2, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1751 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1752 = asUInt(reset) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) when _T_1753 : node _T_1754 = eq(_T_1751, UInt<1>(0h0)) when _T_1754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1751, UInt<1>(0h1), "") : assert_146 node _T_1755 = asUInt(reset) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) when _T_1756 : node _T_1757 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1758 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1759 = asUInt(reset) node _T_1760 = eq(_T_1759, UInt<1>(0h0)) when _T_1760 : node _T_1761 = eq(_T_1758, UInt<1>(0h0)) when _T_1761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1758, UInt<1>(0h1), "") : assert_148 node _T_1762 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_149 node _T_1766 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1766 : node _T_1767 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1768 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1769 = and(_T_1767, _T_1768) node _T_1770 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_1771 = shr(io.in.c.bits.source, 2) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) node _T_1773 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1774 = and(_T_1772, _T_1773) node _T_1775 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_1776 = and(_T_1774, _T_1775) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1777 = shr(io.in.c.bits.source, 2) node _T_1778 = eq(_T_1777, UInt<1>(0h1)) node _T_1779 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1782 = and(_T_1780, _T_1781) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1783 = shr(io.in.c.bits.source, 2) node _T_1784 = eq(_T_1783, UInt<2>(0h2)) node _T_1785 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1788 = and(_T_1786, _T_1787) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1789 = shr(io.in.c.bits.source, 2) node _T_1790 = eq(_T_1789, UInt<2>(0h3)) node _T_1791 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1792 = and(_T_1790, _T_1791) node _T_1793 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1794 = and(_T_1792, _T_1793) node _T_1795 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1796 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1797 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1798 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1799 = or(_T_1770, _T_1776) node _T_1800 = or(_T_1799, _T_1782) node _T_1801 = or(_T_1800, _T_1788) node _T_1802 = or(_T_1801, _T_1794) node _T_1803 = or(_T_1802, _T_1795) node _T_1804 = or(_T_1803, _T_1796) node _T_1805 = or(_T_1804, _T_1797) node _T_1806 = or(_T_1805, _T_1798) node _T_1807 = and(_T_1769, _T_1806) node _T_1808 = or(UInt<1>(0h0), _T_1807) node _T_1809 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1810 = or(UInt<1>(0h0), _T_1809) node _T_1811 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1812 = cvt(_T_1811) node _T_1813 = and(_T_1812, asSInt(UInt<17>(0h10000))) node _T_1814 = asSInt(_T_1813) node _T_1815 = eq(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1817 = cvt(_T_1816) node _T_1818 = and(_T_1817, asSInt(UInt<29>(0h10000000))) node _T_1819 = asSInt(_T_1818) node _T_1820 = eq(_T_1819, asSInt(UInt<1>(0h0))) node _T_1821 = or(_T_1815, _T_1820) node _T_1822 = and(_T_1810, _T_1821) node _T_1823 = or(UInt<1>(0h0), _T_1822) node _T_1824 = and(_T_1808, _T_1823) node _T_1825 = asUInt(reset) node _T_1826 = eq(_T_1825, UInt<1>(0h0)) when _T_1826 : node _T_1827 = eq(_T_1824, UInt<1>(0h0)) when _T_1827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1824, UInt<1>(0h1), "") : assert_150 node _T_1828 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1829 = shr(io.in.c.bits.source, 2) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) node _T_1831 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1832 = and(_T_1830, _T_1831) node _T_1833 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1834 = and(_T_1832, _T_1833) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_1835 = shr(io.in.c.bits.source, 2) node _T_1836 = eq(_T_1835, UInt<1>(0h1)) node _T_1837 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1838 = and(_T_1836, _T_1837) node _T_1839 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_1840 = and(_T_1838, _T_1839) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1841 = shr(io.in.c.bits.source, 2) node _T_1842 = eq(_T_1841, UInt<2>(0h2)) node _T_1843 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1844 = and(_T_1842, _T_1843) node _T_1845 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1846 = and(_T_1844, _T_1845) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1847 = shr(io.in.c.bits.source, 2) node _T_1848 = eq(_T_1847, UInt<2>(0h3)) node _T_1849 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1850 = and(_T_1848, _T_1849) node _T_1851 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1852 = and(_T_1850, _T_1851) node _T_1853 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1854 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1855 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1856 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[9] connect _WIRE_8[0], _T_1828 connect _WIRE_8[1], _T_1834 connect _WIRE_8[2], _T_1840 connect _WIRE_8[3], _T_1846 connect _WIRE_8[4], _T_1852 connect _WIRE_8[5], _T_1853 connect _WIRE_8[6], _T_1854 connect _WIRE_8[7], _T_1855 connect _WIRE_8[8], _T_1856 node _T_1857 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1858 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1859 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1860 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1861 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1862 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1863 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1864 = mux(_WIRE_8[5], _T_1857, UInt<1>(0h0)) node _T_1865 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1866 = mux(_WIRE_8[7], _T_1858, UInt<1>(0h0)) node _T_1867 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1868 = or(_T_1859, _T_1860) node _T_1869 = or(_T_1868, _T_1861) node _T_1870 = or(_T_1869, _T_1862) node _T_1871 = or(_T_1870, _T_1863) node _T_1872 = or(_T_1871, _T_1864) node _T_1873 = or(_T_1872, _T_1865) node _T_1874 = or(_T_1873, _T_1866) node _T_1875 = or(_T_1874, _T_1867) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1875 node _T_1876 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1877 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = or(UInt<1>(0h0), _T_1878) node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1881 = cvt(_T_1880) node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000))) node _T_1883 = asSInt(_T_1882) node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = and(_T_1879, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1891) node _T_1893 = and(_WIRE_9, _T_1892) node _T_1894 = asUInt(reset) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) when _T_1895 : node _T_1896 = eq(_T_1893, UInt<1>(0h0)) when _T_1896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1893, UInt<1>(0h1), "") : assert_151 node _T_1897 = asUInt(reset) node _T_1898 = eq(_T_1897, UInt<1>(0h0)) when _T_1898 : node _T_1899 = eq(source_ok_2, UInt<1>(0h0)) when _T_1899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1900 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1901 = asUInt(reset) node _T_1902 = eq(_T_1901, UInt<1>(0h0)) when _T_1902 : node _T_1903 = eq(_T_1900, UInt<1>(0h0)) when _T_1903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1900, UInt<1>(0h1), "") : assert_153 node _T_1904 = asUInt(reset) node _T_1905 = eq(_T_1904, UInt<1>(0h0)) when _T_1905 : node _T_1906 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1907 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1908 = asUInt(reset) node _T_1909 = eq(_T_1908, UInt<1>(0h0)) when _T_1909 : node _T_1910 = eq(_T_1907, UInt<1>(0h0)) when _T_1910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1907, UInt<1>(0h1), "") : assert_155 node _T_1911 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1911 : node _T_1912 = asUInt(reset) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) when _T_1913 : node _T_1914 = eq(address_ok_1, UInt<1>(0h0)) when _T_1914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(source_ok_2, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1918 = asUInt(reset) node _T_1919 = eq(_T_1918, UInt<1>(0h0)) when _T_1919 : node _T_1920 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1921 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1922 = asUInt(reset) node _T_1923 = eq(_T_1922, UInt<1>(0h0)) when _T_1923 : node _T_1924 = eq(_T_1921, UInt<1>(0h0)) when _T_1924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1921, UInt<1>(0h1), "") : assert_159 node _T_1925 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1926 = asUInt(reset) node _T_1927 = eq(_T_1926, UInt<1>(0h0)) when _T_1927 : node _T_1928 = eq(_T_1925, UInt<1>(0h0)) when _T_1928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1925, UInt<1>(0h1), "") : assert_160 node _T_1929 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1929 : node _T_1930 = asUInt(reset) node _T_1931 = eq(_T_1930, UInt<1>(0h0)) when _T_1931 : node _T_1932 = eq(address_ok_1, UInt<1>(0h0)) when _T_1932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1933 = asUInt(reset) node _T_1934 = eq(_T_1933, UInt<1>(0h0)) when _T_1934 : node _T_1935 = eq(source_ok_2, UInt<1>(0h0)) when _T_1935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1936 = asUInt(reset) node _T_1937 = eq(_T_1936, UInt<1>(0h0)) when _T_1937 : node _T_1938 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1939 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_164 node _T_1943 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1943 : node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(address_ok_1, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1947 = asUInt(reset) node _T_1948 = eq(_T_1947, UInt<1>(0h0)) when _T_1948 : node _T_1949 = eq(source_ok_2, UInt<1>(0h0)) when _T_1949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1950 = asUInt(reset) node _T_1951 = eq(_T_1950, UInt<1>(0h0)) when _T_1951 : node _T_1952 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1953 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(_T_1953, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1953, UInt<1>(0h1), "") : assert_168 node _T_1957 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1964 = eq(a_first, UInt<1>(0h0)) node _T_1965 = and(io.in.a.valid, _T_1964) when _T_1965 : node _T_1966 = eq(io.in.a.bits.opcode, opcode) node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(_T_1966, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1966, UInt<1>(0h1), "") : assert_171 node _T_1970 = eq(io.in.a.bits.param, param) node _T_1971 = asUInt(reset) node _T_1972 = eq(_T_1971, UInt<1>(0h0)) when _T_1972 : node _T_1973 = eq(_T_1970, UInt<1>(0h0)) when _T_1973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1970, UInt<1>(0h1), "") : assert_172 node _T_1974 = eq(io.in.a.bits.size, size) node _T_1975 = asUInt(reset) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : node _T_1977 = eq(_T_1974, UInt<1>(0h0)) when _T_1977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1974, UInt<1>(0h1), "") : assert_173 node _T_1978 = eq(io.in.a.bits.source, source) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_174 node _T_1982 = eq(io.in.a.bits.address, address) node _T_1983 = asUInt(reset) node _T_1984 = eq(_T_1983, UInt<1>(0h0)) when _T_1984 : node _T_1985 = eq(_T_1982, UInt<1>(0h0)) when _T_1985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1982, UInt<1>(0h1), "") : assert_175 node _T_1986 = and(io.in.a.ready, io.in.a.valid) node _T_1987 = and(_T_1986, a_first) when _T_1987 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1988 = eq(d_first, UInt<1>(0h0)) node _T_1989 = and(io.in.d.valid, _T_1988) when _T_1989 : node _T_1990 = eq(io.in.d.bits.opcode, opcode_1) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_176 node _T_1994 = eq(io.in.d.bits.param, param_1) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_177 node _T_1998 = eq(io.in.d.bits.size, size_1) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_178 node _T_2002 = eq(io.in.d.bits.source, source_1) node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(_T_2002, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2002, UInt<1>(0h1), "") : assert_179 node _T_2006 = eq(io.in.d.bits.sink, sink) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_180 node _T_2010 = eq(io.in.d.bits.denied, denied) node _T_2011 = asUInt(reset) node _T_2012 = eq(_T_2011, UInt<1>(0h0)) when _T_2012 : node _T_2013 = eq(_T_2010, UInt<1>(0h0)) when _T_2013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2010, UInt<1>(0h1), "") : assert_181 node _T_2014 = and(io.in.d.ready, io.in.d.valid) node _T_2015 = and(_T_2014, d_first) when _T_2015 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2016 = eq(b_first, UInt<1>(0h0)) node _T_2017 = and(io.in.b.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.b.bits.opcode, opcode_2) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_182 node _T_2022 = eq(io.in.b.bits.param, param_2) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_183 node _T_2026 = eq(io.in.b.bits.size, size_2) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_184 node _T_2030 = eq(io.in.b.bits.source, source_2) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_185 node _T_2034 = eq(io.in.b.bits.address, address_1) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_186 node _T_2038 = and(io.in.b.ready, io.in.b.valid) node _T_2039 = and(_T_2038, b_first) when _T_2039 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2040 = eq(c_first, UInt<1>(0h0)) node _T_2041 = and(io.in.c.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.c.bits.opcode, opcode_3) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_187 node _T_2046 = eq(io.in.c.bits.param, param_3) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_188 node _T_2050 = eq(io.in.c.bits.size, size_3) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_189 node _T_2054 = eq(io.in.c.bits.source, source_3) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_190 node _T_2058 = eq(io.in.c.bits.address, address_2) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_191 node _T_2062 = and(io.in.c.ready, io.in.c.valid) node _T_2063 = and(_T_2062, c_first) when _T_2063 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<39>, clock, reset, UInt<39>(0h0) regreset inflight_opcodes : UInt<156>, clock, reset, UInt<156>(0h0) regreset inflight_sizes : UInt<156>, clock, reset, UInt<156>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<39> connect a_set, UInt<39>(0h0) wire a_set_wo_ready : UInt<39> connect a_set_wo_ready, UInt<39>(0h0) wire a_opcodes_set : UInt<156> connect a_opcodes_set, UInt<156>(0h0) wire a_sizes_set : UInt<156> connect a_sizes_set, UInt<156>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2064 = and(io.in.a.valid, a_first_1) node _T_2065 = and(_T_2064, UInt<1>(0h1)) when _T_2065 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2066 = and(io.in.a.ready, io.in.a.valid) node _T_2067 = and(_T_2066, a_first_1) node _T_2068 = and(_T_2067, UInt<1>(0h1)) when _T_2068 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2069 = dshr(inflight, io.in.a.bits.source) node _T_2070 = bits(_T_2069, 0, 0) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<39> connect d_clr, UInt<39>(0h0) wire d_clr_wo_ready : UInt<39> connect d_clr_wo_ready, UInt<39>(0h0) wire d_opcodes_clr : UInt<156> connect d_opcodes_clr, UInt<156>(0h0) wire d_sizes_clr : UInt<156> connect d_sizes_clr, UInt<156>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2075 = and(io.in.d.valid, d_first_1) node _T_2076 = and(_T_2075, UInt<1>(0h1)) node _T_2077 = eq(d_release_ack, UInt<1>(0h0)) node _T_2078 = and(_T_2076, _T_2077) when _T_2078 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2079 = and(io.in.d.ready, io.in.d.valid) node _T_2080 = and(_T_2079, d_first_1) node _T_2081 = and(_T_2080, UInt<1>(0h1)) node _T_2082 = eq(d_release_ack, UInt<1>(0h0)) node _T_2083 = and(_T_2081, _T_2082) when _T_2083 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2084 = and(io.in.d.valid, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2088 = dshr(inflight, io.in.d.bits.source) node _T_2089 = bits(_T_2088, 0, 0) node _T_2090 = or(_T_2089, same_cycle_resp) node _T_2091 = asUInt(reset) node _T_2092 = eq(_T_2091, UInt<1>(0h0)) when _T_2092 : node _T_2093 = eq(_T_2090, UInt<1>(0h0)) when _T_2093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2090, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2094 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2095 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2096 = or(_T_2094, _T_2095) node _T_2097 = asUInt(reset) node _T_2098 = eq(_T_2097, UInt<1>(0h0)) when _T_2098 : node _T_2099 = eq(_T_2096, UInt<1>(0h0)) when _T_2099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2096, UInt<1>(0h1), "") : assert_194 node _T_2100 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_195 else : node _T_2104 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2105 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2106 = or(_T_2104, _T_2105) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_196 node _T_2110 = eq(io.in.d.bits.size, a_size_lookup) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_197 node _T_2114 = and(io.in.d.valid, d_first_1) node _T_2115 = and(_T_2114, a_first_1) node _T_2116 = and(_T_2115, io.in.a.valid) node _T_2117 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2118 = and(_T_2116, _T_2117) node _T_2119 = eq(d_release_ack, UInt<1>(0h0)) node _T_2120 = and(_T_2118, _T_2119) when _T_2120 : node _T_2121 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2122 = or(_T_2121, io.in.a.ready) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_198 node _T_2126 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2127 = orr(a_set_wo_ready) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) node _T_2129 = or(_T_2126, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_72 node _T_2133 = orr(inflight) node _T_2134 = eq(_T_2133, UInt<1>(0h0)) node _T_2135 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2136 = or(_T_2134, _T_2135) node _T_2137 = lt(watchdog, plusarg_reader.out) node _T_2138 = or(_T_2136, _T_2137) node _T_2139 = asUInt(reset) node _T_2140 = eq(_T_2139, UInt<1>(0h0)) when _T_2140 : node _T_2141 = eq(_T_2138, UInt<1>(0h0)) when _T_2141 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2138, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2142 = and(io.in.a.ready, io.in.a.valid) node _T_2143 = and(io.in.d.ready, io.in.d.valid) node _T_2144 = or(_T_2142, _T_2143) when _T_2144 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<39>, clock, reset, UInt<39>(0h0) regreset inflight_opcodes_1 : UInt<156>, clock, reset, UInt<156>(0h0) regreset inflight_sizes_1 : UInt<156>, clock, reset, UInt<156>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<39> connect c_set, UInt<39>(0h0) wire c_set_wo_ready : UInt<39> connect c_set_wo_ready, UInt<39>(0h0) wire c_opcodes_set : UInt<156> connect c_opcodes_set, UInt<156>(0h0) wire c_sizes_set : UInt<156> connect c_sizes_set, UInt<156>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2145 = and(io.in.c.valid, c_first_1) node _T_2146 = bits(io.in.c.bits.opcode, 2, 2) node _T_2147 = bits(io.in.c.bits.opcode, 1, 1) node _T_2148 = and(_T_2146, _T_2147) node _T_2149 = and(_T_2145, _T_2148) when _T_2149 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2150 = and(io.in.c.ready, io.in.c.valid) node _T_2151 = and(_T_2150, c_first_1) node _T_2152 = bits(io.in.c.bits.opcode, 2, 2) node _T_2153 = bits(io.in.c.bits.opcode, 1, 1) node _T_2154 = and(_T_2152, _T_2153) node _T_2155 = and(_T_2151, _T_2154) when _T_2155 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2156 = dshr(inflight_1, io.in.c.bits.source) node _T_2157 = bits(_T_2156, 0, 0) node _T_2158 = eq(_T_2157, UInt<1>(0h0)) node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(_T_2158, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2158, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<39> connect d_clr_1, UInt<39>(0h0) wire d_clr_wo_ready_1 : UInt<39> connect d_clr_wo_ready_1, UInt<39>(0h0) wire d_opcodes_clr_1 : UInt<156> connect d_opcodes_clr_1, UInt<156>(0h0) wire d_sizes_clr_1 : UInt<156> connect d_sizes_clr_1, UInt<156>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2162 = and(io.in.d.valid, d_first_2) node _T_2163 = and(_T_2162, UInt<1>(0h1)) node _T_2164 = and(_T_2163, d_release_ack_1) when _T_2164 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2165 = and(io.in.d.ready, io.in.d.valid) node _T_2166 = and(_T_2165, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2169 = and(io.in.d.valid, d_first_2) node _T_2170 = and(_T_2169, UInt<1>(0h1)) node _T_2171 = and(_T_2170, d_release_ack_1) when _T_2171 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2172 = dshr(inflight_1, io.in.d.bits.source) node _T_2173 = bits(_T_2172, 0, 0) node _T_2174 = or(_T_2173, same_cycle_resp_1) node _T_2175 = asUInt(reset) node _T_2176 = eq(_T_2175, UInt<1>(0h0)) when _T_2176 : node _T_2177 = eq(_T_2174, UInt<1>(0h0)) when _T_2177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2174, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2178 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2179 = asUInt(reset) node _T_2180 = eq(_T_2179, UInt<1>(0h0)) when _T_2180 : node _T_2181 = eq(_T_2178, UInt<1>(0h0)) when _T_2181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2178, UInt<1>(0h1), "") : assert_203 else : node _T_2182 = eq(io.in.d.bits.size, c_size_lookup) node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(_T_2182, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2182, UInt<1>(0h1), "") : assert_204 node _T_2186 = and(io.in.d.valid, d_first_2) node _T_2187 = and(_T_2186, c_first_1) node _T_2188 = and(_T_2187, io.in.c.valid) node _T_2189 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2190 = and(_T_2188, _T_2189) node _T_2191 = and(_T_2190, d_release_ack_1) node _T_2192 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2193 = and(_T_2191, _T_2192) when _T_2193 : node _T_2194 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2195 = or(_T_2194, io.in.c.ready) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_205 node _T_2199 = orr(c_set_wo_ready) when _T_2199 : node _T_2200 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_73 node _T_2204 = orr(inflight_1) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) node _T_2206 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2207 = or(_T_2205, _T_2206) node _T_2208 = lt(watchdog_1, plusarg_reader_1.out) node _T_2209 = or(_T_2207, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2213 = and(io.in.c.ready, io.in.c.valid) node _T_2214 = and(io.in.d.ready, io.in.d.valid) node _T_2215 = or(_T_2213, _T_2214) when _T_2215 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2216 = and(io.in.d.ready, io.in.d.valid) node _T_2217 = and(_T_2216, d_first_3) node _T_2218 = bits(io.in.d.bits.opcode, 2, 2) node _T_2219 = bits(io.in.d.bits.opcode, 1, 1) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) node _T_2221 = and(_T_2218, _T_2220) node _T_2222 = and(_T_2217, _T_2221) when _T_2222 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2223 = dshr(inflight_2, io.in.d.bits.sink) node _T_2224 = bits(_T_2223, 0, 0) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2229 = and(io.in.e.ready, io.in.e.valid) node _T_2230 = and(_T_2229, UInt<1>(0h1)) node _T_2231 = and(_T_2230, UInt<1>(0h1)) when _T_2231 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2232 = or(d_set, inflight_2) node _T_2233 = dshr(_T_2232, io.in.e.bits.sink) node _T_2234 = bits(_T_2233, 0, 0) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [5:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_30 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_2 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_3 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_37 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_43 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_49 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_55 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire _legal_source_T = io_in_b_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _legal_source_T_1 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_7 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_13 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_19 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_25 = io_in_b_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _legal_source_T_26 = io_in_b_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _legal_source_T_27 = io_in_b_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _legal_source_T_28 = io_in_b_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_2 = _legal_source_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_4 = _legal_source_T_2; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_6 = _legal_source_T_4; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_8 = _legal_source_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_10 = _legal_source_T_8; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_12 = _legal_source_T_10; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_2 = _legal_source_T_12; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_2 = _legal_source_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_14 = _legal_source_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_16 = _legal_source_T_14; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_18 = _legal_source_T_16; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_3 = _legal_source_T_18; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_3 = _legal_source_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_20 = _legal_source_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_22 = _legal_source_T_20; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_24 = _legal_source_T_22; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_4 = _legal_source_T_24; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = _legal_source_T_25; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = _legal_source_T_26; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = _legal_source_T_27; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = _legal_source_T_28; // @[Parameters.scala:1138:31] wire [4:0] _legal_source_T_29 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_38 = _legal_source_T_29; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_31 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_32 = {_legal_source_WIRE_3, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_33 = _legal_source_WIRE_4 ? 4'hC : 4'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_34 = _legal_source_WIRE_5 ? 6'h24 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_35 = _legal_source_WIRE_6 ? 6'h26 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_36 = {_legal_source_WIRE_7, 5'h0}; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_37 = _legal_source_WIRE_8 ? 6'h22 : 6'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_39 = {_legal_source_T_38[4:3], _legal_source_T_38[2:0] \| _legal_source_T_31}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_40 = {_legal_source_T_39[4], _legal_source_T_39[3:0] \| _legal_source_T_32}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = {_legal_source_T_40[4], _legal_source_T_40[3:0] \| _legal_source_T_33}; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_42 = {1'h0, _legal_source_T_41} \| _legal_source_T_34; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_43 = _legal_source_T_42 \| _legal_source_T_35; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_44 = _legal_source_T_43 \| _legal_source_T_36; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = _legal_source_T_44 \| _legal_source_T_37; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1_0 = _legal_source_T_45; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_73 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_74 = _source_ok_T_73 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_c_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_5 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_c_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_c_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_c_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_8 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 \| _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 \| _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_107 \| _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_2142 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2142; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2142; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2216 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2216; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2216; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2216; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2216; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2213 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2213; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2213; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [38:0] inflight; // @[Monitor.scala:614:27] reg [155:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [155:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [38:0] a_set; // @[Monitor.scala:626:34] wire [38:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [155:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [155:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [155:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [155:0] _a_opcode_lookup_T_6 = {152'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [155:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[155:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [155:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [155:0] _a_size_lookup_T_6 = {152'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [155:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[155:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2068 = _T_2142 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2068 ? _a_set_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2068 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2068 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2068 ? _a_opcodes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2068 ? _a_sizes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [38:0] d_clr; // @[Monitor.scala:664:34] wire [38:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [155:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [155:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2114 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2114 & ~d_release_ack ? _d_clr_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2083 = _T_2216 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2083 ? _d_clr_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2083 ? _d_opcodes_clr_T_5[155:0] : 156'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2083 ? _d_sizes_clr_T_5[155:0] : 156'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [38:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [38:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [38:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [155:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [155:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [155:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [155:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [155:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [155:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [38:0] inflight_1; // @[Monitor.scala:726:35] reg [155:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [155:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [38:0] c_set; // @[Monitor.scala:738:34] wire [38:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [155:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [155:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [155:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [155:0] _c_opcode_lookup_T_6 = {152'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [155:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[155:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [155:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [155:0] _c_size_lookup_T_6 = {152'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [155:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[155:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2155 = _T_2213 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2155 ? _c_set_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2155 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2155 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2155 ? _c_opcodes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2155 ? _c_sizes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [38:0] d_clr_1; // @[Monitor.scala:774:34] wire [38:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [155:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [155:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2186 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2186 & d_release_ack_1 ? _d_clr_wo_ready_T_1[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2168 = _T_2216 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2168 ? _d_clr_T_1[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2168 ? _d_opcodes_clr_T_11[155:0] : 156'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2168 ? _d_sizes_clr_T_11[155:0] : 156'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [38:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [38:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [38:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [155:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [155:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [155:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [155:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [155:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [155:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_2222 = _T_2216 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2222 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_4 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_4( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AXI4IdIndexer : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.tl_state.source invalidate nodeOut.r.bits.echo.tl_state.size invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.tl_state.source invalidate nodeOut.ar.bits.echo.tl_state.size invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.tl_state.source invalidate nodeOut.b.bits.echo.tl_state.size invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.tl_state.source invalidate nodeOut.aw.bits.echo.tl_state.size invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.ar.bits.echo.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect nodeOut.ar.bits.echo.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id connect nodeOut.ar.valid, nodeIn.ar.valid connect nodeIn.ar.ready, nodeOut.ar.ready connect nodeOut.aw.bits.echo.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect nodeOut.aw.bits.echo.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id connect nodeOut.aw.valid, nodeIn.aw.valid connect nodeIn.aw.ready, nodeOut.aw.ready connect nodeOut.w.bits.last, nodeIn.w.bits.last connect nodeOut.w.bits.strb, nodeIn.w.bits.strb connect nodeOut.w.bits.data, nodeIn.w.bits.data connect nodeOut.w.valid, nodeIn.w.valid connect nodeIn.w.ready, nodeOut.w.ready connect nodeIn.b.bits.echo.tl_state.source, nodeOut.b.bits.echo.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, nodeOut.b.bits.echo.tl_state.size connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.tl_state.source, nodeOut.r.bits.echo.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, nodeOut.r.bits.echo.tl_state.size connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready extmodule plusarg_reader_22 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_23 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module AXI4IdIndexer( // @[IdIndexer.scala:63:9] input clock, // @[IdIndexer.scala:63:9] input reset, // @[IdIndexer.scala:63:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[IdIndexer.scala:63:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[IdIndexer.scala:63:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[IdIndexer.scala:63:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[IdIndexer.scala:63:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[IdIndexer.scala:63:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[IdIndexer.scala:63:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[IdIndexer.scala:63:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] wire auto_in_w_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_b_valid_0; // @[IdIndexer.scala:63:9] wire auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_out_w_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_b_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_r_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[IdIndexer.scala:63:9] assign nodeOut_aw_valid = nodeIn_aw_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_size = nodeIn_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_source = nodeIn_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[IdIndexer.scala:63:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[IdIndexer.scala:63:9] assign nodeOut_ar_valid = nodeIn_ar_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_size = nodeIn_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_source = nodeIn_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[IdIndexer.scala:63:9] assign nodeIn_aw_ready = nodeOut_aw_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[IdIndexer.scala:63:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_size = nodeOut_b_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_source = nodeOut_b_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_ar_ready = nodeOut_ar_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[IdIndexer.scala:63:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_size = nodeOut_r_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_source = nodeOut_r_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] assign auto_in_aw_ready = auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_w_ready = auto_in_w_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id = auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp = auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size = auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source = auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready = auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_r_valid = auto_in_r_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id = auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data = auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp = auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size = auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source = auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last = auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_valid = auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id = auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr = auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len = auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size = auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst = auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock = auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache = auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot = auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos = auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size = auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source = auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_w_valid = auto_out_w_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data = auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb = auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last = auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_valid = auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id = auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr = auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len = auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size = auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst = auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock = auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache = auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot = auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos = auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size = auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source = auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_r_ready = auto_out_r_ready_0; // @[IdIndexer.scala:63:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<9>(0h100))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<9>(0h100))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<9>(0h100))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<9>(0h100))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<9>(0h100))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<9>(0h100))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<9>(0h100))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<9>(0h100))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<9>(0h100))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<9>(0h100))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_115 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_116 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TageTable_2 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<8>(0hff)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history = bits(io.f1_req_ghist, 7, 0) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 7, 0) node tag_history = bits(io.f1_req_ghist, 7, 0) node _tag_T = shr(_T_1, 8) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 7, 0) smem tage_u_8 : UInt<1>[8] [256] smem tage_table_8 : UInt<12>[4] [256] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] wire s2_req_rus : UInt<1>[8] node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 connect io.f2_resp[0].valid, s2_req_rhits[0] node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0]) connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr connect io.f2_resp[1].valid, s2_req_rhits[1] node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2]) connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr connect io.f2_resp[2].valid, s2_req_rhits[2] node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4]) connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr connect io.f2_resp[3].valid, s2_req_rhits[3] node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6]) connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _clear_u_hi_T = bits(clear_u_ctr, 19, 19) node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1)) node _clear_u_lo_T = bits(clear_u_ctr, 19, 19) node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0)) node clear_u_idx = shr(clear_u_ctr, 11) wire _clear_u_mask_WIRE : UInt<1>[8] connect _clear_u_mask_WIRE[0], clear_u_lo connect _clear_u_mask_WIRE[1], clear_u_hi connect _clear_u_mask_WIRE[2], clear_u_lo connect _clear_u_mask_WIRE[3], clear_u_hi connect _clear_u_mask_WIRE[4], clear_u_lo connect _clear_u_mask_WIRE[5], clear_u_hi connect _clear_u_mask_WIRE[6], clear_u_lo connect _clear_u_mask_WIRE[7], clear_u_hi node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0]) node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2]) node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo) node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4]) node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6]) node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo) node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo) node _T_2 = shr(io.update_pc, 4) node idx_history_1 = bits(io.update_hist, 7, 0) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 7, 0) node tag_history_1 = bits(io.update_hist, 7, 0) node _tag_T_2 = shr(_T_2, 8) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 7, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] node _wen_T = or(io.update_mask[0], io.update_mask[1]) node _wen_T_1 = or(_wen_T, io.update_mask[2]) node _wen_T_2 = or(_wen_T_1, io.update_mask[3]) node _wen_T_3 = or(doing_reset, _wen_T_2) wire wen : UInt<1> connect wen, _wen_T_3 wire _rdata_WIRE : UInt<8> invalidate _rdata_WIRE when io.f1_req_valid : connect _rdata_WIRE, s1_hashed_idx read mport rdata = tage_table_8[_rdata_WIRE], clock reg REG : UInt<1>, clock connect REG, wen node _T_3 = and(REG, UInt<1>(0h0)) when _T_3 : wire _WIRE : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] connect _WIRE[0].ctr, UInt<3>(0h0) connect _WIRE[0].tag, UInt<8>(0h0) connect _WIRE[0].valid, UInt<1>(0h0) connect _WIRE[1].ctr, UInt<3>(0h0) connect _WIRE[1].tag, UInt<8>(0h0) connect _WIRE[1].valid, UInt<1>(0h0) connect _WIRE[2].ctr, UInt<3>(0h0) connect _WIRE[2].tag, UInt<8>(0h0) connect _WIRE[2].valid, UInt<1>(0h0) connect _WIRE[3].ctr, UInt<3>(0h0) connect _WIRE[3].tag, UInt<8>(0h0) connect _WIRE[3].valid, UInt<1>(0h0) connect s2_req_rtage, _WIRE else : wire _WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_2 : UInt<12> connect _WIRE_2, rdata[0] node _T_4 = bits(_WIRE_2, 2, 0) connect _WIRE_1.ctr, _T_4 node _T_5 = bits(_WIRE_2, 10, 3) connect _WIRE_1.tag, _T_5 node _T_6 = bits(_WIRE_2, 11, 11) connect _WIRE_1.valid, _T_6 wire _WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_4 : UInt<12> connect _WIRE_4, rdata[1] node _T_7 = bits(_WIRE_4, 2, 0) connect _WIRE_3.ctr, _T_7 node _T_8 = bits(_WIRE_4, 10, 3) connect _WIRE_3.tag, _T_8 node _T_9 = bits(_WIRE_4, 11, 11) connect _WIRE_3.valid, _T_9 wire _WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_6 : UInt<12> connect _WIRE_6, rdata[2] node _T_10 = bits(_WIRE_6, 2, 0) connect _WIRE_5.ctr, _T_10 node _T_11 = bits(_WIRE_6, 10, 3) connect _WIRE_5.tag, _T_11 node _T_12 = bits(_WIRE_6, 11, 11) connect _WIRE_5.valid, _T_12 wire _WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_8 : UInt<12> connect _WIRE_8, rdata[3] node _T_13 = bits(_WIRE_8, 2, 0) connect _WIRE_7.ctr, _T_13 node _T_14 = bits(_WIRE_8, 10, 3) connect _WIRE_7.tag, _T_14 node _T_15 = bits(_WIRE_8, 11, 11) connect _WIRE_7.valid, _T_15 wire _WIRE_9 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] connect _WIRE_9[0].ctr, _WIRE_1.ctr connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].valid, _WIRE_1.valid connect _WIRE_9[1].ctr, _WIRE_3.ctr connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].valid, _WIRE_3.valid connect _WIRE_9[2].ctr, _WIRE_5.ctr connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].valid, _WIRE_5.valid connect _WIRE_9[3].ctr, _WIRE_7.ctr connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].valid, _WIRE_7.valid connect s2_req_rtage, _WIRE_9 when wen : node widx = mux(doing_reset, reset_idx, update_idx) wire _wdata_WIRE : UInt<12>[4] connect _wdata_WIRE[0], UInt<12>(0h0) connect _wdata_WIRE[1], UInt<12>(0h0) connect _wdata_WIRE[2], UInt<12>(0h0) connect _wdata_WIRE[3], UInt<12>(0h0) node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _wdata_T = cat(wdata_hi, update_wdata[0].ctr) node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr) node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr) node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr) wire _wdata_WIRE_1 : UInt<12>[4] connect _wdata_WIRE_1[0], _wdata_T connect _wdata_WIRE_1[1], _wdata_T_1 connect _wdata_WIRE_1[2], _wdata_T_2 connect _wdata_WIRE_1[3], _wdata_T_3 node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1) node _wmask_T = not(UInt<4>(0h0)) node wmask_lo = cat(io.update_mask[1], io.update_mask[0]) node wmask_hi = cat(io.update_mask[3], io.update_mask[2]) node _wmask_T_1 = cat(wmask_hi, wmask_lo) node wmask = mux(doing_reset, _wmask_T, _wmask_T_1) node _T_16 = bits(wmask, 0, 0) node _T_17 = bits(wmask, 1, 1) node _T_18 = bits(wmask, 2, 2) node _T_19 = bits(wmask, 3, 3) write mport MPORT = tage_table_8[widx], clock when _T_16 : connect MPORT[0], wdata[0] when _T_17 : connect MPORT[1], wdata[1] when _T_18 : connect MPORT[2], wdata[2] when _T_19 : connect MPORT[3], wdata[3] wire update_u_mask : UInt<1>[8] connect update_u_mask[0], io.update_u_mask[0] connect update_u_mask[1], io.update_u_mask[0] connect update_u_mask[2], io.update_u_mask[1] connect update_u_mask[3], io.update_u_mask[1] connect update_u_mask[4], io.update_u_mask[2] connect update_u_mask[5], io.update_u_mask[2] connect update_u_mask[6], io.update_u_mask[3] connect update_u_mask[7], io.update_u_mask[3] node _update_u_wen_T = or(doing_reset, doing_clear_u) node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1]) node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2]) node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3]) node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4]) node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5]) node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6]) node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7]) node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7) wire update_u_wen : UInt<1> connect update_u_wen, _update_u_wen_T_8 wire _u_rdata_WIRE : UInt<8> invalidate _u_rdata_WIRE when io.f1_req_valid : connect _u_rdata_WIRE, s1_hashed_idx read mport u_rdata = tage_u_8[_u_rdata_WIRE], clock connect s2_req_rus, u_rdata when update_u_wen : node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx) node widx_1 = mux(doing_reset, reset_idx, _widx_T) node _wdata_T_4 = or(doing_reset, doing_clear_u) wire _wdata_WIRE_2 : UInt<1>[8] connect _wdata_WIRE_2[0], UInt<1>(0h0) connect _wdata_WIRE_2[1], UInt<1>(0h0) connect _wdata_WIRE_2[2], UInt<1>(0h0) connect _wdata_WIRE_2[3], UInt<1>(0h0) connect _wdata_WIRE_2[4], UInt<1>(0h0) connect _wdata_WIRE_2[5], UInt<1>(0h0) connect _wdata_WIRE_2[6], UInt<1>(0h0) connect _wdata_WIRE_2[7], UInt<1>(0h0) node wdata_lo = cat(io.update_u[1], io.update_u[0]) node wdata_hi_4 = cat(io.update_u[3], io.update_u[2]) node _wdata_T_5 = cat(wdata_hi_4, wdata_lo) node _wdata_T_6 = bits(_wdata_T_5, 0, 0) node _wdata_T_7 = bits(_wdata_T_5, 1, 1) node _wdata_T_8 = bits(_wdata_T_5, 2, 2) node _wdata_T_9 = bits(_wdata_T_5, 3, 3) node _wdata_T_10 = bits(_wdata_T_5, 4, 4) node _wdata_T_11 = bits(_wdata_T_5, 5, 5) node _wdata_T_12 = bits(_wdata_T_5, 6, 6) node _wdata_T_13 = bits(_wdata_T_5, 7, 7) wire _wdata_WIRE_3 : UInt<1>[8] connect _wdata_WIRE_3[0], _wdata_T_6 connect _wdata_WIRE_3[1], _wdata_T_7 connect _wdata_WIRE_3[2], _wdata_T_8 connect _wdata_WIRE_3[3], _wdata_T_9 connect _wdata_WIRE_3[4], _wdata_T_10 connect _wdata_WIRE_3[5], _wdata_T_11 connect _wdata_WIRE_3[6], _wdata_T_12 connect _wdata_WIRE_3[7], _wdata_T_13 node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3) node _wmask_T_2 = not(UInt<8>(0h0)) node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0]) node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2]) node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo) node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4]) node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6]) node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo) node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1) node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3) node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4) node _T_20 = bits(wmask_1, 0, 0) node _T_21 = bits(wmask_1, 1, 1) node _T_22 = bits(wmask_1, 2, 2) node _T_23 = bits(wmask_1, 3, 3) node _T_24 = bits(wmask_1, 4, 4) node _T_25 = bits(wmask_1, 5, 5) node _T_26 = bits(wmask_1, 6, 6) node _T_27 = bits(wmask_1, 7, 7) node _T_28 = bits(widx_1, 7, 0) write mport MPORT_1 = tage_u_8[_T_28], clock when _T_20 : connect MPORT_1[0], wdata_1[0] when _T_21 : connect MPORT_1[1], wdata_1[1] when _T_22 : connect MPORT_1[2], wdata_1[2] when _T_23 : connect MPORT_1[3], wdata_1[3] when _T_24 : connect MPORT_1[4], wdata_1[4] when _T_25 : connect MPORT_1[5], wdata_1[5] when _T_26 : connect MPORT_1[6], wdata_1[6] when _T_27 : connect MPORT_1[7], wdata_1[7] reg wrbypass_tags : UInt<8>[2], clock reg wrbypass_idxs : UInt<8>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _T_29 = or(io.update_mask[0], io.update_mask[1]) node _T_30 = or(_T_29, io.update_mask[2]) node _T_31 = or(_T_30, io.update_mask[3]) when _T_31 : node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_32 : wire _WIRE_10 : UInt<3>[4] connect _WIRE_10[0], update_wdata[0].ctr connect _WIRE_10[1], update_wdata[1].ctr connect _WIRE_10[2], update_wdata[2].ctr connect _WIRE_10[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_10 else : wire _WIRE_11 : UInt<3>[4] connect _WIRE_11[0], update_wdata[0].ctr connect _WIRE_11[1], update_wdata[1].ctr connect _WIRE_11[2], update_wdata[2].ctr connect _WIRE_11[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_11 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2	module TageTable_2( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [47:0] _tage_table_8_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_8_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [11:0] _wdata_WIRE_0 = 12'h0; // @[tage.scala:130:41] wire [11:0] _wdata_WIRE_1 = 12'h0; // @[tage.scala:130:41] wire [11:0] _wdata_WIRE_2 = 12'h0; // @[tage.scala:130:41] wire [11:0] _wdata_WIRE_3 = 12'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [7:0] reset_idx; // @[tage.scala:73:26] wire [8:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [8:0] _reset_idx_T = _GEN + {8'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26] wire [7:0] idx_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:149:35] wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}] wire [7:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [7:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_8_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_8_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_8_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_8_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_8_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_8_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_8_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_8_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [11:0] wdata_0; // @[tage.scala:130:20] wire [11:0] wdata_1; // @[tage.scala:130:20] wire [11:0] wdata_2; // @[tage.scala:130:20] wire [11:0] wdata_3; // @[tage.scala:130:20] reg [7:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [19:0] clear_u_ctr; // @[tage.scala:109:28] wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85] wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [7:0] idx_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}] wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}] wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 \| io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T \| io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset \| _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_8_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_8_R0_data[10:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_8_R0_data[11]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_8_R0_data[14:12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_8_R0_data[22:15]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_8_R0_data[23]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_8_R0_data[26:24]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_8_R0_data[34:27]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_8_R0_data[35]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_8_R0_data[38:36]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_8_R0_data[46:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_8_R0_data[47]; // @[tage.scala:90:27, :98:26, :126:49] wire [7:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [8:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [8:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [8:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [8:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 12'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 12'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 12'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 12'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset \| doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 \| update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 \| update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 \| update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 \| update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 \| update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 \| update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 \| update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T \| _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [8:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [8:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [7:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [7:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [7:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [7:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 8'h0; // @[tage.scala:73:26] clear_u_ctr <= 20'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 \| wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 \| _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_8 tage_u_8 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_8_R0_data), .W0_addr (widx_1[7:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_8 tage_table_8 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_8_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheControl : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip flush_match : UInt<1>, flush_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip flush_resp : UInt<1>} wire ctrlnodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlnodeIn.d.bits.corrupt invalidate ctrlnodeIn.d.bits.data invalidate ctrlnodeIn.d.bits.denied invalidate ctrlnodeIn.d.bits.sink invalidate ctrlnodeIn.d.bits.source invalidate ctrlnodeIn.d.bits.size invalidate ctrlnodeIn.d.bits.param invalidate ctrlnodeIn.d.bits.opcode invalidate ctrlnodeIn.d.valid invalidate ctrlnodeIn.d.ready invalidate ctrlnodeIn.a.bits.corrupt invalidate ctrlnodeIn.a.bits.data invalidate ctrlnodeIn.a.bits.mask invalidate ctrlnodeIn.a.bits.address invalidate ctrlnodeIn.a.bits.source invalidate ctrlnodeIn.a.bits.size invalidate ctrlnodeIn.a.bits.param invalidate ctrlnodeIn.a.bits.opcode invalidate ctrlnodeIn.a.valid invalidate ctrlnodeIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlnodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlnodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlnodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlnodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlnodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlnodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlnodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlnodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlnodeIn.d.valid connect monitor.io.in.d.ready, ctrlnodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlnodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlnodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlnodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlnodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlnodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlnodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlnodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlnodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlnodeIn.a.valid connect monitor.io.in.a.ready, ctrlnodeIn.a.ready connect ctrlnodeIn, auto.ctrl_in regreset flushInValid : UInt<1>, clock, reset, UInt<1>(0h0) reg flushInAddress : UInt<64>, clock regreset flushOutValid : UInt<1>, clock, reset, UInt<1>(0h0) wire flushOutReady : UInt<1> connect flushOutReady, UInt<1>(0h0) when flushOutReady : connect flushOutValid, UInt<1>(0h0) when io.flush_resp : connect flushOutValid, UInt<1>(0h1) when io.flush_req.ready : connect flushInValid, UInt<1>(0h0) connect io.flush_req.valid, flushInValid connect io.flush_req.bits, flushInAddress node _T = eq(io.flush_match, UInt<1>(0h0)) node _T_1 = and(_T, flushInValid) when _T_1 : connect flushInValid, UInt<1>(0h0) connect flushOutValid, UInt<1>(0h1) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(ctrlnodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlnodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlnodeIn.a.bits.data connect in.bits.mask, ctrlnodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlnodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlnodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h48)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[6] wire out_wivalid : UInt<1>[6] wire out_roready : UInt<1>[6] wire out_woready : UInt<1>[6] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = eq(out_rimask, UInt<1>(0h0)) node _out_T_10 = eq(out_wimask, UInt<1>(0h0)) node _out_T_11 = eq(out_romask, UInt<1>(0h0)) node _out_T_12 = eq(out_womask, UInt<1>(0h0)) node _out_T_13 = or(UInt<1>(0h1), UInt<8>(0h0)) node _out_T_14 = bits(_out_T_13, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_15 = bits(out_back_front_q.io.deq.bits.data, 15, 8) node _out_T_16 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_17 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_18 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_20 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_14, UInt<8>(0h0)) node out_prepend = cat(UInt<4>(0h8), _out_prepend_T) node _out_T_22 = or(out_prepend, UInt<16>(0h0)) node _out_T_23 = bits(_out_T_22, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_24 = bits(out_back_front_q.io.deq.bits.data, 23, 16) node _out_T_25 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_26 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_27 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_28 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_29 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_23, UInt<16>(0h0)) node out_prepend_1 = cat(UInt<4>(0ha), _out_prepend_T_1) node _out_T_31 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_32 = bits(_out_T_31, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_33 = bits(out_back_front_q.io.deq.bits.data, 31, 24) node _out_T_34 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_35 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_36 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_37 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_38 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_32, UInt<24>(0h0)) node out_prepend_2 = cat(UInt<3>(0h6), _out_prepend_T_2) node _out_T_40 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_41 = bits(_out_T_40, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 63, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 63, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 63, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 63, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_42 = bits(out_front.bits.data, 63, 0) when out_f_woready_4 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_4 : connect flushInValid, UInt<1>(0h1) node _out_T_43 = eq(flushInValid, UInt<1>(0h0)) node _out_T_44 = and(out_f_wivalid_4, _out_T_43) when _out_T_44 : connect flushInAddress, _out_T_42 node out_f_wiready = eq(flushInValid, UInt<1>(0h0)) node _out_T_45 = and(out_f_wivalid_4, out_f_wiready) node _out_T_46 = and(flushOutValid, out_f_woready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = or(out_f_wiready, _out_T_48) node _out_T_50 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_51 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_52 = or(flushOutValid, _out_T_51) node _out_T_53 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_54 = bits(_out_T_53, 63, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_55 = bits(out_front.bits.data, 31, 0) when out_f_woready_5 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_5 : connect flushInValid, UInt<1>(0h1) node _out_T_56 = eq(flushInValid, UInt<1>(0h0)) node _out_T_57 = and(out_f_wivalid_5, _out_T_56) when _out_T_57 : node _out_flushInAddress_T = shl(_out_T_55, 4) connect flushInAddress, _out_flushInAddress_T node out_f_wiready_1 = eq(flushInValid, UInt<1>(0h0)) node _out_T_58 = and(out_f_wivalid_5, out_f_wiready_1) node _out_T_59 = and(flushOutValid, out_f_woready_5) node _out_T_60 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_61 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_62 = or(out_f_wiready_1, _out_T_61) node _out_T_63 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_64 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_65 = or(flushOutValid, _out_T_64) node _out_T_66 = or(UInt<1>(0h0), UInt<32>(0h0)) node _out_T_67 = bits(_out_T_66, 31, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_6, _out_iindex_T_3) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_6, _out_oindex_T_3) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) connect out_rifireMux_out_1, UInt<1>(0h1) node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_4) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) connect out_wifireMux_out_1, UInt<1>(0h1) node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) node out_wifireMux_all = and(_out_wifireMux_T_12, _out_T_49) connect out_wifireMux_out_2, _out_T_49 connect out_wivalid[4], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_4) node out_wifireMux_all_1 = and(_out_wifireMux_T_16, _out_T_62) connect out_wifireMux_out_3, _out_T_62 connect out_wivalid[5], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) connect out_rofireMux_out_1, UInt<1>(0h1) node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[4], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_5) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) connect out_wofireMux_out_1, UInt<1>(0h1) node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) node out_wofireMux_all = and(_out_wofireMux_T_12, _out_T_52) connect out_wofireMux_out_2, _out_T_52 connect out_woready[4], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_5) node out_wofireMux_all_1 = and(_out_wofireMux_T_16, _out_T_65) connect out_wofireMux_out_3, _out_T_65 connect out_woready[5], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], UInt<1>(0h1) connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], _out_T_5 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_41 connect _out_out_bits_data_WIRE_1[1], UInt<1>(0h0) connect _out_out_bits_data_WIRE_1[2], _out_T_54 connect _out_out_bits_data_WIRE_1[3], _out_T_67 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlnodeIn.a.valid connect ctrlnodeIn.a.ready, in.ready connect ctrlnodeIn.d.valid, out.valid connect out.ready, ctrlnodeIn.d.ready wire ctrlnodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlnodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlnodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlnodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlnodeIn_d_bits_d.data connect ctrlnodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlnodeIn.d.bits.corrupt, ctrlnodeIn_d_bits_d.corrupt connect ctrlnodeIn.d.bits.data, ctrlnodeIn_d_bits_d.data connect ctrlnodeIn.d.bits.denied, ctrlnodeIn_d_bits_d.denied connect ctrlnodeIn.d.bits.sink, ctrlnodeIn_d_bits_d.sink connect ctrlnodeIn.d.bits.source, ctrlnodeIn_d_bits_d.source connect ctrlnodeIn.d.bits.size, ctrlnodeIn_d_bits_d.size connect ctrlnodeIn.d.bits.param, ctrlnodeIn_d_bits_d.param connect ctrlnodeIn.d.bits.opcode, ctrlnodeIn_d_bits_d.opcode connect ctrlnodeIn.d.bits.data, out.bits.data node _ctrlnodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlnodeIn.d.bits.opcode, _ctrlnodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_78 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_79 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [11:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [11:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [11:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [11:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready \| _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid \| _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 \| out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 \| _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid \| _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 \| _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 \| _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 \| _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 \| _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read \| out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read \| out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 \| out_f_wivalid_4 \| ~(_T_1 \| io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 \| io_flush_resp_0 \| ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i32_14 : input clock : Clock input reset : Reset output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 8, 8) node posExp = bits(rawIn.sExp, 7, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 22, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 22) node _alignedSig_T_1 = bits(shiftedSig, 21, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f)) node _roundCarryBut2_T = bits(unroundedInt, 29, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<6>(0h20)) node _common_overflow_T_1 = bits(unroundedInt, 30, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 30, 30) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1	module RecFNToIN_e8_s24_i32_14( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [32:0] io_in, // @[RecFNToIN.scala:49:16] output [31:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53] wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53] wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53] wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53] wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53] wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35] wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28] wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49] wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27] wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31] wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13] wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27] wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41] wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7] wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7] wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [31:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [54:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [32:0] _alignedSig_T = shiftedSig[54:22]; // @[RecFNToIN.scala:83:49, :89:20] wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = \|_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = \|_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 \| _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = \|_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 \| _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 \| magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}] wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31] wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire [31:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11] wire magGeOne_atOverflowEdge = posExp == 8'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = \|(posExp[7:5]); // @[RecFNToIN.scala:62:28, :116:21] wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = \|_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 \| roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 8'h1E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge \| _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24] wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign \| _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_14 = _common_overflow_T \| _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36] wire invalidExc = rawIn_isNaN \| rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27] wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] \| _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc \| common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_23 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_23( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_21 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_21( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_3 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x	module PMPChecker_s3_3( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T \| _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T \| _res_hit_T_5; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess \| _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 \| _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = \|_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 \| res_aligned_lsbMask; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = \|_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound \| res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 \| _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 \| _res_hit_T_18; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 \| _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 \| _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = \|_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 \| res_aligned_lsbMask_1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = \|_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 \| res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 \| _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 \| _res_hit_T_31; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 \| _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 \| _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = \|_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 \| res_aligned_lsbMask_2; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = \|_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 \| res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 \| _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 \| _res_hit_T_44; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 \| _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 \| _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = \|_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 \| res_aligned_lsbMask_3; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = \|_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 \| res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 \| _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 \| _res_hit_T_57; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 \| _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 \| _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = \|_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 \| res_aligned_lsbMask_4; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = \|_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 \| res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 \| _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 \| _res_hit_T_70; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 \| _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 \| _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = \|_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 \| res_aligned_lsbMask_5; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = \|_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 \| res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 \| _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 \| _res_hit_T_83; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 \| _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 \| _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = \|_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 \| res_aligned_lsbMask_6; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = \|_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 \| res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 \| _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 \| _res_hit_T_96; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 \| _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 \| res_aligned_lsbMask_7; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = \|_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TSIToTileLink : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, state : UInt} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut reg cmd : UInt<32>, clock reg addr : UInt<64>, clock reg len : UInt<64>, clock reg body : UInt<32>[2], clock reg bodyValid : UInt<2>, clock reg idx : UInt<1>, clock regreset state : UInt<4>, clock, reset, UInt<4>(0h0) connect io.state, state node _io_tsi_in_ready_T = eq(state, UInt<4>(0h0)) node _io_tsi_in_ready_T_1 = eq(state, UInt<4>(0h1)) node _io_tsi_in_ready_T_2 = eq(state, UInt<4>(0h2)) node _io_tsi_in_ready_T_3 = eq(state, UInt<4>(0h6)) node _io_tsi_in_ready_T_4 = or(_io_tsi_in_ready_T, _io_tsi_in_ready_T_1) node _io_tsi_in_ready_T_5 = or(_io_tsi_in_ready_T_4, _io_tsi_in_ready_T_2) node _io_tsi_in_ready_T_6 = or(_io_tsi_in_ready_T_5, _io_tsi_in_ready_T_3) connect io.tsi.in.ready, _io_tsi_in_ready_T_6 node _io_tsi_out_valid_T = eq(state, UInt<4>(0h5)) connect io.tsi.out.valid, _io_tsi_out_valid_T connect io.tsi.out.bits, body[idx] node beatAddr = bits(addr, 31, 3) node _nextAddr_T = add(beatAddr, UInt<1>(0h1)) node _nextAddr_T_1 = tail(_nextAddr_T, 1) node nextAddr = cat(_nextAddr_T_1, UInt<3>(0h0)) node _wmask_T = bits(bodyValid, 0, 0) node _wmask_T_1 = bits(bodyValid, 1, 1) node _wmask_T_2 = mux(_wmask_T, UInt<4>(0hf), UInt<4>(0h0)) node _wmask_T_3 = mux(_wmask_T_1, UInt<4>(0hf), UInt<4>(0h0)) node wmask = cat(_wmask_T_3, _wmask_T_2) node _addr_size_T = sub(nextAddr, addr) node addr_size = tail(_addr_size_T, 1) node _len_size_T = add(len, UInt<1>(0h1)) node _len_size_T_1 = tail(_len_size_T, 1) node len_size = cat(_len_size_T_1, UInt<2>(0h0)) node _raw_size_T = lt(len_size, addr_size) node raw_size = mux(_raw_size_T, len_size, addr_size) node _rsize_T = eq(UInt<1>(0h1), raw_size) node _rsize_T_1 = mux(_rsize_T, UInt<1>(0h0), UInt<2>(0h3)) node _rsize_T_2 = eq(UInt<2>(0h2), raw_size) node _rsize_T_3 = mux(_rsize_T_2, UInt<1>(0h1), _rsize_T_1) node _rsize_T_4 = eq(UInt<3>(0h4), raw_size) node rsize = mux(_rsize_T_4, UInt<2>(0h2), _rsize_T_3) node _pow2size_T = bits(raw_size, 0, 0) node _pow2size_T_1 = bits(raw_size, 1, 1) node _pow2size_T_2 = bits(raw_size, 2, 2) node _pow2size_T_3 = bits(raw_size, 3, 3) node _pow2size_T_4 = bits(raw_size, 4, 4) node _pow2size_T_5 = bits(raw_size, 5, 5) node _pow2size_T_6 = bits(raw_size, 6, 6) node _pow2size_T_7 = bits(raw_size, 7, 7) node _pow2size_T_8 = bits(raw_size, 8, 8) node _pow2size_T_9 = bits(raw_size, 9, 9) node _pow2size_T_10 = bits(raw_size, 10, 10) node _pow2size_T_11 = bits(raw_size, 11, 11) node _pow2size_T_12 = bits(raw_size, 12, 12) node _pow2size_T_13 = bits(raw_size, 13, 13) node _pow2size_T_14 = bits(raw_size, 14, 14) node _pow2size_T_15 = bits(raw_size, 15, 15) node _pow2size_T_16 = bits(raw_size, 16, 16) node _pow2size_T_17 = bits(raw_size, 17, 17) node _pow2size_T_18 = bits(raw_size, 18, 18) node _pow2size_T_19 = bits(raw_size, 19, 19) node _pow2size_T_20 = bits(raw_size, 20, 20) node _pow2size_T_21 = bits(raw_size, 21, 21) node _pow2size_T_22 = bits(raw_size, 22, 22) node _pow2size_T_23 = bits(raw_size, 23, 23) node _pow2size_T_24 = bits(raw_size, 24, 24) node _pow2size_T_25 = bits(raw_size, 25, 25) node _pow2size_T_26 = bits(raw_size, 26, 26) node _pow2size_T_27 = bits(raw_size, 27, 27) node _pow2size_T_28 = bits(raw_size, 28, 28) node _pow2size_T_29 = bits(raw_size, 29, 29) node _pow2size_T_30 = bits(raw_size, 30, 30) node _pow2size_T_31 = bits(raw_size, 31, 31) node _pow2size_T_32 = bits(raw_size, 32, 32) node _pow2size_T_33 = bits(raw_size, 33, 33) node _pow2size_T_34 = bits(raw_size, 34, 34) node _pow2size_T_35 = bits(raw_size, 35, 35) node _pow2size_T_36 = bits(raw_size, 36, 36) node _pow2size_T_37 = bits(raw_size, 37, 37) node _pow2size_T_38 = bits(raw_size, 38, 38) node _pow2size_T_39 = bits(raw_size, 39, 39) node _pow2size_T_40 = bits(raw_size, 40, 40) node _pow2size_T_41 = bits(raw_size, 41, 41) node _pow2size_T_42 = bits(raw_size, 42, 42) node _pow2size_T_43 = bits(raw_size, 43, 43) node _pow2size_T_44 = bits(raw_size, 44, 44) node _pow2size_T_45 = bits(raw_size, 45, 45) node _pow2size_T_46 = bits(raw_size, 46, 46) node _pow2size_T_47 = bits(raw_size, 47, 47) node _pow2size_T_48 = bits(raw_size, 48, 48) node _pow2size_T_49 = bits(raw_size, 49, 49) node _pow2size_T_50 = bits(raw_size, 50, 50) node _pow2size_T_51 = bits(raw_size, 51, 51) node _pow2size_T_52 = bits(raw_size, 52, 52) node _pow2size_T_53 = bits(raw_size, 53, 53) node _pow2size_T_54 = bits(raw_size, 54, 54) node _pow2size_T_55 = bits(raw_size, 55, 55) node _pow2size_T_56 = bits(raw_size, 56, 56) node _pow2size_T_57 = bits(raw_size, 57, 57) node _pow2size_T_58 = bits(raw_size, 58, 58) node _pow2size_T_59 = bits(raw_size, 59, 59) node _pow2size_T_60 = bits(raw_size, 60, 60) node _pow2size_T_61 = bits(raw_size, 61, 61) node _pow2size_T_62 = bits(raw_size, 62, 62) node _pow2size_T_63 = bits(raw_size, 63, 63) node _pow2size_T_64 = bits(raw_size, 64, 64) node _pow2size_T_65 = bits(raw_size, 65, 65) node _pow2size_T_66 = add(_pow2size_T, _pow2size_T_1) node _pow2size_T_67 = bits(_pow2size_T_66, 1, 0) node _pow2size_T_68 = add(_pow2size_T_2, _pow2size_T_3) node _pow2size_T_69 = bits(_pow2size_T_68, 1, 0) node _pow2size_T_70 = add(_pow2size_T_67, _pow2size_T_69) node _pow2size_T_71 = bits(_pow2size_T_70, 2, 0) node _pow2size_T_72 = add(_pow2size_T_4, _pow2size_T_5) node _pow2size_T_73 = bits(_pow2size_T_72, 1, 0) node _pow2size_T_74 = add(_pow2size_T_6, _pow2size_T_7) node _pow2size_T_75 = bits(_pow2size_T_74, 1, 0) node _pow2size_T_76 = add(_pow2size_T_73, _pow2size_T_75) node _pow2size_T_77 = bits(_pow2size_T_76, 2, 0) node _pow2size_T_78 = add(_pow2size_T_71, _pow2size_T_77) node _pow2size_T_79 = bits(_pow2size_T_78, 3, 0) node _pow2size_T_80 = add(_pow2size_T_8, _pow2size_T_9) node _pow2size_T_81 = bits(_pow2size_T_80, 1, 0) node _pow2size_T_82 = add(_pow2size_T_10, _pow2size_T_11) node _pow2size_T_83 = bits(_pow2size_T_82, 1, 0) node _pow2size_T_84 = add(_pow2size_T_81, _pow2size_T_83) node _pow2size_T_85 = bits(_pow2size_T_84, 2, 0) node _pow2size_T_86 = add(_pow2size_T_12, _pow2size_T_13) node _pow2size_T_87 = bits(_pow2size_T_86, 1, 0) node _pow2size_T_88 = add(_pow2size_T_14, _pow2size_T_15) node _pow2size_T_89 = bits(_pow2size_T_88, 1, 0) node _pow2size_T_90 = add(_pow2size_T_87, _pow2size_T_89) node _pow2size_T_91 = bits(_pow2size_T_90, 2, 0) node _pow2size_T_92 = add(_pow2size_T_85, _pow2size_T_91) node _pow2size_T_93 = bits(_pow2size_T_92, 3, 0) node _pow2size_T_94 = add(_pow2size_T_79, _pow2size_T_93) node _pow2size_T_95 = bits(_pow2size_T_94, 4, 0) node _pow2size_T_96 = add(_pow2size_T_16, _pow2size_T_17) node _pow2size_T_97 = bits(_pow2size_T_96, 1, 0) node _pow2size_T_98 = add(_pow2size_T_18, _pow2size_T_19) node _pow2size_T_99 = bits(_pow2size_T_98, 1, 0) node _pow2size_T_100 = add(_pow2size_T_97, _pow2size_T_99) node _pow2size_T_101 = bits(_pow2size_T_100, 2, 0) node _pow2size_T_102 = add(_pow2size_T_20, _pow2size_T_21) node _pow2size_T_103 = bits(_pow2size_T_102, 1, 0) node _pow2size_T_104 = add(_pow2size_T_22, _pow2size_T_23) node _pow2size_T_105 = bits(_pow2size_T_104, 1, 0) node _pow2size_T_106 = add(_pow2size_T_103, _pow2size_T_105) node _pow2size_T_107 = bits(_pow2size_T_106, 2, 0) node _pow2size_T_108 = add(_pow2size_T_101, _pow2size_T_107) node _pow2size_T_109 = bits(_pow2size_T_108, 3, 0) node _pow2size_T_110 = add(_pow2size_T_24, _pow2size_T_25) node _pow2size_T_111 = bits(_pow2size_T_110, 1, 0) node _pow2size_T_112 = add(_pow2size_T_26, _pow2size_T_27) node _pow2size_T_113 = bits(_pow2size_T_112, 1, 0) node _pow2size_T_114 = add(_pow2size_T_111, _pow2size_T_113) node _pow2size_T_115 = bits(_pow2size_T_114, 2, 0) node _pow2size_T_116 = add(_pow2size_T_28, _pow2size_T_29) node _pow2size_T_117 = bits(_pow2size_T_116, 1, 0) node _pow2size_T_118 = add(_pow2size_T_31, _pow2size_T_32) node _pow2size_T_119 = bits(_pow2size_T_118, 1, 0) node _pow2size_T_120 = add(_pow2size_T_30, _pow2size_T_119) node _pow2size_T_121 = bits(_pow2size_T_120, 1, 0) node _pow2size_T_122 = add(_pow2size_T_117, _pow2size_T_121) node _pow2size_T_123 = bits(_pow2size_T_122, 2, 0) node _pow2size_T_124 = add(_pow2size_T_115, _pow2size_T_123) node _pow2size_T_125 = bits(_pow2size_T_124, 3, 0) node _pow2size_T_126 = add(_pow2size_T_109, _pow2size_T_125) node _pow2size_T_127 = bits(_pow2size_T_126, 4, 0) node _pow2size_T_128 = add(_pow2size_T_95, _pow2size_T_127) node _pow2size_T_129 = bits(_pow2size_T_128, 5, 0) node _pow2size_T_130 = add(_pow2size_T_33, _pow2size_T_34) node _pow2size_T_131 = bits(_pow2size_T_130, 1, 0) node _pow2size_T_132 = add(_pow2size_T_35, _pow2size_T_36) node _pow2size_T_133 = bits(_pow2size_T_132, 1, 0) node _pow2size_T_134 = add(_pow2size_T_131, _pow2size_T_133) node _pow2size_T_135 = bits(_pow2size_T_134, 2, 0) node _pow2size_T_136 = add(_pow2size_T_37, _pow2size_T_38) node _pow2size_T_137 = bits(_pow2size_T_136, 1, 0) node _pow2size_T_138 = add(_pow2size_T_39, _pow2size_T_40) node _pow2size_T_139 = bits(_pow2size_T_138, 1, 0) node _pow2size_T_140 = add(_pow2size_T_137, _pow2size_T_139) node _pow2size_T_141 = bits(_pow2size_T_140, 2, 0) node _pow2size_T_142 = add(_pow2size_T_135, _pow2size_T_141) node _pow2size_T_143 = bits(_pow2size_T_142, 3, 0) node _pow2size_T_144 = add(_pow2size_T_41, _pow2size_T_42) node _pow2size_T_145 = bits(_pow2size_T_144, 1, 0) node _pow2size_T_146 = add(_pow2size_T_43, _pow2size_T_44) node _pow2size_T_147 = bits(_pow2size_T_146, 1, 0) node _pow2size_T_148 = add(_pow2size_T_145, _pow2size_T_147) node _pow2size_T_149 = bits(_pow2size_T_148, 2, 0) node _pow2size_T_150 = add(_pow2size_T_45, _pow2size_T_46) node _pow2size_T_151 = bits(_pow2size_T_150, 1, 0) node _pow2size_T_152 = add(_pow2size_T_47, _pow2size_T_48) node _pow2size_T_153 = bits(_pow2size_T_152, 1, 0) node _pow2size_T_154 = add(_pow2size_T_151, _pow2size_T_153) node _pow2size_T_155 = bits(_pow2size_T_154, 2, 0) node _pow2size_T_156 = add(_pow2size_T_149, _pow2size_T_155) node _pow2size_T_157 = bits(_pow2size_T_156, 3, 0) node _pow2size_T_158 = add(_pow2size_T_143, _pow2size_T_157) node _pow2size_T_159 = bits(_pow2size_T_158, 4, 0) node _pow2size_T_160 = add(_pow2size_T_49, _pow2size_T_50) node _pow2size_T_161 = bits(_pow2size_T_160, 1, 0) node _pow2size_T_162 = add(_pow2size_T_51, _pow2size_T_52) node _pow2size_T_163 = bits(_pow2size_T_162, 1, 0) node _pow2size_T_164 = add(_pow2size_T_161, _pow2size_T_163) node _pow2size_T_165 = bits(_pow2size_T_164, 2, 0) node _pow2size_T_166 = add(_pow2size_T_53, _pow2size_T_54) node _pow2size_T_167 = bits(_pow2size_T_166, 1, 0) node _pow2size_T_168 = add(_pow2size_T_55, _pow2size_T_56) node _pow2size_T_169 = bits(_pow2size_T_168, 1, 0) node _pow2size_T_170 = add(_pow2size_T_167, _pow2size_T_169) node _pow2size_T_171 = bits(_pow2size_T_170, 2, 0) node _pow2size_T_172 = add(_pow2size_T_165, _pow2size_T_171) node _pow2size_T_173 = bits(_pow2size_T_172, 3, 0) node _pow2size_T_174 = add(_pow2size_T_57, _pow2size_T_58) node _pow2size_T_175 = bits(_pow2size_T_174, 1, 0) node _pow2size_T_176 = add(_pow2size_T_59, _pow2size_T_60) node _pow2size_T_177 = bits(_pow2size_T_176, 1, 0) node _pow2size_T_178 = add(_pow2size_T_175, _pow2size_T_177) node _pow2size_T_179 = bits(_pow2size_T_178, 2, 0) node _pow2size_T_180 = add(_pow2size_T_61, _pow2size_T_62) node _pow2size_T_181 = bits(_pow2size_T_180, 1, 0) node _pow2size_T_182 = add(_pow2size_T_64, _pow2size_T_65) node _pow2size_T_183 = bits(_pow2size_T_182, 1, 0) node _pow2size_T_184 = add(_pow2size_T_63, _pow2size_T_183) node _pow2size_T_185 = bits(_pow2size_T_184, 1, 0) node _pow2size_T_186 = add(_pow2size_T_181, _pow2size_T_185) node _pow2size_T_187 = bits(_pow2size_T_186, 2, 0) node _pow2size_T_188 = add(_pow2size_T_179, _pow2size_T_187) node _pow2size_T_189 = bits(_pow2size_T_188, 3, 0) node _pow2size_T_190 = add(_pow2size_T_173, _pow2size_T_189) node _pow2size_T_191 = bits(_pow2size_T_190, 4, 0) node _pow2size_T_192 = add(_pow2size_T_159, _pow2size_T_191) node _pow2size_T_193 = bits(_pow2size_T_192, 5, 0) node _pow2size_T_194 = add(_pow2size_T_129, _pow2size_T_193) node _pow2size_T_195 = bits(_pow2size_T_194, 6, 0) node pow2size = eq(_pow2size_T_195, UInt<1>(0h1)) node _byteAddr_T = bits(addr, 2, 0) node byteAddr = mux(pow2size, _byteAddr_T, UInt<1>(0h0)) node _put_acquire_T = dshl(beatAddr, UInt<2>(0h3)) node _put_acquire_T_1 = cat(body[1], body[0]) node _put_acquire_legal_T = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_1 = leq(UInt<2>(0h3), UInt<4>(0hc)) node _put_acquire_legal_T_2 = and(_put_acquire_legal_T, _put_acquire_legal_T_1) node _put_acquire_legal_T_3 = or(UInt<1>(0h0), _put_acquire_legal_T_2) node _put_acquire_legal_T_4 = xor(_put_acquire_T, UInt<14>(0h3000)) node _put_acquire_legal_T_5 = cvt(_put_acquire_legal_T_4) node _put_acquire_legal_T_6 = and(_put_acquire_legal_T_5, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_7 = asSInt(_put_acquire_legal_T_6) node _put_acquire_legal_T_8 = eq(_put_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_9 = and(_put_acquire_legal_T_3, _put_acquire_legal_T_8) node _put_acquire_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_11 = leq(UInt<2>(0h3), UInt<3>(0h6)) node _put_acquire_legal_T_12 = and(_put_acquire_legal_T_10, _put_acquire_legal_T_11) node _put_acquire_legal_T_13 = or(UInt<1>(0h0), _put_acquire_legal_T_12) node _put_acquire_legal_T_14 = xor(_put_acquire_T, UInt<1>(0h0)) node _put_acquire_legal_T_15 = cvt(_put_acquire_legal_T_14) node _put_acquire_legal_T_16 = and(_put_acquire_legal_T_15, asSInt(UInt<33>(0h9a312000))) node _put_acquire_legal_T_17 = asSInt(_put_acquire_legal_T_16) node _put_acquire_legal_T_18 = eq(_put_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_19 = xor(_put_acquire_T, UInt<21>(0h100000)) node _put_acquire_legal_T_20 = cvt(_put_acquire_legal_T_19) node _put_acquire_legal_T_21 = and(_put_acquire_legal_T_20, asSInt(UInt<33>(0h9a303000))) node _put_acquire_legal_T_22 = asSInt(_put_acquire_legal_T_21) node _put_acquire_legal_T_23 = eq(_put_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_24 = xor(_put_acquire_T, UInt<22>(0h200000)) node _put_acquire_legal_T_25 = cvt(_put_acquire_legal_T_24) node _put_acquire_legal_T_26 = and(_put_acquire_legal_T_25, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_27 = asSInt(_put_acquire_legal_T_26) node _put_acquire_legal_T_28 = eq(_put_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_29 = xor(_put_acquire_T, UInt<22>(0h300000)) node _put_acquire_legal_T_30 = cvt(_put_acquire_legal_T_29) node _put_acquire_legal_T_31 = and(_put_acquire_legal_T_30, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_32 = asSInt(_put_acquire_legal_T_31) node _put_acquire_legal_T_33 = eq(_put_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_34 = xor(_put_acquire_T, UInt<26>(0h2000000)) node _put_acquire_legal_T_35 = cvt(_put_acquire_legal_T_34) node _put_acquire_legal_T_36 = and(_put_acquire_legal_T_35, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_37 = asSInt(_put_acquire_legal_T_36) node _put_acquire_legal_T_38 = eq(_put_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_39 = xor(_put_acquire_T, UInt<26>(0h2010000)) node _put_acquire_legal_T_40 = cvt(_put_acquire_legal_T_39) node _put_acquire_legal_T_41 = and(_put_acquire_legal_T_40, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_42 = asSInt(_put_acquire_legal_T_41) node _put_acquire_legal_T_43 = eq(_put_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_44 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_45 = cvt(_put_acquire_legal_T_44) node _put_acquire_legal_T_46 = and(_put_acquire_legal_T_45, asSInt(UInt<33>(0h98000000))) node _put_acquire_legal_T_47 = asSInt(_put_acquire_legal_T_46) node _put_acquire_legal_T_48 = eq(_put_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_49 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_50 = cvt(_put_acquire_legal_T_49) node _put_acquire_legal_T_51 = and(_put_acquire_legal_T_50, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_52 = asSInt(_put_acquire_legal_T_51) node _put_acquire_legal_T_53 = eq(_put_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_54 = xor(_put_acquire_T, UInt<29>(0h10000000)) node _put_acquire_legal_T_55 = cvt(_put_acquire_legal_T_54) node _put_acquire_legal_T_56 = and(_put_acquire_legal_T_55, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_57 = asSInt(_put_acquire_legal_T_56) node _put_acquire_legal_T_58 = eq(_put_acquire_legal_T_57, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_59 = xor(_put_acquire_T, UInt<32>(0h80000000)) node _put_acquire_legal_T_60 = cvt(_put_acquire_legal_T_59) node _put_acquire_legal_T_61 = and(_put_acquire_legal_T_60, asSInt(UInt<33>(0h90000000))) node _put_acquire_legal_T_62 = asSInt(_put_acquire_legal_T_61) node _put_acquire_legal_T_63 = eq(_put_acquire_legal_T_62, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_64 = or(_put_acquire_legal_T_18, _put_acquire_legal_T_23) node _put_acquire_legal_T_65 = or(_put_acquire_legal_T_64, _put_acquire_legal_T_28) node _put_acquire_legal_T_66 = or(_put_acquire_legal_T_65, _put_acquire_legal_T_33) node _put_acquire_legal_T_67 = or(_put_acquire_legal_T_66, _put_acquire_legal_T_38) node _put_acquire_legal_T_68 = or(_put_acquire_legal_T_67, _put_acquire_legal_T_43) node _put_acquire_legal_T_69 = or(_put_acquire_legal_T_68, _put_acquire_legal_T_48) node _put_acquire_legal_T_70 = or(_put_acquire_legal_T_69, _put_acquire_legal_T_53) node _put_acquire_legal_T_71 = or(_put_acquire_legal_T_70, _put_acquire_legal_T_58) node _put_acquire_legal_T_72 = or(_put_acquire_legal_T_71, _put_acquire_legal_T_63) node _put_acquire_legal_T_73 = and(_put_acquire_legal_T_13, _put_acquire_legal_T_72) node _put_acquire_legal_T_74 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_acquire_legal_T_75 = xor(_put_acquire_T, UInt<17>(0h10000)) node _put_acquire_legal_T_76 = cvt(_put_acquire_legal_T_75) node _put_acquire_legal_T_77 = and(_put_acquire_legal_T_76, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_78 = asSInt(_put_acquire_legal_T_77) node _put_acquire_legal_T_79 = eq(_put_acquire_legal_T_78, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_80 = and(_put_acquire_legal_T_74, _put_acquire_legal_T_79) node _put_acquire_legal_T_81 = or(UInt<1>(0h0), _put_acquire_legal_T_9) node _put_acquire_legal_T_82 = or(_put_acquire_legal_T_81, _put_acquire_legal_T_73) node put_acquire_legal = or(_put_acquire_legal_T_82, _put_acquire_legal_T_80) wire put_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect put_acquire.opcode, UInt<1>(0h1) connect put_acquire.param, UInt<1>(0h0) connect put_acquire.size, UInt<2>(0h3) connect put_acquire.source, UInt<1>(0h0) connect put_acquire.address, _put_acquire_T connect put_acquire.mask, wmask connect put_acquire.data, _put_acquire_T_1 connect put_acquire.corrupt, UInt<1>(0h0) node _get_acquire_T = cat(beatAddr, byteAddr) node _get_acquire_legal_T = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_1 = leq(rsize, UInt<4>(0hc)) node _get_acquire_legal_T_2 = and(_get_acquire_legal_T, _get_acquire_legal_T_1) node _get_acquire_legal_T_3 = or(UInt<1>(0h0), _get_acquire_legal_T_2) node _get_acquire_legal_T_4 = xor(_get_acquire_T, UInt<14>(0h3000)) node _get_acquire_legal_T_5 = cvt(_get_acquire_legal_T_4) node _get_acquire_legal_T_6 = and(_get_acquire_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _get_acquire_legal_T_7 = asSInt(_get_acquire_legal_T_6) node _get_acquire_legal_T_8 = eq(_get_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_9 = and(_get_acquire_legal_T_3, _get_acquire_legal_T_8) node _get_acquire_legal_T_10 = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_11 = leq(rsize, UInt<3>(0h6)) node _get_acquire_legal_T_12 = and(_get_acquire_legal_T_10, _get_acquire_legal_T_11) node _get_acquire_legal_T_13 = or(UInt<1>(0h0), _get_acquire_legal_T_12) node _get_acquire_legal_T_14 = xor(_get_acquire_T, UInt<1>(0h0)) node _get_acquire_legal_T_15 = cvt(_get_acquire_legal_T_14) node _get_acquire_legal_T_16 = and(_get_acquire_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _get_acquire_legal_T_17 = asSInt(_get_acquire_legal_T_16) node _get_acquire_legal_T_18 = eq(_get_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_19 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_20 = cvt(_get_acquire_legal_T_19) node _get_acquire_legal_T_21 = and(_get_acquire_legal_T_20, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_22 = asSInt(_get_acquire_legal_T_21) node _get_acquire_legal_T_23 = eq(_get_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_24 = xor(_get_acquire_T, UInt<21>(0h100000)) node _get_acquire_legal_T_25 = cvt(_get_acquire_legal_T_24) node _get_acquire_legal_T_26 = and(_get_acquire_legal_T_25, asSInt(UInt<33>(0h9a103000))) node _get_acquire_legal_T_27 = asSInt(_get_acquire_legal_T_26) node _get_acquire_legal_T_28 = eq(_get_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_29 = xor(_get_acquire_T, UInt<21>(0h100000)) node _get_acquire_legal_T_30 = cvt(_get_acquire_legal_T_29) node _get_acquire_legal_T_31 = and(_get_acquire_legal_T_30, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_32 = asSInt(_get_acquire_legal_T_31) node _get_acquire_legal_T_33 = eq(_get_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_34 = xor(_get_acquire_T, UInt<26>(0h2000000)) node _get_acquire_legal_T_35 = cvt(_get_acquire_legal_T_34) node _get_acquire_legal_T_36 = and(_get_acquire_legal_T_35, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_37 = asSInt(_get_acquire_legal_T_36) node _get_acquire_legal_T_38 = eq(_get_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_39 = xor(_get_acquire_T, UInt<26>(0h2010000)) node _get_acquire_legal_T_40 = cvt(_get_acquire_legal_T_39) node _get_acquire_legal_T_41 = and(_get_acquire_legal_T_40, asSInt(UInt<33>(0h9a113000))) node _get_acquire_legal_T_42 = asSInt(_get_acquire_legal_T_41) node _get_acquire_legal_T_43 = eq(_get_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_44 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_45 = cvt(_get_acquire_legal_T_44) node _get_acquire_legal_T_46 = and(_get_acquire_legal_T_45, asSInt(UInt<33>(0h98000000))) node _get_acquire_legal_T_47 = asSInt(_get_acquire_legal_T_46) node _get_acquire_legal_T_48 = eq(_get_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_49 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_50 = cvt(_get_acquire_legal_T_49) node _get_acquire_legal_T_51 = and(_get_acquire_legal_T_50, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_52 = asSInt(_get_acquire_legal_T_51) node _get_acquire_legal_T_53 = eq(_get_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_54 = xor(_get_acquire_T, UInt<29>(0h10000000)) node _get_acquire_legal_T_55 = cvt(_get_acquire_legal_T_54) node _get_acquire_legal_T_56 = and(_get_acquire_legal_T_55, asSInt(UInt<33>(0h9a113000))) node _get_acquire_legal_T_57 = asSInt(_get_acquire_legal_T_56) node _get_acquire_legal_T_58 = eq(_get_acquire_legal_T_57, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_59 = xor(_get_acquire_T, UInt<32>(0h80000000)) node _get_acquire_legal_T_60 = cvt(_get_acquire_legal_T_59) node _get_acquire_legal_T_61 = and(_get_acquire_legal_T_60, asSInt(UInt<33>(0h90000000))) node _get_acquire_legal_T_62 = asSInt(_get_acquire_legal_T_61) node _get_acquire_legal_T_63 = eq(_get_acquire_legal_T_62, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_64 = or(_get_acquire_legal_T_18, _get_acquire_legal_T_23) node _get_acquire_legal_T_65 = or(_get_acquire_legal_T_64, _get_acquire_legal_T_28) node _get_acquire_legal_T_66 = or(_get_acquire_legal_T_65, _get_acquire_legal_T_33) node _get_acquire_legal_T_67 = or(_get_acquire_legal_T_66, _get_acquire_legal_T_38) node _get_acquire_legal_T_68 = or(_get_acquire_legal_T_67, _get_acquire_legal_T_43) node _get_acquire_legal_T_69 = or(_get_acquire_legal_T_68, _get_acquire_legal_T_48) node _get_acquire_legal_T_70 = or(_get_acquire_legal_T_69, _get_acquire_legal_T_53) node _get_acquire_legal_T_71 = or(_get_acquire_legal_T_70, _get_acquire_legal_T_58) node _get_acquire_legal_T_72 = or(_get_acquire_legal_T_71, _get_acquire_legal_T_63) node _get_acquire_legal_T_73 = and(_get_acquire_legal_T_13, _get_acquire_legal_T_72) node _get_acquire_legal_T_74 = or(UInt<1>(0h0), _get_acquire_legal_T_9) node get_acquire_legal = or(_get_acquire_legal_T_74, _get_acquire_legal_T_73) wire get_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect get_acquire.opcode, UInt<3>(0h4) connect get_acquire.param, UInt<1>(0h0) connect get_acquire.size, rsize connect get_acquire.source, UInt<1>(0h0) connect get_acquire.address, _get_acquire_T node _get_acquire_a_mask_sizeOH_T = or(rsize, UInt<3>(0h0)) node get_acquire_a_mask_sizeOH_shiftAmount = bits(_get_acquire_a_mask_sizeOH_T, 1, 0) node _get_acquire_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_acquire_a_mask_sizeOH_shiftAmount) node _get_acquire_a_mask_sizeOH_T_2 = bits(_get_acquire_a_mask_sizeOH_T_1, 2, 0) node get_acquire_a_mask_sizeOH = or(_get_acquire_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_acquire_a_mask_sub_sub_sub_0_1 = geq(rsize, UInt<2>(0h3)) node get_acquire_a_mask_sub_sub_size = bits(get_acquire_a_mask_sizeOH, 2, 2) node get_acquire_a_mask_sub_sub_bit = bits(_get_acquire_T, 2, 2) node get_acquire_a_mask_sub_sub_nbit = eq(get_acquire_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_nbit) node _get_acquire_a_mask_sub_sub_acc_T = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_0_2) node get_acquire_a_mask_sub_sub_0_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T) node get_acquire_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_bit) node _get_acquire_a_mask_sub_sub_acc_T_1 = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_1_2) node get_acquire_a_mask_sub_sub_1_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T_1) node get_acquire_a_mask_sub_size = bits(get_acquire_a_mask_sizeOH, 1, 1) node get_acquire_a_mask_sub_bit = bits(_get_acquire_T, 1, 1) node get_acquire_a_mask_sub_nbit = eq(get_acquire_a_mask_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_0_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_0_2) node get_acquire_a_mask_sub_0_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T) node get_acquire_a_mask_sub_1_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_1 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_1_2) node get_acquire_a_mask_sub_1_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T_1) node get_acquire_a_mask_sub_2_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T_2 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_2_2) node get_acquire_a_mask_sub_2_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_2) node get_acquire_a_mask_sub_3_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_3 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_3_2) node get_acquire_a_mask_sub_3_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_3) node get_acquire_a_mask_size = bits(get_acquire_a_mask_sizeOH, 0, 0) node get_acquire_a_mask_bit = bits(_get_acquire_T, 0, 0) node get_acquire_a_mask_nbit = eq(get_acquire_a_mask_bit, UInt<1>(0h0)) node get_acquire_a_mask_eq = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T = and(get_acquire_a_mask_size, get_acquire_a_mask_eq) node get_acquire_a_mask_acc = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T) node get_acquire_a_mask_eq_1 = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_1 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_1) node get_acquire_a_mask_acc_1 = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T_1) node get_acquire_a_mask_eq_2 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_2 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_2) node get_acquire_a_mask_acc_2 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_2) node get_acquire_a_mask_eq_3 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_3 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_3) node get_acquire_a_mask_acc_3 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_3) node get_acquire_a_mask_eq_4 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_4 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_4) node get_acquire_a_mask_acc_4 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_4) node get_acquire_a_mask_eq_5 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_5 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_5) node get_acquire_a_mask_acc_5 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_5) node get_acquire_a_mask_eq_6 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_6 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_6) node get_acquire_a_mask_acc_6 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_6) node get_acquire_a_mask_eq_7 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_7 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_7) node get_acquire_a_mask_acc_7 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_7) node get_acquire_a_mask_lo_lo = cat(get_acquire_a_mask_acc_1, get_acquire_a_mask_acc) node get_acquire_a_mask_lo_hi = cat(get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2) node get_acquire_a_mask_lo = cat(get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo) node get_acquire_a_mask_hi_lo = cat(get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4) node get_acquire_a_mask_hi_hi = cat(get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6) node get_acquire_a_mask_hi = cat(get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo) node _get_acquire_a_mask_T = cat(get_acquire_a_mask_hi, get_acquire_a_mask_lo) connect get_acquire.mask, _get_acquire_a_mask_T invalidate get_acquire.data connect get_acquire.corrupt, UInt<1>(0h0) node _nodeOut_a_valid_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_valid_T_1 = eq(state, UInt<4>(0h3)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_bits_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_bits_T_1 = mux(_nodeOut_a_bits_T, put_acquire, get_acquire) connect nodeOut.a.bits, _nodeOut_a_bits_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) node _nodeOut_d_ready_T = eq(state, UInt<4>(0h8)) node _nodeOut_d_ready_T_1 = eq(state, UInt<4>(0h4)) node _nodeOut_d_ready_T_2 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_T_1) connect nodeOut.d.ready, _nodeOut_d_ready_T_2 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T = eq(state, UInt<4>(0h0)) node _T_1 = and(_T, io.tsi.in.valid) when _T_1 : connect cmd, io.tsi.in.bits connect idx, UInt<1>(0h0) connect addr, UInt<1>(0h0) connect len, UInt<1>(0h0) connect state, UInt<4>(0h1) node _T_2 = eq(state, UInt<4>(0h1)) node _T_3 = and(_T_2, io.tsi.in.valid) when _T_3 : node _addr_T = bits(idx, 0, 0) node _addr_T_1 = cat(_addr_T, UInt<5>(0h0)) node _addr_T_2 = dshl(io.tsi.in.bits, _addr_T_1) node _addr_T_3 = or(addr, _addr_T_2) connect addr, _addr_T_3 node _idx_T = add(idx, UInt<1>(0h1)) node _idx_T_1 = tail(_idx_T, 1) connect idx, _idx_T_1 node _T_4 = eq(idx, UInt<1>(0h1)) when _T_4 : connect idx, UInt<1>(0h0) connect state, UInt<4>(0h2) node _T_5 = eq(state, UInt<4>(0h2)) node _T_6 = and(_T_5, io.tsi.in.valid) when _T_6 : node _len_T = bits(idx, 0, 0) node _len_T_1 = cat(_len_T, UInt<5>(0h0)) node _len_T_2 = dshl(io.tsi.in.bits, _len_T_1) node _len_T_3 = or(len, _len_T_2) connect len, _len_T_3 node _idx_T_2 = add(idx, UInt<1>(0h1)) node _idx_T_3 = tail(_idx_T_2, 1) connect idx, _idx_T_3 node _T_7 = eq(idx, UInt<1>(0h1)) when _T_7 : node _idx_T_4 = bits(addr, 2, 2) connect idx, _idx_T_4 node _T_8 = eq(cmd, UInt<1>(0h1)) when _T_8 : connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) else : node _T_9 = eq(cmd, UInt<1>(0h0)) when _T_9 : connect state, UInt<4>(0h3) else : node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Bad TSI command\n at TSIToTileLink.scala:137 assert(false.B, \"Bad TSI command\")\n") : printf assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert node _T_13 = eq(state, UInt<4>(0h3)) node _T_14 = and(_T_13, nodeOut.a.ready) when _T_14 : connect state, UInt<4>(0h4) node _T_15 = eq(state, UInt<4>(0h4)) node _T_16 = and(_T_15, nodeOut.d.valid) when _T_16 : wire _WIRE_6 : UInt<32>[2] wire _WIRE_7 : UInt<64> connect _WIRE_7, nodeOut.d.bits.data node _T_17 = bits(_WIRE_7, 31, 0) connect _WIRE_6[0], _T_17 node _T_18 = bits(_WIRE_7, 63, 32) connect _WIRE_6[1], _T_18 connect body, _WIRE_6 node _idx_T_5 = bits(addr, 2, 2) connect idx, _idx_T_5 connect addr, nextAddr connect state, UInt<4>(0h5) node _T_19 = eq(state, UInt<4>(0h5)) node _T_20 = and(_T_19, io.tsi.out.ready) when _T_20 : node _idx_T_6 = add(idx, UInt<1>(0h1)) node _idx_T_7 = tail(_idx_T_6, 1) connect idx, _idx_T_7 node _len_T_4 = sub(len, UInt<1>(0h1)) node _len_T_5 = tail(_len_T_4, 1) connect len, _len_T_5 node _T_21 = eq(len, UInt<1>(0h0)) when _T_21 : connect state, UInt<4>(0h0) else : node _T_22 = eq(idx, UInt<1>(0h1)) when _T_22 : connect state, UInt<4>(0h3) node _T_23 = eq(state, UInt<4>(0h6)) node _T_24 = and(_T_23, io.tsi.in.valid) when _T_24 : connect body[idx], io.tsi.in.bits node _bodyValid_T = dshl(UInt<1>(0h1), idx) node _bodyValid_T_1 = or(bodyValid, _bodyValid_T) connect bodyValid, _bodyValid_T_1 node _T_25 = eq(idx, UInt<1>(0h1)) node _T_26 = eq(len, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) when _T_27 : connect state, UInt<4>(0h7) else : node _idx_T_8 = add(idx, UInt<1>(0h1)) node _idx_T_9 = tail(_idx_T_8, 1) connect idx, _idx_T_9 node _len_T_6 = sub(len, UInt<1>(0h1)) node _len_T_7 = tail(_len_T_6, 1) connect len, _len_T_7 node _T_28 = eq(state, UInt<4>(0h7)) node _T_29 = and(_T_28, nodeOut.a.ready) when _T_29 : connect state, UInt<4>(0h8) node _T_30 = eq(state, UInt<4>(0h8)) node _T_31 = and(_T_30, nodeOut.d.valid) when _T_31 : node _T_32 = eq(len, UInt<1>(0h0)) when _T_32 : connect state, UInt<4>(0h0) else : connect addr, nextAddr node _len_T_8 = sub(len, UInt<1>(0h1)) node _len_T_9 = tail(_len_T_8, 1) connect len, _len_T_9 connect idx, UInt<1>(0h0) connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) extmodule plusarg_reader_129 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_74 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_80 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T \| _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 \| _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 \| _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_81 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'h9A312000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'h9A303000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:22], _put_acquire_T[21:0] ^ 22'h200000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:22], _put_acquire_T[21:0] ^ 22'h300000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_34 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_39 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [31:0] _put_acquire_legal_T_44; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_44 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _put_acquire_legal_T_49; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_49 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_54 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_55 = {1'h0, _put_acquire_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_56 = _put_acquire_legal_T_55 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_57 = _put_acquire_legal_T_56; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_59 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_60 = {1'h0, _put_acquire_legal_T_59}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_61 = _put_acquire_legal_T_60 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_62 = _put_acquire_legal_T_61; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_63 = _put_acquire_legal_T_62 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_64 = _put_acquire_legal_T_18 \| _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_65 = _put_acquire_legal_T_64 \| _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_66 = _put_acquire_legal_T_65 \| _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 \| _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_68 = _put_acquire_legal_T_67 \| _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_69 = _put_acquire_legal_T_68 \| _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_70 = _put_acquire_legal_T_69 \| _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_71 = _put_acquire_legal_T_70 \| _put_acquire_legal_T_58; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_72 = _put_acquire_legal_T_71 \| _put_acquire_legal_T_63; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_73 = _put_acquire_legal_T_72; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_75 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_76 = {1'h0, _put_acquire_legal_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_77 = _put_acquire_legal_T_76 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_78 = _put_acquire_legal_T_77; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_79 = _put_acquire_legal_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_82 = _put_acquire_legal_T_81 \| _put_acquire_legal_T_73; // @[Parameters.scala:684:54, :686:26] wire put_acquire_legal = _put_acquire_legal_T_82; // @[Parameters.scala:686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_74 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_19 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {_get_acquire_T[31:21], _get_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_29; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_29 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_34 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_39 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_44; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_49; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_49 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_54 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_55 = {1'h0, _get_acquire_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_56 = _get_acquire_legal_T_55 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_57 = _get_acquire_legal_T_56; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_59 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_60 = {1'h0, _get_acquire_legal_T_59}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_61 = _get_acquire_legal_T_60 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_62 = _get_acquire_legal_T_61; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_63 = _get_acquire_legal_T_62 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_64 = _get_acquire_legal_T_18 \| _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_65 = _get_acquire_legal_T_64 \| _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_66 = _get_acquire_legal_T_65 \| _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_67 = _get_acquire_legal_T_66 \| _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_68 = _get_acquire_legal_T_67 \| _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_69 = _get_acquire_legal_T_68 \| _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_70 = _get_acquire_legal_T_69 \| _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_71 = _get_acquire_legal_T_70 \| _get_acquire_legal_T_58; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_72 = _get_acquire_legal_T_71 \| _get_acquire_legal_T_63; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_73 = _get_acquire_legal_T_72; // @[Parameters.scala:684:54, :685:42] wire get_acquire_legal = _get_acquire_legal_T_74 \| _get_acquire_legal_T_73; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T \| _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_4 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_4 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} \| _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_5 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_6 = _GEN_5 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_6; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_6; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_6; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_6; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_4 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} \| _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_7 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]
Generate the Verilog code corresponding to this FIRRTL code module PE_400 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_144 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_400( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_144 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_98 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_98( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_2 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d128s7k6z4c_2 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<5>(0h13)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<5>(0h12)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<5>(0h11)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<5>(0h10)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_5 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_5 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_5, 1, 0) node _io_flit_bits_egress_id_requestOH_T_25 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_26 = eq(_io_flit_bits_egress_id_requestOH_T_25, UInt<4>(0hf)) node _io_flit_bits_egress_id_requestOH_T_27 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_5) node _io_flit_bits_egress_id_requestOH_T_28 = and(_io_flit_bits_egress_id_requestOH_T_26, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_5, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_5 = and(_io_flit_bits_egress_id_requestOH_T_28, _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_6 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_6 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_6, 1, 0) node _io_flit_bits_egress_id_requestOH_T_30 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_31 = eq(_io_flit_bits_egress_id_requestOH_T_30, UInt<4>(0he)) node _io_flit_bits_egress_id_requestOH_T_32 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_6) node _io_flit_bits_egress_id_requestOH_T_33 = and(_io_flit_bits_egress_id_requestOH_T_31, _io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_6, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_6 = and(_io_flit_bits_egress_id_requestOH_T_33, _io_flit_bits_egress_id_requestOH_T_34) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_7 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_7 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_7, 1, 0) node _io_flit_bits_egress_id_requestOH_T_35 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_36 = eq(_io_flit_bits_egress_id_requestOH_T_35, UInt<4>(0hd)) node _io_flit_bits_egress_id_requestOH_T_37 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_7) node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_36, _io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_7, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_7 = and(_io_flit_bits_egress_id_requestOH_T_38, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_8 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_8 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_8, 1, 0) node _io_flit_bits_egress_id_requestOH_T_40 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_41 = eq(_io_flit_bits_egress_id_requestOH_T_40, UInt<4>(0hc)) node _io_flit_bits_egress_id_requestOH_T_42 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_8) node _io_flit_bits_egress_id_requestOH_T_43 = and(_io_flit_bits_egress_id_requestOH_T_41, _io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_8, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_8 = and(_io_flit_bits_egress_id_requestOH_T_43, _io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_9 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_9 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_9, 1, 0) node _io_flit_bits_egress_id_requestOH_T_45 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_47 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_9) node _io_flit_bits_egress_id_requestOH_T_48 = and(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_47) node _io_flit_bits_egress_id_requestOH_T_49 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_9, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_9 = and(_io_flit_bits_egress_id_requestOH_T_48, _io_flit_bits_egress_id_requestOH_T_49) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_10 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_10 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_10, 1, 0) node _io_flit_bits_egress_id_requestOH_T_50 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_52 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_10) node _io_flit_bits_egress_id_requestOH_T_53 = and(_io_flit_bits_egress_id_requestOH_T_51, _io_flit_bits_egress_id_requestOH_T_52) node _io_flit_bits_egress_id_requestOH_T_54 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_10, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_10 = and(_io_flit_bits_egress_id_requestOH_T_53, _io_flit_bits_egress_id_requestOH_T_54) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_11 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_11 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_11, 1, 0) node _io_flit_bits_egress_id_requestOH_T_55 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_56 = eq(_io_flit_bits_egress_id_requestOH_T_55, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_57 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_11) node _io_flit_bits_egress_id_requestOH_T_58 = and(_io_flit_bits_egress_id_requestOH_T_56, _io_flit_bits_egress_id_requestOH_T_57) node _io_flit_bits_egress_id_requestOH_T_59 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_11, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_11 = and(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_59) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_12 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_12 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_12, 1, 0) node _io_flit_bits_egress_id_requestOH_T_60 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_61 = eq(_io_flit_bits_egress_id_requestOH_T_60, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_62 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_12) node _io_flit_bits_egress_id_requestOH_T_63 = and(_io_flit_bits_egress_id_requestOH_T_61, _io_flit_bits_egress_id_requestOH_T_62) node _io_flit_bits_egress_id_requestOH_T_64 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_12, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_12 = and(_io_flit_bits_egress_id_requestOH_T_63, _io_flit_bits_egress_id_requestOH_T_64) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h0), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<2>(0h2), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<3>(0h4), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<3>(0h6), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_8 = mux(io_flit_bits_egress_id_requestOH_8, UInt<4>(0h8), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_9 = mux(io_flit_bits_egress_id_requestOH_9, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_10 = mux(io_flit_bits_egress_id_requestOH_10, UInt<4>(0ha), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_11 = mux(io_flit_bits_egress_id_requestOH_11, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_12 = mux(io_flit_bits_egress_id_requestOH_12, UInt<4>(0hc), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_15 = or(_io_flit_bits_egress_id_T_14, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_16 = or(_io_flit_bits_egress_id_T_15, _io_flit_bits_egress_id_T_4) node _io_flit_bits_egress_id_T_17 = or(_io_flit_bits_egress_id_T_16, _io_flit_bits_egress_id_T_5) node _io_flit_bits_egress_id_T_18 = or(_io_flit_bits_egress_id_T_17, _io_flit_bits_egress_id_T_6) node _io_flit_bits_egress_id_T_19 = or(_io_flit_bits_egress_id_T_18, _io_flit_bits_egress_id_T_7) node _io_flit_bits_egress_id_T_20 = or(_io_flit_bits_egress_id_T_19, _io_flit_bits_egress_id_T_8) node _io_flit_bits_egress_id_T_21 = or(_io_flit_bits_egress_id_T_20, _io_flit_bits_egress_id_T_9) node _io_flit_bits_egress_id_T_22 = or(_io_flit_bits_egress_id_T_21, _io_flit_bits_egress_id_T_10) node _io_flit_bits_egress_id_T_23 = or(_io_flit_bits_egress_id_T_22, _io_flit_bits_egress_id_T_11) node _io_flit_bits_egress_id_T_24 = or(_io_flit_bits_egress_id_T_23, _io_flit_bits_egress_id_T_12) wire _io_flit_bits_egress_id_WIRE : UInt<4> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_24 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<6>(0h20)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T	module TLDToNoC_2( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [1:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire [1:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:4]) : 2'h0; // @[package.scala:243:{46,71,76}] reg [1:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 2'h1 \| tail_beats1 == 2'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 2'h0; // @[Edges.scala:229:27] tail_counter <= 2'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:4]) : 2'h0) : head_counter - 2'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 2'h0 ? tail_beats1 : tail_counter - 2'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a26d64s7k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a26d64s7k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [25:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [25:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [25:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid \| full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN \| full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_116 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_130 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_116( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_130 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_17 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_177 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_178 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_17( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_177 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_178 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_90 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_91 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_1 : output auto : { icenic_intsink_out : UInt<1>[2], icenic_dma_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, icenic_dma_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip icenic_mmio_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} output nic : { flip in : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, out : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, flip macAddr : UInt<48>, flip rlimit : { inc : UInt<8>, period : UInt<8>, size : UInt<8>}, flip pauser : { threshold : UInt<16>, quanta : UInt<16>, refresh : UInt<16>}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst icenic of IceNIC connect icenic.clock, childClock connect icenic.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect icenic.auto.mmio_in, auto.icenic_mmio_in connect icenic.auto.dma_out_0.d, auto.icenic_dma_out_0.d connect auto.icenic_dma_out_0.a.bits, icenic.auto.dma_out_0.a.bits connect auto.icenic_dma_out_0.a.valid, icenic.auto.dma_out_0.a.valid connect icenic.auto.dma_out_0.a.ready, auto.icenic_dma_out_0.a.ready connect icenic.auto.dma_out_1.d, auto.icenic_dma_out_1.d connect auto.icenic_dma_out_1.a.bits, icenic.auto.dma_out_1.a.bits connect auto.icenic_dma_out_1.a.valid, icenic.auto.dma_out_1.a.valid connect icenic.auto.dma_out_1.a.ready, auto.icenic_dma_out_1.a.ready connect auto.icenic_intsink_out, icenic.auto.intsink_out wire nic_vonly : { flip in : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, out : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, flip macAddr : UInt<48>, flip rlimit : { inc : UInt<8>, period : UInt<8>, size : UInt<8>}, flip pauser : { threshold : UInt<16>, quanta : UInt<16>, refresh : UInt<16>}} connect nic_vonly.out.valid, icenic.io.ext.out.valid connect nic_vonly.out.bits, icenic.io.ext.out.bits connect icenic.io.ext.out.ready, UInt<1>(0h1) connect icenic.io.ext.in.valid, nic_vonly.in.valid connect icenic.io.ext.in.bits.last, nic_vonly.in.bits.last connect icenic.io.ext.in.bits.keep, nic_vonly.in.bits.keep connect icenic.io.ext.in.bits.data, nic_vonly.in.bits.data node _nic_T = eq(nic_vonly.in.valid, UInt<1>(0h0)) node _nic_T_1 = or(_nic_T, icenic.io.ext.in.ready) node _nic_T_2 = asUInt(childReset) node _nic_T_3 = eq(_nic_T_2, UInt<1>(0h0)) when _nic_T_3 : node _nic_T_4 = eq(_nic_T_1, UInt<1>(0h0)) when _nic_T_4 : printf(childClock, UInt<1>(0h1), "Assertion failed: NIC input not ready for valid\n at NIC.scala:525 assert(!vonly.in.valid \|\| nicio.in.ready, \"NIC input not ready for valid\")\n") : nic_printf assert(childClock, _nic_T_1, UInt<1>(0h1), "") : nic_assert connect icenic.io.ext.macAddr, nic_vonly.macAddr connect icenic.io.ext.rlimit.size, nic_vonly.rlimit.size connect icenic.io.ext.rlimit.period, nic_vonly.rlimit.period connect icenic.io.ext.rlimit.inc, nic_vonly.rlimit.inc connect icenic.io.ext.pauser.refresh, nic_vonly.pauser.refresh connect icenic.io.ext.pauser.quanta, nic_vonly.pauser.quanta connect icenic.io.ext.pauser.threshold, nic_vonly.pauser.threshold connect nic, nic_vonly connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_126 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_127 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module ClockSinkDomain_1( // @[ClockDomain.scala:14:9] output auto_icenic_intsink_out_0, // @[LazyModuleImp.scala:107:25] output auto_icenic_intsink_out_1, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icenic_dma_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_dma_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_icenic_dma_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_dma_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icenic_dma_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_icenic_dma_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_icenic_dma_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_icenic_dma_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icenic_dma_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icenic_dma_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icenic_dma_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_icenic_dma_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_dma_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icenic_dma_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_icenic_dma_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icenic_dma_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icenic_dma_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_icenic_mmio_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_icenic_mmio_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_mmio_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_mmio_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icenic_mmio_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_icenic_mmio_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_icenic_mmio_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_icenic_mmio_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icenic_mmio_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icenic_mmio_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_icenic_mmio_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_icenic_mmio_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_mmio_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_icenic_mmio_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_icenic_mmio_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_icenic_mmio_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input nic_in_valid, // @[NIC.scala:568:24] input [63:0] nic_in_bits_data, // @[NIC.scala:568:24] input [7:0] nic_in_bits_keep, // @[NIC.scala:568:24] input nic_in_bits_last, // @[NIC.scala:568:24] output nic_out_valid, // @[NIC.scala:568:24] output [63:0] nic_out_bits_data, // @[NIC.scala:568:24] output [7:0] nic_out_bits_keep, // @[NIC.scala:568:24] output nic_out_bits_last, // @[NIC.scala:568:24] input [47:0] nic_macAddr, // @[NIC.scala:568:24] input [7:0] nic_rlimit_inc, // @[NIC.scala:568:24] input [7:0] nic_rlimit_period, // @[NIC.scala:568:24] input [7:0] nic_rlimit_size, // @[NIC.scala:568:24] input [15:0] nic_pauser_threshold, // @[NIC.scala:568:24] input [15:0] nic_pauser_quanta, // @[NIC.scala:568:24] input [15:0] nic_pauser_refresh, // @[NIC.scala:568:24] output clock // @[ClockDomain.scala:21:19] ); wire auto_icenic_dma_out_1_a_ready_0 = auto_icenic_dma_out_1_a_ready; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_valid_0 = auto_icenic_dma_out_1_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_d_bits_opcode_0 = auto_icenic_dma_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_dma_out_1_d_bits_param_0 = auto_icenic_dma_out_1_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_1_d_bits_size_0 = auto_icenic_dma_out_1_d_bits_size; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_d_bits_source_0 = auto_icenic_dma_out_1_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_1_d_bits_sink_0 = auto_icenic_dma_out_1_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_bits_denied_0 = auto_icenic_dma_out_1_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_1_d_bits_data_0 = auto_icenic_dma_out_1_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_bits_corrupt_0 = auto_icenic_dma_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_a_ready_0 = auto_icenic_dma_out_0_a_ready; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_valid_0 = auto_icenic_dma_out_0_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_d_bits_opcode_0 = auto_icenic_dma_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_dma_out_0_d_bits_param_0 = auto_icenic_dma_out_0_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_0_d_bits_size_0 = auto_icenic_dma_out_0_d_bits_size; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_d_bits_source_0 = auto_icenic_dma_out_0_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_0_d_bits_sink_0 = auto_icenic_dma_out_0_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_bits_denied_0 = auto_icenic_dma_out_0_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_0_d_bits_data_0 = auto_icenic_dma_out_0_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_bits_corrupt_0 = auto_icenic_dma_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_a_valid_0 = auto_icenic_mmio_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_mmio_in_a_bits_opcode_0 = auto_icenic_mmio_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_mmio_in_a_bits_param_0 = auto_icenic_mmio_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_mmio_in_a_bits_size_0 = auto_icenic_mmio_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_icenic_mmio_in_a_bits_source_0 = auto_icenic_mmio_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_icenic_mmio_in_a_bits_address_0 = auto_icenic_mmio_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_icenic_mmio_in_a_bits_mask_0 = auto_icenic_mmio_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_mmio_in_a_bits_data_0 = auto_icenic_mmio_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_a_bits_corrupt_0 = auto_icenic_mmio_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_ready_0 = auto_icenic_mmio_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire nic_in_valid_0 = nic_in_valid; // @[ClockDomain.scala:14:9] wire [63:0] nic_in_bits_data_0 = nic_in_bits_data; // @[ClockDomain.scala:14:9] wire [7:0] nic_in_bits_keep_0 = nic_in_bits_keep; // @[ClockDomain.scala:14:9] wire nic_in_bits_last_0 = nic_in_bits_last; // @[ClockDomain.scala:14:9] wire [47:0] nic_macAddr_0 = nic_macAddr; // @[ClockDomain.scala:14:9] wire [7:0] nic_rlimit_inc_0 = nic_rlimit_inc; // @[ClockDomain.scala:14:9] wire [7:0] nic_rlimit_period_0 = nic_rlimit_period; // @[ClockDomain.scala:14:9] wire [7:0] nic_rlimit_size_0 = nic_rlimit_size; // @[ClockDomain.scala:14:9] wire [15:0] nic_pauser_threshold_0 = nic_pauser_threshold; // @[ClockDomain.scala:14:9] wire [15:0] nic_pauser_quanta_0 = nic_pauser_quanta; // @[ClockDomain.scala:14:9] wire [15:0] nic_pauser_refresh_0 = nic_pauser_refresh; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_a_bits_param = 3'h0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_a_bits_param = 3'h0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_a_bits_opcode = 3'h4; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_0_a_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_ready = 1'h1; // @[ClockDomain.scala:14:9] wire _nic_T_1 = 1'h1; // @[NIC.scala:525:28] wire [1:0] auto_icenic_mmio_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire _nic_T_4 = 1'h0; // @[NIC.scala:525:11] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire nic_vonly_in_valid = nic_in_valid_0; // @[ClockDomain.scala:14:9] wire [63:0] nic_vonly_in_bits_data = nic_in_bits_data_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_in_bits_keep = nic_in_bits_keep_0; // @[ClockDomain.scala:14:9] wire nic_vonly_in_bits_last = nic_in_bits_last_0; // @[ClockDomain.scala:14:9] wire nic_vonly_out_valid; // @[NIC.scala:519:21] wire [63:0] nic_vonly_out_bits_data; // @[NIC.scala:519:21] wire [7:0] nic_vonly_out_bits_keep; // @[NIC.scala:519:21] wire nic_vonly_out_bits_last; // @[NIC.scala:519:21] wire [47:0] nic_vonly_macAddr = nic_macAddr_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_rlimit_inc = nic_rlimit_inc_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_rlimit_period = nic_rlimit_period_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_rlimit_size = nic_rlimit_size_0; // @[ClockDomain.scala:14:9] wire [15:0] nic_vonly_pauser_threshold = nic_pauser_threshold_0; // @[ClockDomain.scala:14:9] wire [15:0] nic_vonly_pauser_quanta = nic_pauser_quanta_0; // @[ClockDomain.scala:14:9] wire auto_icenic_intsink_out_0_0; // @[ClockDomain.scala:14:9] wire auto_icenic_intsink_out_1_0; // @[ClockDomain.scala:14:9] wire [15:0] nic_vonly_pauser_refresh = nic_pauser_refresh_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_icenic_dma_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_icenic_dma_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_icenic_dma_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_icenic_dma_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_mmio_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_mmio_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_icenic_mmio_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_mmio_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [63:0] nic_out_bits_data_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_out_bits_keep_0; // @[ClockDomain.scala:14:9] wire nic_out_bits_last_0; // @[ClockDomain.scala:14:9] wire nic_out_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire _nic_T_2 = childReset; // @[NIC.scala:525:11] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] assign nic_out_valid_0 = nic_vonly_out_valid; // @[ClockDomain.scala:14:9] assign nic_out_bits_data_0 = nic_vonly_out_bits_data; // @[ClockDomain.scala:14:9] assign nic_out_bits_keep_0 = nic_vonly_out_bits_keep; // @[ClockDomain.scala:14:9] assign nic_out_bits_last_0 = nic_vonly_out_bits_last; // @[ClockDomain.scala:14:9] wire _nic_T = ~nic_vonly_in_valid; // @[NIC.scala:519:21, :525:12] wire _nic_T_3 = ~_nic_T_2; // @[NIC.scala:525:11] IceNIC icenic ( // @[NIC.scala:561:37] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_intsink_out_0 (auto_icenic_intsink_out_0_0), .auto_intsink_out_1 (auto_icenic_intsink_out_1_0), .auto_dma_out_1_a_ready (auto_icenic_dma_out_1_a_ready_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_a_valid (auto_icenic_dma_out_1_a_valid_0), .auto_dma_out_1_a_bits_opcode (auto_icenic_dma_out_1_a_bits_opcode_0), .auto_dma_out_1_a_bits_size (auto_icenic_dma_out_1_a_bits_size_0), .auto_dma_out_1_a_bits_source (auto_icenic_dma_out_1_a_bits_source_0), .auto_dma_out_1_a_bits_address (auto_icenic_dma_out_1_a_bits_address_0), .auto_dma_out_1_a_bits_mask (auto_icenic_dma_out_1_a_bits_mask_0), .auto_dma_out_1_a_bits_data (auto_icenic_dma_out_1_a_bits_data_0), .auto_dma_out_1_d_ready (auto_icenic_dma_out_1_d_ready_0), .auto_dma_out_1_d_valid (auto_icenic_dma_out_1_d_valid_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_opcode (auto_icenic_dma_out_1_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_param (auto_icenic_dma_out_1_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_size (auto_icenic_dma_out_1_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_source (auto_icenic_dma_out_1_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_sink (auto_icenic_dma_out_1_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_denied (auto_icenic_dma_out_1_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_data (auto_icenic_dma_out_1_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_corrupt (auto_icenic_dma_out_1_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_a_ready (auto_icenic_dma_out_0_a_ready_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_a_valid (auto_icenic_dma_out_0_a_valid_0), .auto_dma_out_0_a_bits_size (auto_icenic_dma_out_0_a_bits_size_0), .auto_dma_out_0_a_bits_source (auto_icenic_dma_out_0_a_bits_source_0), .auto_dma_out_0_a_bits_address (auto_icenic_dma_out_0_a_bits_address_0), .auto_dma_out_0_a_bits_mask (auto_icenic_dma_out_0_a_bits_mask_0), .auto_dma_out_0_d_valid (auto_icenic_dma_out_0_d_valid_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_opcode (auto_icenic_dma_out_0_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_param (auto_icenic_dma_out_0_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_size (auto_icenic_dma_out_0_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_source (auto_icenic_dma_out_0_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_sink (auto_icenic_dma_out_0_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_denied (auto_icenic_dma_out_0_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_data (auto_icenic_dma_out_0_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_corrupt (auto_icenic_dma_out_0_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_ready (auto_icenic_mmio_in_a_ready_0), .auto_mmio_in_a_valid (auto_icenic_mmio_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_opcode (auto_icenic_mmio_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_param (auto_icenic_mmio_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_size (auto_icenic_mmio_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_source (auto_icenic_mmio_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_address (auto_icenic_mmio_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_mask (auto_icenic_mmio_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_data (auto_icenic_mmio_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_corrupt (auto_icenic_mmio_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_d_ready (auto_icenic_mmio_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_d_valid (auto_icenic_mmio_in_d_valid_0), .auto_mmio_in_d_bits_opcode (auto_icenic_mmio_in_d_bits_opcode_0), .auto_mmio_in_d_bits_size (auto_icenic_mmio_in_d_bits_size_0), .auto_mmio_in_d_bits_source (auto_icenic_mmio_in_d_bits_source_0), .auto_mmio_in_d_bits_data (auto_icenic_mmio_in_d_bits_data_0), .io_ext_in_valid (nic_vonly_in_valid), // @[NIC.scala:519:21] .io_ext_in_bits_data (nic_vonly_in_bits_data), // @[NIC.scala:519:21] .io_ext_in_bits_keep (nic_vonly_in_bits_keep), // @[NIC.scala:519:21] .io_ext_in_bits_last (nic_vonly_in_bits_last), // @[NIC.scala:519:21] .io_ext_out_valid (nic_vonly_out_valid), .io_ext_out_bits_data (nic_vonly_out_bits_data), .io_ext_out_bits_keep (nic_vonly_out_bits_keep), .io_ext_out_bits_last (nic_vonly_out_bits_last), .io_ext_macAddr (nic_vonly_macAddr), // @[NIC.scala:519:21] .io_ext_rlimit_inc (nic_vonly_rlimit_inc), // @[NIC.scala:519:21] .io_ext_rlimit_period (nic_vonly_rlimit_period), // @[NIC.scala:519:21] .io_ext_rlimit_size (nic_vonly_rlimit_size), // @[NIC.scala:519:21] .io_ext_pauser_threshold (nic_vonly_pauser_threshold), // @[NIC.scala:519:21] .io_ext_pauser_quanta (nic_vonly_pauser_quanta), // @[NIC.scala:519:21] .io_ext_pauser_refresh (nic_vonly_pauser_refresh) // @[NIC.scala:519:21] ); // @[NIC.scala:561:37] assign auto_icenic_intsink_out_0 = auto_icenic_intsink_out_0_0; // @[ClockDomain.scala:14:9] assign auto_icenic_intsink_out_1 = auto_icenic_intsink_out_1_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_valid = auto_icenic_dma_out_1_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_opcode = auto_icenic_dma_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_size = auto_icenic_dma_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_source = auto_icenic_dma_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_address = auto_icenic_dma_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_mask = auto_icenic_dma_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_data = auto_icenic_dma_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_d_ready = auto_icenic_dma_out_1_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_valid = auto_icenic_dma_out_0_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_size = auto_icenic_dma_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_source = auto_icenic_dma_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_address = auto_icenic_dma_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_mask = auto_icenic_dma_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_a_ready = auto_icenic_mmio_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_valid = auto_icenic_mmio_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_opcode = auto_icenic_mmio_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_size = auto_icenic_mmio_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_source = auto_icenic_mmio_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_data = auto_icenic_mmio_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign nic_out_valid = nic_out_valid_0; // @[ClockDomain.scala:14:9] assign nic_out_bits_data = nic_out_bits_data_0; // @[ClockDomain.scala:14:9] assign nic_out_bits_keep = nic_out_bits_keep_0; // @[ClockDomain.scala:14:9] assign nic_out_bits_last = nic_out_bits_last_0; // @[ClockDomain.scala:14:9] assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_500 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_244 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_500( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_244 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLUART : input clock : Clock input reset : Reset output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}} inst buffer of TLBuffer_a29d64s12k1z2u connect buffer.clock, clock connect buffer.reset, reset inst intsource of IntSyncCrossingSource_n1x1_60 connect intsource.clock, clock connect intsource.reset, reset wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeOut.rxd invalidate ioNodeOut.txd wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_115 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn connect intsource.auto.in[0], intnodeOut[0] connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect intXingIn, intsource.auto.out connect auto.io_out, ioNodeOut connect controlXingIn, auto.control_xing_in connect auto.int_xing_out, intXingOut inst txm of UARTTx connect txm.clock, clock connect txm.reset, reset inst txq of Queue8_UInt8 connect txq.clock, clock connect txq.reset, reset inst rxm of UARTRx connect rxm.clock, clock connect rxm.reset, reset inst rxq of Queue8_UInt8_1 connect rxq.clock, clock connect rxq.reset, reset regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4) regreset txen : UInt<1>, clock, reset, UInt<1>(0h0) regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0) regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0) regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset parity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errie : UInt<1>, clock, reset, UInt<1>(0h0) regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0) regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1) connect txm.io.en, txen connect txm.io.in, txq.io.deq connect txm.io.div, div connect txm.io.nstop, nstop connect ioNodeOut.txd, txm.io.out connect rxm.io.en, rxen connect rxm.io.in, ioNodeOut.rxd connect rxq.io.enq.valid, rxm.io.out.valid connect rxq.io.enq.bits, rxm.io.out.bits connect rxm.io.div, div node _tx_busy_T = orr(txq.io.count) node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T) node tx_busy = and(_tx_busy_T_1, txen) wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>} connect _ie_WIRE.txwm, UInt<1>(0h0) connect _ie_WIRE.rxwm, UInt<1>(0h0) regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE wire ip : { rxwm : UInt<1>, txwm : UInt<1>} node _ip_txwm_T = lt(txq.io.count, txwm) connect ip.txwm, _ip_txwm_T node _ip_rxwm_T = gt(rxq.io.count, rxwm) connect ip.rxwm, _ip_rxwm_T node _intnodeOut_0_T = and(ip.txwm, ie.txwm) node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm) node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1) connect intnodeOut[0], _intnodeOut_0_T_2 wire quash : UInt<1> node _T = eq(txq.io.enq.ready, UInt<1>(0h0)) node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0)) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[16] wire out_wivalid : UInt<1>[16] wire out_roready : UInt<1>[16] wire out_woready : UInt<1>[16] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 7, 0) node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0)) node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T) connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1 connect txq.io.enq.bits, _out_T_8 node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0)) node _out_T_16 = bits(_out_T_15, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 30, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 30, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 30, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 30, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 30, 8) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<8>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<31>(0h0)) node _out_T_25 = bits(_out_T_24, 30, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 31) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 31) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 31) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 31) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 31, 31) node _out_quash_T = bits(_out_T_26, 0, 0) node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T) connect quash, _out_quash_T_1 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0)) node out_prepend_1 = cat(_T, _out_prepend_T_1) node _out_T_33 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_34 = bits(_out_T_33, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 39, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 39, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 39, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 39, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxq.io.deq.ready, out_f_roready_3 node _out_T_35 = bits(out_front.bits.data, 39, 32) node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0)) node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2) node _out_T_42 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_43 = bits(_out_T_42, 39, 0) node _out_rimask_T_4 = bits(out_frontMask, 62, 40) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 62, 40) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 62, 40) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 62, 40) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_44 = bits(out_front.bits.data, 62, 40) node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_51 = or(out_prepend_3, UInt<63>(0h0)) node _out_T_52 = bits(_out_T_51, 62, 0) node _out_rimask_T_5 = bits(out_frontMask, 63, 63) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 63, 63) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 63, 63) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 63, 63) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_53 = bits(out_front.bits.data, 63, 63) node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0)) node out_prepend_4 = cat(_T_1, _out_prepend_T_4) node _out_T_60 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_61 = bits(_out_T_60, 63, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_62 = bits(out_front.bits.data, 0, 0) when out_f_woready_6 : connect txen, _out_T_62 node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_69 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_71 = or(txen, UInt<1>(0h0)) node _out_T_72 = bits(_out_T_71, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 1, 1) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 1, 1) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 1, 1) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 1, 1) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_73 = bits(out_front.bits.data, 1, 1) when out_f_woready_7 : connect nstop, _out_T_73 node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_80 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0)) node out_prepend_5 = cat(nstop, _out_prepend_T_5) node _out_T_82 = or(out_prepend_5, UInt<2>(0h0)) node _out_T_83 = bits(_out_T_82, 1, 0) node _out_rimask_T_8 = bits(out_frontMask, 19, 16) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 19, 16) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 19, 16) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 19, 16) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_84 = bits(out_front.bits.data, 19, 16) when out_f_woready_8 : connect txwm, _out_T_84 node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0)) node out_prepend_6 = cat(txwm, _out_prepend_T_6) node _out_T_93 = or(out_prepend_6, UInt<20>(0h0)) node _out_T_94 = bits(_out_T_93, 19, 0) node _out_rimask_T_9 = bits(out_frontMask, 32, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 32, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 32, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 32, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 32, 32) when out_f_woready_9 : connect rxen, _out_T_95 node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0)) node out_prepend_7 = cat(rxen, _out_prepend_T_7) node _out_T_104 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_105 = bits(_out_T_104, 32, 0) node _out_rimask_T_10 = bits(out_frontMask, 51, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 51, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 51, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 51, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_106 = bits(out_front.bits.data, 51, 48) when out_f_woready_10 : connect rxwm, _out_T_106 node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_113 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_114 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0)) node out_prepend_8 = cat(rxwm, _out_prepend_T_8) node _out_T_115 = or(out_prepend_8, UInt<52>(0h0)) node _out_T_116 = bits(_out_T_115, 51, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_117 = bits(out_front.bits.data, 0, 0) when out_f_woready_11 : connect ie.txwm, _out_T_117 node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_126 = or(ie.txwm, UInt<1>(0h0)) node _out_T_127 = bits(_out_T_126, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_128 = bits(out_front.bits.data, 1, 1) when out_f_woready_12 : connect ie.rxwm, _out_T_128 node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_135 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_136 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0)) node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9) node _out_T_137 = or(out_prepend_9, UInt<2>(0h0)) node _out_T_138 = bits(_out_T_137, 1, 0) node _out_rimask_T_13 = bits(out_frontMask, 32, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 32, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 32, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 32, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_139 = bits(out_front.bits.data, 32, 32) node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_144 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_145 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0)) node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10) node _out_T_146 = or(out_prepend_10, UInt<33>(0h0)) node _out_T_147 = bits(_out_T_146, 32, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 33) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 33) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 33) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 33) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_148 = bits(out_front.bits.data, 33, 33) node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_153 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_154 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0)) node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11) node _out_T_155 = or(out_prepend_11, UInt<34>(0h0)) node _out_T_156 = bits(_out_T_155, 33, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 0) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 0) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 0) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 0) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_157 = bits(out_front.bits.data, 15, 0) when out_f_woready_15 : connect div, _out_T_157 node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_164 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_165 = eq(out_womask_15, UInt<1>(0h0)) node _out_T_166 = or(div, UInt<16>(0h0)) node _out_T_167 = bits(_out_T_166, 15, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_7 connect out_rivalid[9], _out_rifireMux_T_7 connect out_rivalid[8], _out_rifireMux_T_7 connect out_rivalid[7], _out_rifireMux_T_7 connect out_rivalid[6], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_11 connect out_rivalid[13], _out_rifireMux_T_11 connect out_rivalid[12], _out_rifireMux_T_11 connect out_rivalid[11], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_8 connect out_wivalid[9], _out_wifireMux_T_8 connect out_wivalid[8], _out_wifireMux_T_8 connect out_wivalid[7], _out_wifireMux_T_8 connect out_wivalid[6], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_12 connect out_wivalid[13], _out_wifireMux_T_12 connect out_wivalid[12], _out_wifireMux_T_12 connect out_wivalid[11], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_7 connect out_roready[9], _out_rofireMux_T_7 connect out_roready[8], _out_rofireMux_T_7 connect out_roready[7], _out_rofireMux_T_7 connect out_roready[6], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_11 connect out_roready[13], _out_rofireMux_T_11 connect out_roready[12], _out_rofireMux_T_11 connect out_roready[11], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_8 connect out_woready[9], _out_wofireMux_T_8 connect out_woready[8], _out_wofireMux_T_8 connect out_woready[7], _out_wofireMux_T_8 connect out_woready[6], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_12 connect out_woready[13], _out_wofireMux_T_12 connect out_woready[12], _out_wofireMux_T_12 connect out_woready[11], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_61 connect _out_out_bits_data_WIRE_1[1], _out_T_116 connect _out_out_bits_data_WIRE_1[2], _out_T_156 connect _out_out_bits_data_WIRE_1[3], _out_T_167 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_woready_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] wire out_backSel_0; // @[RegisterRouter.scala:87:24] wire quash; // @[RegisterRouter.scala:87:24] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] reg [15:0] div; // @[UART.scala:135:20] reg txen; // @[UART.scala:141:21] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire ip_txwm = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] wire ip_rxwm = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] wire in_bits_read = auto_control_xing_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_7 = auto_control_xing_in_a_bits_address[11:5] == 7'h0; // @[RegisterRouter.scala:75:19, :87:24] assign quash = out_woready_2 & auto_control_xing_in_a_bits_mask[3] & auto_control_xing_in_a_bits_data[31]; // @[RegisterRouter.scala:87:24] assign out_backSel_0 = auto_control_xing_in_a_bits_address[4:3] == 2'h0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = auto_control_xing_in_a_valid & auto_control_xing_in_d_ready; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_2 = _out_wofireMux_T_2 & out_backSel_0 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_9 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h1 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_12 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h2 & _out_T_7; // @[RegisterRouter.scala:87:24] wire [3:0][63:0] _GEN = {{{48'h0, div}}, {{30'h0, ip_rxwm, ip_txwm, 30'h0, ie_rxwm, ie_txwm}}, {{12'h0, rxwm, 15'h0, rxen, 12'h0, txwm, 14'h0, nstop, txen}}, {{~_rxq_io_deq_valid, 23'h0, _rxq_io_deq_bits, ~_txq_io_enq_ready, 31'h0}}}; // @[MuxLiteral.scala:49:{10,48}] wire [2:0] controlXingIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:127:25, :141:21] rxen <= 1'h0; // @[UART.scala:127:25, :142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:127:25, :151:22] ie_rxwm <= 1'h0; // @[UART.scala:127:25, :186:19] ie_txwm <= 1'h0; // @[UART.scala:127:25, :186:19] end else begin // @[UART.scala:127:25] if (_out_wofireMux_T_2 & (&(auto_control_xing_in_a_bits_address[4:3])) & _out_T_7 & (&{{8{auto_control_xing_in_a_bits_mask[1]}}, {8{auto_control_xing_in_a_bits_mask[0]}}})) // @[RegisterRouter.scala:87:24] div <= auto_control_xing_in_a_bits_data[15:0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] txen <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[4]) // @[RegisterRouter.scala:87:24] rxen <= auto_control_xing_in_a_bits_data[32]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[2]) // @[RegisterRouter.scala:87:24] txwm <= auto_control_xing_in_a_bits_data[19:16]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[6]) // @[RegisterRouter.scala:87:24] rxwm <= auto_control_xing_in_a_bits_data[51:48]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] nstop <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_rxwm <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_txwm <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module CLINT : input clock : Clock input reset : Reset output auto : { int_out : UInt<1>[2], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip rtcTick : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_49 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeOut : UInt<1>[2] invalidate intnodeOut[0] invalidate intnodeOut[1] connect nodeIn, auto.in connect auto.int_out, intnodeOut regreset time : UInt<64>, clock, reset, UInt<64>(0h0) when io.rtcTick : node _time_T = add(time, UInt<1>(0h1)) node _time_T_1 = tail(_time_T, 1) connect time, _time_T_1 reg timecmp_0 : UInt<64>, clock regreset ipi_0 : UInt<1>, clock, reset, UInt<1>(0h0) node _intnodeOut_0_T = bits(ipi_0, 0, 0) connect intnodeOut[0], _intnodeOut_0_T node _intnodeOut_1_T = geq(time, timecmp_0) connect intnodeOut[1], _intnodeOut_1_T node pad = or(timecmp_0, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node timecmp_0_lo_lo = cat(newBytes[1], newBytes[0]) node timecmp_0_lo_hi = cat(newBytes[3], newBytes[2]) node timecmp_0_lo = cat(timecmp_0_lo_hi, timecmp_0_lo_lo) node timecmp_0_hi_lo = cat(newBytes[5], newBytes[4]) node timecmp_0_hi_hi = cat(newBytes[7], newBytes[6]) node timecmp_0_hi = cat(timecmp_0_hi_hi, timecmp_0_hi_lo) node _timecmp_0_T = cat(timecmp_0_hi, timecmp_0_lo) connect timecmp_0, _timecmp_0_T node pad_1 = or(time, UInt<64>(0h0)) node _oldBytes_T_8 = bits(pad_1, 7, 0) node _oldBytes_T_9 = bits(pad_1, 15, 8) node _oldBytes_T_10 = bits(pad_1, 23, 16) node _oldBytes_T_11 = bits(pad_1, 31, 24) node _oldBytes_T_12 = bits(pad_1, 39, 32) node _oldBytes_T_13 = bits(pad_1, 47, 40) node _oldBytes_T_14 = bits(pad_1, 55, 48) node _oldBytes_T_15 = bits(pad_1, 63, 56) wire oldBytes_1 : UInt<8>[8] connect oldBytes_1[0], _oldBytes_T_8 connect oldBytes_1[1], _oldBytes_T_9 connect oldBytes_1[2], _oldBytes_T_10 connect oldBytes_1[3], _oldBytes_T_11 connect oldBytes_1[4], _oldBytes_T_12 connect oldBytes_1[5], _oldBytes_T_13 connect oldBytes_1[6], _oldBytes_T_14 connect oldBytes_1[7], _oldBytes_T_15 wire newBytes_1 : UInt<8>[8] connect newBytes_1, oldBytes_1 wire _valids_WIRE_1 : UInt<1>[8] connect _valids_WIRE_1[0], UInt<1>(0h0) connect _valids_WIRE_1[1], UInt<1>(0h0) connect _valids_WIRE_1[2], UInt<1>(0h0) connect _valids_WIRE_1[3], UInt<1>(0h0) connect _valids_WIRE_1[4], UInt<1>(0h0) connect _valids_WIRE_1[5], UInt<1>(0h0) connect _valids_WIRE_1[6], UInt<1>(0h0) connect _valids_WIRE_1[7], UInt<1>(0h0) wire valids_1 : UInt<1>[8] connect valids_1, _valids_WIRE_1 node _T_7 = or(valids_1[0], valids_1[1]) node _T_8 = or(_T_7, valids_1[2]) node _T_9 = or(_T_8, valids_1[3]) node _T_10 = or(_T_9, valids_1[4]) node _T_11 = or(_T_10, valids_1[5]) node _T_12 = or(_T_11, valids_1[6]) node _T_13 = or(_T_12, valids_1[7]) when _T_13 : node time_lo_lo = cat(newBytes_1[1], newBytes_1[0]) node time_lo_hi = cat(newBytes_1[3], newBytes_1[2]) node time_lo = cat(time_lo_hi, time_lo_lo) node time_hi_lo = cat(newBytes_1[5], newBytes_1[4]) node time_hi_hi = cat(newBytes_1[7], newBytes_1[6]) node time_hi = cat(time_hi_hi, time_hi_lo) node _time_T_2 = cat(time_hi, time_lo) connect time, _time_T_2 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<13>(0h1800)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<13>(0h0)) node _out_T_1 = eq(out_bindex, UInt<13>(0h0)) node _out_T_2 = eq(out_findex, UInt<13>(0h7ff)) node _out_T_3 = eq(out_bindex, UInt<13>(0h7ff)) node _out_T_4 = eq(out_findex, UInt<13>(0h0)) node _out_T_5 = eq(out_bindex, UInt<13>(0h0)) wire out_rivalid : UInt<1>[18] wire out_wivalid : UInt<1>[18] wire out_roready : UInt<1>[18] wire out_woready : UInt<1>[18] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_front.bits.data, 0, 0) when out_f_woready : connect ipi_0, _out_T_6 node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(ipi_0, UInt<1>(0h0)) node _out_T_16 = bits(_out_T_15, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 31, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 31, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 31, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 31, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 31, 1) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<1>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<32>(0h0)) node _out_T_25 = bits(_out_T_24, 31, 0) node _out_rimask_T_2 = bits(out_frontMask, 7, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 7, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 7, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 7, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 7, 0) connect valids_1[0], out_f_woready_2 when out_f_woready_2 : connect newBytes_1[0], _out_T_26 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_35 = or(oldBytes_1[0], UInt<8>(0h0)) node _out_T_36 = bits(_out_T_35, 7, 0) node _out_rimask_T_3 = bits(out_frontMask, 15, 8) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 15, 8) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 15, 8) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 15, 8) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_37 = bits(out_front.bits.data, 15, 8) connect valids_1[1], out_f_woready_3 when out_f_woready_3 : connect newBytes_1[1], _out_T_37 node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_40 = and(out_f_wivalid_3, UInt<1>(0h1)) node _out_T_41 = and(UInt<1>(0h1), out_f_woready_3) node _out_T_42 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_43 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_44 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_45 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_36, UInt<8>(0h0)) node out_prepend_1 = cat(oldBytes_1[1], _out_prepend_T_1) node _out_T_46 = or(out_prepend_1, UInt<16>(0h0)) node _out_T_47 = bits(_out_T_46, 15, 0) node _out_rimask_T_4 = bits(out_frontMask, 23, 16) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 23, 16) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 23, 16) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 23, 16) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_48 = bits(out_front.bits.data, 23, 16) connect valids_1[2], out_f_woready_4 when out_f_woready_4 : connect newBytes_1[2], _out_T_48 node _out_T_49 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_50 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_51 = and(out_f_wivalid_4, UInt<1>(0h1)) node _out_T_52 = and(UInt<1>(0h1), out_f_woready_4) node _out_T_53 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_54 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_55 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_56 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_47, UInt<16>(0h0)) node out_prepend_2 = cat(oldBytes_1[2], _out_prepend_T_2) node _out_T_57 = or(out_prepend_2, UInt<24>(0h0)) node _out_T_58 = bits(_out_T_57, 23, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 24) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 24) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 24) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 24) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_59 = bits(out_front.bits.data, 31, 24) connect valids_1[3], out_f_woready_5 when out_f_woready_5 : connect newBytes_1[3], _out_T_59 node _out_T_60 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_61 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_62 = and(out_f_wivalid_5, UInt<1>(0h1)) node _out_T_63 = and(UInt<1>(0h1), out_f_woready_5) node _out_T_64 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_65 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_66 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_67 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_58, UInt<24>(0h0)) node out_prepend_3 = cat(oldBytes_1[3], _out_prepend_T_3) node _out_T_68 = or(out_prepend_3, UInt<32>(0h0)) node _out_T_69 = bits(_out_T_68, 31, 0) node _out_rimask_T_6 = bits(out_frontMask, 39, 32) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 39, 32) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 39, 32) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 39, 32) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_70 = bits(out_front.bits.data, 39, 32) connect valids_1[4], out_f_woready_6 when out_f_woready_6 : connect newBytes_1[4], _out_T_70 node _out_T_71 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_72 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_73 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_74 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_75 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_76 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_77 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_78 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_69, UInt<32>(0h0)) node out_prepend_4 = cat(oldBytes_1[4], _out_prepend_T_4) node _out_T_79 = or(out_prepend_4, UInt<40>(0h0)) node _out_T_80 = bits(_out_T_79, 39, 0) node _out_rimask_T_7 = bits(out_frontMask, 47, 40) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 47, 40) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 47, 40) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 47, 40) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_81 = bits(out_front.bits.data, 47, 40) connect valids_1[5], out_f_woready_7 when out_f_woready_7 : connect newBytes_1[5], _out_T_81 node _out_T_82 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_83 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_84 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_85 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_86 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_87 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_88 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_89 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_80, UInt<40>(0h0)) node out_prepend_5 = cat(oldBytes_1[5], _out_prepend_T_5) node _out_T_90 = or(out_prepend_5, UInt<48>(0h0)) node _out_T_91 = bits(_out_T_90, 47, 0) node _out_rimask_T_8 = bits(out_frontMask, 55, 48) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 55, 48) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 55, 48) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 55, 48) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_92 = bits(out_front.bits.data, 55, 48) connect valids_1[6], out_f_woready_8 when out_f_woready_8 : connect newBytes_1[6], _out_T_92 node _out_T_93 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_94 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_95 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_96 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_97 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_98 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_99 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_100 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_91, UInt<48>(0h0)) node out_prepend_6 = cat(oldBytes_1[6], _out_prepend_T_6) node _out_T_101 = or(out_prepend_6, UInt<56>(0h0)) node _out_T_102 = bits(_out_T_101, 55, 0) node _out_rimask_T_9 = bits(out_frontMask, 63, 56) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 63, 56) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 63, 56) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 63, 56) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_103 = bits(out_front.bits.data, 63, 56) connect valids_1[7], out_f_woready_9 when out_f_woready_9 : connect newBytes_1[7], _out_T_103 node _out_T_104 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_105 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_106 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_107 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_108 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_109 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_110 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_111 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_102, UInt<56>(0h0)) node out_prepend_7 = cat(oldBytes_1[7], _out_prepend_T_7) node _out_T_112 = or(out_prepend_7, UInt<64>(0h0)) node _out_T_113 = bits(_out_T_112, 63, 0) node _out_rimask_T_10 = bits(out_frontMask, 7, 0) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 7, 0) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 7, 0) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 7, 0) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_114 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready_10 when out_f_woready_10 : connect newBytes[0], _out_T_114 node _out_T_115 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_116 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_117 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_118 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_119 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_120 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_121 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_122 = eq(out_womask_10, UInt<1>(0h0)) node _out_T_123 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_124 = bits(_out_T_123, 7, 0) node _out_rimask_T_11 = bits(out_frontMask, 15, 8) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 15, 8) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 15, 8) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 15, 8) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_125 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_11 when out_f_woready_11 : connect newBytes[1], _out_T_125 node _out_T_126 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_127 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_128 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_129 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_130 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_131 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_132 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_133 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_124, UInt<8>(0h0)) node out_prepend_8 = cat(oldBytes[1], _out_prepend_T_8) node _out_T_134 = or(out_prepend_8, UInt<16>(0h0)) node _out_T_135 = bits(_out_T_134, 15, 0) node _out_rimask_T_12 = bits(out_frontMask, 23, 16) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 23, 16) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 23, 16) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 23, 16) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_136 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_12 when out_f_woready_12 : connect newBytes[2], _out_T_136 node _out_T_137 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_138 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_139 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_140 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_141 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_142 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_143 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_144 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_135, UInt<16>(0h0)) node out_prepend_9 = cat(oldBytes[2], _out_prepend_T_9) node _out_T_145 = or(out_prepend_9, UInt<24>(0h0)) node _out_T_146 = bits(_out_T_145, 23, 0) node _out_rimask_T_13 = bits(out_frontMask, 31, 24) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 31, 24) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 31, 24) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 31, 24) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_147 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_13 when out_f_woready_13 : connect newBytes[3], _out_T_147 node _out_T_148 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_149 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_150 = and(out_f_wivalid_13, UInt<1>(0h1)) node _out_T_151 = and(UInt<1>(0h1), out_f_woready_13) node _out_T_152 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_153 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_154 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_155 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_146, UInt<24>(0h0)) node out_prepend_10 = cat(oldBytes[3], _out_prepend_T_10) node _out_T_156 = or(out_prepend_10, UInt<32>(0h0)) node _out_T_157 = bits(_out_T_156, 31, 0) node _out_rimask_T_14 = bits(out_frontMask, 39, 32) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 39, 32) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 39, 32) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 39, 32) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_158 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_14 when out_f_woready_14 : connect newBytes[4], _out_T_158 node _out_T_159 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_160 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_161 = and(out_f_wivalid_14, UInt<1>(0h1)) node _out_T_162 = and(UInt<1>(0h1), out_f_woready_14) node _out_T_163 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_164 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_165 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_166 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_157, UInt<32>(0h0)) node out_prepend_11 = cat(oldBytes[4], _out_prepend_T_11) node _out_T_167 = or(out_prepend_11, UInt<40>(0h0)) node _out_T_168 = bits(_out_T_167, 39, 0) node _out_rimask_T_15 = bits(out_frontMask, 47, 40) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 47, 40) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 47, 40) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 47, 40) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_169 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_15 when out_f_woready_15 : connect newBytes[5], _out_T_169 node _out_T_170 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_171 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_172 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_173 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_174 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_175 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_176 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_177 = eq(out_womask_15, UInt<1>(0h0)) node _out_prepend_T_12 = or(_out_T_168, UInt<40>(0h0)) node out_prepend_12 = cat(oldBytes[5], _out_prepend_T_12) node _out_T_178 = or(out_prepend_12, UInt<48>(0h0)) node _out_T_179 = bits(_out_T_178, 47, 0) node _out_rimask_T_16 = bits(out_frontMask, 55, 48) node out_rimask_16 = orr(_out_rimask_T_16) node _out_wimask_T_16 = bits(out_frontMask, 55, 48) node out_wimask_16 = andr(_out_wimask_T_16) node _out_romask_T_16 = bits(out_backMask, 55, 48) node out_romask_16 = orr(_out_romask_T_16) node _out_womask_T_16 = bits(out_backMask, 55, 48) node out_womask_16 = andr(_out_womask_T_16) node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) node out_f_roready_16 = and(out_roready[16], out_romask_16) node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) node out_f_woready_16 = and(out_woready[16], out_womask_16) node _out_T_180 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_16 when out_f_woready_16 : connect newBytes[6], _out_T_180 node _out_T_181 = and(out_f_rivalid_16, UInt<1>(0h1)) node _out_T_182 = and(UInt<1>(0h1), out_f_roready_16) node _out_T_183 = and(out_f_wivalid_16, UInt<1>(0h1)) node _out_T_184 = and(UInt<1>(0h1), out_f_woready_16) node _out_T_185 = eq(out_rimask_16, UInt<1>(0h0)) node _out_T_186 = eq(out_wimask_16, UInt<1>(0h0)) node _out_T_187 = eq(out_romask_16, UInt<1>(0h0)) node _out_T_188 = eq(out_womask_16, UInt<1>(0h0)) node _out_prepend_T_13 = or(_out_T_179, UInt<48>(0h0)) node out_prepend_13 = cat(oldBytes[6], _out_prepend_T_13) node _out_T_189 = or(out_prepend_13, UInt<56>(0h0)) node _out_T_190 = bits(_out_T_189, 55, 0) node _out_rimask_T_17 = bits(out_frontMask, 63, 56) node out_rimask_17 = orr(_out_rimask_T_17) node _out_wimask_T_17 = bits(out_frontMask, 63, 56) node out_wimask_17 = andr(_out_wimask_T_17) node _out_romask_T_17 = bits(out_backMask, 63, 56) node out_romask_17 = orr(_out_romask_T_17) node _out_womask_T_17 = bits(out_backMask, 63, 56) node out_womask_17 = andr(_out_womask_T_17) node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) node out_f_roready_17 = and(out_roready[17], out_romask_17) node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) node out_f_woready_17 = and(out_woready[17], out_womask_17) node _out_T_191 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_17 when out_f_woready_17 : connect newBytes[7], _out_T_191 node _out_T_192 = and(out_f_rivalid_17, UInt<1>(0h1)) node _out_T_193 = and(UInt<1>(0h1), out_f_roready_17) node _out_T_194 = and(out_f_wivalid_17, UInt<1>(0h1)) node _out_T_195 = and(UInt<1>(0h1), out_f_woready_17) node _out_T_196 = eq(out_rimask_17, UInt<1>(0h0)) node _out_T_197 = eq(out_wimask_17, UInt<1>(0h0)) node _out_T_198 = eq(out_romask_17, UInt<1>(0h0)) node _out_T_199 = eq(out_womask_17, UInt<1>(0h0)) node _out_prepend_T_14 = or(_out_T_190, UInt<56>(0h0)) node out_prepend_14 = cat(oldBytes[7], _out_prepend_T_14) node _out_T_200 = or(out_prepend_14, UInt<64>(0h0)) node _out_T_201 = bits(_out_T_200, 63, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node out_iindex = cat(_out_iindex_T_12, _out_iindex_T_11) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_front.bits.index, 12, 12) node out_oindex = cat(_out_oindex_T_12, _out_oindex_T_11) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[17], _out_rifireMux_T_7 connect out_rivalid[16], _out_rifireMux_T_7 connect out_rivalid[15], _out_rifireMux_T_7 connect out_rivalid[14], _out_rifireMux_T_7 connect out_rivalid[13], _out_rifireMux_T_7 connect out_rivalid[12], _out_rifireMux_T_7 connect out_rivalid[11], _out_rifireMux_T_7 connect out_rivalid[10], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[9], _out_rifireMux_T_11 connect out_rivalid[8], _out_rifireMux_T_11 connect out_rivalid[7], _out_rifireMux_T_11 connect out_rivalid[6], _out_rifireMux_T_11 connect out_rivalid[5], _out_rifireMux_T_11 connect out_rivalid[4], _out_rifireMux_T_11 connect out_rivalid[3], _out_rifireMux_T_11 connect out_rivalid[2], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[17], _out_wifireMux_T_8 connect out_wivalid[16], _out_wifireMux_T_8 connect out_wivalid[15], _out_wifireMux_T_8 connect out_wivalid[14], _out_wifireMux_T_8 connect out_wivalid[13], _out_wifireMux_T_8 connect out_wivalid[12], _out_wifireMux_T_8 connect out_wivalid[11], _out_wifireMux_T_8 connect out_wivalid[10], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[9], _out_wifireMux_T_12 connect out_wivalid[8], _out_wifireMux_T_12 connect out_wivalid[7], _out_wifireMux_T_12 connect out_wivalid[6], _out_wifireMux_T_12 connect out_wivalid[5], _out_wifireMux_T_12 connect out_wivalid[4], _out_wifireMux_T_12 connect out_wivalid[3], _out_wifireMux_T_12 connect out_wivalid[2], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[17], _out_rofireMux_T_7 connect out_roready[16], _out_rofireMux_T_7 connect out_roready[15], _out_rofireMux_T_7 connect out_roready[14], _out_rofireMux_T_7 connect out_roready[13], _out_rofireMux_T_7 connect out_roready[12], _out_rofireMux_T_7 connect out_roready[11], _out_rofireMux_T_7 connect out_roready[10], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[9], _out_rofireMux_T_11 connect out_roready[8], _out_rofireMux_T_11 connect out_roready[7], _out_rofireMux_T_11 connect out_roready[6], _out_rofireMux_T_11 connect out_roready[5], _out_rofireMux_T_11 connect out_roready[4], _out_rofireMux_T_11 connect out_roready[3], _out_rofireMux_T_11 connect out_roready[2], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[17], _out_wofireMux_T_8 connect out_woready[16], _out_wofireMux_T_8 connect out_woready[15], _out_wofireMux_T_8 connect out_woready[14], _out_wofireMux_T_8 connect out_woready[13], _out_wofireMux_T_8 connect out_woready[12], _out_wofireMux_T_8 connect out_woready[11], _out_wofireMux_T_8 connect out_woready[10], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[9], _out_wofireMux_T_12 connect out_woready[8], _out_wofireMux_T_12 connect out_woready[7], _out_wofireMux_T_12 connect out_woready[6], _out_wofireMux_T_12 connect out_woready[5], _out_wofireMux_T_12 connect out_woready[4], _out_wofireMux_T_12 connect out_woready[3], _out_wofireMux_T_12 connect out_woready[2], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], UInt<1>(0h1) node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_25 connect _out_out_bits_data_WIRE_1[1], _out_T_201 connect _out_out_bits_data_WIRE_1[2], _out_T_113 connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0) node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [11:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = \|_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = \|_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 \| valids_1_1 \| valids_1_2 \| valids_1_3 \| valids_1_4 \| valids_1_5 \| valids_1_6 \| valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_49 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_4 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 9, 6) node req_tag = shr(req.addr, 10) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_4 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock reg refill_ctr : UInt<3>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) invalidate io.meta_write.bits.data.tag invalidate io.meta_write.bits.data.coh.state invalidate io.meta_write.bits.tag invalidate io.meta_write.bits.way_en invalidate io.meta_write.bits.idx connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) invalidate io.mem_acquire.bits.corrupt invalidate io.mem_acquire.bits.data invalidate io.mem_acquire.bits.mask invalidate io.mem_acquire.bits.address invalidate io.mem_acquire.bits.source invalidate io.mem_acquire.bits.size invalidate io.mem_acquire.bits.param invalidate io.mem_acquire.bits.opcode connect io.refill.valid, UInt<1>(0h0) invalidate io.refill.bits.data invalidate io.refill.bits.wmask invalidate io.refill.bits.addr invalidate io.refill.bits.way_en connect io.replay.valid, UInt<1>(0h0) invalidate io.replay.bits.sdq_id invalidate io.replay.bits.way_en invalidate io.replay.bits.old_meta.tag invalidate io.replay.bits.old_meta.coh.state invalidate io.replay.bits.tag_match invalidate io.replay.bits.is_hella invalidate io.replay.bits.data invalidate io.replay.bits.addr invalidate io.replay.bits.uop.debug_tsrc invalidate io.replay.bits.uop.debug_fsrc invalidate io.replay.bits.uop.bp_xcpt_if invalidate io.replay.bits.uop.bp_debug_if invalidate io.replay.bits.uop.xcpt_ma_if invalidate io.replay.bits.uop.xcpt_ae_if invalidate io.replay.bits.uop.xcpt_pf_if invalidate io.replay.bits.uop.fp_single invalidate io.replay.bits.uop.fp_val invalidate io.replay.bits.uop.frs3_en invalidate io.replay.bits.uop.lrs2_rtype invalidate io.replay.bits.uop.lrs1_rtype invalidate io.replay.bits.uop.dst_rtype invalidate io.replay.bits.uop.ldst_val invalidate io.replay.bits.uop.lrs3 invalidate io.replay.bits.uop.lrs2 invalidate io.replay.bits.uop.lrs1 invalidate io.replay.bits.uop.ldst invalidate io.replay.bits.uop.ldst_is_rs1 invalidate io.replay.bits.uop.flush_on_commit invalidate io.replay.bits.uop.is_unique invalidate io.replay.bits.uop.is_sys_pc2epc invalidate io.replay.bits.uop.uses_stq invalidate io.replay.bits.uop.uses_ldq invalidate io.replay.bits.uop.is_amo invalidate io.replay.bits.uop.is_fencei invalidate io.replay.bits.uop.is_fence invalidate io.replay.bits.uop.mem_signed invalidate io.replay.bits.uop.mem_size invalidate io.replay.bits.uop.mem_cmd invalidate io.replay.bits.uop.bypassable invalidate io.replay.bits.uop.exc_cause invalidate io.replay.bits.uop.exception invalidate io.replay.bits.uop.stale_pdst invalidate io.replay.bits.uop.ppred_busy invalidate io.replay.bits.uop.prs3_busy invalidate io.replay.bits.uop.prs2_busy invalidate io.replay.bits.uop.prs1_busy invalidate io.replay.bits.uop.ppred invalidate io.replay.bits.uop.prs3 invalidate io.replay.bits.uop.prs2 invalidate io.replay.bits.uop.prs1 invalidate io.replay.bits.uop.pdst invalidate io.replay.bits.uop.rxq_idx invalidate io.replay.bits.uop.stq_idx invalidate io.replay.bits.uop.ldq_idx invalidate io.replay.bits.uop.rob_idx invalidate io.replay.bits.uop.csr_addr invalidate io.replay.bits.uop.imm_packed invalidate io.replay.bits.uop.taken invalidate io.replay.bits.uop.pc_lob invalidate io.replay.bits.uop.edge_inst invalidate io.replay.bits.uop.ftq_idx invalidate io.replay.bits.uop.br_tag invalidate io.replay.bits.uop.br_mask invalidate io.replay.bits.uop.is_sfb invalidate io.replay.bits.uop.is_jal invalidate io.replay.bits.uop.is_jalr invalidate io.replay.bits.uop.is_br invalidate io.replay.bits.uop.iw_p2_poisoned invalidate io.replay.bits.uop.iw_p1_poisoned invalidate io.replay.bits.uop.iw_state invalidate io.replay.bits.uop.ctrl.is_std invalidate io.replay.bits.uop.ctrl.is_sta invalidate io.replay.bits.uop.ctrl.is_load invalidate io.replay.bits.uop.ctrl.csr_cmd invalidate io.replay.bits.uop.ctrl.fcn_dw invalidate io.replay.bits.uop.ctrl.op_fcn invalidate io.replay.bits.uop.ctrl.imm_sel invalidate io.replay.bits.uop.ctrl.op2_sel invalidate io.replay.bits.uop.ctrl.op1_sel invalidate io.replay.bits.uop.ctrl.br_type invalidate io.replay.bits.uop.fu_code invalidate io.replay.bits.uop.iq_type invalidate io.replay.bits.uop.debug_pc invalidate io.replay.bits.uop.is_rvc invalidate io.replay.bits.uop.debug_inst invalidate io.replay.bits.uop.inst invalidate io.replay.bits.uop.uopc connect io.wb_req.valid, UInt<1>(0h0) invalidate io.wb_req.bits.voluntary invalidate io.wb_req.bits.way_en invalidate io.wb_req.bits.param invalidate io.wb_req.bits.source invalidate io.wb_req.bits.idx invalidate io.wb_req.bits.tag connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.is_hella invalidate io.resp.bits.data invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) invalidate io.meta_read.bits.tag invalidate io.meta_read.bits.way_en invalidate io.meta_read.bits.idx connect io.mem_finish.valid, UInt<1>(0h0) invalidate io.mem_finish.bits.sink connect io.lb_write.valid, UInt<1>(0h0) invalidate io.lb_write.bits.data invalidate io.lb_write.bits.offset invalidate io.lb_write.bits.id connect io.lb_read.valid, UInt<1>(0h0) invalidate io.lb_read.bits.offset invalidate io.lb_read.bits.id connect io.mem_grant.ready, UInt<1>(0h0) node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5) node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7) node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9) node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.mem_grant.ready, io.lb_write.ready connect io.lb_write.valid, io.mem_grant.valid connect io.lb_write.bits.id, io.id node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<3>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready) node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1 node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load) connect io.lb_read.valid, _io_lb_read_valid_T connect io.lb_read.bits.id, io.id node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3) connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid) node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T) node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load) connect io.resp.valid, _io_resp_valid_T_2 connect io.resp.bits.uop, rpq.io.deq.bits.uop node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.valid, UInt<1>(0h1) connect io.lb_read.bits.id, io.id connect io.lb_read.bits.offset, refill_ctr node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid) connect io.refill.valid, _io_refill_valid_T node _io_refill_bits_addr_T = shl(refill_ctr, 3) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<1>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<3>(0h7)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid connect io.mem_finish.bits, grantack.bits node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1	module BoomMSHR_4( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [2:0] io_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h4; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h4; // @[mshrs.scala:36:7] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h4; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26] wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [27:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata \| io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 \| _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_229 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_229( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_24 = shr(io.in.a.bits.source, 3) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h10000))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h10000000))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h10000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h10000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_102 = shr(io.in.a.bits.source, 3) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h10000))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h10000000))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h10000000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_184 = shr(io.in.a.bits.source, 3) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h10000000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_237 = shr(io.in.a.bits.source, 3) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h10000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h10000000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_284 = shr(io.in.a.bits.source, 3) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_333 = shr(io.in.a.bits.source, 3) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h10000000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_377 = shr(io.in.a.bits.source, 3) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h10000))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h10000000))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_421 = shr(io.in.a.bits.source, 3) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h10000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h10000000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 3) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_602 = shr(io.in.b.bits.source, 3) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h10000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h10000000))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h10000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h10000000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h10000000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h10000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h10000000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h10000))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h10000000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 3) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_906 = shr(io.in.c.bits.source, 3) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_966 = shr(io.in.c.bits.source, 3) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h10000))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h10000000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h10000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h10000000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1039 = shr(io.in.c.bits.source, 3) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h10000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h10000000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h10000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h10000000))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes : UInt<20>, clock, reset, UInt<20>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<5> connect a_set, UInt<5>(0h0) wire a_set_wo_ready : UInt<5> connect a_set_wo_ready, UInt<5>(0h0) wire a_opcodes_set : UInt<20> connect a_opcodes_set, UInt<20>(0h0) wire a_sizes_set : UInt<20> connect a_sizes_set, UInt<20>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<5> connect d_clr, UInt<5>(0h0) wire d_clr_wo_ready : UInt<5> connect d_clr_wo_ready, UInt<5>(0h0) wire d_opcodes_clr : UInt<20> connect d_opcodes_clr, UInt<20>(0h0) wire d_sizes_clr : UInt<20> connect d_sizes_clr, UInt<20>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_90 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes_1 : UInt<20>, clock, reset, UInt<20>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<5> connect c_set, UInt<5>(0h0) wire c_set_wo_ready : UInt<5> connect c_set_wo_ready, UInt<5>(0h0) wire c_opcodes_set : UInt<20> connect c_opcodes_set, UInt<20>(0h0) wire c_sizes_set : UInt<20> connect c_sizes_set, UInt<20>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<5> connect d_clr_1, UInt<5>(0h0) wire d_clr_wo_ready_1 : UInt<5> connect d_clr_wo_ready_1, UInt<5>(0h0) wire d_opcodes_clr_1 : UInt<20> connect d_opcodes_clr_1, UInt<20>(0h0) wire d_sizes_clr_1 : UInt<20> connect d_sizes_clr_1, UInt<20>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_91 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [19:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [7:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_Debug : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_28 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a12d64s9k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full \|\| !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full \|\| in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<9>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<9>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLFragmenter_Debug( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [8:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [11:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [8:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [12:0] _find_T_2 = 13'h0; // @[Parameters.scala:137:46] wire [12:0] _find_T_3 = 13'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [8:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [11:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [12:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [12:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [8:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [8:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [12:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData \| _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] \| dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = \|dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} \| dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = \|dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 \| dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[12:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [11:0] _find_T; // @[Parameters.scala:137:31] wire [12:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(\|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = \|aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T \| _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] \| aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[11:6], _repeater_io_deq_bits_address[5:0] \| _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [9:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_127 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_127( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s7k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s7k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s7k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s7k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_8 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [6:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [6:0] in_xbar__addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar__requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar__requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] in_xbar_requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56] wire [6:0] in_xbar__beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar__beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar__portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar_portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] in_xbar__portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar_portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} \| fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire in_ready; // @[RegisterRouter.scala:73:18] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34] wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52] wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35] bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 \| fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 \| fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 \| fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 \| fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 \| fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 \| fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 \| fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 \| fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 \| fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 \| fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA \| fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB \| fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC \| fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD \| fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE \| fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF \| fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 \| fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 \| fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 \| fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 \| fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 \| fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 \| fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 \| fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 \| fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 \| fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 \| fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A \| fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B \| fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C \| fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D \| fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E \| fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F \| fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 \| fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 \| fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 \| fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 \| fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 \| fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 \| fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 \| fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 \| fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 \| fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 \| fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A \| fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B \| fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C \| fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D \| fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E \| fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F \| fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 \| fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 \| fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 \| fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 \| fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 \| fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 \| fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 \| fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 \| fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 \| fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 \| fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A \| fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B \| fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C \| fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D \| fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E \| fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F \| fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 \| fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_pbus_out_i1_o2_a29d64s7k1z3u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s7k1z3u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] TLBuffer_a29d64s7k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (bus_xingOut_a_ready), .auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (bus_xingOut_d_valid), .auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode), .auto_in_d_bits_param (bus_xingOut_d_bits_param), .auto_in_d_bits_size (bus_xingOut_d_bits_size), .auto_in_d_bits_source (bus_xingOut_d_bits_source), .auto_in_d_bits_sink (bus_xingOut_d_bits_sink), .auto_in_d_bits_denied (bus_xingOut_d_bits_denied), .auto_in_d_bits_data (bus_xingOut_d_bits_data), .auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt), .auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_out_a_valid (in_xbar_auto_anon_in_a_valid), .auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param), .auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size), .auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source), .auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (in_xbar_auto_anon_in_d_ready), .auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9] .auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9] .auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_a_valid (nodeIn_a_valid), .auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param), .auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size), .auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source), .auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address), .auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask), .auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data), .auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_fragmenter_anon_out_d_ready (nodeIn_d_ready), .auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0), .auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0), .auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0), .auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0), .auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0), .auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0), .auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0), .auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0), .auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0), .auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0), .auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLMonitor_8 monitor ( // @[Nodes.scala:27:25] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_100 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_100( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_111 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_111( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] next_uop_ppred = 5'h0; // @[issue-slot.scala:103:21] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21] wire _p3_T = 1'h1; // @[issue-slot.scala:171:11] wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module NoC : input clock : Clock input reset : Reset output auto : { } output io : { ingress : { flip `22` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `21` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `20` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `19` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}}, egress : { `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}, flip router_clocks : { clock : Clock, reset : Reset}[13]} inst router_sink_domain of TLSplitACDxBENoC_acd_router_0ClockSinkDomain inst router_sink_domain_1 of TLSplitACDxBENoC_acd_router_1ClockSinkDomain inst router_sink_domain_2 of TLSplitACDxBENoC_acd_router_2ClockSinkDomain inst router_sink_domain_3 of TLSplitACDxBENoC_acd_router_3ClockSinkDomain inst router_sink_domain_4 of TLSplitACDxBENoC_acd_router_4ClockSinkDomain inst router_sink_domain_5 of TLSplitACDxBENoC_acd_router_5ClockSinkDomain inst router_sink_domain_6 of TLSplitACDxBENoC_acd_router_6ClockSinkDomain inst router_sink_domain_7 of TLSplitACDxBENoC_acd_router_7ClockSinkDomain inst router_sink_domain_8 of TLSplitACDxBENoC_acd_router_8ClockSinkDomain inst router_sink_domain_9 of TLSplitACDxBENoC_acd_router_9ClockSinkDomain inst router_sink_domain_10 of TLSplitACDxBENoC_acd_router_10ClockSinkDomain inst router_sink_domain_11 of TLSplitACDxBENoC_acd_router_11ClockSinkDomain inst router_sink_domain_12 of TLSplitACDxBENoC_acd_router_12ClockSinkDomain wire clockSourceNodesOut : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut.reset invalidate clockSourceNodesOut.clock wire clockSourceNodesOut_1 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_1.reset invalidate clockSourceNodesOut_1.clock wire clockSourceNodesOut_2 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_2.reset invalidate clockSourceNodesOut_2.clock wire clockSourceNodesOut_3 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_3.reset invalidate clockSourceNodesOut_3.clock wire clockSourceNodesOut_4 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_4.reset invalidate clockSourceNodesOut_4.clock wire clockSourceNodesOut_5 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_5.reset invalidate clockSourceNodesOut_5.clock wire clockSourceNodesOut_6 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_6.reset invalidate clockSourceNodesOut_6.clock wire clockSourceNodesOut_7 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_7.reset invalidate clockSourceNodesOut_7.clock wire clockSourceNodesOut_8 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_8.reset invalidate clockSourceNodesOut_8.clock wire clockSourceNodesOut_9 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_9.reset invalidate clockSourceNodesOut_9.clock wire clockSourceNodesOut_10 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_10.reset invalidate clockSourceNodesOut_10.clock wire clockSourceNodesOut_11 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_11.reset invalidate clockSourceNodesOut_11.clock wire clockSourceNodesOut_12 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_12.reset invalidate clockSourceNodesOut_12.clock wire ingressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut.flit.bits.egress_id invalidate ingressNodesOut.flit.bits.payload invalidate ingressNodesOut.flit.bits.tail invalidate ingressNodesOut.flit.bits.head invalidate ingressNodesOut.flit.valid invalidate ingressNodesOut.flit.ready wire ingressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_1.flit.bits.egress_id invalidate ingressNodesOut_1.flit.bits.payload invalidate ingressNodesOut_1.flit.bits.tail invalidate ingressNodesOut_1.flit.bits.head invalidate ingressNodesOut_1.flit.valid invalidate ingressNodesOut_1.flit.ready wire ingressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_2.flit.bits.egress_id invalidate ingressNodesOut_2.flit.bits.payload invalidate ingressNodesOut_2.flit.bits.tail invalidate ingressNodesOut_2.flit.bits.head invalidate ingressNodesOut_2.flit.valid invalidate ingressNodesOut_2.flit.ready wire ingressNodesOut_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_3.flit.bits.egress_id invalidate ingressNodesOut_3.flit.bits.payload invalidate ingressNodesOut_3.flit.bits.tail invalidate ingressNodesOut_3.flit.bits.head invalidate ingressNodesOut_3.flit.valid invalidate ingressNodesOut_3.flit.ready wire ingressNodesOut_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_4.flit.bits.egress_id invalidate ingressNodesOut_4.flit.bits.payload invalidate ingressNodesOut_4.flit.bits.tail invalidate ingressNodesOut_4.flit.bits.head invalidate ingressNodesOut_4.flit.valid invalidate ingressNodesOut_4.flit.ready wire ingressNodesOut_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_5.flit.bits.egress_id invalidate ingressNodesOut_5.flit.bits.payload invalidate ingressNodesOut_5.flit.bits.tail invalidate ingressNodesOut_5.flit.bits.head invalidate ingressNodesOut_5.flit.valid invalidate ingressNodesOut_5.flit.ready wire ingressNodesOut_6 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_6.flit.bits.egress_id invalidate ingressNodesOut_6.flit.bits.payload invalidate ingressNodesOut_6.flit.bits.tail invalidate ingressNodesOut_6.flit.bits.head invalidate ingressNodesOut_6.flit.valid invalidate ingressNodesOut_6.flit.ready wire ingressNodesOut_7 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_7.flit.bits.egress_id invalidate ingressNodesOut_7.flit.bits.payload invalidate ingressNodesOut_7.flit.bits.tail invalidate ingressNodesOut_7.flit.bits.head invalidate ingressNodesOut_7.flit.valid invalidate ingressNodesOut_7.flit.ready wire ingressNodesOut_8 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_8.flit.bits.egress_id invalidate ingressNodesOut_8.flit.bits.payload invalidate ingressNodesOut_8.flit.bits.tail invalidate ingressNodesOut_8.flit.bits.head invalidate ingressNodesOut_8.flit.valid invalidate ingressNodesOut_8.flit.ready wire ingressNodesOut_9 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_9.flit.bits.egress_id invalidate ingressNodesOut_9.flit.bits.payload invalidate ingressNodesOut_9.flit.bits.tail invalidate ingressNodesOut_9.flit.bits.head invalidate ingressNodesOut_9.flit.valid invalidate ingressNodesOut_9.flit.ready wire ingressNodesOut_10 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_10.flit.bits.egress_id invalidate ingressNodesOut_10.flit.bits.payload invalidate ingressNodesOut_10.flit.bits.tail invalidate ingressNodesOut_10.flit.bits.head invalidate ingressNodesOut_10.flit.valid invalidate ingressNodesOut_10.flit.ready wire ingressNodesOut_11 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_11.flit.bits.egress_id invalidate ingressNodesOut_11.flit.bits.payload invalidate ingressNodesOut_11.flit.bits.tail invalidate ingressNodesOut_11.flit.bits.head invalidate ingressNodesOut_11.flit.valid invalidate ingressNodesOut_11.flit.ready wire ingressNodesOut_12 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_12.flit.bits.egress_id invalidate ingressNodesOut_12.flit.bits.payload invalidate ingressNodesOut_12.flit.bits.tail invalidate ingressNodesOut_12.flit.bits.head invalidate ingressNodesOut_12.flit.valid invalidate ingressNodesOut_12.flit.ready wire ingressNodesOut_13 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_13.flit.bits.egress_id invalidate ingressNodesOut_13.flit.bits.payload invalidate ingressNodesOut_13.flit.bits.tail invalidate ingressNodesOut_13.flit.bits.head invalidate ingressNodesOut_13.flit.valid invalidate ingressNodesOut_13.flit.ready wire ingressNodesOut_14 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_14.flit.bits.egress_id invalidate ingressNodesOut_14.flit.bits.payload invalidate ingressNodesOut_14.flit.bits.tail invalidate ingressNodesOut_14.flit.bits.head invalidate ingressNodesOut_14.flit.valid invalidate ingressNodesOut_14.flit.ready wire ingressNodesOut_15 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_15.flit.bits.egress_id invalidate ingressNodesOut_15.flit.bits.payload invalidate ingressNodesOut_15.flit.bits.tail invalidate ingressNodesOut_15.flit.bits.head invalidate ingressNodesOut_15.flit.valid invalidate ingressNodesOut_15.flit.ready wire ingressNodesOut_16 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_16.flit.bits.egress_id invalidate ingressNodesOut_16.flit.bits.payload invalidate ingressNodesOut_16.flit.bits.tail invalidate ingressNodesOut_16.flit.bits.head invalidate ingressNodesOut_16.flit.valid invalidate ingressNodesOut_16.flit.ready wire ingressNodesOut_17 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_17.flit.bits.egress_id invalidate ingressNodesOut_17.flit.bits.payload invalidate ingressNodesOut_17.flit.bits.tail invalidate ingressNodesOut_17.flit.bits.head invalidate ingressNodesOut_17.flit.valid invalidate ingressNodesOut_17.flit.ready wire ingressNodesOut_18 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_18.flit.bits.egress_id invalidate ingressNodesOut_18.flit.bits.payload invalidate ingressNodesOut_18.flit.bits.tail invalidate ingressNodesOut_18.flit.bits.head invalidate ingressNodesOut_18.flit.valid invalidate ingressNodesOut_18.flit.ready wire ingressNodesOut_19 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_19.flit.bits.egress_id invalidate ingressNodesOut_19.flit.bits.payload invalidate ingressNodesOut_19.flit.bits.tail invalidate ingressNodesOut_19.flit.bits.head invalidate ingressNodesOut_19.flit.valid invalidate ingressNodesOut_19.flit.ready wire ingressNodesOut_20 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_20.flit.bits.egress_id invalidate ingressNodesOut_20.flit.bits.payload invalidate ingressNodesOut_20.flit.bits.tail invalidate ingressNodesOut_20.flit.bits.head invalidate ingressNodesOut_20.flit.valid invalidate ingressNodesOut_20.flit.ready wire ingressNodesOut_21 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_21.flit.bits.egress_id invalidate ingressNodesOut_21.flit.bits.payload invalidate ingressNodesOut_21.flit.bits.tail invalidate ingressNodesOut_21.flit.bits.head invalidate ingressNodesOut_21.flit.valid invalidate ingressNodesOut_21.flit.ready wire ingressNodesOut_22 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_22.flit.bits.egress_id invalidate ingressNodesOut_22.flit.bits.payload invalidate ingressNodesOut_22.flit.bits.tail invalidate ingressNodesOut_22.flit.bits.head invalidate ingressNodesOut_22.flit.valid invalidate ingressNodesOut_22.flit.ready wire egressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn.flit.bits.ingress_id invalidate egressNodesIn.flit.bits.payload invalidate egressNodesIn.flit.bits.tail invalidate egressNodesIn.flit.bits.head invalidate egressNodesIn.flit.valid invalidate egressNodesIn.flit.ready wire egressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_1.flit.bits.ingress_id invalidate egressNodesIn_1.flit.bits.payload invalidate egressNodesIn_1.flit.bits.tail invalidate egressNodesIn_1.flit.bits.head invalidate egressNodesIn_1.flit.valid invalidate egressNodesIn_1.flit.ready wire egressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_2.flit.bits.ingress_id invalidate egressNodesIn_2.flit.bits.payload invalidate egressNodesIn_2.flit.bits.tail invalidate egressNodesIn_2.flit.bits.head invalidate egressNodesIn_2.flit.valid invalidate egressNodesIn_2.flit.ready wire egressNodesIn_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_3.flit.bits.ingress_id invalidate egressNodesIn_3.flit.bits.payload invalidate egressNodesIn_3.flit.bits.tail invalidate egressNodesIn_3.flit.bits.head invalidate egressNodesIn_3.flit.valid invalidate egressNodesIn_3.flit.ready wire egressNodesIn_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_4.flit.bits.ingress_id invalidate egressNodesIn_4.flit.bits.payload invalidate egressNodesIn_4.flit.bits.tail invalidate egressNodesIn_4.flit.bits.head invalidate egressNodesIn_4.flit.valid invalidate egressNodesIn_4.flit.ready wire egressNodesIn_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_5.flit.bits.ingress_id invalidate egressNodesIn_5.flit.bits.payload invalidate egressNodesIn_5.flit.bits.tail invalidate egressNodesIn_5.flit.bits.head invalidate egressNodesIn_5.flit.valid invalidate egressNodesIn_5.flit.ready wire egressNodesIn_6 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_6.flit.bits.ingress_id invalidate egressNodesIn_6.flit.bits.payload invalidate egressNodesIn_6.flit.bits.tail invalidate egressNodesIn_6.flit.bits.head invalidate egressNodesIn_6.flit.valid invalidate egressNodesIn_6.flit.ready wire egressNodesIn_7 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_7.flit.bits.ingress_id invalidate egressNodesIn_7.flit.bits.payload invalidate egressNodesIn_7.flit.bits.tail invalidate egressNodesIn_7.flit.bits.head invalidate egressNodesIn_7.flit.valid invalidate egressNodesIn_7.flit.ready wire egressNodesIn_8 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_8.flit.bits.ingress_id invalidate egressNodesIn_8.flit.bits.payload invalidate egressNodesIn_8.flit.bits.tail invalidate egressNodesIn_8.flit.bits.head invalidate egressNodesIn_8.flit.valid invalidate egressNodesIn_8.flit.ready wire egressNodesIn_9 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_9.flit.bits.ingress_id invalidate egressNodesIn_9.flit.bits.payload invalidate egressNodesIn_9.flit.bits.tail invalidate egressNodesIn_9.flit.bits.head invalidate egressNodesIn_9.flit.valid invalidate egressNodesIn_9.flit.ready wire egressNodesIn_10 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_10.flit.bits.ingress_id invalidate egressNodesIn_10.flit.bits.payload invalidate egressNodesIn_10.flit.bits.tail invalidate egressNodesIn_10.flit.bits.head invalidate egressNodesIn_10.flit.valid invalidate egressNodesIn_10.flit.ready wire egressNodesIn_11 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_11.flit.bits.ingress_id invalidate egressNodesIn_11.flit.bits.payload invalidate egressNodesIn_11.flit.bits.tail invalidate egressNodesIn_11.flit.bits.head invalidate egressNodesIn_11.flit.valid invalidate egressNodesIn_11.flit.ready wire egressNodesIn_12 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_12.flit.bits.ingress_id invalidate egressNodesIn_12.flit.bits.payload invalidate egressNodesIn_12.flit.bits.tail invalidate egressNodesIn_12.flit.bits.head invalidate egressNodesIn_12.flit.valid invalidate egressNodesIn_12.flit.ready wire egressNodesIn_13 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_13.flit.bits.ingress_id invalidate egressNodesIn_13.flit.bits.payload invalidate egressNodesIn_13.flit.bits.tail invalidate egressNodesIn_13.flit.bits.head invalidate egressNodesIn_13.flit.valid invalidate egressNodesIn_13.flit.ready wire egressNodesIn_14 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_14.flit.bits.ingress_id invalidate egressNodesIn_14.flit.bits.payload invalidate egressNodesIn_14.flit.bits.tail invalidate egressNodesIn_14.flit.bits.head invalidate egressNodesIn_14.flit.valid invalidate egressNodesIn_14.flit.ready wire egressNodesIn_15 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_15.flit.bits.ingress_id invalidate egressNodesIn_15.flit.bits.payload invalidate egressNodesIn_15.flit.bits.tail invalidate egressNodesIn_15.flit.bits.head invalidate egressNodesIn_15.flit.valid invalidate egressNodesIn_15.flit.ready wire egressNodesIn_16 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_16.flit.bits.ingress_id invalidate egressNodesIn_16.flit.bits.payload invalidate egressNodesIn_16.flit.bits.tail invalidate egressNodesIn_16.flit.bits.head invalidate egressNodesIn_16.flit.valid invalidate egressNodesIn_16.flit.ready wire egressNodesIn_17 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_17.flit.bits.ingress_id invalidate egressNodesIn_17.flit.bits.payload invalidate egressNodesIn_17.flit.bits.tail invalidate egressNodesIn_17.flit.bits.head invalidate egressNodesIn_17.flit.valid invalidate egressNodesIn_17.flit.ready wire egressNodesIn_18 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_18.flit.bits.ingress_id invalidate egressNodesIn_18.flit.bits.payload invalidate egressNodesIn_18.flit.bits.tail invalidate egressNodesIn_18.flit.bits.head invalidate egressNodesIn_18.flit.valid invalidate egressNodesIn_18.flit.ready wire sinkIn : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn.sa_stall[0] invalidate sinkIn.sa_stall[1] invalidate sinkIn.sa_stall[2] invalidate sinkIn.va_stall[0] invalidate sinkIn.va_stall[1] invalidate sinkIn.va_stall[2] wire sinkIn_1 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_1.sa_stall[0] invalidate sinkIn_1.sa_stall[1] invalidate sinkIn_1.sa_stall[2] invalidate sinkIn_1.va_stall[0] invalidate sinkIn_1.va_stall[1] invalidate sinkIn_1.va_stall[2] wire sinkIn_2 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_2.sa_stall[0] invalidate sinkIn_2.sa_stall[1] invalidate sinkIn_2.sa_stall[2] invalidate sinkIn_2.va_stall[0] invalidate sinkIn_2.va_stall[1] invalidate sinkIn_2.va_stall[2] wire sinkIn_3 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_3.sa_stall[0] invalidate sinkIn_3.sa_stall[1] invalidate sinkIn_3.sa_stall[2] invalidate sinkIn_3.va_stall[0] invalidate sinkIn_3.va_stall[1] invalidate sinkIn_3.va_stall[2] wire sinkIn_4 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_4.sa_stall[0] invalidate sinkIn_4.sa_stall[1] invalidate sinkIn_4.sa_stall[2] invalidate sinkIn_4.va_stall[0] invalidate sinkIn_4.va_stall[1] invalidate sinkIn_4.va_stall[2] wire sinkIn_5 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_5.sa_stall[0] invalidate sinkIn_5.sa_stall[1] invalidate sinkIn_5.sa_stall[2] invalidate sinkIn_5.va_stall[0] invalidate sinkIn_5.va_stall[1] invalidate sinkIn_5.va_stall[2] wire sinkIn_6 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_6.sa_stall[0] invalidate sinkIn_6.sa_stall[1] invalidate sinkIn_6.sa_stall[2] invalidate sinkIn_6.va_stall[0] invalidate sinkIn_6.va_stall[1] invalidate sinkIn_6.va_stall[2] wire sinkIn_7 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_7.sa_stall[0] invalidate sinkIn_7.sa_stall[1] invalidate sinkIn_7.sa_stall[2] invalidate sinkIn_7.va_stall[0] invalidate sinkIn_7.va_stall[1] invalidate sinkIn_7.va_stall[2] wire sinkIn_8 : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate sinkIn_8.sa_stall[0] invalidate sinkIn_8.sa_stall[1] invalidate sinkIn_8.sa_stall[2] invalidate sinkIn_8.sa_stall[3] invalidate sinkIn_8.va_stall[0] invalidate sinkIn_8.va_stall[1] invalidate sinkIn_8.va_stall[2] invalidate sinkIn_8.va_stall[3] wire sinkIn_9 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_9.sa_stall[0] invalidate sinkIn_9.sa_stall[1] invalidate sinkIn_9.va_stall[0] invalidate sinkIn_9.va_stall[1] wire sinkIn_10 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_10.sa_stall[0] invalidate sinkIn_10.sa_stall[1] invalidate sinkIn_10.va_stall[0] invalidate sinkIn_10.va_stall[1] wire sinkIn_11 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_11.sa_stall[0] invalidate sinkIn_11.sa_stall[1] invalidate sinkIn_11.va_stall[0] invalidate sinkIn_11.va_stall[1] wire sinkIn_12 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_12.sa_stall[0] invalidate sinkIn_12.sa_stall[1] invalidate sinkIn_12.va_stall[0] invalidate sinkIn_12.va_stall[1] connect router_sink_domain.auto.clock_in, clockSourceNodesOut connect router_sink_domain_1.auto.clock_in, clockSourceNodesOut_1 connect router_sink_domain_2.auto.clock_in, clockSourceNodesOut_2 connect router_sink_domain_3.auto.clock_in, clockSourceNodesOut_3 connect router_sink_domain_4.auto.clock_in, clockSourceNodesOut_4 connect router_sink_domain_5.auto.clock_in, clockSourceNodesOut_5 connect router_sink_domain_6.auto.clock_in, clockSourceNodesOut_6 connect router_sink_domain_7.auto.clock_in, clockSourceNodesOut_7 connect router_sink_domain_8.auto.clock_in, clockSourceNodesOut_8 connect router_sink_domain_9.auto.clock_in, clockSourceNodesOut_9 connect router_sink_domain_10.auto.clock_in, clockSourceNodesOut_10 connect router_sink_domain_11.auto.clock_in, clockSourceNodesOut_11 connect router_sink_domain_12.auto.clock_in, clockSourceNodesOut_12 connect router_sink_domain_1.auto.routers_dest_nodes_in, router_sink_domain.auto.routers_source_nodes_out connect egressNodesIn_1.flit.bits, router_sink_domain.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_1.flit.valid, router_sink_domain.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_1.flit.ready connect sinkIn, router_sink_domain.auto.routers_debug_out connect router_sink_domain_2.auto.routers_dest_nodes_in, router_sink_domain_1.auto.routers_source_nodes_out connect egressNodesIn_2.flit.bits, router_sink_domain_1.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_2.flit.valid, router_sink_domain_1.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_1.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_2.flit.ready connect sinkIn_1, router_sink_domain_1.auto.routers_debug_out connect router_sink_domain_3.auto.routers_dest_nodes_in, router_sink_domain_2.auto.routers_source_nodes_out connect egressNodesIn_3.flit.bits, router_sink_domain_2.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_3.flit.valid, router_sink_domain_2.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_2.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_3.flit.ready connect sinkIn_2, router_sink_domain_2.auto.routers_debug_out connect router_sink_domain_4.auto.routers_dest_nodes_in, router_sink_domain_3.auto.routers_source_nodes_out connect egressNodesIn_4.flit.bits, router_sink_domain_3.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_4.flit.valid, router_sink_domain_3.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_3.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_4.flit.ready connect sinkIn_3, router_sink_domain_3.auto.routers_debug_out connect router_sink_domain_5.auto.routers_dest_nodes_in, router_sink_domain_4.auto.routers_source_nodes_out connect egressNodesIn_5.flit.bits, router_sink_domain_4.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_5.flit.valid, router_sink_domain_4.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_4.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_5.flit.ready connect sinkIn_4, router_sink_domain_4.auto.routers_debug_out connect router_sink_domain_6.auto.routers_dest_nodes_in, router_sink_domain_5.auto.routers_source_nodes_out connect egressNodesIn_6.flit.bits, router_sink_domain_5.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_6.flit.valid, router_sink_domain_5.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_5.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_6.flit.ready connect sinkIn_5, router_sink_domain_5.auto.routers_debug_out connect router_sink_domain_7.auto.routers_dest_nodes_in, router_sink_domain_6.auto.routers_source_nodes_out connect egressNodesIn_7.flit.bits, router_sink_domain_6.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_7.flit.valid, router_sink_domain_6.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_6.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_7.flit.ready connect sinkIn_6, router_sink_domain_6.auto.routers_debug_out connect router_sink_domain_8.auto.routers_dest_nodes_in, router_sink_domain_7.auto.routers_source_nodes_out connect egressNodesIn_8.flit.bits, router_sink_domain_7.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_8.flit.valid, router_sink_domain_7.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_7.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_8.flit.ready connect sinkIn_7, router_sink_domain_7.auto.routers_debug_out connect router_sink_domain_9.auto.routers_dest_nodes_in, router_sink_domain_8.auto.routers_source_nodes_out connect egressNodesIn.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn.flit.ready connect egressNodesIn_9.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_9.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_9.flit.ready connect egressNodesIn_10.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_2.flit.bits connect egressNodesIn_10.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_2.flit.valid connect router_sink_domain_8.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_10.flit.ready connect sinkIn_8, router_sink_domain_8.auto.routers_debug_out connect router_sink_domain_10.auto.routers_dest_nodes_in, router_sink_domain_9.auto.routers_source_nodes_out connect egressNodesIn_11.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_11.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_11.flit.ready connect egressNodesIn_12.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_12.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_12.flit.ready connect sinkIn_9, router_sink_domain_9.auto.routers_debug_out connect router_sink_domain_11.auto.routers_dest_nodes_in, router_sink_domain_10.auto.routers_source_nodes_out connect egressNodesIn_13.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_13.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_13.flit.ready connect egressNodesIn_14.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_14.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_14.flit.ready connect sinkIn_10, router_sink_domain_10.auto.routers_debug_out connect router_sink_domain_12.auto.routers_dest_nodes_in, router_sink_domain_11.auto.routers_source_nodes_out connect egressNodesIn_15.flit.bits, router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_15.flit.valid, router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_15.flit.ready connect egressNodesIn_16.flit.bits, router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_16.flit.valid, router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_16.flit.ready connect sinkIn_11, router_sink_domain_11.auto.routers_debug_out connect router_sink_domain.auto.routers_dest_nodes_in, router_sink_domain_12.auto.routers_source_nodes_out connect egressNodesIn_17.flit.bits, router_sink_domain_12.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_17.flit.valid, router_sink_domain_12.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_12.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_17.flit.ready connect egressNodesIn_18.flit.bits, router_sink_domain_12.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_18.flit.valid, router_sink_domain_12.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_12.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_18.flit.ready connect sinkIn_12, router_sink_domain_12.auto.routers_debug_out connect router_sink_domain_8.auto.routers_ingress_nodes_in_0, ingressNodesOut connect router_sink_domain_8.auto.routers_ingress_nodes_in_1, ingressNodesOut_1 connect router_sink_domain.auto.routers_ingress_nodes_in_0, ingressNodesOut_2 connect router_sink_domain.auto.routers_ingress_nodes_in_1, ingressNodesOut_3 connect router_sink_domain_1.auto.routers_ingress_nodes_in_0, ingressNodesOut_4 connect router_sink_domain_1.auto.routers_ingress_nodes_in_1, ingressNodesOut_5 connect router_sink_domain_2.auto.routers_ingress_nodes_in_0, ingressNodesOut_6 connect router_sink_domain_2.auto.routers_ingress_nodes_in_1, ingressNodesOut_7 connect router_sink_domain_3.auto.routers_ingress_nodes_in_0, ingressNodesOut_8 connect router_sink_domain_3.auto.routers_ingress_nodes_in_1, ingressNodesOut_9 connect router_sink_domain_4.auto.routers_ingress_nodes_in_0, ingressNodesOut_10 connect router_sink_domain_4.auto.routers_ingress_nodes_in_1, ingressNodesOut_11 connect router_sink_domain_5.auto.routers_ingress_nodes_in_0, ingressNodesOut_12 connect router_sink_domain_5.auto.routers_ingress_nodes_in_1, ingressNodesOut_13 connect router_sink_domain_6.auto.routers_ingress_nodes_in_0, ingressNodesOut_14 connect router_sink_domain_6.auto.routers_ingress_nodes_in_1, ingressNodesOut_15 connect router_sink_domain_7.auto.routers_ingress_nodes_in_0, ingressNodesOut_16 connect router_sink_domain_7.auto.routers_ingress_nodes_in_1, ingressNodesOut_17 connect router_sink_domain_8.auto.routers_ingress_nodes_in_2, ingressNodesOut_18 connect router_sink_domain_9.auto.routers_ingress_nodes_in, ingressNodesOut_19 connect router_sink_domain_10.auto.routers_ingress_nodes_in, ingressNodesOut_20 connect router_sink_domain_11.auto.routers_ingress_nodes_in, ingressNodesOut_21 connect router_sink_domain_12.auto.routers_ingress_nodes_in, ingressNodesOut_22 connect ingressNodesOut, io.ingress.`0` connect ingressNodesOut_1, io.ingress.`1` connect ingressNodesOut_2, io.ingress.`2` connect ingressNodesOut_3, io.ingress.`3` connect ingressNodesOut_4, io.ingress.`4` connect ingressNodesOut_5, io.ingress.`5` connect ingressNodesOut_6, io.ingress.`6` connect ingressNodesOut_7, io.ingress.`7` connect ingressNodesOut_8, io.ingress.`8` connect ingressNodesOut_9, io.ingress.`9` connect ingressNodesOut_10, io.ingress.`10` connect ingressNodesOut_11, io.ingress.`11` connect ingressNodesOut_12, io.ingress.`12` connect ingressNodesOut_13, io.ingress.`13` connect ingressNodesOut_14, io.ingress.`14` connect ingressNodesOut_15, io.ingress.`15` connect ingressNodesOut_16, io.ingress.`16` connect ingressNodesOut_17, io.ingress.`17` connect ingressNodesOut_18, io.ingress.`18` connect ingressNodesOut_19, io.ingress.`19` connect ingressNodesOut_20, io.ingress.`20` connect ingressNodesOut_21, io.ingress.`21` connect ingressNodesOut_22, io.ingress.`22` connect io.egress.`0`, egressNodesIn connect io.egress.`1`, egressNodesIn_1 connect io.egress.`2`, egressNodesIn_2 connect io.egress.`3`, egressNodesIn_3 connect io.egress.`4`, egressNodesIn_4 connect io.egress.`5`, egressNodesIn_5 connect io.egress.`6`, egressNodesIn_6 connect io.egress.`7`, egressNodesIn_7 connect io.egress.`8`, egressNodesIn_8 connect io.egress.`9`, egressNodesIn_9 connect io.egress.`10`, egressNodesIn_10 connect io.egress.`11`, egressNodesIn_11 connect io.egress.`12`, egressNodesIn_12 connect io.egress.`13`, egressNodesIn_13 connect io.egress.`14`, egressNodesIn_14 connect io.egress.`15`, egressNodesIn_15 connect io.egress.`16`, egressNodesIn_16 connect io.egress.`17`, egressNodesIn_17 connect io.egress.`18`, egressNodesIn_18 connect clockSourceNodesOut, io.router_clocks[0] connect clockSourceNodesOut_1, io.router_clocks[1] connect clockSourceNodesOut_2, io.router_clocks[2] connect clockSourceNodesOut_3, io.router_clocks[3] connect clockSourceNodesOut_4, io.router_clocks[4] connect clockSourceNodesOut_5, io.router_clocks[5] connect clockSourceNodesOut_6, io.router_clocks[6] connect clockSourceNodesOut_7, io.router_clocks[7] connect clockSourceNodesOut_8, io.router_clocks[8] connect clockSourceNodesOut_9, io.router_clocks[9] connect clockSourceNodesOut_10, io.router_clocks[10] connect clockSourceNodesOut_11, io.router_clocks[11] connect clockSourceNodesOut_12, io.router_clocks[12] regreset debug_va_stall_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset debug_sa_stall_ctr : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_any_stall_ctr_T = add(debug_va_stall_ctr, debug_sa_stall_ctr) node debug_any_stall_ctr = tail(_debug_any_stall_ctr_T, 1) node _debug_va_stall_ctr_T = add(sinkIn.va_stall[0], sinkIn.va_stall[1]) node _debug_va_stall_ctr_T_1 = tail(_debug_va_stall_ctr_T, 1) node _debug_va_stall_ctr_T_2 = add(_debug_va_stall_ctr_T_1, sinkIn.va_stall[2]) node _debug_va_stall_ctr_T_3 = tail(_debug_va_stall_ctr_T_2, 1) node _debug_va_stall_ctr_T_4 = add(sinkIn_1.va_stall[0], sinkIn_1.va_stall[1]) node _debug_va_stall_ctr_T_5 = tail(_debug_va_stall_ctr_T_4, 1) node _debug_va_stall_ctr_T_6 = add(_debug_va_stall_ctr_T_5, sinkIn_1.va_stall[2]) node _debug_va_stall_ctr_T_7 = tail(_debug_va_stall_ctr_T_6, 1) node _debug_va_stall_ctr_T_8 = add(sinkIn_2.va_stall[0], sinkIn_2.va_stall[1]) node _debug_va_stall_ctr_T_9 = tail(_debug_va_stall_ctr_T_8, 1) node _debug_va_stall_ctr_T_10 = add(_debug_va_stall_ctr_T_9, sinkIn_2.va_stall[2]) node _debug_va_stall_ctr_T_11 = tail(_debug_va_stall_ctr_T_10, 1) node _debug_va_stall_ctr_T_12 = add(sinkIn_3.va_stall[0], sinkIn_3.va_stall[1]) node _debug_va_stall_ctr_T_13 = tail(_debug_va_stall_ctr_T_12, 1) node _debug_va_stall_ctr_T_14 = add(_debug_va_stall_ctr_T_13, sinkIn_3.va_stall[2]) node _debug_va_stall_ctr_T_15 = tail(_debug_va_stall_ctr_T_14, 1) node _debug_va_stall_ctr_T_16 = add(sinkIn_4.va_stall[0], sinkIn_4.va_stall[1]) node _debug_va_stall_ctr_T_17 = tail(_debug_va_stall_ctr_T_16, 1) node _debug_va_stall_ctr_T_18 = add(_debug_va_stall_ctr_T_17, sinkIn_4.va_stall[2]) node _debug_va_stall_ctr_T_19 = tail(_debug_va_stall_ctr_T_18, 1) node _debug_va_stall_ctr_T_20 = add(sinkIn_5.va_stall[0], sinkIn_5.va_stall[1]) node _debug_va_stall_ctr_T_21 = tail(_debug_va_stall_ctr_T_20, 1) node _debug_va_stall_ctr_T_22 = add(_debug_va_stall_ctr_T_21, sinkIn_5.va_stall[2]) node _debug_va_stall_ctr_T_23 = tail(_debug_va_stall_ctr_T_22, 1) node _debug_va_stall_ctr_T_24 = add(sinkIn_6.va_stall[0], sinkIn_6.va_stall[1]) node _debug_va_stall_ctr_T_25 = tail(_debug_va_stall_ctr_T_24, 1) node _debug_va_stall_ctr_T_26 = add(_debug_va_stall_ctr_T_25, sinkIn_6.va_stall[2]) node _debug_va_stall_ctr_T_27 = tail(_debug_va_stall_ctr_T_26, 1) node _debug_va_stall_ctr_T_28 = add(sinkIn_7.va_stall[0], sinkIn_7.va_stall[1]) node _debug_va_stall_ctr_T_29 = tail(_debug_va_stall_ctr_T_28, 1) node _debug_va_stall_ctr_T_30 = add(_debug_va_stall_ctr_T_29, sinkIn_7.va_stall[2]) node _debug_va_stall_ctr_T_31 = tail(_debug_va_stall_ctr_T_30, 1) node _debug_va_stall_ctr_T_32 = add(sinkIn_8.va_stall[0], sinkIn_8.va_stall[1]) node _debug_va_stall_ctr_T_33 = tail(_debug_va_stall_ctr_T_32, 1) node _debug_va_stall_ctr_T_34 = add(_debug_va_stall_ctr_T_33, sinkIn_8.va_stall[2]) node _debug_va_stall_ctr_T_35 = tail(_debug_va_stall_ctr_T_34, 1) node _debug_va_stall_ctr_T_36 = add(_debug_va_stall_ctr_T_35, sinkIn_8.va_stall[3]) node _debug_va_stall_ctr_T_37 = tail(_debug_va_stall_ctr_T_36, 1) node _debug_va_stall_ctr_T_38 = add(sinkIn_9.va_stall[0], sinkIn_9.va_stall[1]) node _debug_va_stall_ctr_T_39 = tail(_debug_va_stall_ctr_T_38, 1) node _debug_va_stall_ctr_T_40 = add(sinkIn_10.va_stall[0], sinkIn_10.va_stall[1]) node _debug_va_stall_ctr_T_41 = tail(_debug_va_stall_ctr_T_40, 1) node _debug_va_stall_ctr_T_42 = add(sinkIn_11.va_stall[0], sinkIn_11.va_stall[1]) node _debug_va_stall_ctr_T_43 = tail(_debug_va_stall_ctr_T_42, 1) node _debug_va_stall_ctr_T_44 = add(sinkIn_12.va_stall[0], sinkIn_12.va_stall[1]) node _debug_va_stall_ctr_T_45 = tail(_debug_va_stall_ctr_T_44, 1) node _debug_va_stall_ctr_T_46 = add(_debug_va_stall_ctr_T_3, _debug_va_stall_ctr_T_7) node _debug_va_stall_ctr_T_47 = tail(_debug_va_stall_ctr_T_46, 1) node _debug_va_stall_ctr_T_48 = add(_debug_va_stall_ctr_T_47, _debug_va_stall_ctr_T_11) node _debug_va_stall_ctr_T_49 = tail(_debug_va_stall_ctr_T_48, 1) node _debug_va_stall_ctr_T_50 = add(_debug_va_stall_ctr_T_49, _debug_va_stall_ctr_T_15) node _debug_va_stall_ctr_T_51 = tail(_debug_va_stall_ctr_T_50, 1) node _debug_va_stall_ctr_T_52 = add(_debug_va_stall_ctr_T_51, _debug_va_stall_ctr_T_19) node _debug_va_stall_ctr_T_53 = tail(_debug_va_stall_ctr_T_52, 1) node _debug_va_stall_ctr_T_54 = add(_debug_va_stall_ctr_T_53, _debug_va_stall_ctr_T_23) node _debug_va_stall_ctr_T_55 = tail(_debug_va_stall_ctr_T_54, 1) node _debug_va_stall_ctr_T_56 = add(_debug_va_stall_ctr_T_55, _debug_va_stall_ctr_T_27) node _debug_va_stall_ctr_T_57 = tail(_debug_va_stall_ctr_T_56, 1) node _debug_va_stall_ctr_T_58 = add(_debug_va_stall_ctr_T_57, _debug_va_stall_ctr_T_31) node _debug_va_stall_ctr_T_59 = tail(_debug_va_stall_ctr_T_58, 1) node _debug_va_stall_ctr_T_60 = add(_debug_va_stall_ctr_T_59, _debug_va_stall_ctr_T_37) node _debug_va_stall_ctr_T_61 = tail(_debug_va_stall_ctr_T_60, 1) node _debug_va_stall_ctr_T_62 = add(_debug_va_stall_ctr_T_61, _debug_va_stall_ctr_T_39) node _debug_va_stall_ctr_T_63 = tail(_debug_va_stall_ctr_T_62, 1) node _debug_va_stall_ctr_T_64 = add(_debug_va_stall_ctr_T_63, _debug_va_stall_ctr_T_41) node _debug_va_stall_ctr_T_65 = tail(_debug_va_stall_ctr_T_64, 1) node _debug_va_stall_ctr_T_66 = add(_debug_va_stall_ctr_T_65, _debug_va_stall_ctr_T_43) node _debug_va_stall_ctr_T_67 = tail(_debug_va_stall_ctr_T_66, 1) node _debug_va_stall_ctr_T_68 = add(_debug_va_stall_ctr_T_67, _debug_va_stall_ctr_T_45) node _debug_va_stall_ctr_T_69 = tail(_debug_va_stall_ctr_T_68, 1) node _debug_va_stall_ctr_T_70 = add(debug_va_stall_ctr, _debug_va_stall_ctr_T_69) node _debug_va_stall_ctr_T_71 = tail(_debug_va_stall_ctr_T_70, 1) connect debug_va_stall_ctr, _debug_va_stall_ctr_T_71 node _debug_sa_stall_ctr_T = add(sinkIn.sa_stall[0], sinkIn.sa_stall[1]) node _debug_sa_stall_ctr_T_1 = tail(_debug_sa_stall_ctr_T, 1) node _debug_sa_stall_ctr_T_2 = add(_debug_sa_stall_ctr_T_1, sinkIn.sa_stall[2]) node _debug_sa_stall_ctr_T_3 = tail(_debug_sa_stall_ctr_T_2, 1) node _debug_sa_stall_ctr_T_4 = add(sinkIn_1.sa_stall[0], sinkIn_1.sa_stall[1]) node _debug_sa_stall_ctr_T_5 = tail(_debug_sa_stall_ctr_T_4, 1) node _debug_sa_stall_ctr_T_6 = add(_debug_sa_stall_ctr_T_5, sinkIn_1.sa_stall[2]) node _debug_sa_stall_ctr_T_7 = tail(_debug_sa_stall_ctr_T_6, 1) node _debug_sa_stall_ctr_T_8 = add(sinkIn_2.sa_stall[0], sinkIn_2.sa_stall[1]) node _debug_sa_stall_ctr_T_9 = tail(_debug_sa_stall_ctr_T_8, 1) node _debug_sa_stall_ctr_T_10 = add(_debug_sa_stall_ctr_T_9, sinkIn_2.sa_stall[2]) node _debug_sa_stall_ctr_T_11 = tail(_debug_sa_stall_ctr_T_10, 1) node _debug_sa_stall_ctr_T_12 = add(sinkIn_3.sa_stall[0], sinkIn_3.sa_stall[1]) node _debug_sa_stall_ctr_T_13 = tail(_debug_sa_stall_ctr_T_12, 1) node _debug_sa_stall_ctr_T_14 = add(_debug_sa_stall_ctr_T_13, sinkIn_3.sa_stall[2]) node _debug_sa_stall_ctr_T_15 = tail(_debug_sa_stall_ctr_T_14, 1) node _debug_sa_stall_ctr_T_16 = add(sinkIn_4.sa_stall[0], sinkIn_4.sa_stall[1]) node _debug_sa_stall_ctr_T_17 = tail(_debug_sa_stall_ctr_T_16, 1) node _debug_sa_stall_ctr_T_18 = add(_debug_sa_stall_ctr_T_17, sinkIn_4.sa_stall[2]) node _debug_sa_stall_ctr_T_19 = tail(_debug_sa_stall_ctr_T_18, 1) node _debug_sa_stall_ctr_T_20 = add(sinkIn_5.sa_stall[0], sinkIn_5.sa_stall[1]) node _debug_sa_stall_ctr_T_21 = tail(_debug_sa_stall_ctr_T_20, 1) node _debug_sa_stall_ctr_T_22 = add(_debug_sa_stall_ctr_T_21, sinkIn_5.sa_stall[2]) node _debug_sa_stall_ctr_T_23 = tail(_debug_sa_stall_ctr_T_22, 1) node _debug_sa_stall_ctr_T_24 = add(sinkIn_6.sa_stall[0], sinkIn_6.sa_stall[1]) node _debug_sa_stall_ctr_T_25 = tail(_debug_sa_stall_ctr_T_24, 1) node _debug_sa_stall_ctr_T_26 = add(_debug_sa_stall_ctr_T_25, sinkIn_6.sa_stall[2]) node _debug_sa_stall_ctr_T_27 = tail(_debug_sa_stall_ctr_T_26, 1) node _debug_sa_stall_ctr_T_28 = add(sinkIn_7.sa_stall[0], sinkIn_7.sa_stall[1]) node _debug_sa_stall_ctr_T_29 = tail(_debug_sa_stall_ctr_T_28, 1) node _debug_sa_stall_ctr_T_30 = add(_debug_sa_stall_ctr_T_29, sinkIn_7.sa_stall[2]) node _debug_sa_stall_ctr_T_31 = tail(_debug_sa_stall_ctr_T_30, 1) node _debug_sa_stall_ctr_T_32 = add(sinkIn_8.sa_stall[0], sinkIn_8.sa_stall[1]) node _debug_sa_stall_ctr_T_33 = tail(_debug_sa_stall_ctr_T_32, 1) node _debug_sa_stall_ctr_T_34 = add(_debug_sa_stall_ctr_T_33, sinkIn_8.sa_stall[2]) node _debug_sa_stall_ctr_T_35 = tail(_debug_sa_stall_ctr_T_34, 1) node _debug_sa_stall_ctr_T_36 = add(_debug_sa_stall_ctr_T_35, sinkIn_8.sa_stall[3]) node _debug_sa_stall_ctr_T_37 = tail(_debug_sa_stall_ctr_T_36, 1) node _debug_sa_stall_ctr_T_38 = add(sinkIn_9.sa_stall[0], sinkIn_9.sa_stall[1]) node _debug_sa_stall_ctr_T_39 = tail(_debug_sa_stall_ctr_T_38, 1) node _debug_sa_stall_ctr_T_40 = add(sinkIn_10.sa_stall[0], sinkIn_10.sa_stall[1]) node _debug_sa_stall_ctr_T_41 = tail(_debug_sa_stall_ctr_T_40, 1) node _debug_sa_stall_ctr_T_42 = add(sinkIn_11.sa_stall[0], sinkIn_11.sa_stall[1]) node _debug_sa_stall_ctr_T_43 = tail(_debug_sa_stall_ctr_T_42, 1) node _debug_sa_stall_ctr_T_44 = add(sinkIn_12.sa_stall[0], sinkIn_12.sa_stall[1]) node _debug_sa_stall_ctr_T_45 = tail(_debug_sa_stall_ctr_T_44, 1) node _debug_sa_stall_ctr_T_46 = add(_debug_sa_stall_ctr_T_3, _debug_sa_stall_ctr_T_7) node _debug_sa_stall_ctr_T_47 = tail(_debug_sa_stall_ctr_T_46, 1) node _debug_sa_stall_ctr_T_48 = add(_debug_sa_stall_ctr_T_47, _debug_sa_stall_ctr_T_11) node _debug_sa_stall_ctr_T_49 = tail(_debug_sa_stall_ctr_T_48, 1) node _debug_sa_stall_ctr_T_50 = add(_debug_sa_stall_ctr_T_49, _debug_sa_stall_ctr_T_15) node _debug_sa_stall_ctr_T_51 = tail(_debug_sa_stall_ctr_T_50, 1) node _debug_sa_stall_ctr_T_52 = add(_debug_sa_stall_ctr_T_51, _debug_sa_stall_ctr_T_19) node _debug_sa_stall_ctr_T_53 = tail(_debug_sa_stall_ctr_T_52, 1) node _debug_sa_stall_ctr_T_54 = add(_debug_sa_stall_ctr_T_53, _debug_sa_stall_ctr_T_23) node _debug_sa_stall_ctr_T_55 = tail(_debug_sa_stall_ctr_T_54, 1) node _debug_sa_stall_ctr_T_56 = add(_debug_sa_stall_ctr_T_55, _debug_sa_stall_ctr_T_27) node _debug_sa_stall_ctr_T_57 = tail(_debug_sa_stall_ctr_T_56, 1) node _debug_sa_stall_ctr_T_58 = add(_debug_sa_stall_ctr_T_57, _debug_sa_stall_ctr_T_31) node _debug_sa_stall_ctr_T_59 = tail(_debug_sa_stall_ctr_T_58, 1) node _debug_sa_stall_ctr_T_60 = add(_debug_sa_stall_ctr_T_59, _debug_sa_stall_ctr_T_37) node _debug_sa_stall_ctr_T_61 = tail(_debug_sa_stall_ctr_T_60, 1) node _debug_sa_stall_ctr_T_62 = add(_debug_sa_stall_ctr_T_61, _debug_sa_stall_ctr_T_39) node _debug_sa_stall_ctr_T_63 = tail(_debug_sa_stall_ctr_T_62, 1) node _debug_sa_stall_ctr_T_64 = add(_debug_sa_stall_ctr_T_63, _debug_sa_stall_ctr_T_41) node _debug_sa_stall_ctr_T_65 = tail(_debug_sa_stall_ctr_T_64, 1) node _debug_sa_stall_ctr_T_66 = add(_debug_sa_stall_ctr_T_65, _debug_sa_stall_ctr_T_43) node _debug_sa_stall_ctr_T_67 = tail(_debug_sa_stall_ctr_T_66, 1) node _debug_sa_stall_ctr_T_68 = add(_debug_sa_stall_ctr_T_67, _debug_sa_stall_ctr_T_45) node _debug_sa_stall_ctr_T_69 = tail(_debug_sa_stall_ctr_T_68, 1) node _debug_sa_stall_ctr_T_70 = add(debug_sa_stall_ctr, _debug_sa_stall_ctr_T_69) node _debug_sa_stall_ctr_T_71 = tail(_debug_sa_stall_ctr_T_70, 1) connect debug_sa_stall_ctr, _debug_sa_stall_ctr_T_71	module NoC( // @[NoC.scala:141:9] input clock, // @[NoC.scala:141:9] input reset, // @[NoC.scala:141:9] output io_ingress_22_flit_ready, // @[NoC.scala:143:16] input io_ingress_22_flit_valid, // @[NoC.scala:143:16] input io_ingress_22_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_22_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_22_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_22_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_21_flit_ready, // @[NoC.scala:143:16] input io_ingress_21_flit_valid, // @[NoC.scala:143:16] input io_ingress_21_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_21_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_21_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_21_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_20_flit_ready, // @[NoC.scala:143:16] input io_ingress_20_flit_valid, // @[NoC.scala:143:16] input io_ingress_20_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_20_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_20_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_20_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_19_flit_ready, // @[NoC.scala:143:16] input io_ingress_19_flit_valid, // @[NoC.scala:143:16] input io_ingress_19_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_19_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_19_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_19_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_18_flit_ready, // @[NoC.scala:143:16] input io_ingress_18_flit_valid, // @[NoC.scala:143:16] input io_ingress_18_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_18_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_18_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_18_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_17_flit_ready, // @[NoC.scala:143:16] input io_ingress_17_flit_valid, // @[NoC.scala:143:16] input io_ingress_17_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_17_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_17_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_17_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_16_flit_ready, // @[NoC.scala:143:16] input io_ingress_16_flit_valid, // @[NoC.scala:143:16] input io_ingress_16_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_16_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_16_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_16_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_15_flit_ready, // @[NoC.scala:143:16] input io_ingress_15_flit_valid, // @[NoC.scala:143:16] input io_ingress_15_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_15_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_15_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_15_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_14_flit_ready, // @[NoC.scala:143:16] input io_ingress_14_flit_valid, // @[NoC.scala:143:16] input io_ingress_14_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_14_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_14_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_14_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_13_flit_ready, // @[NoC.scala:143:16] input io_ingress_13_flit_valid, // @[NoC.scala:143:16] input io_ingress_13_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_13_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_13_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_13_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_12_flit_ready, // @[NoC.scala:143:16] input io_ingress_12_flit_valid, // @[NoC.scala:143:16] input io_ingress_12_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_12_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_12_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_12_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_11_flit_ready, // @[NoC.scala:143:16] input io_ingress_11_flit_valid, // @[NoC.scala:143:16] input io_ingress_11_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_11_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_11_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_11_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_10_flit_ready, // @[NoC.scala:143:16] input io_ingress_10_flit_valid, // @[NoC.scala:143:16] input io_ingress_10_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_10_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_10_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_10_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_9_flit_ready, // @[NoC.scala:143:16] input io_ingress_9_flit_valid, // @[NoC.scala:143:16] input io_ingress_9_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_9_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_9_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_9_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_8_flit_ready, // @[NoC.scala:143:16] input io_ingress_8_flit_valid, // @[NoC.scala:143:16] input io_ingress_8_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_8_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_8_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_8_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_7_flit_ready, // @[NoC.scala:143:16] input io_ingress_7_flit_valid, // @[NoC.scala:143:16] input io_ingress_7_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_7_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_7_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_7_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_6_flit_ready, // @[NoC.scala:143:16] input io_ingress_6_flit_valid, // @[NoC.scala:143:16] input io_ingress_6_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_6_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_6_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_6_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_5_flit_ready, // @[NoC.scala:143:16] input io_ingress_5_flit_valid, // @[NoC.scala:143:16] input io_ingress_5_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_5_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_5_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_5_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_4_flit_ready, // @[NoC.scala:143:16] input io_ingress_4_flit_valid, // @[NoC.scala:143:16] input io_ingress_4_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_4_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_4_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_4_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_3_flit_ready, // @[NoC.scala:143:16] input io_ingress_3_flit_valid, // @[NoC.scala:143:16] input io_ingress_3_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_3_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_3_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_3_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_2_flit_ready, // @[NoC.scala:143:16] input io_ingress_2_flit_valid, // @[NoC.scala:143:16] input io_ingress_2_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_2_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_2_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_2_flit_bits_egress_id, // @[NoC.scala:143:16] input io_ingress_1_flit_valid, // @[NoC.scala:143:16] output io_ingress_0_flit_ready, // @[NoC.scala:143:16] input io_ingress_0_flit_valid, // @[NoC.scala:143:16] input io_ingress_0_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_0_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_0_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_0_flit_bits_egress_id, // @[NoC.scala:143:16] input io_egress_18_flit_ready, // @[NoC.scala:143:16] output io_egress_18_flit_valid, // @[NoC.scala:143:16] output io_egress_18_flit_bits_head, // @[NoC.scala:143:16] output io_egress_18_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_18_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_17_flit_ready, // @[NoC.scala:143:16] output io_egress_17_flit_valid, // @[NoC.scala:143:16] output io_egress_17_flit_bits_head, // @[NoC.scala:143:16] output io_egress_17_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_17_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_16_flit_ready, // @[NoC.scala:143:16] output io_egress_16_flit_valid, // @[NoC.scala:143:16] output io_egress_16_flit_bits_head, // @[NoC.scala:143:16] output io_egress_16_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_16_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_15_flit_ready, // @[NoC.scala:143:16] output io_egress_15_flit_valid, // @[NoC.scala:143:16] output io_egress_15_flit_bits_head, // @[NoC.scala:143:16] output io_egress_15_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_15_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_14_flit_ready, // @[NoC.scala:143:16] output io_egress_14_flit_valid, // @[NoC.scala:143:16] output io_egress_14_flit_bits_head, // @[NoC.scala:143:16] output io_egress_14_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_14_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_13_flit_ready, // @[NoC.scala:143:16] output io_egress_13_flit_valid, // @[NoC.scala:143:16] output io_egress_13_flit_bits_head, // @[NoC.scala:143:16] output io_egress_13_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_13_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_12_flit_ready, // @[NoC.scala:143:16] output io_egress_12_flit_valid, // @[NoC.scala:143:16] output io_egress_12_flit_bits_head, // @[NoC.scala:143:16] output io_egress_12_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_12_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_11_flit_ready, // @[NoC.scala:143:16] output io_egress_11_flit_valid, // @[NoC.scala:143:16] output io_egress_11_flit_bits_head, // @[NoC.scala:143:16] output io_egress_11_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_11_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_10_flit_ready, // @[NoC.scala:143:16] output io_egress_10_flit_valid, // @[NoC.scala:143:16] output io_egress_10_flit_bits_head, // @[NoC.scala:143:16] output io_egress_10_flit_bits_tail, // @[NoC.scala:143:16] input io_egress_9_flit_ready, // @[NoC.scala:143:16] output io_egress_9_flit_valid, // @[NoC.scala:143:16] output io_egress_9_flit_bits_head, // @[NoC.scala:143:16] output io_egress_9_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_9_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_8_flit_ready, // @[NoC.scala:143:16] output io_egress_8_flit_valid, // @[NoC.scala:143:16] output io_egress_8_flit_bits_head, // @[NoC.scala:143:16] output io_egress_8_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_8_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_7_flit_ready, // @[NoC.scala:143:16] output io_egress_7_flit_valid, // @[NoC.scala:143:16] output io_egress_7_flit_bits_head, // @[NoC.scala:143:16] output io_egress_7_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_7_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_6_flit_ready, // @[NoC.scala:143:16] output io_egress_6_flit_valid, // @[NoC.scala:143:16] output io_egress_6_flit_bits_head, // @[NoC.scala:143:16] output io_egress_6_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_6_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_5_flit_ready, // @[NoC.scala:143:16] output io_egress_5_flit_valid, // @[NoC.scala:143:16] output io_egress_5_flit_bits_head, // @[NoC.scala:143:16] output io_egress_5_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_5_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_4_flit_ready, // @[NoC.scala:143:16] output io_egress_4_flit_valid, // @[NoC.scala:143:16] output io_egress_4_flit_bits_head, // @[NoC.scala:143:16] output io_egress_4_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_4_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_3_flit_ready, // @[NoC.scala:143:16] output io_egress_3_flit_valid, // @[NoC.scala:143:16] output io_egress_3_flit_bits_head, // @[NoC.scala:143:16] output io_egress_3_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_3_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_2_flit_ready, // @[NoC.scala:143:16] output io_egress_2_flit_valid, // @[NoC.scala:143:16] output io_egress_2_flit_bits_head, // @[NoC.scala:143:16] output io_egress_2_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_2_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_1_flit_ready, // @[NoC.scala:143:16] output io_egress_1_flit_valid, // @[NoC.scala:143:16] output io_egress_1_flit_bits_head, // @[NoC.scala:143:16] output io_egress_1_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_1_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_0_flit_ready, // @[NoC.scala:143:16] output io_egress_0_flit_valid, // @[NoC.scala:143:16] output io_egress_0_flit_bits_head, // @[NoC.scala:143:16] output io_egress_0_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_0_flit_bits_payload, // @[NoC.scala:143:16] input io_router_clocks_0_clock, // @[NoC.scala:143:16] input io_router_clocks_0_reset, // @[NoC.scala:143:16] input io_router_clocks_1_clock, // @[NoC.scala:143:16] input io_router_clocks_1_reset, // @[NoC.scala:143:16] input io_router_clocks_2_clock, // @[NoC.scala:143:16] input io_router_clocks_2_reset, // @[NoC.scala:143:16] input io_router_clocks_3_clock, // @[NoC.scala:143:16] input io_router_clocks_3_reset, // @[NoC.scala:143:16] input io_router_clocks_4_clock, // @[NoC.scala:143:16] input io_router_clocks_4_reset, // @[NoC.scala:143:16] input io_router_clocks_5_clock, // @[NoC.scala:143:16] input io_router_clocks_5_reset, // @[NoC.scala:143:16] input io_router_clocks_6_clock, // @[NoC.scala:143:16] input io_router_clocks_6_reset, // @[NoC.scala:143:16] input io_router_clocks_7_clock, // @[NoC.scala:143:16] input io_router_clocks_7_reset, // @[NoC.scala:143:16] input io_router_clocks_8_clock, // @[NoC.scala:143:16] input io_router_clocks_8_reset, // @[NoC.scala:143:16] input io_router_clocks_9_clock, // @[NoC.scala:143:16] input io_router_clocks_9_reset, // @[NoC.scala:143:16] input io_router_clocks_10_clock, // @[NoC.scala:143:16] input io_router_clocks_10_reset, // @[NoC.scala:143:16] input io_router_clocks_11_clock, // @[NoC.scala:143:16] input io_router_clocks_11_reset, // @[NoC.scala:143:16] input io_router_clocks_12_clock, // @[NoC.scala:143:16] input io_router_clocks_12_reset // @[NoC.scala:143:16] ); wire [2:0] _router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_12_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_12_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_11_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_11_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_10_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_10_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_9_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_9_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_8_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_8_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_7_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_7_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_6_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_6_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_5_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_5_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_4_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_4_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_2_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_2_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_1_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_1_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] reg [63:0] debug_va_stall_ctr; // @[NoC.scala:163:37] reg [63:0] debug_sa_stall_ctr; // @[NoC.scala:164:37] wire [63:0] debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50] always @(posedge clock) begin // @[NoC.scala:141:9] if (reset) begin // @[NoC.scala:141:9] debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37] debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37] end else begin // @[NoC.scala:141:9] debug_va_stall_ctr <= debug_va_stall_ctr + {61'h0, _router_sink_domain_auto_routers_debug_out_va_stall_0 + _router_sink_domain_auto_routers_debug_out_va_stall_1 + _router_sink_domain_auto_routers_debug_out_va_stall_2 + _router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _router_sink_domain_3_auto_routers_debug_out_va_stall_1 + _router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _router_sink_domain_8_auto_routers_debug_out_va_stall_3 + _router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _router_sink_domain_12_auto_routers_debug_out_va_stall_1}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}] debug_sa_stall_ctr <= debug_sa_stall_ctr + {61'h0, _router_sink_domain_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_12_auto_routers_debug_out_sa_stall_1}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e5_s11_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e5_s11_1( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_290 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_34 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_290( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_34 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_47 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_47 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_47(); // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out = 33'h180000000; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [26:0] io_in_sig = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [9:0] io_in_sExp = 10'hFF; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_sign = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_47 roundAnyRawFNToRecFN (); // @[RoundAnyRawFNToRecFN.scala:310:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_1 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e8_s24_1( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ComposedBranchPredictorBank : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid inst loop of LoopBranchPredictorBank connect loop.clock, clock connect loop.reset, reset inst tage of TageBranchPredictorBank connect tage.clock, clock connect tage.reset, reset inst btb of BTBBranchPredictorBank connect btb.clock, clock connect btb.reset, reset inst bim of BIMBranchPredictorBank connect bim.clock, clock connect bim.reset, reset inst ubtb of FAMicroBTBBranchPredictorBank connect ubtb.clock, clock connect ubtb.reset, reset invalidate loop.io.update.bits.meta invalidate loop.io.update.bits.target invalidate loop.io.update.bits.lhist invalidate loop.io.update.bits.ghist invalidate loop.io.update.bits.cfi_is_jalr invalidate loop.io.update.bits.cfi_is_jal invalidate loop.io.update.bits.cfi_is_br invalidate loop.io.update.bits.cfi_mispredicted invalidate loop.io.update.bits.cfi_taken invalidate loop.io.update.bits.cfi_idx.bits invalidate loop.io.update.bits.cfi_idx.valid invalidate loop.io.update.bits.br_mask invalidate loop.io.update.bits.pc invalidate loop.io.update.bits.btb_mispredicts invalidate loop.io.update.bits.is_repair_update invalidate loop.io.update.bits.is_mispredict_update invalidate loop.io.update.valid invalidate loop.io.f3_fire invalidate loop.io.f3_meta invalidate loop.io.resp.f3[0].predicted_pc.bits invalidate loop.io.resp.f3[0].predicted_pc.valid invalidate loop.io.resp.f3[0].is_jal invalidate loop.io.resp.f3[0].is_br invalidate loop.io.resp.f3[0].taken invalidate loop.io.resp.f3[1].predicted_pc.bits invalidate loop.io.resp.f3[1].predicted_pc.valid invalidate loop.io.resp.f3[1].is_jal invalidate loop.io.resp.f3[1].is_br invalidate loop.io.resp.f3[1].taken invalidate loop.io.resp.f3[2].predicted_pc.bits invalidate loop.io.resp.f3[2].predicted_pc.valid invalidate loop.io.resp.f3[2].is_jal invalidate loop.io.resp.f3[2].is_br invalidate loop.io.resp.f3[2].taken invalidate loop.io.resp.f3[3].predicted_pc.bits invalidate loop.io.resp.f3[3].predicted_pc.valid invalidate loop.io.resp.f3[3].is_jal invalidate loop.io.resp.f3[3].is_br invalidate loop.io.resp.f3[3].taken invalidate loop.io.resp.f2[0].predicted_pc.bits invalidate loop.io.resp.f2[0].predicted_pc.valid invalidate loop.io.resp.f2[0].is_jal invalidate loop.io.resp.f2[0].is_br invalidate loop.io.resp.f2[0].taken invalidate loop.io.resp.f2[1].predicted_pc.bits invalidate loop.io.resp.f2[1].predicted_pc.valid invalidate loop.io.resp.f2[1].is_jal invalidate loop.io.resp.f2[1].is_br invalidate loop.io.resp.f2[1].taken invalidate loop.io.resp.f2[2].predicted_pc.bits invalidate loop.io.resp.f2[2].predicted_pc.valid invalidate loop.io.resp.f2[2].is_jal invalidate loop.io.resp.f2[2].is_br invalidate loop.io.resp.f2[2].taken invalidate loop.io.resp.f2[3].predicted_pc.bits invalidate loop.io.resp.f2[3].predicted_pc.valid invalidate loop.io.resp.f2[3].is_jal invalidate loop.io.resp.f2[3].is_br invalidate loop.io.resp.f2[3].taken invalidate loop.io.resp.f1[0].predicted_pc.bits invalidate loop.io.resp.f1[0].predicted_pc.valid invalidate loop.io.resp.f1[0].is_jal invalidate loop.io.resp.f1[0].is_br invalidate loop.io.resp.f1[0].taken invalidate loop.io.resp.f1[1].predicted_pc.bits invalidate loop.io.resp.f1[1].predicted_pc.valid invalidate loop.io.resp.f1[1].is_jal invalidate loop.io.resp.f1[1].is_br invalidate loop.io.resp.f1[1].taken invalidate loop.io.resp.f1[2].predicted_pc.bits invalidate loop.io.resp.f1[2].predicted_pc.valid invalidate loop.io.resp.f1[2].is_jal invalidate loop.io.resp.f1[2].is_br invalidate loop.io.resp.f1[2].taken invalidate loop.io.resp.f1[3].predicted_pc.bits invalidate loop.io.resp.f1[3].predicted_pc.valid invalidate loop.io.resp.f1[3].is_jal invalidate loop.io.resp.f1[3].is_br invalidate loop.io.resp.f1[3].taken invalidate loop.io.resp_in[0].f3[0].predicted_pc.bits invalidate loop.io.resp_in[0].f3[0].predicted_pc.valid invalidate loop.io.resp_in[0].f3[0].is_jal invalidate loop.io.resp_in[0].f3[0].is_br invalidate loop.io.resp_in[0].f3[0].taken invalidate loop.io.resp_in[0].f3[1].predicted_pc.bits invalidate loop.io.resp_in[0].f3[1].predicted_pc.valid invalidate loop.io.resp_in[0].f3[1].is_jal invalidate loop.io.resp_in[0].f3[1].is_br invalidate loop.io.resp_in[0].f3[1].taken invalidate loop.io.resp_in[0].f3[2].predicted_pc.bits invalidate loop.io.resp_in[0].f3[2].predicted_pc.valid invalidate loop.io.resp_in[0].f3[2].is_jal invalidate loop.io.resp_in[0].f3[2].is_br invalidate loop.io.resp_in[0].f3[2].taken invalidate loop.io.resp_in[0].f3[3].predicted_pc.bits invalidate loop.io.resp_in[0].f3[3].predicted_pc.valid invalidate loop.io.resp_in[0].f3[3].is_jal invalidate loop.io.resp_in[0].f3[3].is_br invalidate loop.io.resp_in[0].f3[3].taken invalidate loop.io.resp_in[0].f2[0].predicted_pc.bits invalidate loop.io.resp_in[0].f2[0].predicted_pc.valid invalidate loop.io.resp_in[0].f2[0].is_jal invalidate loop.io.resp_in[0].f2[0].is_br invalidate loop.io.resp_in[0].f2[0].taken invalidate loop.io.resp_in[0].f2[1].predicted_pc.bits invalidate loop.io.resp_in[0].f2[1].predicted_pc.valid invalidate loop.io.resp_in[0].f2[1].is_jal invalidate loop.io.resp_in[0].f2[1].is_br invalidate loop.io.resp_in[0].f2[1].taken invalidate loop.io.resp_in[0].f2[2].predicted_pc.bits invalidate loop.io.resp_in[0].f2[2].predicted_pc.valid invalidate loop.io.resp_in[0].f2[2].is_jal invalidate loop.io.resp_in[0].f2[2].is_br invalidate loop.io.resp_in[0].f2[2].taken invalidate loop.io.resp_in[0].f2[3].predicted_pc.bits invalidate loop.io.resp_in[0].f2[3].predicted_pc.valid invalidate loop.io.resp_in[0].f2[3].is_jal invalidate loop.io.resp_in[0].f2[3].is_br invalidate loop.io.resp_in[0].f2[3].taken invalidate loop.io.resp_in[0].f1[0].predicted_pc.bits invalidate loop.io.resp_in[0].f1[0].predicted_pc.valid invalidate loop.io.resp_in[0].f1[0].is_jal invalidate loop.io.resp_in[0].f1[0].is_br invalidate loop.io.resp_in[0].f1[0].taken invalidate loop.io.resp_in[0].f1[1].predicted_pc.bits invalidate loop.io.resp_in[0].f1[1].predicted_pc.valid invalidate loop.io.resp_in[0].f1[1].is_jal invalidate loop.io.resp_in[0].f1[1].is_br invalidate loop.io.resp_in[0].f1[1].taken invalidate loop.io.resp_in[0].f1[2].predicted_pc.bits invalidate loop.io.resp_in[0].f1[2].predicted_pc.valid invalidate loop.io.resp_in[0].f1[2].is_jal invalidate loop.io.resp_in[0].f1[2].is_br invalidate loop.io.resp_in[0].f1[2].taken invalidate loop.io.resp_in[0].f1[3].predicted_pc.bits invalidate loop.io.resp_in[0].f1[3].predicted_pc.valid invalidate loop.io.resp_in[0].f1[3].is_jal invalidate loop.io.resp_in[0].f1[3].is_br invalidate loop.io.resp_in[0].f1[3].taken invalidate loop.io.f1_lhist invalidate loop.io.f1_ghist invalidate loop.io.f0_mask invalidate loop.io.f0_pc invalidate loop.io.f0_valid invalidate tage.io.update.bits.meta invalidate tage.io.update.bits.target invalidate tage.io.update.bits.lhist invalidate tage.io.update.bits.ghist invalidate tage.io.update.bits.cfi_is_jalr invalidate tage.io.update.bits.cfi_is_jal invalidate tage.io.update.bits.cfi_is_br invalidate tage.io.update.bits.cfi_mispredicted invalidate tage.io.update.bits.cfi_taken invalidate tage.io.update.bits.cfi_idx.bits invalidate tage.io.update.bits.cfi_idx.valid invalidate tage.io.update.bits.br_mask invalidate tage.io.update.bits.pc invalidate tage.io.update.bits.btb_mispredicts invalidate tage.io.update.bits.is_repair_update invalidate tage.io.update.bits.is_mispredict_update invalidate tage.io.update.valid invalidate tage.io.f3_fire invalidate tage.io.f3_meta invalidate tage.io.resp.f3[0].predicted_pc.bits invalidate tage.io.resp.f3[0].predicted_pc.valid invalidate tage.io.resp.f3[0].is_jal invalidate tage.io.resp.f3[0].is_br invalidate tage.io.resp.f3[0].taken invalidate tage.io.resp.f3[1].predicted_pc.bits invalidate tage.io.resp.f3[1].predicted_pc.valid invalidate tage.io.resp.f3[1].is_jal invalidate tage.io.resp.f3[1].is_br invalidate tage.io.resp.f3[1].taken invalidate tage.io.resp.f3[2].predicted_pc.bits invalidate tage.io.resp.f3[2].predicted_pc.valid invalidate tage.io.resp.f3[2].is_jal invalidate tage.io.resp.f3[2].is_br invalidate tage.io.resp.f3[2].taken invalidate tage.io.resp.f3[3].predicted_pc.bits invalidate tage.io.resp.f3[3].predicted_pc.valid invalidate tage.io.resp.f3[3].is_jal invalidate tage.io.resp.f3[3].is_br invalidate tage.io.resp.f3[3].taken invalidate tage.io.resp.f2[0].predicted_pc.bits invalidate tage.io.resp.f2[0].predicted_pc.valid invalidate tage.io.resp.f2[0].is_jal invalidate tage.io.resp.f2[0].is_br invalidate tage.io.resp.f2[0].taken invalidate tage.io.resp.f2[1].predicted_pc.bits invalidate tage.io.resp.f2[1].predicted_pc.valid invalidate tage.io.resp.f2[1].is_jal invalidate tage.io.resp.f2[1].is_br invalidate tage.io.resp.f2[1].taken invalidate tage.io.resp.f2[2].predicted_pc.bits invalidate tage.io.resp.f2[2].predicted_pc.valid invalidate tage.io.resp.f2[2].is_jal invalidate tage.io.resp.f2[2].is_br invalidate tage.io.resp.f2[2].taken invalidate tage.io.resp.f2[3].predicted_pc.bits invalidate tage.io.resp.f2[3].predicted_pc.valid invalidate tage.io.resp.f2[3].is_jal invalidate tage.io.resp.f2[3].is_br invalidate tage.io.resp.f2[3].taken invalidate tage.io.resp.f1[0].predicted_pc.bits invalidate tage.io.resp.f1[0].predicted_pc.valid invalidate tage.io.resp.f1[0].is_jal invalidate tage.io.resp.f1[0].is_br invalidate tage.io.resp.f1[0].taken invalidate tage.io.resp.f1[1].predicted_pc.bits invalidate tage.io.resp.f1[1].predicted_pc.valid invalidate tage.io.resp.f1[1].is_jal invalidate tage.io.resp.f1[1].is_br invalidate tage.io.resp.f1[1].taken invalidate tage.io.resp.f1[2].predicted_pc.bits invalidate tage.io.resp.f1[2].predicted_pc.valid invalidate tage.io.resp.f1[2].is_jal invalidate tage.io.resp.f1[2].is_br invalidate tage.io.resp.f1[2].taken invalidate tage.io.resp.f1[3].predicted_pc.bits invalidate tage.io.resp.f1[3].predicted_pc.valid invalidate tage.io.resp.f1[3].is_jal invalidate tage.io.resp.f1[3].is_br invalidate tage.io.resp.f1[3].taken invalidate tage.io.resp_in[0].f3[0].predicted_pc.bits invalidate tage.io.resp_in[0].f3[0].predicted_pc.valid invalidate tage.io.resp_in[0].f3[0].is_jal invalidate tage.io.resp_in[0].f3[0].is_br invalidate tage.io.resp_in[0].f3[0].taken invalidate tage.io.resp_in[0].f3[1].predicted_pc.bits invalidate tage.io.resp_in[0].f3[1].predicted_pc.valid invalidate tage.io.resp_in[0].f3[1].is_jal invalidate tage.io.resp_in[0].f3[1].is_br invalidate tage.io.resp_in[0].f3[1].taken invalidate tage.io.resp_in[0].f3[2].predicted_pc.bits invalidate tage.io.resp_in[0].f3[2].predicted_pc.valid invalidate tage.io.resp_in[0].f3[2].is_jal invalidate tage.io.resp_in[0].f3[2].is_br invalidate tage.io.resp_in[0].f3[2].taken invalidate tage.io.resp_in[0].f3[3].predicted_pc.bits invalidate tage.io.resp_in[0].f3[3].predicted_pc.valid invalidate tage.io.resp_in[0].f3[3].is_jal invalidate tage.io.resp_in[0].f3[3].is_br invalidate tage.io.resp_in[0].f3[3].taken invalidate tage.io.resp_in[0].f2[0].predicted_pc.bits invalidate tage.io.resp_in[0].f2[0].predicted_pc.valid invalidate tage.io.resp_in[0].f2[0].is_jal invalidate tage.io.resp_in[0].f2[0].is_br invalidate tage.io.resp_in[0].f2[0].taken invalidate tage.io.resp_in[0].f2[1].predicted_pc.bits invalidate tage.io.resp_in[0].f2[1].predicted_pc.valid invalidate tage.io.resp_in[0].f2[1].is_jal invalidate tage.io.resp_in[0].f2[1].is_br invalidate tage.io.resp_in[0].f2[1].taken invalidate tage.io.resp_in[0].f2[2].predicted_pc.bits invalidate tage.io.resp_in[0].f2[2].predicted_pc.valid invalidate tage.io.resp_in[0].f2[2].is_jal invalidate tage.io.resp_in[0].f2[2].is_br invalidate tage.io.resp_in[0].f2[2].taken invalidate tage.io.resp_in[0].f2[3].predicted_pc.bits invalidate tage.io.resp_in[0].f2[3].predicted_pc.valid invalidate tage.io.resp_in[0].f2[3].is_jal invalidate tage.io.resp_in[0].f2[3].is_br invalidate tage.io.resp_in[0].f2[3].taken invalidate tage.io.resp_in[0].f1[0].predicted_pc.bits invalidate tage.io.resp_in[0].f1[0].predicted_pc.valid invalidate tage.io.resp_in[0].f1[0].is_jal invalidate tage.io.resp_in[0].f1[0].is_br invalidate tage.io.resp_in[0].f1[0].taken invalidate tage.io.resp_in[0].f1[1].predicted_pc.bits invalidate tage.io.resp_in[0].f1[1].predicted_pc.valid invalidate tage.io.resp_in[0].f1[1].is_jal invalidate tage.io.resp_in[0].f1[1].is_br invalidate tage.io.resp_in[0].f1[1].taken invalidate tage.io.resp_in[0].f1[2].predicted_pc.bits invalidate tage.io.resp_in[0].f1[2].predicted_pc.valid invalidate tage.io.resp_in[0].f1[2].is_jal invalidate tage.io.resp_in[0].f1[2].is_br invalidate tage.io.resp_in[0].f1[2].taken invalidate tage.io.resp_in[0].f1[3].predicted_pc.bits invalidate tage.io.resp_in[0].f1[3].predicted_pc.valid invalidate tage.io.resp_in[0].f1[3].is_jal invalidate tage.io.resp_in[0].f1[3].is_br invalidate tage.io.resp_in[0].f1[3].taken invalidate tage.io.f1_lhist invalidate tage.io.f1_ghist invalidate tage.io.f0_mask invalidate tage.io.f0_pc invalidate tage.io.f0_valid invalidate btb.io.update.bits.meta invalidate btb.io.update.bits.target invalidate btb.io.update.bits.lhist invalidate btb.io.update.bits.ghist invalidate btb.io.update.bits.cfi_is_jalr invalidate btb.io.update.bits.cfi_is_jal invalidate btb.io.update.bits.cfi_is_br invalidate btb.io.update.bits.cfi_mispredicted invalidate btb.io.update.bits.cfi_taken invalidate btb.io.update.bits.cfi_idx.bits invalidate btb.io.update.bits.cfi_idx.valid invalidate btb.io.update.bits.br_mask invalidate btb.io.update.bits.pc invalidate btb.io.update.bits.btb_mispredicts invalidate btb.io.update.bits.is_repair_update invalidate btb.io.update.bits.is_mispredict_update invalidate btb.io.update.valid invalidate btb.io.f3_fire invalidate btb.io.f3_meta invalidate btb.io.resp.f3[0].predicted_pc.bits invalidate btb.io.resp.f3[0].predicted_pc.valid invalidate btb.io.resp.f3[0].is_jal invalidate btb.io.resp.f3[0].is_br invalidate btb.io.resp.f3[0].taken invalidate btb.io.resp.f3[1].predicted_pc.bits invalidate btb.io.resp.f3[1].predicted_pc.valid invalidate btb.io.resp.f3[1].is_jal invalidate btb.io.resp.f3[1].is_br invalidate btb.io.resp.f3[1].taken invalidate btb.io.resp.f3[2].predicted_pc.bits invalidate btb.io.resp.f3[2].predicted_pc.valid invalidate btb.io.resp.f3[2].is_jal invalidate btb.io.resp.f3[2].is_br invalidate btb.io.resp.f3[2].taken invalidate btb.io.resp.f3[3].predicted_pc.bits invalidate btb.io.resp.f3[3].predicted_pc.valid invalidate btb.io.resp.f3[3].is_jal invalidate btb.io.resp.f3[3].is_br invalidate btb.io.resp.f3[3].taken invalidate btb.io.resp.f2[0].predicted_pc.bits invalidate btb.io.resp.f2[0].predicted_pc.valid invalidate btb.io.resp.f2[0].is_jal invalidate btb.io.resp.f2[0].is_br invalidate btb.io.resp.f2[0].taken invalidate btb.io.resp.f2[1].predicted_pc.bits invalidate btb.io.resp.f2[1].predicted_pc.valid invalidate btb.io.resp.f2[1].is_jal invalidate btb.io.resp.f2[1].is_br invalidate btb.io.resp.f2[1].taken invalidate btb.io.resp.f2[2].predicted_pc.bits invalidate btb.io.resp.f2[2].predicted_pc.valid invalidate btb.io.resp.f2[2].is_jal invalidate btb.io.resp.f2[2].is_br invalidate btb.io.resp.f2[2].taken invalidate btb.io.resp.f2[3].predicted_pc.bits invalidate btb.io.resp.f2[3].predicted_pc.valid invalidate btb.io.resp.f2[3].is_jal invalidate btb.io.resp.f2[3].is_br invalidate btb.io.resp.f2[3].taken invalidate btb.io.resp.f1[0].predicted_pc.bits invalidate btb.io.resp.f1[0].predicted_pc.valid invalidate btb.io.resp.f1[0].is_jal invalidate btb.io.resp.f1[0].is_br invalidate btb.io.resp.f1[0].taken invalidate btb.io.resp.f1[1].predicted_pc.bits invalidate btb.io.resp.f1[1].predicted_pc.valid invalidate btb.io.resp.f1[1].is_jal invalidate btb.io.resp.f1[1].is_br invalidate btb.io.resp.f1[1].taken invalidate btb.io.resp.f1[2].predicted_pc.bits invalidate btb.io.resp.f1[2].predicted_pc.valid invalidate btb.io.resp.f1[2].is_jal invalidate btb.io.resp.f1[2].is_br invalidate btb.io.resp.f1[2].taken invalidate btb.io.resp.f1[3].predicted_pc.bits invalidate btb.io.resp.f1[3].predicted_pc.valid invalidate btb.io.resp.f1[3].is_jal invalidate btb.io.resp.f1[3].is_br invalidate btb.io.resp.f1[3].taken invalidate btb.io.resp_in[0].f3[0].predicted_pc.bits invalidate btb.io.resp_in[0].f3[0].predicted_pc.valid invalidate btb.io.resp_in[0].f3[0].is_jal invalidate btb.io.resp_in[0].f3[0].is_br invalidate btb.io.resp_in[0].f3[0].taken invalidate btb.io.resp_in[0].f3[1].predicted_pc.bits invalidate btb.io.resp_in[0].f3[1].predicted_pc.valid invalidate btb.io.resp_in[0].f3[1].is_jal invalidate btb.io.resp_in[0].f3[1].is_br invalidate btb.io.resp_in[0].f3[1].taken invalidate btb.io.resp_in[0].f3[2].predicted_pc.bits invalidate btb.io.resp_in[0].f3[2].predicted_pc.valid invalidate btb.io.resp_in[0].f3[2].is_jal invalidate btb.io.resp_in[0].f3[2].is_br invalidate btb.io.resp_in[0].f3[2].taken invalidate btb.io.resp_in[0].f3[3].predicted_pc.bits invalidate btb.io.resp_in[0].f3[3].predicted_pc.valid invalidate btb.io.resp_in[0].f3[3].is_jal invalidate btb.io.resp_in[0].f3[3].is_br invalidate btb.io.resp_in[0].f3[3].taken invalidate btb.io.resp_in[0].f2[0].predicted_pc.bits invalidate btb.io.resp_in[0].f2[0].predicted_pc.valid invalidate btb.io.resp_in[0].f2[0].is_jal invalidate btb.io.resp_in[0].f2[0].is_br invalidate btb.io.resp_in[0].f2[0].taken invalidate btb.io.resp_in[0].f2[1].predicted_pc.bits invalidate btb.io.resp_in[0].f2[1].predicted_pc.valid invalidate btb.io.resp_in[0].f2[1].is_jal invalidate btb.io.resp_in[0].f2[1].is_br invalidate btb.io.resp_in[0].f2[1].taken invalidate btb.io.resp_in[0].f2[2].predicted_pc.bits invalidate btb.io.resp_in[0].f2[2].predicted_pc.valid invalidate btb.io.resp_in[0].f2[2].is_jal invalidate btb.io.resp_in[0].f2[2].is_br invalidate btb.io.resp_in[0].f2[2].taken invalidate btb.io.resp_in[0].f2[3].predicted_pc.bits invalidate btb.io.resp_in[0].f2[3].predicted_pc.valid invalidate btb.io.resp_in[0].f2[3].is_jal invalidate btb.io.resp_in[0].f2[3].is_br invalidate btb.io.resp_in[0].f2[3].taken invalidate btb.io.resp_in[0].f1[0].predicted_pc.bits invalidate btb.io.resp_in[0].f1[0].predicted_pc.valid invalidate btb.io.resp_in[0].f1[0].is_jal invalidate btb.io.resp_in[0].f1[0].is_br invalidate btb.io.resp_in[0].f1[0].taken invalidate btb.io.resp_in[0].f1[1].predicted_pc.bits invalidate btb.io.resp_in[0].f1[1].predicted_pc.valid invalidate btb.io.resp_in[0].f1[1].is_jal invalidate btb.io.resp_in[0].f1[1].is_br invalidate btb.io.resp_in[0].f1[1].taken invalidate btb.io.resp_in[0].f1[2].predicted_pc.bits invalidate btb.io.resp_in[0].f1[2].predicted_pc.valid invalidate btb.io.resp_in[0].f1[2].is_jal invalidate btb.io.resp_in[0].f1[2].is_br invalidate btb.io.resp_in[0].f1[2].taken invalidate btb.io.resp_in[0].f1[3].predicted_pc.bits invalidate btb.io.resp_in[0].f1[3].predicted_pc.valid invalidate btb.io.resp_in[0].f1[3].is_jal invalidate btb.io.resp_in[0].f1[3].is_br invalidate btb.io.resp_in[0].f1[3].taken invalidate btb.io.f1_lhist invalidate btb.io.f1_ghist invalidate btb.io.f0_mask invalidate btb.io.f0_pc invalidate btb.io.f0_valid invalidate ubtb.io.update.bits.meta invalidate ubtb.io.update.bits.target invalidate ubtb.io.update.bits.lhist invalidate ubtb.io.update.bits.ghist invalidate ubtb.io.update.bits.cfi_is_jalr invalidate ubtb.io.update.bits.cfi_is_jal invalidate ubtb.io.update.bits.cfi_is_br invalidate ubtb.io.update.bits.cfi_mispredicted invalidate ubtb.io.update.bits.cfi_taken invalidate ubtb.io.update.bits.cfi_idx.bits invalidate ubtb.io.update.bits.cfi_idx.valid invalidate ubtb.io.update.bits.br_mask invalidate ubtb.io.update.bits.pc invalidate ubtb.io.update.bits.btb_mispredicts invalidate ubtb.io.update.bits.is_repair_update invalidate ubtb.io.update.bits.is_mispredict_update invalidate ubtb.io.update.valid invalidate ubtb.io.f3_fire invalidate ubtb.io.f3_meta invalidate ubtb.io.resp.f3[0].predicted_pc.bits invalidate ubtb.io.resp.f3[0].predicted_pc.valid invalidate ubtb.io.resp.f3[0].is_jal invalidate ubtb.io.resp.f3[0].is_br invalidate ubtb.io.resp.f3[0].taken invalidate ubtb.io.resp.f3[1].predicted_pc.bits invalidate ubtb.io.resp.f3[1].predicted_pc.valid invalidate ubtb.io.resp.f3[1].is_jal invalidate ubtb.io.resp.f3[1].is_br invalidate ubtb.io.resp.f3[1].taken invalidate ubtb.io.resp.f3[2].predicted_pc.bits invalidate ubtb.io.resp.f3[2].predicted_pc.valid invalidate ubtb.io.resp.f3[2].is_jal invalidate ubtb.io.resp.f3[2].is_br invalidate ubtb.io.resp.f3[2].taken invalidate ubtb.io.resp.f3[3].predicted_pc.bits invalidate ubtb.io.resp.f3[3].predicted_pc.valid invalidate ubtb.io.resp.f3[3].is_jal invalidate ubtb.io.resp.f3[3].is_br invalidate ubtb.io.resp.f3[3].taken invalidate ubtb.io.resp.f2[0].predicted_pc.bits invalidate ubtb.io.resp.f2[0].predicted_pc.valid invalidate ubtb.io.resp.f2[0].is_jal invalidate ubtb.io.resp.f2[0].is_br invalidate ubtb.io.resp.f2[0].taken invalidate ubtb.io.resp.f2[1].predicted_pc.bits invalidate ubtb.io.resp.f2[1].predicted_pc.valid invalidate ubtb.io.resp.f2[1].is_jal invalidate ubtb.io.resp.f2[1].is_br invalidate ubtb.io.resp.f2[1].taken invalidate ubtb.io.resp.f2[2].predicted_pc.bits invalidate ubtb.io.resp.f2[2].predicted_pc.valid invalidate ubtb.io.resp.f2[2].is_jal invalidate ubtb.io.resp.f2[2].is_br invalidate ubtb.io.resp.f2[2].taken invalidate ubtb.io.resp.f2[3].predicted_pc.bits invalidate ubtb.io.resp.f2[3].predicted_pc.valid invalidate ubtb.io.resp.f2[3].is_jal invalidate ubtb.io.resp.f2[3].is_br invalidate ubtb.io.resp.f2[3].taken invalidate ubtb.io.resp.f1[0].predicted_pc.bits invalidate ubtb.io.resp.f1[0].predicted_pc.valid invalidate ubtb.io.resp.f1[0].is_jal invalidate ubtb.io.resp.f1[0].is_br invalidate ubtb.io.resp.f1[0].taken invalidate ubtb.io.resp.f1[1].predicted_pc.bits invalidate ubtb.io.resp.f1[1].predicted_pc.valid invalidate ubtb.io.resp.f1[1].is_jal invalidate ubtb.io.resp.f1[1].is_br invalidate ubtb.io.resp.f1[1].taken invalidate ubtb.io.resp.f1[2].predicted_pc.bits invalidate ubtb.io.resp.f1[2].predicted_pc.valid invalidate ubtb.io.resp.f1[2].is_jal invalidate ubtb.io.resp.f1[2].is_br invalidate ubtb.io.resp.f1[2].taken invalidate ubtb.io.resp.f1[3].predicted_pc.bits invalidate ubtb.io.resp.f1[3].predicted_pc.valid invalidate ubtb.io.resp.f1[3].is_jal invalidate ubtb.io.resp.f1[3].is_br invalidate ubtb.io.resp.f1[3].taken invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[0].is_jal invalidate ubtb.io.resp_in[0].f3[0].is_br invalidate ubtb.io.resp_in[0].f3[0].taken invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[1].is_jal invalidate ubtb.io.resp_in[0].f3[1].is_br invalidate ubtb.io.resp_in[0].f3[1].taken invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[2].is_jal invalidate ubtb.io.resp_in[0].f3[2].is_br invalidate ubtb.io.resp_in[0].f3[2].taken invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[3].is_jal invalidate ubtb.io.resp_in[0].f3[3].is_br invalidate ubtb.io.resp_in[0].f3[3].taken invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[0].is_jal invalidate ubtb.io.resp_in[0].f2[0].is_br invalidate ubtb.io.resp_in[0].f2[0].taken invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[1].is_jal invalidate ubtb.io.resp_in[0].f2[1].is_br invalidate ubtb.io.resp_in[0].f2[1].taken invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[2].is_jal invalidate ubtb.io.resp_in[0].f2[2].is_br invalidate ubtb.io.resp_in[0].f2[2].taken invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[3].is_jal invalidate ubtb.io.resp_in[0].f2[3].is_br invalidate ubtb.io.resp_in[0].f2[3].taken invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[0].is_jal invalidate ubtb.io.resp_in[0].f1[0].is_br invalidate ubtb.io.resp_in[0].f1[0].taken invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[1].is_jal invalidate ubtb.io.resp_in[0].f1[1].is_br invalidate ubtb.io.resp_in[0].f1[1].taken invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[2].is_jal invalidate ubtb.io.resp_in[0].f1[2].is_br invalidate ubtb.io.resp_in[0].f1[2].taken invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[3].is_jal invalidate ubtb.io.resp_in[0].f1[3].is_br invalidate ubtb.io.resp_in[0].f1[3].taken invalidate ubtb.io.f1_lhist invalidate ubtb.io.f1_ghist invalidate ubtb.io.f0_mask invalidate ubtb.io.f0_pc invalidate ubtb.io.f0_valid invalidate bim.io.update.bits.meta invalidate bim.io.update.bits.target invalidate bim.io.update.bits.lhist invalidate bim.io.update.bits.ghist invalidate bim.io.update.bits.cfi_is_jalr invalidate bim.io.update.bits.cfi_is_jal invalidate bim.io.update.bits.cfi_is_br invalidate bim.io.update.bits.cfi_mispredicted invalidate bim.io.update.bits.cfi_taken invalidate bim.io.update.bits.cfi_idx.bits invalidate bim.io.update.bits.cfi_idx.valid invalidate bim.io.update.bits.br_mask invalidate bim.io.update.bits.pc invalidate bim.io.update.bits.btb_mispredicts invalidate bim.io.update.bits.is_repair_update invalidate bim.io.update.bits.is_mispredict_update invalidate bim.io.update.valid invalidate bim.io.f3_fire invalidate bim.io.f3_meta invalidate bim.io.resp.f3[0].predicted_pc.bits invalidate bim.io.resp.f3[0].predicted_pc.valid invalidate bim.io.resp.f3[0].is_jal invalidate bim.io.resp.f3[0].is_br invalidate bim.io.resp.f3[0].taken invalidate bim.io.resp.f3[1].predicted_pc.bits invalidate bim.io.resp.f3[1].predicted_pc.valid invalidate bim.io.resp.f3[1].is_jal invalidate bim.io.resp.f3[1].is_br invalidate bim.io.resp.f3[1].taken invalidate bim.io.resp.f3[2].predicted_pc.bits invalidate bim.io.resp.f3[2].predicted_pc.valid invalidate bim.io.resp.f3[2].is_jal invalidate bim.io.resp.f3[2].is_br invalidate bim.io.resp.f3[2].taken invalidate bim.io.resp.f3[3].predicted_pc.bits invalidate bim.io.resp.f3[3].predicted_pc.valid invalidate bim.io.resp.f3[3].is_jal invalidate bim.io.resp.f3[3].is_br invalidate bim.io.resp.f3[3].taken invalidate bim.io.resp.f2[0].predicted_pc.bits invalidate bim.io.resp.f2[0].predicted_pc.valid invalidate bim.io.resp.f2[0].is_jal invalidate bim.io.resp.f2[0].is_br invalidate bim.io.resp.f2[0].taken invalidate bim.io.resp.f2[1].predicted_pc.bits invalidate bim.io.resp.f2[1].predicted_pc.valid invalidate bim.io.resp.f2[1].is_jal invalidate bim.io.resp.f2[1].is_br invalidate bim.io.resp.f2[1].taken invalidate bim.io.resp.f2[2].predicted_pc.bits invalidate bim.io.resp.f2[2].predicted_pc.valid invalidate bim.io.resp.f2[2].is_jal invalidate bim.io.resp.f2[2].is_br invalidate bim.io.resp.f2[2].taken invalidate bim.io.resp.f2[3].predicted_pc.bits invalidate bim.io.resp.f2[3].predicted_pc.valid invalidate bim.io.resp.f2[3].is_jal invalidate bim.io.resp.f2[3].is_br invalidate bim.io.resp.f2[3].taken invalidate bim.io.resp.f1[0].predicted_pc.bits invalidate bim.io.resp.f1[0].predicted_pc.valid invalidate bim.io.resp.f1[0].is_jal invalidate bim.io.resp.f1[0].is_br invalidate bim.io.resp.f1[0].taken invalidate bim.io.resp.f1[1].predicted_pc.bits invalidate bim.io.resp.f1[1].predicted_pc.valid invalidate bim.io.resp.f1[1].is_jal invalidate bim.io.resp.f1[1].is_br invalidate bim.io.resp.f1[1].taken invalidate bim.io.resp.f1[2].predicted_pc.bits invalidate bim.io.resp.f1[2].predicted_pc.valid invalidate bim.io.resp.f1[2].is_jal invalidate bim.io.resp.f1[2].is_br invalidate bim.io.resp.f1[2].taken invalidate bim.io.resp.f1[3].predicted_pc.bits invalidate bim.io.resp.f1[3].predicted_pc.valid invalidate bim.io.resp.f1[3].is_jal invalidate bim.io.resp.f1[3].is_br invalidate bim.io.resp.f1[3].taken invalidate bim.io.resp_in[0].f3[0].predicted_pc.bits invalidate bim.io.resp_in[0].f3[0].predicted_pc.valid invalidate bim.io.resp_in[0].f3[0].is_jal invalidate bim.io.resp_in[0].f3[0].is_br invalidate bim.io.resp_in[0].f3[0].taken invalidate bim.io.resp_in[0].f3[1].predicted_pc.bits invalidate bim.io.resp_in[0].f3[1].predicted_pc.valid invalidate bim.io.resp_in[0].f3[1].is_jal invalidate bim.io.resp_in[0].f3[1].is_br invalidate bim.io.resp_in[0].f3[1].taken invalidate bim.io.resp_in[0].f3[2].predicted_pc.bits invalidate bim.io.resp_in[0].f3[2].predicted_pc.valid invalidate bim.io.resp_in[0].f3[2].is_jal invalidate bim.io.resp_in[0].f3[2].is_br invalidate bim.io.resp_in[0].f3[2].taken invalidate bim.io.resp_in[0].f3[3].predicted_pc.bits invalidate bim.io.resp_in[0].f3[3].predicted_pc.valid invalidate bim.io.resp_in[0].f3[3].is_jal invalidate bim.io.resp_in[0].f3[3].is_br invalidate bim.io.resp_in[0].f3[3].taken invalidate bim.io.resp_in[0].f2[0].predicted_pc.bits invalidate bim.io.resp_in[0].f2[0].predicted_pc.valid invalidate bim.io.resp_in[0].f2[0].is_jal invalidate bim.io.resp_in[0].f2[0].is_br invalidate bim.io.resp_in[0].f2[0].taken invalidate bim.io.resp_in[0].f2[1].predicted_pc.bits invalidate bim.io.resp_in[0].f2[1].predicted_pc.valid invalidate bim.io.resp_in[0].f2[1].is_jal invalidate bim.io.resp_in[0].f2[1].is_br invalidate bim.io.resp_in[0].f2[1].taken invalidate bim.io.resp_in[0].f2[2].predicted_pc.bits invalidate bim.io.resp_in[0].f2[2].predicted_pc.valid invalidate bim.io.resp_in[0].f2[2].is_jal invalidate bim.io.resp_in[0].f2[2].is_br invalidate bim.io.resp_in[0].f2[2].taken invalidate bim.io.resp_in[0].f2[3].predicted_pc.bits invalidate bim.io.resp_in[0].f2[3].predicted_pc.valid invalidate bim.io.resp_in[0].f2[3].is_jal invalidate bim.io.resp_in[0].f2[3].is_br invalidate bim.io.resp_in[0].f2[3].taken invalidate bim.io.resp_in[0].f1[0].predicted_pc.bits invalidate bim.io.resp_in[0].f1[0].predicted_pc.valid invalidate bim.io.resp_in[0].f1[0].is_jal invalidate bim.io.resp_in[0].f1[0].is_br invalidate bim.io.resp_in[0].f1[0].taken invalidate bim.io.resp_in[0].f1[1].predicted_pc.bits invalidate bim.io.resp_in[0].f1[1].predicted_pc.valid invalidate bim.io.resp_in[0].f1[1].is_jal invalidate bim.io.resp_in[0].f1[1].is_br invalidate bim.io.resp_in[0].f1[1].taken invalidate bim.io.resp_in[0].f1[2].predicted_pc.bits invalidate bim.io.resp_in[0].f1[2].predicted_pc.valid invalidate bim.io.resp_in[0].f1[2].is_jal invalidate bim.io.resp_in[0].f1[2].is_br invalidate bim.io.resp_in[0].f1[2].taken invalidate bim.io.resp_in[0].f1[3].predicted_pc.bits invalidate bim.io.resp_in[0].f1[3].predicted_pc.valid invalidate bim.io.resp_in[0].f1[3].is_jal invalidate bim.io.resp_in[0].f1[3].is_br invalidate bim.io.resp_in[0].f1[3].taken invalidate bim.io.f1_lhist invalidate bim.io.f1_ghist invalidate bim.io.f0_mask invalidate bim.io.f0_pc invalidate bim.io.f0_valid connect ubtb.io.resp_in[0].f3[0].predicted_pc.bits, io.resp_in[0].f3[0].predicted_pc.bits connect ubtb.io.resp_in[0].f3[0].predicted_pc.valid, io.resp_in[0].f3[0].predicted_pc.valid connect ubtb.io.resp_in[0].f3[0].is_jal, io.resp_in[0].f3[0].is_jal connect ubtb.io.resp_in[0].f3[0].is_br, io.resp_in[0].f3[0].is_br connect ubtb.io.resp_in[0].f3[0].taken, io.resp_in[0].f3[0].taken connect ubtb.io.resp_in[0].f3[1].predicted_pc.bits, io.resp_in[0].f3[1].predicted_pc.bits connect ubtb.io.resp_in[0].f3[1].predicted_pc.valid, io.resp_in[0].f3[1].predicted_pc.valid connect ubtb.io.resp_in[0].f3[1].is_jal, io.resp_in[0].f3[1].is_jal connect ubtb.io.resp_in[0].f3[1].is_br, io.resp_in[0].f3[1].is_br connect ubtb.io.resp_in[0].f3[1].taken, io.resp_in[0].f3[1].taken connect ubtb.io.resp_in[0].f3[2].predicted_pc.bits, io.resp_in[0].f3[2].predicted_pc.bits connect ubtb.io.resp_in[0].f3[2].predicted_pc.valid, io.resp_in[0].f3[2].predicted_pc.valid connect ubtb.io.resp_in[0].f3[2].is_jal, io.resp_in[0].f3[2].is_jal connect ubtb.io.resp_in[0].f3[2].is_br, io.resp_in[0].f3[2].is_br connect ubtb.io.resp_in[0].f3[2].taken, io.resp_in[0].f3[2].taken connect ubtb.io.resp_in[0].f3[3].predicted_pc.bits, io.resp_in[0].f3[3].predicted_pc.bits connect ubtb.io.resp_in[0].f3[3].predicted_pc.valid, io.resp_in[0].f3[3].predicted_pc.valid connect ubtb.io.resp_in[0].f3[3].is_jal, io.resp_in[0].f3[3].is_jal connect ubtb.io.resp_in[0].f3[3].is_br, io.resp_in[0].f3[3].is_br connect ubtb.io.resp_in[0].f3[3].taken, io.resp_in[0].f3[3].taken connect ubtb.io.resp_in[0].f2[0].predicted_pc.bits, io.resp_in[0].f2[0].predicted_pc.bits connect ubtb.io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].predicted_pc.valid connect ubtb.io.resp_in[0].f2[0].is_jal, io.resp_in[0].f2[0].is_jal connect ubtb.io.resp_in[0].f2[0].is_br, io.resp_in[0].f2[0].is_br connect ubtb.io.resp_in[0].f2[0].taken, io.resp_in[0].f2[0].taken connect ubtb.io.resp_in[0].f2[1].predicted_pc.bits, io.resp_in[0].f2[1].predicted_pc.bits connect ubtb.io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].predicted_pc.valid connect ubtb.io.resp_in[0].f2[1].is_jal, io.resp_in[0].f2[1].is_jal connect ubtb.io.resp_in[0].f2[1].is_br, io.resp_in[0].f2[1].is_br connect ubtb.io.resp_in[0].f2[1].taken, io.resp_in[0].f2[1].taken connect ubtb.io.resp_in[0].f2[2].predicted_pc.bits, io.resp_in[0].f2[2].predicted_pc.bits connect ubtb.io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].predicted_pc.valid connect ubtb.io.resp_in[0].f2[2].is_jal, io.resp_in[0].f2[2].is_jal connect ubtb.io.resp_in[0].f2[2].is_br, io.resp_in[0].f2[2].is_br connect ubtb.io.resp_in[0].f2[2].taken, io.resp_in[0].f2[2].taken connect ubtb.io.resp_in[0].f2[3].predicted_pc.bits, io.resp_in[0].f2[3].predicted_pc.bits connect ubtb.io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].predicted_pc.valid connect ubtb.io.resp_in[0].f2[3].is_jal, io.resp_in[0].f2[3].is_jal connect ubtb.io.resp_in[0].f2[3].is_br, io.resp_in[0].f2[3].is_br connect ubtb.io.resp_in[0].f2[3].taken, io.resp_in[0].f2[3].taken connect ubtb.io.resp_in[0].f1[0].predicted_pc.bits, io.resp_in[0].f1[0].predicted_pc.bits connect ubtb.io.resp_in[0].f1[0].predicted_pc.valid, io.resp_in[0].f1[0].predicted_pc.valid connect ubtb.io.resp_in[0].f1[0].is_jal, io.resp_in[0].f1[0].is_jal connect ubtb.io.resp_in[0].f1[0].is_br, io.resp_in[0].f1[0].is_br connect ubtb.io.resp_in[0].f1[0].taken, io.resp_in[0].f1[0].taken connect ubtb.io.resp_in[0].f1[1].predicted_pc.bits, io.resp_in[0].f1[1].predicted_pc.bits connect ubtb.io.resp_in[0].f1[1].predicted_pc.valid, io.resp_in[0].f1[1].predicted_pc.valid connect ubtb.io.resp_in[0].f1[1].is_jal, io.resp_in[0].f1[1].is_jal connect ubtb.io.resp_in[0].f1[1].is_br, io.resp_in[0].f1[1].is_br connect ubtb.io.resp_in[0].f1[1].taken, io.resp_in[0].f1[1].taken connect ubtb.io.resp_in[0].f1[2].predicted_pc.bits, io.resp_in[0].f1[2].predicted_pc.bits connect ubtb.io.resp_in[0].f1[2].predicted_pc.valid, io.resp_in[0].f1[2].predicted_pc.valid connect ubtb.io.resp_in[0].f1[2].is_jal, io.resp_in[0].f1[2].is_jal connect ubtb.io.resp_in[0].f1[2].is_br, io.resp_in[0].f1[2].is_br connect ubtb.io.resp_in[0].f1[2].taken, io.resp_in[0].f1[2].taken connect ubtb.io.resp_in[0].f1[3].predicted_pc.bits, io.resp_in[0].f1[3].predicted_pc.bits connect ubtb.io.resp_in[0].f1[3].predicted_pc.valid, io.resp_in[0].f1[3].predicted_pc.valid connect ubtb.io.resp_in[0].f1[3].is_jal, io.resp_in[0].f1[3].is_jal connect ubtb.io.resp_in[0].f1[3].is_br, io.resp_in[0].f1[3].is_br connect ubtb.io.resp_in[0].f1[3].taken, io.resp_in[0].f1[3].taken connect bim.io.resp_in[0].f3[0].predicted_pc.bits, ubtb.io.resp.f3[0].predicted_pc.bits connect bim.io.resp_in[0].f3[0].predicted_pc.valid, ubtb.io.resp.f3[0].predicted_pc.valid connect bim.io.resp_in[0].f3[0].is_jal, ubtb.io.resp.f3[0].is_jal connect bim.io.resp_in[0].f3[0].is_br, ubtb.io.resp.f3[0].is_br connect bim.io.resp_in[0].f3[0].taken, ubtb.io.resp.f3[0].taken connect bim.io.resp_in[0].f3[1].predicted_pc.bits, ubtb.io.resp.f3[1].predicted_pc.bits connect bim.io.resp_in[0].f3[1].predicted_pc.valid, ubtb.io.resp.f3[1].predicted_pc.valid connect bim.io.resp_in[0].f3[1].is_jal, ubtb.io.resp.f3[1].is_jal connect bim.io.resp_in[0].f3[1].is_br, ubtb.io.resp.f3[1].is_br connect bim.io.resp_in[0].f3[1].taken, ubtb.io.resp.f3[1].taken connect bim.io.resp_in[0].f3[2].predicted_pc.bits, ubtb.io.resp.f3[2].predicted_pc.bits connect bim.io.resp_in[0].f3[2].predicted_pc.valid, ubtb.io.resp.f3[2].predicted_pc.valid connect bim.io.resp_in[0].f3[2].is_jal, ubtb.io.resp.f3[2].is_jal connect bim.io.resp_in[0].f3[2].is_br, ubtb.io.resp.f3[2].is_br connect bim.io.resp_in[0].f3[2].taken, ubtb.io.resp.f3[2].taken connect bim.io.resp_in[0].f3[3].predicted_pc.bits, ubtb.io.resp.f3[3].predicted_pc.bits connect bim.io.resp_in[0].f3[3].predicted_pc.valid, ubtb.io.resp.f3[3].predicted_pc.valid connect bim.io.resp_in[0].f3[3].is_jal, ubtb.io.resp.f3[3].is_jal connect bim.io.resp_in[0].f3[3].is_br, ubtb.io.resp.f3[3].is_br connect bim.io.resp_in[0].f3[3].taken, ubtb.io.resp.f3[3].taken connect bim.io.resp_in[0].f2[0].predicted_pc.bits, ubtb.io.resp.f2[0].predicted_pc.bits connect bim.io.resp_in[0].f2[0].predicted_pc.valid, ubtb.io.resp.f2[0].predicted_pc.valid connect bim.io.resp_in[0].f2[0].is_jal, ubtb.io.resp.f2[0].is_jal connect bim.io.resp_in[0].f2[0].is_br, ubtb.io.resp.f2[0].is_br connect bim.io.resp_in[0].f2[0].taken, ubtb.io.resp.f2[0].taken connect bim.io.resp_in[0].f2[1].predicted_pc.bits, ubtb.io.resp.f2[1].predicted_pc.bits connect bim.io.resp_in[0].f2[1].predicted_pc.valid, ubtb.io.resp.f2[1].predicted_pc.valid connect bim.io.resp_in[0].f2[1].is_jal, ubtb.io.resp.f2[1].is_jal connect bim.io.resp_in[0].f2[1].is_br, ubtb.io.resp.f2[1].is_br connect bim.io.resp_in[0].f2[1].taken, ubtb.io.resp.f2[1].taken connect bim.io.resp_in[0].f2[2].predicted_pc.bits, ubtb.io.resp.f2[2].predicted_pc.bits connect bim.io.resp_in[0].f2[2].predicted_pc.valid, ubtb.io.resp.f2[2].predicted_pc.valid connect bim.io.resp_in[0].f2[2].is_jal, ubtb.io.resp.f2[2].is_jal connect bim.io.resp_in[0].f2[2].is_br, ubtb.io.resp.f2[2].is_br connect bim.io.resp_in[0].f2[2].taken, ubtb.io.resp.f2[2].taken connect bim.io.resp_in[0].f2[3].predicted_pc.bits, ubtb.io.resp.f2[3].predicted_pc.bits connect bim.io.resp_in[0].f2[3].predicted_pc.valid, ubtb.io.resp.f2[3].predicted_pc.valid connect bim.io.resp_in[0].f2[3].is_jal, ubtb.io.resp.f2[3].is_jal connect bim.io.resp_in[0].f2[3].is_br, ubtb.io.resp.f2[3].is_br connect bim.io.resp_in[0].f2[3].taken, ubtb.io.resp.f2[3].taken connect bim.io.resp_in[0].f1[0].predicted_pc.bits, ubtb.io.resp.f1[0].predicted_pc.bits connect bim.io.resp_in[0].f1[0].predicted_pc.valid, ubtb.io.resp.f1[0].predicted_pc.valid connect bim.io.resp_in[0].f1[0].is_jal, ubtb.io.resp.f1[0].is_jal connect bim.io.resp_in[0].f1[0].is_br, ubtb.io.resp.f1[0].is_br connect bim.io.resp_in[0].f1[0].taken, ubtb.io.resp.f1[0].taken connect bim.io.resp_in[0].f1[1].predicted_pc.bits, ubtb.io.resp.f1[1].predicted_pc.bits connect bim.io.resp_in[0].f1[1].predicted_pc.valid, ubtb.io.resp.f1[1].predicted_pc.valid connect bim.io.resp_in[0].f1[1].is_jal, ubtb.io.resp.f1[1].is_jal connect bim.io.resp_in[0].f1[1].is_br, ubtb.io.resp.f1[1].is_br connect bim.io.resp_in[0].f1[1].taken, ubtb.io.resp.f1[1].taken connect bim.io.resp_in[0].f1[2].predicted_pc.bits, ubtb.io.resp.f1[2].predicted_pc.bits connect bim.io.resp_in[0].f1[2].predicted_pc.valid, ubtb.io.resp.f1[2].predicted_pc.valid connect bim.io.resp_in[0].f1[2].is_jal, ubtb.io.resp.f1[2].is_jal connect bim.io.resp_in[0].f1[2].is_br, ubtb.io.resp.f1[2].is_br connect bim.io.resp_in[0].f1[2].taken, ubtb.io.resp.f1[2].taken connect bim.io.resp_in[0].f1[3].predicted_pc.bits, ubtb.io.resp.f1[3].predicted_pc.bits connect bim.io.resp_in[0].f1[3].predicted_pc.valid, ubtb.io.resp.f1[3].predicted_pc.valid connect bim.io.resp_in[0].f1[3].is_jal, ubtb.io.resp.f1[3].is_jal connect bim.io.resp_in[0].f1[3].is_br, ubtb.io.resp.f1[3].is_br connect bim.io.resp_in[0].f1[3].taken, ubtb.io.resp.f1[3].taken connect btb.io.resp_in[0].f3[0].predicted_pc.bits, bim.io.resp.f3[0].predicted_pc.bits connect btb.io.resp_in[0].f3[0].predicted_pc.valid, bim.io.resp.f3[0].predicted_pc.valid connect btb.io.resp_in[0].f3[0].is_jal, bim.io.resp.f3[0].is_jal connect btb.io.resp_in[0].f3[0].is_br, bim.io.resp.f3[0].is_br connect btb.io.resp_in[0].f3[0].taken, bim.io.resp.f3[0].taken connect btb.io.resp_in[0].f3[1].predicted_pc.bits, bim.io.resp.f3[1].predicted_pc.bits connect btb.io.resp_in[0].f3[1].predicted_pc.valid, bim.io.resp.f3[1].predicted_pc.valid connect btb.io.resp_in[0].f3[1].is_jal, bim.io.resp.f3[1].is_jal connect btb.io.resp_in[0].f3[1].is_br, bim.io.resp.f3[1].is_br connect btb.io.resp_in[0].f3[1].taken, bim.io.resp.f3[1].taken connect btb.io.resp_in[0].f3[2].predicted_pc.bits, bim.io.resp.f3[2].predicted_pc.bits connect btb.io.resp_in[0].f3[2].predicted_pc.valid, bim.io.resp.f3[2].predicted_pc.valid connect btb.io.resp_in[0].f3[2].is_jal, bim.io.resp.f3[2].is_jal connect btb.io.resp_in[0].f3[2].is_br, bim.io.resp.f3[2].is_br connect btb.io.resp_in[0].f3[2].taken, bim.io.resp.f3[2].taken connect btb.io.resp_in[0].f3[3].predicted_pc.bits, bim.io.resp.f3[3].predicted_pc.bits connect btb.io.resp_in[0].f3[3].predicted_pc.valid, bim.io.resp.f3[3].predicted_pc.valid connect btb.io.resp_in[0].f3[3].is_jal, bim.io.resp.f3[3].is_jal connect btb.io.resp_in[0].f3[3].is_br, bim.io.resp.f3[3].is_br connect btb.io.resp_in[0].f3[3].taken, bim.io.resp.f3[3].taken connect btb.io.resp_in[0].f2[0].predicted_pc.bits, bim.io.resp.f2[0].predicted_pc.bits connect btb.io.resp_in[0].f2[0].predicted_pc.valid, bim.io.resp.f2[0].predicted_pc.valid connect btb.io.resp_in[0].f2[0].is_jal, bim.io.resp.f2[0].is_jal connect btb.io.resp_in[0].f2[0].is_br, bim.io.resp.f2[0].is_br connect btb.io.resp_in[0].f2[0].taken, bim.io.resp.f2[0].taken connect btb.io.resp_in[0].f2[1].predicted_pc.bits, bim.io.resp.f2[1].predicted_pc.bits connect btb.io.resp_in[0].f2[1].predicted_pc.valid, bim.io.resp.f2[1].predicted_pc.valid connect btb.io.resp_in[0].f2[1].is_jal, bim.io.resp.f2[1].is_jal connect btb.io.resp_in[0].f2[1].is_br, bim.io.resp.f2[1].is_br connect btb.io.resp_in[0].f2[1].taken, bim.io.resp.f2[1].taken connect btb.io.resp_in[0].f2[2].predicted_pc.bits, bim.io.resp.f2[2].predicted_pc.bits connect btb.io.resp_in[0].f2[2].predicted_pc.valid, bim.io.resp.f2[2].predicted_pc.valid connect btb.io.resp_in[0].f2[2].is_jal, bim.io.resp.f2[2].is_jal connect btb.io.resp_in[0].f2[2].is_br, bim.io.resp.f2[2].is_br connect btb.io.resp_in[0].f2[2].taken, bim.io.resp.f2[2].taken connect btb.io.resp_in[0].f2[3].predicted_pc.bits, bim.io.resp.f2[3].predicted_pc.bits connect btb.io.resp_in[0].f2[3].predicted_pc.valid, bim.io.resp.f2[3].predicted_pc.valid connect btb.io.resp_in[0].f2[3].is_jal, bim.io.resp.f2[3].is_jal connect btb.io.resp_in[0].f2[3].is_br, bim.io.resp.f2[3].is_br connect btb.io.resp_in[0].f2[3].taken, bim.io.resp.f2[3].taken connect btb.io.resp_in[0].f1[0].predicted_pc.bits, bim.io.resp.f1[0].predicted_pc.bits connect btb.io.resp_in[0].f1[0].predicted_pc.valid, bim.io.resp.f1[0].predicted_pc.valid connect btb.io.resp_in[0].f1[0].is_jal, bim.io.resp.f1[0].is_jal connect btb.io.resp_in[0].f1[0].is_br, bim.io.resp.f1[0].is_br connect btb.io.resp_in[0].f1[0].taken, bim.io.resp.f1[0].taken connect btb.io.resp_in[0].f1[1].predicted_pc.bits, bim.io.resp.f1[1].predicted_pc.bits connect btb.io.resp_in[0].f1[1].predicted_pc.valid, bim.io.resp.f1[1].predicted_pc.valid connect btb.io.resp_in[0].f1[1].is_jal, bim.io.resp.f1[1].is_jal connect btb.io.resp_in[0].f1[1].is_br, bim.io.resp.f1[1].is_br connect btb.io.resp_in[0].f1[1].taken, bim.io.resp.f1[1].taken connect btb.io.resp_in[0].f1[2].predicted_pc.bits, bim.io.resp.f1[2].predicted_pc.bits connect btb.io.resp_in[0].f1[2].predicted_pc.valid, bim.io.resp.f1[2].predicted_pc.valid connect btb.io.resp_in[0].f1[2].is_jal, bim.io.resp.f1[2].is_jal connect btb.io.resp_in[0].f1[2].is_br, bim.io.resp.f1[2].is_br connect btb.io.resp_in[0].f1[2].taken, bim.io.resp.f1[2].taken connect btb.io.resp_in[0].f1[3].predicted_pc.bits, bim.io.resp.f1[3].predicted_pc.bits connect btb.io.resp_in[0].f1[3].predicted_pc.valid, bim.io.resp.f1[3].predicted_pc.valid connect btb.io.resp_in[0].f1[3].is_jal, bim.io.resp.f1[3].is_jal connect btb.io.resp_in[0].f1[3].is_br, bim.io.resp.f1[3].is_br connect btb.io.resp_in[0].f1[3].taken, bim.io.resp.f1[3].taken connect tage.io.resp_in[0].f3[0].predicted_pc.bits, btb.io.resp.f3[0].predicted_pc.bits connect tage.io.resp_in[0].f3[0].predicted_pc.valid, btb.io.resp.f3[0].predicted_pc.valid connect tage.io.resp_in[0].f3[0].is_jal, btb.io.resp.f3[0].is_jal connect tage.io.resp_in[0].f3[0].is_br, btb.io.resp.f3[0].is_br connect tage.io.resp_in[0].f3[0].taken, btb.io.resp.f3[0].taken connect tage.io.resp_in[0].f3[1].predicted_pc.bits, btb.io.resp.f3[1].predicted_pc.bits connect tage.io.resp_in[0].f3[1].predicted_pc.valid, btb.io.resp.f3[1].predicted_pc.valid connect tage.io.resp_in[0].f3[1].is_jal, btb.io.resp.f3[1].is_jal connect tage.io.resp_in[0].f3[1].is_br, btb.io.resp.f3[1].is_br connect tage.io.resp_in[0].f3[1].taken, btb.io.resp.f3[1].taken connect tage.io.resp_in[0].f3[2].predicted_pc.bits, btb.io.resp.f3[2].predicted_pc.bits connect tage.io.resp_in[0].f3[2].predicted_pc.valid, btb.io.resp.f3[2].predicted_pc.valid connect tage.io.resp_in[0].f3[2].is_jal, btb.io.resp.f3[2].is_jal connect tage.io.resp_in[0].f3[2].is_br, btb.io.resp.f3[2].is_br connect tage.io.resp_in[0].f3[2].taken, btb.io.resp.f3[2].taken connect tage.io.resp_in[0].f3[3].predicted_pc.bits, btb.io.resp.f3[3].predicted_pc.bits connect tage.io.resp_in[0].f3[3].predicted_pc.valid, btb.io.resp.f3[3].predicted_pc.valid connect tage.io.resp_in[0].f3[3].is_jal, btb.io.resp.f3[3].is_jal connect tage.io.resp_in[0].f3[3].is_br, btb.io.resp.f3[3].is_br connect tage.io.resp_in[0].f3[3].taken, btb.io.resp.f3[3].taken connect tage.io.resp_in[0].f2[0].predicted_pc.bits, btb.io.resp.f2[0].predicted_pc.bits connect tage.io.resp_in[0].f2[0].predicted_pc.valid, btb.io.resp.f2[0].predicted_pc.valid connect tage.io.resp_in[0].f2[0].is_jal, btb.io.resp.f2[0].is_jal connect tage.io.resp_in[0].f2[0].is_br, btb.io.resp.f2[0].is_br connect tage.io.resp_in[0].f2[0].taken, btb.io.resp.f2[0].taken connect tage.io.resp_in[0].f2[1].predicted_pc.bits, btb.io.resp.f2[1].predicted_pc.bits connect tage.io.resp_in[0].f2[1].predicted_pc.valid, btb.io.resp.f2[1].predicted_pc.valid connect tage.io.resp_in[0].f2[1].is_jal, btb.io.resp.f2[1].is_jal connect tage.io.resp_in[0].f2[1].is_br, btb.io.resp.f2[1].is_br connect tage.io.resp_in[0].f2[1].taken, btb.io.resp.f2[1].taken connect tage.io.resp_in[0].f2[2].predicted_pc.bits, btb.io.resp.f2[2].predicted_pc.bits connect tage.io.resp_in[0].f2[2].predicted_pc.valid, btb.io.resp.f2[2].predicted_pc.valid connect tage.io.resp_in[0].f2[2].is_jal, btb.io.resp.f2[2].is_jal connect tage.io.resp_in[0].f2[2].is_br, btb.io.resp.f2[2].is_br connect tage.io.resp_in[0].f2[2].taken, btb.io.resp.f2[2].taken connect tage.io.resp_in[0].f2[3].predicted_pc.bits, btb.io.resp.f2[3].predicted_pc.bits connect tage.io.resp_in[0].f2[3].predicted_pc.valid, btb.io.resp.f2[3].predicted_pc.valid connect tage.io.resp_in[0].f2[3].is_jal, btb.io.resp.f2[3].is_jal connect tage.io.resp_in[0].f2[3].is_br, btb.io.resp.f2[3].is_br connect tage.io.resp_in[0].f2[3].taken, btb.io.resp.f2[3].taken connect tage.io.resp_in[0].f1[0].predicted_pc.bits, btb.io.resp.f1[0].predicted_pc.bits connect tage.io.resp_in[0].f1[0].predicted_pc.valid, btb.io.resp.f1[0].predicted_pc.valid connect tage.io.resp_in[0].f1[0].is_jal, btb.io.resp.f1[0].is_jal connect tage.io.resp_in[0].f1[0].is_br, btb.io.resp.f1[0].is_br connect tage.io.resp_in[0].f1[0].taken, btb.io.resp.f1[0].taken connect tage.io.resp_in[0].f1[1].predicted_pc.bits, btb.io.resp.f1[1].predicted_pc.bits connect tage.io.resp_in[0].f1[1].predicted_pc.valid, btb.io.resp.f1[1].predicted_pc.valid connect tage.io.resp_in[0].f1[1].is_jal, btb.io.resp.f1[1].is_jal connect tage.io.resp_in[0].f1[1].is_br, btb.io.resp.f1[1].is_br connect tage.io.resp_in[0].f1[1].taken, btb.io.resp.f1[1].taken connect tage.io.resp_in[0].f1[2].predicted_pc.bits, btb.io.resp.f1[2].predicted_pc.bits connect tage.io.resp_in[0].f1[2].predicted_pc.valid, btb.io.resp.f1[2].predicted_pc.valid connect tage.io.resp_in[0].f1[2].is_jal, btb.io.resp.f1[2].is_jal connect tage.io.resp_in[0].f1[2].is_br, btb.io.resp.f1[2].is_br connect tage.io.resp_in[0].f1[2].taken, btb.io.resp.f1[2].taken connect tage.io.resp_in[0].f1[3].predicted_pc.bits, btb.io.resp.f1[3].predicted_pc.bits connect tage.io.resp_in[0].f1[3].predicted_pc.valid, btb.io.resp.f1[3].predicted_pc.valid connect tage.io.resp_in[0].f1[3].is_jal, btb.io.resp.f1[3].is_jal connect tage.io.resp_in[0].f1[3].is_br, btb.io.resp.f1[3].is_br connect tage.io.resp_in[0].f1[3].taken, btb.io.resp.f1[3].taken connect loop.io.resp_in[0].f3[0].predicted_pc.bits, tage.io.resp.f3[0].predicted_pc.bits connect loop.io.resp_in[0].f3[0].predicted_pc.valid, tage.io.resp.f3[0].predicted_pc.valid connect loop.io.resp_in[0].f3[0].is_jal, tage.io.resp.f3[0].is_jal connect loop.io.resp_in[0].f3[0].is_br, tage.io.resp.f3[0].is_br connect loop.io.resp_in[0].f3[0].taken, tage.io.resp.f3[0].taken connect loop.io.resp_in[0].f3[1].predicted_pc.bits, tage.io.resp.f3[1].predicted_pc.bits connect loop.io.resp_in[0].f3[1].predicted_pc.valid, tage.io.resp.f3[1].predicted_pc.valid connect loop.io.resp_in[0].f3[1].is_jal, tage.io.resp.f3[1].is_jal connect loop.io.resp_in[0].f3[1].is_br, tage.io.resp.f3[1].is_br connect loop.io.resp_in[0].f3[1].taken, tage.io.resp.f3[1].taken connect loop.io.resp_in[0].f3[2].predicted_pc.bits, tage.io.resp.f3[2].predicted_pc.bits connect loop.io.resp_in[0].f3[2].predicted_pc.valid, tage.io.resp.f3[2].predicted_pc.valid connect loop.io.resp_in[0].f3[2].is_jal, tage.io.resp.f3[2].is_jal connect loop.io.resp_in[0].f3[2].is_br, tage.io.resp.f3[2].is_br connect loop.io.resp_in[0].f3[2].taken, tage.io.resp.f3[2].taken connect loop.io.resp_in[0].f3[3].predicted_pc.bits, tage.io.resp.f3[3].predicted_pc.bits connect loop.io.resp_in[0].f3[3].predicted_pc.valid, tage.io.resp.f3[3].predicted_pc.valid connect loop.io.resp_in[0].f3[3].is_jal, tage.io.resp.f3[3].is_jal connect loop.io.resp_in[0].f3[3].is_br, tage.io.resp.f3[3].is_br connect loop.io.resp_in[0].f3[3].taken, tage.io.resp.f3[3].taken connect loop.io.resp_in[0].f2[0].predicted_pc.bits, tage.io.resp.f2[0].predicted_pc.bits connect loop.io.resp_in[0].f2[0].predicted_pc.valid, tage.io.resp.f2[0].predicted_pc.valid connect loop.io.resp_in[0].f2[0].is_jal, tage.io.resp.f2[0].is_jal connect loop.io.resp_in[0].f2[0].is_br, tage.io.resp.f2[0].is_br connect loop.io.resp_in[0].f2[0].taken, tage.io.resp.f2[0].taken connect loop.io.resp_in[0].f2[1].predicted_pc.bits, tage.io.resp.f2[1].predicted_pc.bits connect loop.io.resp_in[0].f2[1].predicted_pc.valid, tage.io.resp.f2[1].predicted_pc.valid connect loop.io.resp_in[0].f2[1].is_jal, tage.io.resp.f2[1].is_jal connect loop.io.resp_in[0].f2[1].is_br, tage.io.resp.f2[1].is_br connect loop.io.resp_in[0].f2[1].taken, tage.io.resp.f2[1].taken connect loop.io.resp_in[0].f2[2].predicted_pc.bits, tage.io.resp.f2[2].predicted_pc.bits connect loop.io.resp_in[0].f2[2].predicted_pc.valid, tage.io.resp.f2[2].predicted_pc.valid connect loop.io.resp_in[0].f2[2].is_jal, tage.io.resp.f2[2].is_jal connect loop.io.resp_in[0].f2[2].is_br, tage.io.resp.f2[2].is_br connect loop.io.resp_in[0].f2[2].taken, tage.io.resp.f2[2].taken connect loop.io.resp_in[0].f2[3].predicted_pc.bits, tage.io.resp.f2[3].predicted_pc.bits connect loop.io.resp_in[0].f2[3].predicted_pc.valid, tage.io.resp.f2[3].predicted_pc.valid connect loop.io.resp_in[0].f2[3].is_jal, tage.io.resp.f2[3].is_jal connect loop.io.resp_in[0].f2[3].is_br, tage.io.resp.f2[3].is_br connect loop.io.resp_in[0].f2[3].taken, tage.io.resp.f2[3].taken connect loop.io.resp_in[0].f1[0].predicted_pc.bits, tage.io.resp.f1[0].predicted_pc.bits connect loop.io.resp_in[0].f1[0].predicted_pc.valid, tage.io.resp.f1[0].predicted_pc.valid connect loop.io.resp_in[0].f1[0].is_jal, tage.io.resp.f1[0].is_jal connect loop.io.resp_in[0].f1[0].is_br, tage.io.resp.f1[0].is_br connect loop.io.resp_in[0].f1[0].taken, tage.io.resp.f1[0].taken connect loop.io.resp_in[0].f1[1].predicted_pc.bits, tage.io.resp.f1[1].predicted_pc.bits connect loop.io.resp_in[0].f1[1].predicted_pc.valid, tage.io.resp.f1[1].predicted_pc.valid connect loop.io.resp_in[0].f1[1].is_jal, tage.io.resp.f1[1].is_jal connect loop.io.resp_in[0].f1[1].is_br, tage.io.resp.f1[1].is_br connect loop.io.resp_in[0].f1[1].taken, tage.io.resp.f1[1].taken connect loop.io.resp_in[0].f1[2].predicted_pc.bits, tage.io.resp.f1[2].predicted_pc.bits connect loop.io.resp_in[0].f1[2].predicted_pc.valid, tage.io.resp.f1[2].predicted_pc.valid connect loop.io.resp_in[0].f1[2].is_jal, tage.io.resp.f1[2].is_jal connect loop.io.resp_in[0].f1[2].is_br, tage.io.resp.f1[2].is_br connect loop.io.resp_in[0].f1[2].taken, tage.io.resp.f1[2].taken connect loop.io.resp_in[0].f1[3].predicted_pc.bits, tage.io.resp.f1[3].predicted_pc.bits connect loop.io.resp_in[0].f1[3].predicted_pc.valid, tage.io.resp.f1[3].predicted_pc.valid connect loop.io.resp_in[0].f1[3].is_jal, tage.io.resp.f1[3].is_jal connect loop.io.resp_in[0].f1[3].is_br, tage.io.resp.f1[3].is_br connect loop.io.resp_in[0].f1[3].taken, tage.io.resp.f1[3].taken connect io.resp, loop.io.resp connect loop.io.f0_valid, io.f0_valid connect loop.io.f0_pc, io.f0_pc connect loop.io.f0_mask, io.f0_mask connect loop.io.f1_ghist, io.f1_ghist connect loop.io.f1_lhist, io.f1_lhist connect loop.io.f3_fire, io.f3_fire node _T = shl(UInt<1>(0h0), 40) node _T_1 = bits(loop.io.f3_meta, 39, 0) node _T_2 = or(_T, _T_1) connect tage.io.f0_valid, io.f0_valid connect tage.io.f0_pc, io.f0_pc connect tage.io.f0_mask, io.f0_mask connect tage.io.f1_ghist, io.f1_ghist connect tage.io.f1_lhist, io.f1_lhist connect tage.io.f3_fire, io.f3_fire node _T_3 = shl(_T_2, 56) node _T_4 = bits(tage.io.f3_meta, 55, 0) node _T_5 = or(_T_3, _T_4) connect btb.io.f0_valid, io.f0_valid connect btb.io.f0_pc, io.f0_pc connect btb.io.f0_mask, io.f0_mask connect btb.io.f1_ghist, io.f1_ghist connect btb.io.f1_lhist, io.f1_lhist connect btb.io.f3_fire, io.f3_fire node _T_6 = shl(_T_5, 1) node _T_7 = bits(btb.io.f3_meta, 0, 0) node _T_8 = or(_T_6, _T_7) connect ubtb.io.f0_valid, io.f0_valid connect ubtb.io.f0_pc, io.f0_pc connect ubtb.io.f0_mask, io.f0_mask connect ubtb.io.f1_ghist, io.f1_ghist connect ubtb.io.f1_lhist, io.f1_lhist connect ubtb.io.f3_fire, io.f3_fire node _T_9 = shl(_T_8, 8) node _T_10 = bits(ubtb.io.f3_meta, 7, 0) node _T_11 = or(_T_9, _T_10) connect bim.io.f0_valid, io.f0_valid connect bim.io.f0_pc, io.f0_pc connect bim.io.f0_mask, io.f0_mask connect bim.io.f1_ghist, io.f1_ghist connect bim.io.f1_lhist, io.f1_lhist connect bim.io.f3_fire, io.f3_fire node _T_12 = shl(_T_11, 8) node _T_13 = bits(bim.io.f3_meta, 7, 0) node _T_14 = or(_T_12, _T_13) connect io.f3_meta, _T_14 connect bim.io.update.bits.meta, io.update.bits.meta connect bim.io.update.bits.target, io.update.bits.target connect bim.io.update.bits.lhist, io.update.bits.lhist connect bim.io.update.bits.ghist, io.update.bits.ghist connect bim.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect bim.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect bim.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect bim.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect bim.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect bim.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect bim.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect bim.io.update.bits.br_mask, io.update.bits.br_mask connect bim.io.update.bits.pc, io.update.bits.pc connect bim.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect bim.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect bim.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect bim.io.update.valid, io.update.valid connect bim.io.update.bits.meta, io.update.bits.meta node _T_15 = shr(io.update.bits.meta, 8) connect ubtb.io.update.bits.meta, io.update.bits.meta connect ubtb.io.update.bits.target, io.update.bits.target connect ubtb.io.update.bits.lhist, io.update.bits.lhist connect ubtb.io.update.bits.ghist, io.update.bits.ghist connect ubtb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect ubtb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect ubtb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect ubtb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect ubtb.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect ubtb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect ubtb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect ubtb.io.update.bits.br_mask, io.update.bits.br_mask connect ubtb.io.update.bits.pc, io.update.bits.pc connect ubtb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect ubtb.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect ubtb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect ubtb.io.update.valid, io.update.valid connect ubtb.io.update.bits.meta, _T_15 node _T_16 = shr(_T_15, 8) connect btb.io.update.bits.meta, io.update.bits.meta connect btb.io.update.bits.target, io.update.bits.target connect btb.io.update.bits.lhist, io.update.bits.lhist connect btb.io.update.bits.ghist, io.update.bits.ghist connect btb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect btb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect btb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect btb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect btb.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect btb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect btb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect btb.io.update.bits.br_mask, io.update.bits.br_mask connect btb.io.update.bits.pc, io.update.bits.pc connect btb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect btb.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect btb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect btb.io.update.valid, io.update.valid connect btb.io.update.bits.meta, _T_16 node _T_17 = shr(_T_16, 1) connect tage.io.update.bits.meta, io.update.bits.meta connect tage.io.update.bits.target, io.update.bits.target connect tage.io.update.bits.lhist, io.update.bits.lhist connect tage.io.update.bits.ghist, io.update.bits.ghist connect tage.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect tage.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect tage.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect tage.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect tage.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect tage.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect tage.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect tage.io.update.bits.br_mask, io.update.bits.br_mask connect tage.io.update.bits.pc, io.update.bits.pc connect tage.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect tage.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect tage.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect tage.io.update.valid, io.update.valid connect tage.io.update.bits.meta, _T_17 node _T_18 = shr(_T_17, 56) connect loop.io.update.bits.meta, io.update.bits.meta connect loop.io.update.bits.target, io.update.bits.target connect loop.io.update.bits.lhist, io.update.bits.lhist connect loop.io.update.bits.ghist, io.update.bits.ghist connect loop.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect loop.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect loop.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect loop.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect loop.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect loop.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect loop.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect loop.io.update.bits.br_mask, io.update.bits.br_mask connect loop.io.update.bits.pc, io.update.bits.pc connect loop.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect loop.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect loop.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect loop.io.update.valid, io.update.valid connect loop.io.update.bits.meta, _T_18 node _T_19 = shr(_T_18, 40)	module ComposedBranchPredictorBank( // @[composer.scala:14:7] input clock, // @[composer.scala:14:7] input reset, // @[composer.scala:14:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26] wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25] wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25] wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26] wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26] wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7] wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7] wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_0_taken_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_1_taken_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_2_taken_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_3_taken_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_0_taken_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_1_taken_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_2_taken_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_3_taken_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_0_taken_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_1_taken_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_2_taken_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_3_taken_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] wire [119:0] io_f3_meta_0; // @[composer.scala:14:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [36:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14] always @(posedge clock) begin // @[composer.scala:14:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] always @(posedge) LoopBranchPredictorBank loop ( // @[config-mixins.scala:445:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_f1_0_taken (io_resp_f1_0_taken_0), .io_resp_f1_0_is_br (io_resp_f1_0_is_br_0), .io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0), .io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0), .io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0), .io_resp_f1_1_taken (io_resp_f1_1_taken_0), .io_resp_f1_1_is_br (io_resp_f1_1_is_br_0), .io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0), .io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0), .io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0), .io_resp_f1_2_taken (io_resp_f1_2_taken_0), .io_resp_f1_2_is_br (io_resp_f1_2_is_br_0), .io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0), .io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0), .io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0), .io_resp_f1_3_taken (io_resp_f1_3_taken_0), .io_resp_f1_3_is_br (io_resp_f1_3_is_br_0), .io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0), .io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0), .io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0), .io_resp_f2_0_taken (io_resp_f2_0_taken_0), .io_resp_f2_0_is_br (io_resp_f2_0_is_br_0), .io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0), .io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0), .io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0), .io_resp_f2_1_taken (io_resp_f2_1_taken_0), .io_resp_f2_1_is_br (io_resp_f2_1_is_br_0), .io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0), .io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0), .io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0), .io_resp_f2_2_taken (io_resp_f2_2_taken_0), .io_resp_f2_2_is_br (io_resp_f2_2_is_br_0), .io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0), .io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0), .io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0), .io_resp_f2_3_taken (io_resp_f2_3_taken_0), .io_resp_f2_3_is_br (io_resp_f2_3_is_br_0), .io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0), .io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0), .io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0), .io_resp_f3_0_taken (io_resp_f3_0_taken_0), .io_resp_f3_0_is_br (io_resp_f3_0_is_br_0), .io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0), .io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0), .io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0), .io_resp_f3_1_taken (io_resp_f3_1_taken_0), .io_resp_f3_1_is_br (io_resp_f3_1_is_br_0), .io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0), .io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0), .io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0), .io_resp_f3_2_taken (io_resp_f3_2_taken_0), .io_resp_f3_2_is_br (io_resp_f3_2_is_br_0), .io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0), .io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0), .io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0), .io_resp_f3_3_taken (io_resp_f3_3_taken_0), .io_resp_f3_3_is_br (io_resp_f3_3_is_br_0), .io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0), .io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0), .io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0), .io_f3_meta (_loop_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:445:26] TageBranchPredictorBank tage ( // @[config-mixins.scala:446:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_f1_0_taken (_tage_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_tage_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_tage_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_tage_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_tage_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_tage_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_tage_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_tage_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_tage_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_tage_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_tage_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_tage_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_tage_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:446:26] BTBBranchPredictorBank btb ( // @[config-mixins.scala:447:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_f1_0_taken (_btb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_btb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_btb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_btb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_btb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_btb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_btb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_btb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_btb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_btb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_btb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_btb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_btb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:447:25] BIMBranchPredictorBank bim ( // @[config-mixins.scala:448:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_f1_0_taken (_bim_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_bim_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_bim_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_bim_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_bim_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_bim_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_bim_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_bim_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_bim_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_bim_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_bim_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_bim_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_bim_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7] ); // @[config-mixins.scala:448:25] FAMicroBTBBranchPredictorBank ubtb ( // @[config-mixins.scala:449:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_ubtb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31] ); // @[config-mixins.scala:449:26] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_PutBufferAEntry_q40_e40_1 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}}}, valid : UInt<40>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}} regreset valid : UInt<40>, clock, reset, UInt<40>(0h0) cmem head : UInt<6> [40] cmem tail : UInt<6> [40] regreset used : UInt<40>, clock, reset, UInt<40>(0h0) cmem next : UInt<6> [40] cmem data : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>} [40] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = shl(_freeOH_T_15, 32) node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0) node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17) node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0) node _freeOH_T_20 = shl(_freeOH_T_19, 1) node _freeOH_T_21 = not(_freeOH_T_20) node _freeOH_T_22 = not(used) node freeOH = and(_freeOH_T_21, _freeOH_T_22) node freeIdx_hi = bits(freeOH, 40, 32) node freeIdx_lo = bits(freeOH, 31, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16) node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8) node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4) node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2) node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0) node _freeIdx_T_8 = orr(freeIdx_hi_4) node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4) node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1) node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10) node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11) node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12) node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13) node freeIdx = cat(_freeIdx_T, _freeIdx_T_14) wire valid_set : UInt<40> connect valid_set, UInt<40>(0h0) wire valid_clr : UInt<40> connect valid_clr, UInt<40>(0h0) wire used_set : UInt<40> connect used_set, UInt<40>(0h0) wire used_clr : UInt<40> connect used_clr, UInt<40>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 39, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH write mport MPORT = data[freeIdx], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_1 = eq(io.pop.valid, UInt<1>(0h0)) node _T_2 = dshr(io.valid, io.pop.bits) node _T_3 = bits(_T_2, 0, 0) node _T_4 = or(_T_1, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire \|\| (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 5, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 39, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_8 = eq(pop_head, MPORT_4) when _T_8 : node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 39, 0) connect valid_clr, _valid_clr_T_1 node _T_9 = and(io.push.ready, io.push.valid) node _T_10 = and(_T_9, push_valid) node _T_11 = eq(push_tail, pop_head) node _T_12 = and(_T_10, _T_11) read mport MPORT_5 = next[pop_head], clock node _T_13 = mux(_T_12, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_13 node _T_14 = eq(io.pop.valid, UInt<1>(0h0)) node _T_15 = or(UInt<1>(0h1), _T_14) node _T_16 = or(_T_15, pop_valid) when _T_16 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2	module ListBuffer_PutBufferAEntry_q40_e40_1( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input [127:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14] input [15:0] io_push_bits_data_mask, // @[ListBuffer.scala:39:14] input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14] output [39:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output [127:0] io_data_data, // @[ListBuffer.scala:39:14] output [15:0] io_data_mask, // @[ListBuffer.scala:39:14] output io_data_corrupt // @[ListBuffer.scala:39:14] ); wire [144:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire [127:0] io_push_bits_data_data_0 = io_push_bits_data_data; // @[ListBuffer.scala:36:7] wire [15:0] io_push_bits_data_mask_0 = io_push_bits_data_mask; // @[ListBuffer.scala:36:7] wire io_push_bits_data_corrupt_0 = io_push_bits_data_corrupt; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire [127:0] io_data_data_0; // @[ListBuffer.scala:36:7] wire [15:0] io_data_mask_0; // @[ListBuffer.scala:36:7] wire io_data_corrupt_0; // @[ListBuffer.scala:36:7] wire [39:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [39:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [39:0] used; // @[ListBuffer.scala:50:22] assign io_data_data_0 = _data_ext_R0_data[127:0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_mask_0 = _data_ext_R0_data[143:128]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_corrupt_0 = _data_ext_R0_data[144]; // @[ListBuffer.scala:36:7, :52:18] wire [39:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T \| _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 \| _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 \| _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 \| _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 \| _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 \| _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}] wire [39:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = \|freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} \| freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = \|freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 \| freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = \|freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 \| freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = \|freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 \| freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = \|freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 \| freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire [39:0] valid_set; // @[ListBuffer.scala:57:30] wire [39:0] valid_clr; // @[ListBuffer.scala:58:30] wire [39:0] used_set; // @[ListBuffer.scala:59:30] wire [39:0] used_clr; // @[ListBuffer.scala:60:30] wire [39:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _valid_set_T_1 = _valid_set_T[39:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 40'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[39:0] : 40'h0; // @[Decoupled.scala:51:35] wire [39:0] _GEN = {34'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [39:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to this FIRRTL code module PE_360 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_104 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_360( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_104 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_20 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_d : { bits : UInt<32>}, out_a : { bits : UInt<32>}, out_b : { bits : UInt<32>}, out_c : { bits : UInt<32>}, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<4>, out_id : UInt<4>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_4 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : { bits : UInt<32>}, clock reg c2 : { bits : UInt<32>}, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a.bits, io.in_a.bits reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node io_out_c_self_rec_rawIn_sign = bits(c1.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn = bits(c1.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn = bits(c1.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn = eq(io_out_c_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn = eq(io_out_c_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T = bits(io_out_c_self_rec_rawIn_fractIn, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_1 = bits(io_out_c_self_rec_rawIn_fractIn, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_2 = bits(io_out_c_self_rec_rawIn_fractIn, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_3 = bits(io_out_c_self_rec_rawIn_fractIn, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_4 = bits(io_out_c_self_rec_rawIn_fractIn, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_5 = bits(io_out_c_self_rec_rawIn_fractIn, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_6 = bits(io_out_c_self_rec_rawIn_fractIn, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_7 = bits(io_out_c_self_rec_rawIn_fractIn, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_8 = bits(io_out_c_self_rec_rawIn_fractIn, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_9 = bits(io_out_c_self_rec_rawIn_fractIn, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_10 = bits(io_out_c_self_rec_rawIn_fractIn, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_11 = bits(io_out_c_self_rec_rawIn_fractIn, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_12 = bits(io_out_c_self_rec_rawIn_fractIn, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_13 = bits(io_out_c_self_rec_rawIn_fractIn, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_14 = bits(io_out_c_self_rec_rawIn_fractIn, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_15 = bits(io_out_c_self_rec_rawIn_fractIn, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_16 = bits(io_out_c_self_rec_rawIn_fractIn, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_17 = bits(io_out_c_self_rec_rawIn_fractIn, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_18 = bits(io_out_c_self_rec_rawIn_fractIn, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_19 = bits(io_out_c_self_rec_rawIn_fractIn, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_20 = bits(io_out_c_self_rec_rawIn_fractIn, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_21 = bits(io_out_c_self_rec_rawIn_fractIn, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_22 = bits(io_out_c_self_rec_rawIn_fractIn, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_23 = mux(_io_out_c_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_24 = mux(_io_out_c_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_23) node _io_out_c_self_rec_rawIn_normDist_T_25 = mux(_io_out_c_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_24) node _io_out_c_self_rec_rawIn_normDist_T_26 = mux(_io_out_c_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_25) node _io_out_c_self_rec_rawIn_normDist_T_27 = mux(_io_out_c_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_26) node _io_out_c_self_rec_rawIn_normDist_T_28 = mux(_io_out_c_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_27) node _io_out_c_self_rec_rawIn_normDist_T_29 = mux(_io_out_c_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_28) node _io_out_c_self_rec_rawIn_normDist_T_30 = mux(_io_out_c_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_29) node _io_out_c_self_rec_rawIn_normDist_T_31 = mux(_io_out_c_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_30) node _io_out_c_self_rec_rawIn_normDist_T_32 = mux(_io_out_c_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_31) node _io_out_c_self_rec_rawIn_normDist_T_33 = mux(_io_out_c_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_32) node _io_out_c_self_rec_rawIn_normDist_T_34 = mux(_io_out_c_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_33) node _io_out_c_self_rec_rawIn_normDist_T_35 = mux(_io_out_c_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_34) node _io_out_c_self_rec_rawIn_normDist_T_36 = mux(_io_out_c_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_35) node _io_out_c_self_rec_rawIn_normDist_T_37 = mux(_io_out_c_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_36) node _io_out_c_self_rec_rawIn_normDist_T_38 = mux(_io_out_c_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_37) node _io_out_c_self_rec_rawIn_normDist_T_39 = mux(_io_out_c_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_38) node _io_out_c_self_rec_rawIn_normDist_T_40 = mux(_io_out_c_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_39) node _io_out_c_self_rec_rawIn_normDist_T_41 = mux(_io_out_c_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_40) node _io_out_c_self_rec_rawIn_normDist_T_42 = mux(_io_out_c_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_41) node _io_out_c_self_rec_rawIn_normDist_T_43 = mux(_io_out_c_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_42) node io_out_c_self_rec_rawIn_normDist = mux(_io_out_c_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_43) node _io_out_c_self_rec_rawIn_subnormFract_T = dshl(io_out_c_self_rec_rawIn_fractIn, io_out_c_self_rec_rawIn_normDist) node _io_out_c_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_self_rec_rawIn_subnormFract = shl(_io_out_c_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T = xor(io_out_c_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, _io_out_c_self_rec_rawIn_adjustedExp_T, io_out_c_self_rec_rawIn_expIn) node _io_out_c_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_1, _io_out_c_self_rec_rawIn_adjustedExp_T_3) node io_out_c_self_rec_rawIn_adjustedExp = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_self_rec_rawIn_isZero = and(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_isZeroFractIn) node _io_out_c_self_rec_rawIn_isSpecial_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 7) node io_out_c_self_rec_rawIn_isSpecial = eq(_io_out_c_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T = eq(io_out_c_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_1 = and(io_out_c_self_rec_rawIn_isSpecial, _io_out_c_self_rec_rawIn_out_isNaN_T) connect io_out_c_self_rec_rawIn.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_1 node _io_out_c_self_rec_rawIn_out_isInf_T = and(io_out_c_self_rec_rawIn_isSpecial, io_out_c_self_rec_rawIn_isZeroFractIn) connect io_out_c_self_rec_rawIn.isInf, _io_out_c_self_rec_rawIn_out_isInf_T connect io_out_c_self_rec_rawIn.isZero, io_out_c_self_rec_rawIn_isZero connect io_out_c_self_rec_rawIn.sign, io_out_c_self_rec_rawIn_sign node _io_out_c_self_rec_rawIn_out_sExp_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T) connect io_out_c_self_rec_rawIn.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_1 node _io_out_c_self_rec_rawIn_out_sig_T = eq(io_out_c_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T) node _io_out_c_self_rec_rawIn_out_sig_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_subnormFract, io_out_c_self_rec_rawIn_fractIn) node _io_out_c_self_rec_rawIn_out_sig_T_3 = cat(_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2) connect io_out_c_self_rec_rawIn.sig, _io_out_c_self_rec_rawIn_out_sig_T_3 node _io_out_c_self_rec_T = bits(io_out_c_self_rec_rawIn.sExp, 8, 6) node _io_out_c_self_rec_T_1 = mux(io_out_c_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_self_rec_T) node _io_out_c_self_rec_T_2 = mux(io_out_c_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_3 = or(_io_out_c_self_rec_T_1, _io_out_c_self_rec_T_2) node _io_out_c_self_rec_T_4 = cat(io_out_c_self_rec_rawIn.sign, _io_out_c_self_rec_T_3) node _io_out_c_self_rec_T_5 = bits(io_out_c_self_rec_rawIn.sExp, 5, 0) node _io_out_c_self_rec_T_6 = cat(_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5) node _io_out_c_self_rec_T_7 = bits(io_out_c_self_rec_rawIn.sig, 22, 0) node io_out_c_self_rec = cat(_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7) wire io_out_c_shift_exp : UInt<8> node _io_out_c_shift_exp_T = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_1 = tail(_io_out_c_shift_exp_T, 1) connect io_out_c_shift_exp, _io_out_c_shift_exp_T_1 node io_out_c_shift_fn_hi = cat(UInt<1>(0h0), io_out_c_shift_exp) node io_out_c_shift_fn = cat(io_out_c_shift_fn_hi, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign = bits(io_out_c_shift_fn, 31, 31) node io_out_c_shift_rec_rawIn_expIn = bits(io_out_c_shift_fn, 30, 23) node io_out_c_shift_rec_rawIn_fractIn = bits(io_out_c_shift_fn, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn = eq(io_out_c_shift_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn = eq(io_out_c_shift_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T = bits(io_out_c_shift_rec_rawIn_fractIn, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_1 = bits(io_out_c_shift_rec_rawIn_fractIn, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_2 = bits(io_out_c_shift_rec_rawIn_fractIn, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_3 = bits(io_out_c_shift_rec_rawIn_fractIn, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_4 = bits(io_out_c_shift_rec_rawIn_fractIn, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_5 = bits(io_out_c_shift_rec_rawIn_fractIn, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_6 = bits(io_out_c_shift_rec_rawIn_fractIn, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_7 = bits(io_out_c_shift_rec_rawIn_fractIn, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_8 = bits(io_out_c_shift_rec_rawIn_fractIn, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_9 = bits(io_out_c_shift_rec_rawIn_fractIn, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_10 = bits(io_out_c_shift_rec_rawIn_fractIn, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_11 = bits(io_out_c_shift_rec_rawIn_fractIn, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_12 = bits(io_out_c_shift_rec_rawIn_fractIn, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_13 = bits(io_out_c_shift_rec_rawIn_fractIn, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_14 = bits(io_out_c_shift_rec_rawIn_fractIn, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_15 = bits(io_out_c_shift_rec_rawIn_fractIn, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_16 = bits(io_out_c_shift_rec_rawIn_fractIn, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_17 = bits(io_out_c_shift_rec_rawIn_fractIn, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_18 = bits(io_out_c_shift_rec_rawIn_fractIn, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_19 = bits(io_out_c_shift_rec_rawIn_fractIn, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_20 = bits(io_out_c_shift_rec_rawIn_fractIn, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_21 = bits(io_out_c_shift_rec_rawIn_fractIn, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_22 = bits(io_out_c_shift_rec_rawIn_fractIn, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_23 = mux(_io_out_c_shift_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_24 = mux(_io_out_c_shift_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_23) node _io_out_c_shift_rec_rawIn_normDist_T_25 = mux(_io_out_c_shift_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_24) node _io_out_c_shift_rec_rawIn_normDist_T_26 = mux(_io_out_c_shift_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_25) node _io_out_c_shift_rec_rawIn_normDist_T_27 = mux(_io_out_c_shift_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_26) node _io_out_c_shift_rec_rawIn_normDist_T_28 = mux(_io_out_c_shift_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_27) node _io_out_c_shift_rec_rawIn_normDist_T_29 = mux(_io_out_c_shift_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_28) node _io_out_c_shift_rec_rawIn_normDist_T_30 = mux(_io_out_c_shift_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_29) node _io_out_c_shift_rec_rawIn_normDist_T_31 = mux(_io_out_c_shift_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_30) node _io_out_c_shift_rec_rawIn_normDist_T_32 = mux(_io_out_c_shift_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_31) node _io_out_c_shift_rec_rawIn_normDist_T_33 = mux(_io_out_c_shift_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_32) node _io_out_c_shift_rec_rawIn_normDist_T_34 = mux(_io_out_c_shift_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_33) node _io_out_c_shift_rec_rawIn_normDist_T_35 = mux(_io_out_c_shift_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_34) node _io_out_c_shift_rec_rawIn_normDist_T_36 = mux(_io_out_c_shift_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_35) node _io_out_c_shift_rec_rawIn_normDist_T_37 = mux(_io_out_c_shift_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_36) node _io_out_c_shift_rec_rawIn_normDist_T_38 = mux(_io_out_c_shift_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_37) node _io_out_c_shift_rec_rawIn_normDist_T_39 = mux(_io_out_c_shift_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_38) node _io_out_c_shift_rec_rawIn_normDist_T_40 = mux(_io_out_c_shift_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_39) node _io_out_c_shift_rec_rawIn_normDist_T_41 = mux(_io_out_c_shift_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_40) node _io_out_c_shift_rec_rawIn_normDist_T_42 = mux(_io_out_c_shift_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_41) node _io_out_c_shift_rec_rawIn_normDist_T_43 = mux(_io_out_c_shift_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_42) node io_out_c_shift_rec_rawIn_normDist = mux(_io_out_c_shift_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_43) node _io_out_c_shift_rec_rawIn_subnormFract_T = dshl(io_out_c_shift_rec_rawIn_fractIn, io_out_c_shift_rec_rawIn_normDist) node _io_out_c_shift_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T = xor(io_out_c_shift_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, _io_out_c_shift_rec_rawIn_adjustedExp_T, io_out_c_shift_rec_rawIn_expIn) node _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_2) node _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_3) node io_out_c_shift_rec_rawIn_adjustedExp = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_shift_rec_rawIn_isZero = and(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_isZeroFractIn) node _io_out_c_shift_rec_rawIn_isSpecial_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial = eq(_io_out_c_shift_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T = eq(io_out_c_shift_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial, _io_out_c_shift_rec_rawIn_out_isNaN_T) connect io_out_c_shift_rec_rawIn.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_1 node _io_out_c_shift_rec_rawIn_out_isInf_T = and(io_out_c_shift_rec_rawIn_isSpecial, io_out_c_shift_rec_rawIn_isZeroFractIn) connect io_out_c_shift_rec_rawIn.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T connect io_out_c_shift_rec_rawIn.isZero, io_out_c_shift_rec_rawIn_isZero connect io_out_c_shift_rec_rawIn.sign, io_out_c_shift_rec_rawIn_sign node _io_out_c_shift_rec_rawIn_out_sExp_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T) connect io_out_c_shift_rec_rawIn.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_1 node _io_out_c_shift_rec_rawIn_out_sig_T = eq(io_out_c_shift_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T) node _io_out_c_shift_rec_rawIn_out_sig_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_subnormFract, io_out_c_shift_rec_rawIn_fractIn) node _io_out_c_shift_rec_rawIn_out_sig_T_3 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2) connect io_out_c_shift_rec_rawIn.sig, _io_out_c_shift_rec_rawIn_out_sig_T_3 node _io_out_c_shift_rec_T = bits(io_out_c_shift_rec_rawIn.sExp, 8, 6) node _io_out_c_shift_rec_T_1 = mux(io_out_c_shift_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T) node _io_out_c_shift_rec_T_2 = mux(io_out_c_shift_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_3 = or(_io_out_c_shift_rec_T_1, _io_out_c_shift_rec_T_2) node _io_out_c_shift_rec_T_4 = cat(io_out_c_shift_rec_rawIn.sign, _io_out_c_shift_rec_T_3) node _io_out_c_shift_rec_T_5 = bits(io_out_c_shift_rec_rawIn.sExp, 5, 0) node _io_out_c_shift_rec_T_6 = cat(_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5) node _io_out_c_shift_rec_T_7 = bits(io_out_c_shift_rec_rawIn.sig, 22, 0) node io_out_c_shift_rec = cat(_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7) node _io_out_c_T = neq(io_out_c_shift_exp, UInt<1>(0h0)) node _io_out_c_T_1 = asUInt(reset) node _io_out_c_T_2 = eq(_io_out_c_T_1, UInt<1>(0h0)) when _io_out_c_T_2 : node _io_out_c_T_3 = eq(_io_out_c_T, UInt<1>(0h0)) when _io_out_c_T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf assert(clock, _io_out_c_T, UInt<1>(0h1), "") : io_out_c_assert inst io_out_c_muladder of MulRecFN_32 connect io_out_c_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder.io.a, io_out_c_self_rec connect io_out_c_muladder.io.b, io_out_c_shift_rec wire io_out_c_result : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp = bits(io_out_c_muladder.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T = bits(io_out_c_result_bits_rawIn_exp, 8, 6) node io_out_c_result_bits_rawIn_isZero = eq(_io_out_c_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T = bits(io_out_c_result_bits_rawIn_exp, 8, 7) node io_out_c_result_bits_rawIn_isSpecial = eq(_io_out_c_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_1 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isNaN_T) connect io_out_c_result_bits_rawIn.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_1 node _io_out_c_result_bits_rawIn_out_isInf_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_1 = eq(_io_out_c_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_2 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isInf_T_1) connect io_out_c_result_bits_rawIn.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_2 connect io_out_c_result_bits_rawIn.isZero, io_out_c_result_bits_rawIn_isZero node _io_out_c_result_bits_rawIn_out_sign_T = bits(io_out_c_muladder.io.out, 32, 32) connect io_out_c_result_bits_rawIn.sign, _io_out_c_result_bits_rawIn_out_sign_T node _io_out_c_result_bits_rawIn_out_sExp_T = cvt(io_out_c_result_bits_rawIn_exp) connect io_out_c_result_bits_rawIn.sExp, _io_out_c_result_bits_rawIn_out_sExp_T node _io_out_c_result_bits_rawIn_out_sig_T = eq(io_out_c_result_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T) node _io_out_c_result_bits_rawIn_out_sig_T_2 = bits(io_out_c_muladder.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_3 = cat(_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2) connect io_out_c_result_bits_rawIn.sig, _io_out_c_result_bits_rawIn_out_sig_T_3 node io_out_c_result_bits_isSubnormal = lt(io_out_c_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T = bits(io_out_c_result_bits_rawIn.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T) node io_out_c_result_bits_denormShiftDist = tail(_io_out_c_result_bits_denormShiftDist_T_1, 1) node _io_out_c_result_bits_denormFract_T = shr(io_out_c_result_bits_rawIn.sig, 1) node _io_out_c_result_bits_denormFract_T_1 = dshr(_io_out_c_result_bits_denormFract_T, io_out_c_result_bits_denormShiftDist) node io_out_c_result_bits_denormFract = bits(_io_out_c_result_bits_denormFract_T_1, 22, 0) node _io_out_c_result_bits_expOut_T = bits(io_out_c_result_bits_rawIn.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_1 = sub(_io_out_c_result_bits_expOut_T, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_2 = tail(_io_out_c_result_bits_expOut_T_1, 1) node _io_out_c_result_bits_expOut_T_3 = mux(io_out_c_result_bits_isSubnormal, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_2) node _io_out_c_result_bits_expOut_T_4 = or(io_out_c_result_bits_rawIn.isNaN, io_out_c_result_bits_rawIn.isInf) node _io_out_c_result_bits_expOut_T_5 = mux(_io_out_c_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut = or(_io_out_c_result_bits_expOut_T_3, _io_out_c_result_bits_expOut_T_5) node _io_out_c_result_bits_fractOut_T = bits(io_out_c_result_bits_rawIn.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_1 = mux(io_out_c_result_bits_rawIn.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T) node io_out_c_result_bits_fractOut = mux(io_out_c_result_bits_isSubnormal, io_out_c_result_bits_denormFract, _io_out_c_result_bits_fractOut_T_1) node io_out_c_result_bits_hi = cat(io_out_c_result_bits_rawIn.sign, io_out_c_result_bits_expOut) node _io_out_c_result_bits_T = cat(io_out_c_result_bits_hi, io_out_c_result_bits_fractOut) connect io_out_c_result.bits, _io_out_c_result_bits_T node io_out_c_self_rec_rawIn_sign_1 = bits(io_out_c_result.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_1 = bits(io_out_c_result.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_1 = bits(io_out_c_result.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_self_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_44 = bits(io_out_c_self_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_45 = bits(io_out_c_self_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_46 = bits(io_out_c_self_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_47 = bits(io_out_c_self_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_48 = bits(io_out_c_self_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_49 = bits(io_out_c_self_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_50 = bits(io_out_c_self_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_51 = bits(io_out_c_self_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_52 = bits(io_out_c_self_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_53 = bits(io_out_c_self_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_54 = bits(io_out_c_self_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_55 = bits(io_out_c_self_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_56 = bits(io_out_c_self_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_57 = bits(io_out_c_self_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_58 = bits(io_out_c_self_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_59 = bits(io_out_c_self_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_60 = bits(io_out_c_self_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_61 = bits(io_out_c_self_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_62 = bits(io_out_c_self_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_63 = bits(io_out_c_self_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_64 = bits(io_out_c_self_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_65 = bits(io_out_c_self_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_66 = bits(io_out_c_self_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_67 = mux(_io_out_c_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_68 = mux(_io_out_c_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_67) node _io_out_c_self_rec_rawIn_normDist_T_69 = mux(_io_out_c_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_68) node _io_out_c_self_rec_rawIn_normDist_T_70 = mux(_io_out_c_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_69) node _io_out_c_self_rec_rawIn_normDist_T_71 = mux(_io_out_c_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_70) node _io_out_c_self_rec_rawIn_normDist_T_72 = mux(_io_out_c_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_71) node _io_out_c_self_rec_rawIn_normDist_T_73 = mux(_io_out_c_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_72) node _io_out_c_self_rec_rawIn_normDist_T_74 = mux(_io_out_c_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_73) node _io_out_c_self_rec_rawIn_normDist_T_75 = mux(_io_out_c_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_74) node _io_out_c_self_rec_rawIn_normDist_T_76 = mux(_io_out_c_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_75) node _io_out_c_self_rec_rawIn_normDist_T_77 = mux(_io_out_c_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_76) node _io_out_c_self_rec_rawIn_normDist_T_78 = mux(_io_out_c_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_77) node _io_out_c_self_rec_rawIn_normDist_T_79 = mux(_io_out_c_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_78) node _io_out_c_self_rec_rawIn_normDist_T_80 = mux(_io_out_c_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_79) node _io_out_c_self_rec_rawIn_normDist_T_81 = mux(_io_out_c_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_80) node _io_out_c_self_rec_rawIn_normDist_T_82 = mux(_io_out_c_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_81) node _io_out_c_self_rec_rawIn_normDist_T_83 = mux(_io_out_c_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_82) node _io_out_c_self_rec_rawIn_normDist_T_84 = mux(_io_out_c_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_83) node _io_out_c_self_rec_rawIn_normDist_T_85 = mux(_io_out_c_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_84) node _io_out_c_self_rec_rawIn_normDist_T_86 = mux(_io_out_c_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_85) node _io_out_c_self_rec_rawIn_normDist_T_87 = mux(_io_out_c_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_86) node io_out_c_self_rec_rawIn_normDist_1 = mux(_io_out_c_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_87) node _io_out_c_self_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_self_rec_rawIn_fractIn_1, io_out_c_self_rec_rawIn_normDist_1) node _io_out_c_self_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_1 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, _io_out_c_self_rec_rawIn_adjustedExp_T_5, io_out_c_self_rec_rawIn_expIn_1) node _io_out_c_self_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_7) node _io_out_c_self_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_6, _io_out_c_self_rec_rawIn_adjustedExp_T_8) node io_out_c_self_rec_rawIn_adjustedExp_1 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_self_rec_rawIn_isZero_1 = and(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) node _io_out_c_self_rec_rawIn_isSpecial_T_1 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_1 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_1, _io_out_c_self_rec_rawIn_out_isNaN_T_2) connect io_out_c_self_rec_rawIn_1.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_3 node _io_out_c_self_rec_rawIn_out_isInf_T_1 = and(io_out_c_self_rec_rawIn_isSpecial_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) connect io_out_c_self_rec_rawIn_1.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_1 connect io_out_c_self_rec_rawIn_1.isZero, io_out_c_self_rec_rawIn_isZero_1 connect io_out_c_self_rec_rawIn_1.sign, io_out_c_self_rec_rawIn_sign_1 node _io_out_c_self_rec_rawIn_out_sExp_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_2) connect io_out_c_self_rec_rawIn_1.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_3 node _io_out_c_self_rec_rawIn_out_sig_T_4 = eq(io_out_c_self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_4) node _io_out_c_self_rec_rawIn_out_sig_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_subnormFract_1, io_out_c_self_rec_rawIn_fractIn_1) node _io_out_c_self_rec_rawIn_out_sig_T_7 = cat(_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6) connect io_out_c_self_rec_rawIn_1.sig, _io_out_c_self_rec_rawIn_out_sig_T_7 node _io_out_c_self_rec_T_8 = bits(io_out_c_self_rec_rawIn_1.sExp, 8, 6) node _io_out_c_self_rec_T_9 = mux(io_out_c_self_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_8) node _io_out_c_self_rec_T_10 = mux(io_out_c_self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_11 = or(_io_out_c_self_rec_T_9, _io_out_c_self_rec_T_10) node _io_out_c_self_rec_T_12 = cat(io_out_c_self_rec_rawIn_1.sign, _io_out_c_self_rec_T_11) node _io_out_c_self_rec_T_13 = bits(io_out_c_self_rec_rawIn_1.sExp, 5, 0) node _io_out_c_self_rec_T_14 = cat(_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13) node _io_out_c_self_rec_T_15 = bits(io_out_c_self_rec_rawIn_1.sig, 22, 0) node io_out_c_self_rec_1 = cat(_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15) inst io_out_c_resizer of RecFNToRecFN_170 connect io_out_c_resizer.io.in, io_out_c_self_rec_1 connect io_out_c_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_1 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_1 = bits(io_out_c_resizer.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 6) node io_out_c_result_bits_rawIn_isZero_1 = eq(_io_out_c_result_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_1 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_2 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_3 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isNaN_T_2) connect io_out_c_result_bits_rawIn_1.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_3 node _io_out_c_result_bits_rawIn_out_isInf_T_3 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_4 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isInf_T_4) connect io_out_c_result_bits_rawIn_1.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_5 connect io_out_c_result_bits_rawIn_1.isZero, io_out_c_result_bits_rawIn_isZero_1 node _io_out_c_result_bits_rawIn_out_sign_T_1 = bits(io_out_c_resizer.io.out, 32, 32) connect io_out_c_result_bits_rawIn_1.sign, _io_out_c_result_bits_rawIn_out_sign_T_1 node _io_out_c_result_bits_rawIn_out_sExp_T_1 = cvt(io_out_c_result_bits_rawIn_exp_1) connect io_out_c_result_bits_rawIn_1.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_1 node _io_out_c_result_bits_rawIn_out_sig_T_4 = eq(io_out_c_result_bits_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_4) node _io_out_c_result_bits_rawIn_out_sig_T_6 = bits(io_out_c_resizer.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_7 = cat(_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6) connect io_out_c_result_bits_rawIn_1.sig, _io_out_c_result_bits_rawIn_out_sig_T_7 node io_out_c_result_bits_isSubnormal_1 = lt(io_out_c_result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_2 = bits(io_out_c_result_bits_rawIn_1.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_2) node io_out_c_result_bits_denormShiftDist_1 = tail(_io_out_c_result_bits_denormShiftDist_T_3, 1) node _io_out_c_result_bits_denormFract_T_2 = shr(io_out_c_result_bits_rawIn_1.sig, 1) node _io_out_c_result_bits_denormFract_T_3 = dshr(_io_out_c_result_bits_denormFract_T_2, io_out_c_result_bits_denormShiftDist_1) node io_out_c_result_bits_denormFract_1 = bits(_io_out_c_result_bits_denormFract_T_3, 22, 0) node _io_out_c_result_bits_expOut_T_6 = bits(io_out_c_result_bits_rawIn_1.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_7 = sub(_io_out_c_result_bits_expOut_T_6, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_8 = tail(_io_out_c_result_bits_expOut_T_7, 1) node _io_out_c_result_bits_expOut_T_9 = mux(io_out_c_result_bits_isSubnormal_1, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_8) node _io_out_c_result_bits_expOut_T_10 = or(io_out_c_result_bits_rawIn_1.isNaN, io_out_c_result_bits_rawIn_1.isInf) node _io_out_c_result_bits_expOut_T_11 = mux(_io_out_c_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_1 = or(_io_out_c_result_bits_expOut_T_9, _io_out_c_result_bits_expOut_T_11) node _io_out_c_result_bits_fractOut_T_2 = bits(io_out_c_result_bits_rawIn_1.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_3 = mux(io_out_c_result_bits_rawIn_1.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_2) node io_out_c_result_bits_fractOut_1 = mux(io_out_c_result_bits_isSubnormal_1, io_out_c_result_bits_denormFract_1, _io_out_c_result_bits_fractOut_T_3) node io_out_c_result_bits_hi_1 = cat(io_out_c_result_bits_rawIn_1.sign, io_out_c_result_bits_expOut_1) node _io_out_c_result_bits_T_1 = cat(io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1) connect io_out_c_result_1.bits, _io_out_c_result_bits_T_1 connect io.out_c, io_out_c_result_1 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_1 : UInt<32> connect _mac_unit_io_in_b_WIRE_1, io.in_b.bits node _mac_unit_io_in_b_T = bits(_mac_unit_io_in_b_WIRE_1, 31, 0) connect _mac_unit_io_in_b_WIRE.bits, _mac_unit_io_in_b_T connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE.bits connect mac_unit.io.in_c.bits, c2.bits connect c2, mac_unit.io.out_d node c1_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c1_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c1_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c1_self_rec_rawIn_isZeroExpIn = eq(c1_self_rec_rawIn_expIn, UInt<1>(0h0)) node c1_self_rec_rawIn_isZeroFractIn = eq(c1_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_normDist_T = bits(c1_self_rec_rawIn_fractIn, 0, 0) node _c1_self_rec_rawIn_normDist_T_1 = bits(c1_self_rec_rawIn_fractIn, 1, 1) node _c1_self_rec_rawIn_normDist_T_2 = bits(c1_self_rec_rawIn_fractIn, 2, 2) node _c1_self_rec_rawIn_normDist_T_3 = bits(c1_self_rec_rawIn_fractIn, 3, 3) node _c1_self_rec_rawIn_normDist_T_4 = bits(c1_self_rec_rawIn_fractIn, 4, 4) node _c1_self_rec_rawIn_normDist_T_5 = bits(c1_self_rec_rawIn_fractIn, 5, 5) node _c1_self_rec_rawIn_normDist_T_6 = bits(c1_self_rec_rawIn_fractIn, 6, 6) node _c1_self_rec_rawIn_normDist_T_7 = bits(c1_self_rec_rawIn_fractIn, 7, 7) node _c1_self_rec_rawIn_normDist_T_8 = bits(c1_self_rec_rawIn_fractIn, 8, 8) node _c1_self_rec_rawIn_normDist_T_9 = bits(c1_self_rec_rawIn_fractIn, 9, 9) node _c1_self_rec_rawIn_normDist_T_10 = bits(c1_self_rec_rawIn_fractIn, 10, 10) node _c1_self_rec_rawIn_normDist_T_11 = bits(c1_self_rec_rawIn_fractIn, 11, 11) node _c1_self_rec_rawIn_normDist_T_12 = bits(c1_self_rec_rawIn_fractIn, 12, 12) node _c1_self_rec_rawIn_normDist_T_13 = bits(c1_self_rec_rawIn_fractIn, 13, 13) node _c1_self_rec_rawIn_normDist_T_14 = bits(c1_self_rec_rawIn_fractIn, 14, 14) node _c1_self_rec_rawIn_normDist_T_15 = bits(c1_self_rec_rawIn_fractIn, 15, 15) node _c1_self_rec_rawIn_normDist_T_16 = bits(c1_self_rec_rawIn_fractIn, 16, 16) node _c1_self_rec_rawIn_normDist_T_17 = bits(c1_self_rec_rawIn_fractIn, 17, 17) node _c1_self_rec_rawIn_normDist_T_18 = bits(c1_self_rec_rawIn_fractIn, 18, 18) node _c1_self_rec_rawIn_normDist_T_19 = bits(c1_self_rec_rawIn_fractIn, 19, 19) node _c1_self_rec_rawIn_normDist_T_20 = bits(c1_self_rec_rawIn_fractIn, 20, 20) node _c1_self_rec_rawIn_normDist_T_21 = bits(c1_self_rec_rawIn_fractIn, 21, 21) node _c1_self_rec_rawIn_normDist_T_22 = bits(c1_self_rec_rawIn_fractIn, 22, 22) node _c1_self_rec_rawIn_normDist_T_23 = mux(_c1_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c1_self_rec_rawIn_normDist_T_24 = mux(_c1_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c1_self_rec_rawIn_normDist_T_23) node _c1_self_rec_rawIn_normDist_T_25 = mux(_c1_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c1_self_rec_rawIn_normDist_T_24) node _c1_self_rec_rawIn_normDist_T_26 = mux(_c1_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c1_self_rec_rawIn_normDist_T_25) node _c1_self_rec_rawIn_normDist_T_27 = mux(_c1_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c1_self_rec_rawIn_normDist_T_26) node _c1_self_rec_rawIn_normDist_T_28 = mux(_c1_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c1_self_rec_rawIn_normDist_T_27) node _c1_self_rec_rawIn_normDist_T_29 = mux(_c1_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c1_self_rec_rawIn_normDist_T_28) node _c1_self_rec_rawIn_normDist_T_30 = mux(_c1_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c1_self_rec_rawIn_normDist_T_29) node _c1_self_rec_rawIn_normDist_T_31 = mux(_c1_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c1_self_rec_rawIn_normDist_T_30) node _c1_self_rec_rawIn_normDist_T_32 = mux(_c1_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c1_self_rec_rawIn_normDist_T_31) node _c1_self_rec_rawIn_normDist_T_33 = mux(_c1_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c1_self_rec_rawIn_normDist_T_32) node _c1_self_rec_rawIn_normDist_T_34 = mux(_c1_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c1_self_rec_rawIn_normDist_T_33) node _c1_self_rec_rawIn_normDist_T_35 = mux(_c1_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c1_self_rec_rawIn_normDist_T_34) node _c1_self_rec_rawIn_normDist_T_36 = mux(_c1_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c1_self_rec_rawIn_normDist_T_35) node _c1_self_rec_rawIn_normDist_T_37 = mux(_c1_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c1_self_rec_rawIn_normDist_T_36) node _c1_self_rec_rawIn_normDist_T_38 = mux(_c1_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c1_self_rec_rawIn_normDist_T_37) node _c1_self_rec_rawIn_normDist_T_39 = mux(_c1_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c1_self_rec_rawIn_normDist_T_38) node _c1_self_rec_rawIn_normDist_T_40 = mux(_c1_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c1_self_rec_rawIn_normDist_T_39) node _c1_self_rec_rawIn_normDist_T_41 = mux(_c1_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c1_self_rec_rawIn_normDist_T_40) node _c1_self_rec_rawIn_normDist_T_42 = mux(_c1_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c1_self_rec_rawIn_normDist_T_41) node _c1_self_rec_rawIn_normDist_T_43 = mux(_c1_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c1_self_rec_rawIn_normDist_T_42) node c1_self_rec_rawIn_normDist = mux(_c1_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c1_self_rec_rawIn_normDist_T_43) node _c1_self_rec_rawIn_subnormFract_T = dshl(c1_self_rec_rawIn_fractIn, c1_self_rec_rawIn_normDist) node _c1_self_rec_rawIn_subnormFract_T_1 = bits(_c1_self_rec_rawIn_subnormFract_T, 21, 0) node c1_self_rec_rawIn_subnormFract = shl(_c1_self_rec_rawIn_subnormFract_T_1, 1) node _c1_self_rec_rawIn_adjustedExp_T = xor(c1_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c1_self_rec_rawIn_adjustedExp_T_1 = mux(c1_self_rec_rawIn_isZeroExpIn, _c1_self_rec_rawIn_adjustedExp_T, c1_self_rec_rawIn_expIn) node _c1_self_rec_rawIn_adjustedExp_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c1_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c1_self_rec_rawIn_adjustedExp_T_2) node _c1_self_rec_rawIn_adjustedExp_T_4 = add(_c1_self_rec_rawIn_adjustedExp_T_1, _c1_self_rec_rawIn_adjustedExp_T_3) node c1_self_rec_rawIn_adjustedExp = tail(_c1_self_rec_rawIn_adjustedExp_T_4, 1) node c1_self_rec_rawIn_isZero = and(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_isZeroFractIn) node _c1_self_rec_rawIn_isSpecial_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 7) node c1_self_rec_rawIn_isSpecial = eq(_c1_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_self_rec_rawIn_out_isNaN_T = eq(c1_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_isNaN_T_1 = and(c1_self_rec_rawIn_isSpecial, _c1_self_rec_rawIn_out_isNaN_T) connect c1_self_rec_rawIn.isNaN, _c1_self_rec_rawIn_out_isNaN_T_1 node _c1_self_rec_rawIn_out_isInf_T = and(c1_self_rec_rawIn_isSpecial, c1_self_rec_rawIn_isZeroFractIn) connect c1_self_rec_rawIn.isInf, _c1_self_rec_rawIn_out_isInf_T connect c1_self_rec_rawIn.isZero, c1_self_rec_rawIn_isZero connect c1_self_rec_rawIn.sign, c1_self_rec_rawIn_sign node _c1_self_rec_rawIn_out_sExp_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 0) node _c1_self_rec_rawIn_out_sExp_T_1 = cvt(_c1_self_rec_rawIn_out_sExp_T) connect c1_self_rec_rawIn.sExp, _c1_self_rec_rawIn_out_sExp_T_1 node _c1_self_rec_rawIn_out_sig_T = eq(c1_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_self_rec_rawIn_out_sig_T) node _c1_self_rec_rawIn_out_sig_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_subnormFract, c1_self_rec_rawIn_fractIn) node _c1_self_rec_rawIn_out_sig_T_3 = cat(_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2) connect c1_self_rec_rawIn.sig, _c1_self_rec_rawIn_out_sig_T_3 node _c1_self_rec_T = bits(c1_self_rec_rawIn.sExp, 8, 6) node _c1_self_rec_T_1 = mux(c1_self_rec_rawIn.isZero, UInt<3>(0h0), _c1_self_rec_T) node _c1_self_rec_T_2 = mux(c1_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c1_self_rec_T_3 = or(_c1_self_rec_T_1, _c1_self_rec_T_2) node _c1_self_rec_T_4 = cat(c1_self_rec_rawIn.sign, _c1_self_rec_T_3) node _c1_self_rec_T_5 = bits(c1_self_rec_rawIn.sExp, 5, 0) node _c1_self_rec_T_6 = cat(_c1_self_rec_T_4, _c1_self_rec_T_5) node _c1_self_rec_T_7 = bits(c1_self_rec_rawIn.sig, 22, 0) node c1_self_rec = cat(_c1_self_rec_T_6, _c1_self_rec_T_7) inst c1_resizer of RecFNToRecFN_171 connect c1_resizer.io.in, c1_self_rec connect c1_resizer.io.roundingMode, UInt<3>(0h0) connect c1_resizer.io.detectTininess, UInt<1>(0h1) wire c1_result : { bits : UInt<32>} node c1_result_bits_rawIn_exp = bits(c1_resizer.io.out, 31, 23) node _c1_result_bits_rawIn_isZero_T = bits(c1_result_bits_rawIn_exp, 8, 6) node c1_result_bits_rawIn_isZero = eq(_c1_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_isSpecial_T = bits(c1_result_bits_rawIn_exp, 8, 7) node c1_result_bits_rawIn_isSpecial = eq(_c1_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_result_bits_rawIn_out_isNaN_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isNaN_T_1 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isNaN_T) connect c1_result_bits_rawIn.isNaN, _c1_result_bits_rawIn_out_isNaN_T_1 node _c1_result_bits_rawIn_out_isInf_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isInf_T_1 = eq(_c1_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_isInf_T_2 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isInf_T_1) connect c1_result_bits_rawIn.isInf, _c1_result_bits_rawIn_out_isInf_T_2 connect c1_result_bits_rawIn.isZero, c1_result_bits_rawIn_isZero node _c1_result_bits_rawIn_out_sign_T = bits(c1_resizer.io.out, 32, 32) connect c1_result_bits_rawIn.sign, _c1_result_bits_rawIn_out_sign_T node _c1_result_bits_rawIn_out_sExp_T = cvt(c1_result_bits_rawIn_exp) connect c1_result_bits_rawIn.sExp, _c1_result_bits_rawIn_out_sExp_T node _c1_result_bits_rawIn_out_sig_T = eq(c1_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_result_bits_rawIn_out_sig_T) node _c1_result_bits_rawIn_out_sig_T_2 = bits(c1_resizer.io.out, 22, 0) node _c1_result_bits_rawIn_out_sig_T_3 = cat(_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2) connect c1_result_bits_rawIn.sig, _c1_result_bits_rawIn_out_sig_T_3 node c1_result_bits_isSubnormal = lt(c1_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c1_result_bits_denormShiftDist_T = bits(c1_result_bits_rawIn.sExp, 4, 0) node _c1_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c1_result_bits_denormShiftDist_T) node c1_result_bits_denormShiftDist = tail(_c1_result_bits_denormShiftDist_T_1, 1) node _c1_result_bits_denormFract_T = shr(c1_result_bits_rawIn.sig, 1) node _c1_result_bits_denormFract_T_1 = dshr(_c1_result_bits_denormFract_T, c1_result_bits_denormShiftDist) node c1_result_bits_denormFract = bits(_c1_result_bits_denormFract_T_1, 22, 0) node _c1_result_bits_expOut_T = bits(c1_result_bits_rawIn.sExp, 7, 0) node _c1_result_bits_expOut_T_1 = sub(_c1_result_bits_expOut_T, UInt<8>(0h81)) node _c1_result_bits_expOut_T_2 = tail(_c1_result_bits_expOut_T_1, 1) node _c1_result_bits_expOut_T_3 = mux(c1_result_bits_isSubnormal, UInt<1>(0h0), _c1_result_bits_expOut_T_2) node _c1_result_bits_expOut_T_4 = or(c1_result_bits_rawIn.isNaN, c1_result_bits_rawIn.isInf) node _c1_result_bits_expOut_T_5 = mux(_c1_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c1_result_bits_expOut = or(_c1_result_bits_expOut_T_3, _c1_result_bits_expOut_T_5) node _c1_result_bits_fractOut_T = bits(c1_result_bits_rawIn.sig, 22, 0) node _c1_result_bits_fractOut_T_1 = mux(c1_result_bits_rawIn.isInf, UInt<1>(0h0), _c1_result_bits_fractOut_T) node c1_result_bits_fractOut = mux(c1_result_bits_isSubnormal, c1_result_bits_denormFract, _c1_result_bits_fractOut_T_1) node c1_result_bits_hi = cat(c1_result_bits_rawIn.sign, c1_result_bits_expOut) node _c1_result_bits_T = cat(c1_result_bits_hi, c1_result_bits_fractOut) connect c1_result.bits, _c1_result_bits_T connect c1, c1_result else : node io_out_c_self_rec_rawIn_sign_2 = bits(c2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_2 = bits(c2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_2 = bits(c2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_2 = eq(io_out_c_self_rec_rawIn_expIn_2, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_2 = eq(io_out_c_self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_88 = bits(io_out_c_self_rec_rawIn_fractIn_2, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_89 = bits(io_out_c_self_rec_rawIn_fractIn_2, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_90 = bits(io_out_c_self_rec_rawIn_fractIn_2, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_91 = bits(io_out_c_self_rec_rawIn_fractIn_2, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_92 = bits(io_out_c_self_rec_rawIn_fractIn_2, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_93 = bits(io_out_c_self_rec_rawIn_fractIn_2, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_94 = bits(io_out_c_self_rec_rawIn_fractIn_2, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_95 = bits(io_out_c_self_rec_rawIn_fractIn_2, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_96 = bits(io_out_c_self_rec_rawIn_fractIn_2, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_97 = bits(io_out_c_self_rec_rawIn_fractIn_2, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_98 = bits(io_out_c_self_rec_rawIn_fractIn_2, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_99 = bits(io_out_c_self_rec_rawIn_fractIn_2, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_100 = bits(io_out_c_self_rec_rawIn_fractIn_2, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_101 = bits(io_out_c_self_rec_rawIn_fractIn_2, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_102 = bits(io_out_c_self_rec_rawIn_fractIn_2, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_103 = bits(io_out_c_self_rec_rawIn_fractIn_2, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_104 = bits(io_out_c_self_rec_rawIn_fractIn_2, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_105 = bits(io_out_c_self_rec_rawIn_fractIn_2, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_106 = bits(io_out_c_self_rec_rawIn_fractIn_2, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_107 = bits(io_out_c_self_rec_rawIn_fractIn_2, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_108 = bits(io_out_c_self_rec_rawIn_fractIn_2, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_109 = bits(io_out_c_self_rec_rawIn_fractIn_2, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_110 = bits(io_out_c_self_rec_rawIn_fractIn_2, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_111 = mux(_io_out_c_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_112 = mux(_io_out_c_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_111) node _io_out_c_self_rec_rawIn_normDist_T_113 = mux(_io_out_c_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_112) node _io_out_c_self_rec_rawIn_normDist_T_114 = mux(_io_out_c_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_113) node _io_out_c_self_rec_rawIn_normDist_T_115 = mux(_io_out_c_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_114) node _io_out_c_self_rec_rawIn_normDist_T_116 = mux(_io_out_c_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_115) node _io_out_c_self_rec_rawIn_normDist_T_117 = mux(_io_out_c_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_116) node _io_out_c_self_rec_rawIn_normDist_T_118 = mux(_io_out_c_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_117) node _io_out_c_self_rec_rawIn_normDist_T_119 = mux(_io_out_c_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_118) node _io_out_c_self_rec_rawIn_normDist_T_120 = mux(_io_out_c_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_119) node _io_out_c_self_rec_rawIn_normDist_T_121 = mux(_io_out_c_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_120) node _io_out_c_self_rec_rawIn_normDist_T_122 = mux(_io_out_c_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_121) node _io_out_c_self_rec_rawIn_normDist_T_123 = mux(_io_out_c_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_122) node _io_out_c_self_rec_rawIn_normDist_T_124 = mux(_io_out_c_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_123) node _io_out_c_self_rec_rawIn_normDist_T_125 = mux(_io_out_c_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_124) node _io_out_c_self_rec_rawIn_normDist_T_126 = mux(_io_out_c_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_125) node _io_out_c_self_rec_rawIn_normDist_T_127 = mux(_io_out_c_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_126) node _io_out_c_self_rec_rawIn_normDist_T_128 = mux(_io_out_c_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_127) node _io_out_c_self_rec_rawIn_normDist_T_129 = mux(_io_out_c_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_128) node _io_out_c_self_rec_rawIn_normDist_T_130 = mux(_io_out_c_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_129) node _io_out_c_self_rec_rawIn_normDist_T_131 = mux(_io_out_c_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_130) node io_out_c_self_rec_rawIn_normDist_2 = mux(_io_out_c_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_131) node _io_out_c_self_rec_rawIn_subnormFract_T_4 = dshl(io_out_c_self_rec_rawIn_fractIn_2, io_out_c_self_rec_rawIn_normDist_2) node _io_out_c_self_rec_rawIn_subnormFract_T_5 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_4, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_2 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_5, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_10 = xor(io_out_c_self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_11 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, _io_out_c_self_rec_rawIn_adjustedExp_T_10, io_out_c_self_rec_rawIn_expIn_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_12 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_12) node _io_out_c_self_rec_rawIn_adjustedExp_T_14 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_11, _io_out_c_self_rec_rawIn_adjustedExp_T_13) node io_out_c_self_rec_rawIn_adjustedExp_2 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_14, 1) node io_out_c_self_rec_rawIn_isZero_2 = and(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) node _io_out_c_self_rec_rawIn_isSpecial_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_2 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_4 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_5 = and(io_out_c_self_rec_rawIn_isSpecial_2, _io_out_c_self_rec_rawIn_out_isNaN_T_4) connect io_out_c_self_rec_rawIn_2.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_5 node _io_out_c_self_rec_rawIn_out_isInf_T_2 = and(io_out_c_self_rec_rawIn_isSpecial_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) connect io_out_c_self_rec_rawIn_2.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_2 connect io_out_c_self_rec_rawIn_2.isZero, io_out_c_self_rec_rawIn_isZero_2 connect io_out_c_self_rec_rawIn_2.sign, io_out_c_self_rec_rawIn_sign_2 node _io_out_c_self_rec_rawIn_out_sExp_T_4 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_5 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_4) connect io_out_c_self_rec_rawIn_2.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_5 node _io_out_c_self_rec_rawIn_out_sig_T_8 = eq(io_out_c_self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_8) node _io_out_c_self_rec_rawIn_out_sig_T_10 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_subnormFract_2, io_out_c_self_rec_rawIn_fractIn_2) node _io_out_c_self_rec_rawIn_out_sig_T_11 = cat(_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10) connect io_out_c_self_rec_rawIn_2.sig, _io_out_c_self_rec_rawIn_out_sig_T_11 node _io_out_c_self_rec_T_16 = bits(io_out_c_self_rec_rawIn_2.sExp, 8, 6) node _io_out_c_self_rec_T_17 = mux(io_out_c_self_rec_rawIn_2.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_16) node _io_out_c_self_rec_T_18 = mux(io_out_c_self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_19 = or(_io_out_c_self_rec_T_17, _io_out_c_self_rec_T_18) node _io_out_c_self_rec_T_20 = cat(io_out_c_self_rec_rawIn_2.sign, _io_out_c_self_rec_T_19) node _io_out_c_self_rec_T_21 = bits(io_out_c_self_rec_rawIn_2.sExp, 5, 0) node _io_out_c_self_rec_T_22 = cat(_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21) node _io_out_c_self_rec_T_23 = bits(io_out_c_self_rec_rawIn_2.sig, 22, 0) node io_out_c_self_rec_2 = cat(_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23) wire io_out_c_shift_exp_1 : UInt<8> node _io_out_c_shift_exp_T_2 = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_3 = tail(_io_out_c_shift_exp_T_2, 1) connect io_out_c_shift_exp_1, _io_out_c_shift_exp_T_3 node io_out_c_shift_fn_hi_1 = cat(UInt<1>(0h0), io_out_c_shift_exp_1) node io_out_c_shift_fn_1 = cat(io_out_c_shift_fn_hi_1, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign_1 = bits(io_out_c_shift_fn_1, 31, 31) node io_out_c_shift_rec_rawIn_expIn_1 = bits(io_out_c_shift_fn_1, 30, 23) node io_out_c_shift_rec_rawIn_fractIn_1 = bits(io_out_c_shift_fn_1, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_shift_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_shift_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T_44 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_45 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_46 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_47 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_48 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_49 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_50 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_51 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_52 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_53 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_54 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_55 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_56 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_57 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_58 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_59 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_60 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_61 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_62 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_63 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_64 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_65 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_66 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_67 = mux(_io_out_c_shift_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_68 = mux(_io_out_c_shift_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_67) node _io_out_c_shift_rec_rawIn_normDist_T_69 = mux(_io_out_c_shift_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_68) node _io_out_c_shift_rec_rawIn_normDist_T_70 = mux(_io_out_c_shift_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_69) node _io_out_c_shift_rec_rawIn_normDist_T_71 = mux(_io_out_c_shift_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_70) node _io_out_c_shift_rec_rawIn_normDist_T_72 = mux(_io_out_c_shift_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_71) node _io_out_c_shift_rec_rawIn_normDist_T_73 = mux(_io_out_c_shift_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_72) node _io_out_c_shift_rec_rawIn_normDist_T_74 = mux(_io_out_c_shift_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_73) node _io_out_c_shift_rec_rawIn_normDist_T_75 = mux(_io_out_c_shift_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_74) node _io_out_c_shift_rec_rawIn_normDist_T_76 = mux(_io_out_c_shift_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_75) node _io_out_c_shift_rec_rawIn_normDist_T_77 = mux(_io_out_c_shift_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_76) node _io_out_c_shift_rec_rawIn_normDist_T_78 = mux(_io_out_c_shift_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_77) node _io_out_c_shift_rec_rawIn_normDist_T_79 = mux(_io_out_c_shift_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_78) node _io_out_c_shift_rec_rawIn_normDist_T_80 = mux(_io_out_c_shift_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_79) node _io_out_c_shift_rec_rawIn_normDist_T_81 = mux(_io_out_c_shift_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_80) node _io_out_c_shift_rec_rawIn_normDist_T_82 = mux(_io_out_c_shift_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_81) node _io_out_c_shift_rec_rawIn_normDist_T_83 = mux(_io_out_c_shift_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_82) node _io_out_c_shift_rec_rawIn_normDist_T_84 = mux(_io_out_c_shift_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_83) node _io_out_c_shift_rec_rawIn_normDist_T_85 = mux(_io_out_c_shift_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_84) node _io_out_c_shift_rec_rawIn_normDist_T_86 = mux(_io_out_c_shift_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_85) node _io_out_c_shift_rec_rawIn_normDist_T_87 = mux(_io_out_c_shift_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_86) node io_out_c_shift_rec_rawIn_normDist_1 = mux(_io_out_c_shift_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_87) node _io_out_c_shift_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_shift_rec_rawIn_fractIn_1, io_out_c_shift_rec_rawIn_normDist_1) node _io_out_c_shift_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract_1 = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_shift_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_5, io_out_c_shift_rec_rawIn_expIn_1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_7) node _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_6, _io_out_c_shift_rec_rawIn_adjustedExp_T_8) node io_out_c_shift_rec_rawIn_adjustedExp_1 = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_shift_rec_rawIn_isZero_1 = and(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) node _io_out_c_shift_rec_rawIn_isSpecial_T_1 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial_1 = eq(_io_out_c_shift_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_shift_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = and(io_out_c_shift_rec_rawIn_isSpecial_1, _io_out_c_shift_rec_rawIn_out_isNaN_T_2) connect io_out_c_shift_rec_rawIn_1.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_3 node _io_out_c_shift_rec_rawIn_out_isInf_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) connect io_out_c_shift_rec_rawIn_1.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T_1 connect io_out_c_shift_rec_rawIn_1.isZero, io_out_c_shift_rec_rawIn_isZero_1 connect io_out_c_shift_rec_rawIn_1.sign, io_out_c_shift_rec_rawIn_sign_1 node _io_out_c_shift_rec_rawIn_out_sExp_T_2 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T_2) connect io_out_c_shift_rec_rawIn_1.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_3 node _io_out_c_shift_rec_rawIn_out_sig_T_4 = eq(io_out_c_shift_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T_4) node _io_out_c_shift_rec_rawIn_out_sig_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_subnormFract_1, io_out_c_shift_rec_rawIn_fractIn_1) node _io_out_c_shift_rec_rawIn_out_sig_T_7 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6) connect io_out_c_shift_rec_rawIn_1.sig, _io_out_c_shift_rec_rawIn_out_sig_T_7 node _io_out_c_shift_rec_T_8 = bits(io_out_c_shift_rec_rawIn_1.sExp, 8, 6) node _io_out_c_shift_rec_T_9 = mux(io_out_c_shift_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T_8) node _io_out_c_shift_rec_T_10 = mux(io_out_c_shift_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_11 = or(_io_out_c_shift_rec_T_9, _io_out_c_shift_rec_T_10) node _io_out_c_shift_rec_T_12 = cat(io_out_c_shift_rec_rawIn_1.sign, _io_out_c_shift_rec_T_11) node _io_out_c_shift_rec_T_13 = bits(io_out_c_shift_rec_rawIn_1.sExp, 5, 0) node _io_out_c_shift_rec_T_14 = cat(_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13) node _io_out_c_shift_rec_T_15 = bits(io_out_c_shift_rec_rawIn_1.sig, 22, 0) node io_out_c_shift_rec_1 = cat(_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15) node _io_out_c_T_4 = neq(io_out_c_shift_exp_1, UInt<1>(0h0)) node _io_out_c_T_5 = asUInt(reset) node _io_out_c_T_6 = eq(_io_out_c_T_5, UInt<1>(0h0)) when _io_out_c_T_6 : node _io_out_c_T_7 = eq(_io_out_c_T_4, UInt<1>(0h0)) when _io_out_c_T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf_1 assert(clock, _io_out_c_T_4, UInt<1>(0h1), "") : io_out_c_assert_1 inst io_out_c_muladder_1 of MulRecFN_33 connect io_out_c_muladder_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder_1.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder_1.io.a, io_out_c_self_rec_2 connect io_out_c_muladder_1.io.b, io_out_c_shift_rec_1 wire io_out_c_result_2 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_2 = bits(io_out_c_muladder_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 6) node io_out_c_result_bits_rawIn_isZero_2 = eq(_io_out_c_result_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_2 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_4 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isNaN_T_4) connect io_out_c_result_bits_rawIn_2.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_5 node _io_out_c_result_bits_rawIn_out_isInf_T_6 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_7 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_8 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isInf_T_7) connect io_out_c_result_bits_rawIn_2.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_8 connect io_out_c_result_bits_rawIn_2.isZero, io_out_c_result_bits_rawIn_isZero_2 node _io_out_c_result_bits_rawIn_out_sign_T_2 = bits(io_out_c_muladder_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_2.sign, _io_out_c_result_bits_rawIn_out_sign_T_2 node _io_out_c_result_bits_rawIn_out_sExp_T_2 = cvt(io_out_c_result_bits_rawIn_exp_2) connect io_out_c_result_bits_rawIn_2.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_2 node _io_out_c_result_bits_rawIn_out_sig_T_8 = eq(io_out_c_result_bits_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_8) node _io_out_c_result_bits_rawIn_out_sig_T_10 = bits(io_out_c_muladder_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_11 = cat(_io_out_c_result_bits_rawIn_out_sig_T_9, _io_out_c_result_bits_rawIn_out_sig_T_10) connect io_out_c_result_bits_rawIn_2.sig, _io_out_c_result_bits_rawIn_out_sig_T_11 node io_out_c_result_bits_isSubnormal_2 = lt(io_out_c_result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_4 = bits(io_out_c_result_bits_rawIn_2.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_4) node io_out_c_result_bits_denormShiftDist_2 = tail(_io_out_c_result_bits_denormShiftDist_T_5, 1) node _io_out_c_result_bits_denormFract_T_4 = shr(io_out_c_result_bits_rawIn_2.sig, 1) node _io_out_c_result_bits_denormFract_T_5 = dshr(_io_out_c_result_bits_denormFract_T_4, io_out_c_result_bits_denormShiftDist_2) node io_out_c_result_bits_denormFract_2 = bits(_io_out_c_result_bits_denormFract_T_5, 22, 0) node _io_out_c_result_bits_expOut_T_12 = bits(io_out_c_result_bits_rawIn_2.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_13 = sub(_io_out_c_result_bits_expOut_T_12, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_14 = tail(_io_out_c_result_bits_expOut_T_13, 1) node _io_out_c_result_bits_expOut_T_15 = mux(io_out_c_result_bits_isSubnormal_2, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_14) node _io_out_c_result_bits_expOut_T_16 = or(io_out_c_result_bits_rawIn_2.isNaN, io_out_c_result_bits_rawIn_2.isInf) node _io_out_c_result_bits_expOut_T_17 = mux(_io_out_c_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_2 = or(_io_out_c_result_bits_expOut_T_15, _io_out_c_result_bits_expOut_T_17) node _io_out_c_result_bits_fractOut_T_4 = bits(io_out_c_result_bits_rawIn_2.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_5 = mux(io_out_c_result_bits_rawIn_2.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_4) node io_out_c_result_bits_fractOut_2 = mux(io_out_c_result_bits_isSubnormal_2, io_out_c_result_bits_denormFract_2, _io_out_c_result_bits_fractOut_T_5) node io_out_c_result_bits_hi_2 = cat(io_out_c_result_bits_rawIn_2.sign, io_out_c_result_bits_expOut_2) node _io_out_c_result_bits_T_2 = cat(io_out_c_result_bits_hi_2, io_out_c_result_bits_fractOut_2) connect io_out_c_result_2.bits, _io_out_c_result_bits_T_2 node io_out_c_self_rec_rawIn_sign_3 = bits(io_out_c_result_2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_3 = bits(io_out_c_result_2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_3 = bits(io_out_c_result_2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_3 = eq(io_out_c_self_rec_rawIn_expIn_3, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_3 = eq(io_out_c_self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_132 = bits(io_out_c_self_rec_rawIn_fractIn_3, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_133 = bits(io_out_c_self_rec_rawIn_fractIn_3, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_134 = bits(io_out_c_self_rec_rawIn_fractIn_3, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_135 = bits(io_out_c_self_rec_rawIn_fractIn_3, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_136 = bits(io_out_c_self_rec_rawIn_fractIn_3, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_137 = bits(io_out_c_self_rec_rawIn_fractIn_3, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_138 = bits(io_out_c_self_rec_rawIn_fractIn_3, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_139 = bits(io_out_c_self_rec_rawIn_fractIn_3, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_140 = bits(io_out_c_self_rec_rawIn_fractIn_3, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_141 = bits(io_out_c_self_rec_rawIn_fractIn_3, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_142 = bits(io_out_c_self_rec_rawIn_fractIn_3, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_143 = bits(io_out_c_self_rec_rawIn_fractIn_3, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_144 = bits(io_out_c_self_rec_rawIn_fractIn_3, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_145 = bits(io_out_c_self_rec_rawIn_fractIn_3, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_146 = bits(io_out_c_self_rec_rawIn_fractIn_3, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_147 = bits(io_out_c_self_rec_rawIn_fractIn_3, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_148 = bits(io_out_c_self_rec_rawIn_fractIn_3, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_149 = bits(io_out_c_self_rec_rawIn_fractIn_3, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_150 = bits(io_out_c_self_rec_rawIn_fractIn_3, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_151 = bits(io_out_c_self_rec_rawIn_fractIn_3, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_152 = bits(io_out_c_self_rec_rawIn_fractIn_3, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_153 = bits(io_out_c_self_rec_rawIn_fractIn_3, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_154 = bits(io_out_c_self_rec_rawIn_fractIn_3, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_155 = mux(_io_out_c_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_156 = mux(_io_out_c_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_155) node _io_out_c_self_rec_rawIn_normDist_T_157 = mux(_io_out_c_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_156) node _io_out_c_self_rec_rawIn_normDist_T_158 = mux(_io_out_c_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_157) node _io_out_c_self_rec_rawIn_normDist_T_159 = mux(_io_out_c_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_158) node _io_out_c_self_rec_rawIn_normDist_T_160 = mux(_io_out_c_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_159) node _io_out_c_self_rec_rawIn_normDist_T_161 = mux(_io_out_c_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_160) node _io_out_c_self_rec_rawIn_normDist_T_162 = mux(_io_out_c_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_161) node _io_out_c_self_rec_rawIn_normDist_T_163 = mux(_io_out_c_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_162) node _io_out_c_self_rec_rawIn_normDist_T_164 = mux(_io_out_c_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_163) node _io_out_c_self_rec_rawIn_normDist_T_165 = mux(_io_out_c_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_164) node _io_out_c_self_rec_rawIn_normDist_T_166 = mux(_io_out_c_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_165) node _io_out_c_self_rec_rawIn_normDist_T_167 = mux(_io_out_c_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_166) node _io_out_c_self_rec_rawIn_normDist_T_168 = mux(_io_out_c_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_167) node _io_out_c_self_rec_rawIn_normDist_T_169 = mux(_io_out_c_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_168) node _io_out_c_self_rec_rawIn_normDist_T_170 = mux(_io_out_c_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_169) node _io_out_c_self_rec_rawIn_normDist_T_171 = mux(_io_out_c_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_170) node _io_out_c_self_rec_rawIn_normDist_T_172 = mux(_io_out_c_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_171) node _io_out_c_self_rec_rawIn_normDist_T_173 = mux(_io_out_c_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_172) node _io_out_c_self_rec_rawIn_normDist_T_174 = mux(_io_out_c_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_173) node _io_out_c_self_rec_rawIn_normDist_T_175 = mux(_io_out_c_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_174) node io_out_c_self_rec_rawIn_normDist_3 = mux(_io_out_c_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_175) node _io_out_c_self_rec_rawIn_subnormFract_T_6 = dshl(io_out_c_self_rec_rawIn_fractIn_3, io_out_c_self_rec_rawIn_normDist_3) node _io_out_c_self_rec_rawIn_subnormFract_T_7 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_6, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_3 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_7, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_15 = xor(io_out_c_self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_16 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, _io_out_c_self_rec_rawIn_adjustedExp_T_15, io_out_c_self_rec_rawIn_expIn_3) node _io_out_c_self_rec_rawIn_adjustedExp_T_17 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_17) node _io_out_c_self_rec_rawIn_adjustedExp_T_19 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_16, _io_out_c_self_rec_rawIn_adjustedExp_T_18) node io_out_c_self_rec_rawIn_adjustedExp_3 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_19, 1) node io_out_c_self_rec_rawIn_isZero_3 = and(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) node _io_out_c_self_rec_rawIn_isSpecial_T_3 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_3 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_6 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_7 = and(io_out_c_self_rec_rawIn_isSpecial_3, _io_out_c_self_rec_rawIn_out_isNaN_T_6) connect io_out_c_self_rec_rawIn_3.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_7 node _io_out_c_self_rec_rawIn_out_isInf_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) connect io_out_c_self_rec_rawIn_3.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_3 connect io_out_c_self_rec_rawIn_3.isZero, io_out_c_self_rec_rawIn_isZero_3 connect io_out_c_self_rec_rawIn_3.sign, io_out_c_self_rec_rawIn_sign_3 node _io_out_c_self_rec_rawIn_out_sExp_T_6 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_7 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_6) connect io_out_c_self_rec_rawIn_3.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_7 node _io_out_c_self_rec_rawIn_out_sig_T_12 = eq(io_out_c_self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_12) node _io_out_c_self_rec_rawIn_out_sig_T_14 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_subnormFract_3, io_out_c_self_rec_rawIn_fractIn_3) node _io_out_c_self_rec_rawIn_out_sig_T_15 = cat(_io_out_c_self_rec_rawIn_out_sig_T_13, _io_out_c_self_rec_rawIn_out_sig_T_14) connect io_out_c_self_rec_rawIn_3.sig, _io_out_c_self_rec_rawIn_out_sig_T_15 node _io_out_c_self_rec_T_24 = bits(io_out_c_self_rec_rawIn_3.sExp, 8, 6) node _io_out_c_self_rec_T_25 = mux(io_out_c_self_rec_rawIn_3.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_24) node _io_out_c_self_rec_T_26 = mux(io_out_c_self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_27 = or(_io_out_c_self_rec_T_25, _io_out_c_self_rec_T_26) node _io_out_c_self_rec_T_28 = cat(io_out_c_self_rec_rawIn_3.sign, _io_out_c_self_rec_T_27) node _io_out_c_self_rec_T_29 = bits(io_out_c_self_rec_rawIn_3.sExp, 5, 0) node _io_out_c_self_rec_T_30 = cat(_io_out_c_self_rec_T_28, _io_out_c_self_rec_T_29) node _io_out_c_self_rec_T_31 = bits(io_out_c_self_rec_rawIn_3.sig, 22, 0) node io_out_c_self_rec_3 = cat(_io_out_c_self_rec_T_30, _io_out_c_self_rec_T_31) inst io_out_c_resizer_1 of RecFNToRecFN_172 connect io_out_c_resizer_1.io.in, io_out_c_self_rec_3 connect io_out_c_resizer_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer_1.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_3 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_3 = bits(io_out_c_resizer_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 6) node io_out_c_result_bits_rawIn_isZero_3 = eq(_io_out_c_result_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_3 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_6 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_7 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isNaN_T_6) connect io_out_c_result_bits_rawIn_3.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_7 node _io_out_c_result_bits_rawIn_out_isInf_T_9 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_10 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_11 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isInf_T_10) connect io_out_c_result_bits_rawIn_3.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_11 connect io_out_c_result_bits_rawIn_3.isZero, io_out_c_result_bits_rawIn_isZero_3 node _io_out_c_result_bits_rawIn_out_sign_T_3 = bits(io_out_c_resizer_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_3.sign, _io_out_c_result_bits_rawIn_out_sign_T_3 node _io_out_c_result_bits_rawIn_out_sExp_T_3 = cvt(io_out_c_result_bits_rawIn_exp_3) connect io_out_c_result_bits_rawIn_3.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_3 node _io_out_c_result_bits_rawIn_out_sig_T_12 = eq(io_out_c_result_bits_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_12) node _io_out_c_result_bits_rawIn_out_sig_T_14 = bits(io_out_c_resizer_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_15 = cat(_io_out_c_result_bits_rawIn_out_sig_T_13, _io_out_c_result_bits_rawIn_out_sig_T_14) connect io_out_c_result_bits_rawIn_3.sig, _io_out_c_result_bits_rawIn_out_sig_T_15 node io_out_c_result_bits_isSubnormal_3 = lt(io_out_c_result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_6 = bits(io_out_c_result_bits_rawIn_3.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_6) node io_out_c_result_bits_denormShiftDist_3 = tail(_io_out_c_result_bits_denormShiftDist_T_7, 1) node _io_out_c_result_bits_denormFract_T_6 = shr(io_out_c_result_bits_rawIn_3.sig, 1) node _io_out_c_result_bits_denormFract_T_7 = dshr(_io_out_c_result_bits_denormFract_T_6, io_out_c_result_bits_denormShiftDist_3) node io_out_c_result_bits_denormFract_3 = bits(_io_out_c_result_bits_denormFract_T_7, 22, 0) node _io_out_c_result_bits_expOut_T_18 = bits(io_out_c_result_bits_rawIn_3.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_19 = sub(_io_out_c_result_bits_expOut_T_18, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_20 = tail(_io_out_c_result_bits_expOut_T_19, 1) node _io_out_c_result_bits_expOut_T_21 = mux(io_out_c_result_bits_isSubnormal_3, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_20) node _io_out_c_result_bits_expOut_T_22 = or(io_out_c_result_bits_rawIn_3.isNaN, io_out_c_result_bits_rawIn_3.isInf) node _io_out_c_result_bits_expOut_T_23 = mux(_io_out_c_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_3 = or(_io_out_c_result_bits_expOut_T_21, _io_out_c_result_bits_expOut_T_23) node _io_out_c_result_bits_fractOut_T_6 = bits(io_out_c_result_bits_rawIn_3.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_7 = mux(io_out_c_result_bits_rawIn_3.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_6) node io_out_c_result_bits_fractOut_3 = mux(io_out_c_result_bits_isSubnormal_3, io_out_c_result_bits_denormFract_3, _io_out_c_result_bits_fractOut_T_7) node io_out_c_result_bits_hi_3 = cat(io_out_c_result_bits_rawIn_3.sign, io_out_c_result_bits_expOut_3) node _io_out_c_result_bits_T_3 = cat(io_out_c_result_bits_hi_3, io_out_c_result_bits_fractOut_3) connect io_out_c_result_3.bits, _io_out_c_result_bits_T_3 connect io.out_c, io_out_c_result_3 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_2 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_3 : UInt<32> connect _mac_unit_io_in_b_WIRE_3, io.in_b.bits node _mac_unit_io_in_b_T_1 = bits(_mac_unit_io_in_b_WIRE_3, 31, 0) connect _mac_unit_io_in_b_WIRE_2.bits, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_2.bits connect mac_unit.io.in_c.bits, c1.bits connect c1, mac_unit.io.out_d node c2_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c2_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c2_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c2_self_rec_rawIn_isZeroExpIn = eq(c2_self_rec_rawIn_expIn, UInt<1>(0h0)) node c2_self_rec_rawIn_isZeroFractIn = eq(c2_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_normDist_T = bits(c2_self_rec_rawIn_fractIn, 0, 0) node _c2_self_rec_rawIn_normDist_T_1 = bits(c2_self_rec_rawIn_fractIn, 1, 1) node _c2_self_rec_rawIn_normDist_T_2 = bits(c2_self_rec_rawIn_fractIn, 2, 2) node _c2_self_rec_rawIn_normDist_T_3 = bits(c2_self_rec_rawIn_fractIn, 3, 3) node _c2_self_rec_rawIn_normDist_T_4 = bits(c2_self_rec_rawIn_fractIn, 4, 4) node _c2_self_rec_rawIn_normDist_T_5 = bits(c2_self_rec_rawIn_fractIn, 5, 5) node _c2_self_rec_rawIn_normDist_T_6 = bits(c2_self_rec_rawIn_fractIn, 6, 6) node _c2_self_rec_rawIn_normDist_T_7 = bits(c2_self_rec_rawIn_fractIn, 7, 7) node _c2_self_rec_rawIn_normDist_T_8 = bits(c2_self_rec_rawIn_fractIn, 8, 8) node _c2_self_rec_rawIn_normDist_T_9 = bits(c2_self_rec_rawIn_fractIn, 9, 9) node _c2_self_rec_rawIn_normDist_T_10 = bits(c2_self_rec_rawIn_fractIn, 10, 10) node _c2_self_rec_rawIn_normDist_T_11 = bits(c2_self_rec_rawIn_fractIn, 11, 11) node _c2_self_rec_rawIn_normDist_T_12 = bits(c2_self_rec_rawIn_fractIn, 12, 12) node _c2_self_rec_rawIn_normDist_T_13 = bits(c2_self_rec_rawIn_fractIn, 13, 13) node _c2_self_rec_rawIn_normDist_T_14 = bits(c2_self_rec_rawIn_fractIn, 14, 14) node _c2_self_rec_rawIn_normDist_T_15 = bits(c2_self_rec_rawIn_fractIn, 15, 15) node _c2_self_rec_rawIn_normDist_T_16 = bits(c2_self_rec_rawIn_fractIn, 16, 16) node _c2_self_rec_rawIn_normDist_T_17 = bits(c2_self_rec_rawIn_fractIn, 17, 17) node _c2_self_rec_rawIn_normDist_T_18 = bits(c2_self_rec_rawIn_fractIn, 18, 18) node _c2_self_rec_rawIn_normDist_T_19 = bits(c2_self_rec_rawIn_fractIn, 19, 19) node _c2_self_rec_rawIn_normDist_T_20 = bits(c2_self_rec_rawIn_fractIn, 20, 20) node _c2_self_rec_rawIn_normDist_T_21 = bits(c2_self_rec_rawIn_fractIn, 21, 21) node _c2_self_rec_rawIn_normDist_T_22 = bits(c2_self_rec_rawIn_fractIn, 22, 22) node _c2_self_rec_rawIn_normDist_T_23 = mux(_c2_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c2_self_rec_rawIn_normDist_T_24 = mux(_c2_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c2_self_rec_rawIn_normDist_T_23) node _c2_self_rec_rawIn_normDist_T_25 = mux(_c2_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c2_self_rec_rawIn_normDist_T_24) node _c2_self_rec_rawIn_normDist_T_26 = mux(_c2_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c2_self_rec_rawIn_normDist_T_25) node _c2_self_rec_rawIn_normDist_T_27 = mux(_c2_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c2_self_rec_rawIn_normDist_T_26) node _c2_self_rec_rawIn_normDist_T_28 = mux(_c2_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c2_self_rec_rawIn_normDist_T_27) node _c2_self_rec_rawIn_normDist_T_29 = mux(_c2_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c2_self_rec_rawIn_normDist_T_28) node _c2_self_rec_rawIn_normDist_T_30 = mux(_c2_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c2_self_rec_rawIn_normDist_T_29) node _c2_self_rec_rawIn_normDist_T_31 = mux(_c2_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c2_self_rec_rawIn_normDist_T_30) node _c2_self_rec_rawIn_normDist_T_32 = mux(_c2_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c2_self_rec_rawIn_normDist_T_31) node _c2_self_rec_rawIn_normDist_T_33 = mux(_c2_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c2_self_rec_rawIn_normDist_T_32) node _c2_self_rec_rawIn_normDist_T_34 = mux(_c2_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c2_self_rec_rawIn_normDist_T_33) node _c2_self_rec_rawIn_normDist_T_35 = mux(_c2_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c2_self_rec_rawIn_normDist_T_34) node _c2_self_rec_rawIn_normDist_T_36 = mux(_c2_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c2_self_rec_rawIn_normDist_T_35) node _c2_self_rec_rawIn_normDist_T_37 = mux(_c2_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c2_self_rec_rawIn_normDist_T_36) node _c2_self_rec_rawIn_normDist_T_38 = mux(_c2_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c2_self_rec_rawIn_normDist_T_37) node _c2_self_rec_rawIn_normDist_T_39 = mux(_c2_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c2_self_rec_rawIn_normDist_T_38) node _c2_self_rec_rawIn_normDist_T_40 = mux(_c2_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c2_self_rec_rawIn_normDist_T_39) node _c2_self_rec_rawIn_normDist_T_41 = mux(_c2_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c2_self_rec_rawIn_normDist_T_40) node _c2_self_rec_rawIn_normDist_T_42 = mux(_c2_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c2_self_rec_rawIn_normDist_T_41) node _c2_self_rec_rawIn_normDist_T_43 = mux(_c2_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c2_self_rec_rawIn_normDist_T_42) node c2_self_rec_rawIn_normDist = mux(_c2_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c2_self_rec_rawIn_normDist_T_43) node _c2_self_rec_rawIn_subnormFract_T = dshl(c2_self_rec_rawIn_fractIn, c2_self_rec_rawIn_normDist) node _c2_self_rec_rawIn_subnormFract_T_1 = bits(_c2_self_rec_rawIn_subnormFract_T, 21, 0) node c2_self_rec_rawIn_subnormFract = shl(_c2_self_rec_rawIn_subnormFract_T_1, 1) node _c2_self_rec_rawIn_adjustedExp_T = xor(c2_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c2_self_rec_rawIn_adjustedExp_T_1 = mux(c2_self_rec_rawIn_isZeroExpIn, _c2_self_rec_rawIn_adjustedExp_T, c2_self_rec_rawIn_expIn) node _c2_self_rec_rawIn_adjustedExp_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c2_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c2_self_rec_rawIn_adjustedExp_T_2) node _c2_self_rec_rawIn_adjustedExp_T_4 = add(_c2_self_rec_rawIn_adjustedExp_T_1, _c2_self_rec_rawIn_adjustedExp_T_3) node c2_self_rec_rawIn_adjustedExp = tail(_c2_self_rec_rawIn_adjustedExp_T_4, 1) node c2_self_rec_rawIn_isZero = and(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_isZeroFractIn) node _c2_self_rec_rawIn_isSpecial_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 7) node c2_self_rec_rawIn_isSpecial = eq(_c2_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_self_rec_rawIn_out_isNaN_T = eq(c2_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_isNaN_T_1 = and(c2_self_rec_rawIn_isSpecial, _c2_self_rec_rawIn_out_isNaN_T) connect c2_self_rec_rawIn.isNaN, _c2_self_rec_rawIn_out_isNaN_T_1 node _c2_self_rec_rawIn_out_isInf_T = and(c2_self_rec_rawIn_isSpecial, c2_self_rec_rawIn_isZeroFractIn) connect c2_self_rec_rawIn.isInf, _c2_self_rec_rawIn_out_isInf_T connect c2_self_rec_rawIn.isZero, c2_self_rec_rawIn_isZero connect c2_self_rec_rawIn.sign, c2_self_rec_rawIn_sign node _c2_self_rec_rawIn_out_sExp_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 0) node _c2_self_rec_rawIn_out_sExp_T_1 = cvt(_c2_self_rec_rawIn_out_sExp_T) connect c2_self_rec_rawIn.sExp, _c2_self_rec_rawIn_out_sExp_T_1 node _c2_self_rec_rawIn_out_sig_T = eq(c2_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_self_rec_rawIn_out_sig_T) node _c2_self_rec_rawIn_out_sig_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_subnormFract, c2_self_rec_rawIn_fractIn) node _c2_self_rec_rawIn_out_sig_T_3 = cat(_c2_self_rec_rawIn_out_sig_T_1, _c2_self_rec_rawIn_out_sig_T_2) connect c2_self_rec_rawIn.sig, _c2_self_rec_rawIn_out_sig_T_3 node _c2_self_rec_T = bits(c2_self_rec_rawIn.sExp, 8, 6) node _c2_self_rec_T_1 = mux(c2_self_rec_rawIn.isZero, UInt<3>(0h0), _c2_self_rec_T) node _c2_self_rec_T_2 = mux(c2_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c2_self_rec_T_3 = or(_c2_self_rec_T_1, _c2_self_rec_T_2) node _c2_self_rec_T_4 = cat(c2_self_rec_rawIn.sign, _c2_self_rec_T_3) node _c2_self_rec_T_5 = bits(c2_self_rec_rawIn.sExp, 5, 0) node _c2_self_rec_T_6 = cat(_c2_self_rec_T_4, _c2_self_rec_T_5) node _c2_self_rec_T_7 = bits(c2_self_rec_rawIn.sig, 22, 0) node c2_self_rec = cat(_c2_self_rec_T_6, _c2_self_rec_T_7) inst c2_resizer of RecFNToRecFN_173 connect c2_resizer.io.in, c2_self_rec connect c2_resizer.io.roundingMode, UInt<3>(0h0) connect c2_resizer.io.detectTininess, UInt<1>(0h1) wire c2_result : { bits : UInt<32>} node c2_result_bits_rawIn_exp = bits(c2_resizer.io.out, 31, 23) node _c2_result_bits_rawIn_isZero_T = bits(c2_result_bits_rawIn_exp, 8, 6) node c2_result_bits_rawIn_isZero = eq(_c2_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_isSpecial_T = bits(c2_result_bits_rawIn_exp, 8, 7) node c2_result_bits_rawIn_isSpecial = eq(_c2_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_result_bits_rawIn_out_isNaN_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isNaN_T_1 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isNaN_T) connect c2_result_bits_rawIn.isNaN, _c2_result_bits_rawIn_out_isNaN_T_1 node _c2_result_bits_rawIn_out_isInf_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isInf_T_1 = eq(_c2_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_isInf_T_2 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isInf_T_1) connect c2_result_bits_rawIn.isInf, _c2_result_bits_rawIn_out_isInf_T_2 connect c2_result_bits_rawIn.isZero, c2_result_bits_rawIn_isZero node _c2_result_bits_rawIn_out_sign_T = bits(c2_resizer.io.out, 32, 32) connect c2_result_bits_rawIn.sign, _c2_result_bits_rawIn_out_sign_T node _c2_result_bits_rawIn_out_sExp_T = cvt(c2_result_bits_rawIn_exp) connect c2_result_bits_rawIn.sExp, _c2_result_bits_rawIn_out_sExp_T node _c2_result_bits_rawIn_out_sig_T = eq(c2_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_result_bits_rawIn_out_sig_T) node _c2_result_bits_rawIn_out_sig_T_2 = bits(c2_resizer.io.out, 22, 0) node _c2_result_bits_rawIn_out_sig_T_3 = cat(_c2_result_bits_rawIn_out_sig_T_1, _c2_result_bits_rawIn_out_sig_T_2) connect c2_result_bits_rawIn.sig, _c2_result_bits_rawIn_out_sig_T_3 node c2_result_bits_isSubnormal = lt(c2_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c2_result_bits_denormShiftDist_T = bits(c2_result_bits_rawIn.sExp, 4, 0) node _c2_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c2_result_bits_denormShiftDist_T) node c2_result_bits_denormShiftDist = tail(_c2_result_bits_denormShiftDist_T_1, 1) node _c2_result_bits_denormFract_T = shr(c2_result_bits_rawIn.sig, 1) node _c2_result_bits_denormFract_T_1 = dshr(_c2_result_bits_denormFract_T, c2_result_bits_denormShiftDist) node c2_result_bits_denormFract = bits(_c2_result_bits_denormFract_T_1, 22, 0) node _c2_result_bits_expOut_T = bits(c2_result_bits_rawIn.sExp, 7, 0) node _c2_result_bits_expOut_T_1 = sub(_c2_result_bits_expOut_T, UInt<8>(0h81)) node _c2_result_bits_expOut_T_2 = tail(_c2_result_bits_expOut_T_1, 1) node _c2_result_bits_expOut_T_3 = mux(c2_result_bits_isSubnormal, UInt<1>(0h0), _c2_result_bits_expOut_T_2) node _c2_result_bits_expOut_T_4 = or(c2_result_bits_rawIn.isNaN, c2_result_bits_rawIn.isInf) node _c2_result_bits_expOut_T_5 = mux(_c2_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c2_result_bits_expOut = or(_c2_result_bits_expOut_T_3, _c2_result_bits_expOut_T_5) node _c2_result_bits_fractOut_T = bits(c2_result_bits_rawIn.sig, 22, 0) node _c2_result_bits_fractOut_T_1 = mux(c2_result_bits_rawIn.isInf, UInt<1>(0h0), _c2_result_bits_fractOut_T) node c2_result_bits_fractOut = mux(c2_result_bits_isSubnormal, c2_result_bits_denormFract, _c2_result_bits_fractOut_T_1) node c2_result_bits_hi = cat(c2_result_bits_rawIn.sign, c2_result_bits_expOut) node _c2_result_bits_T = cat(c2_result_bits_hi, c2_result_bits_fractOut) connect c2_result.bits, _c2_result_bits_T connect c2, c2_result else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_4 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_5 : UInt<32> connect _mac_unit_io_in_b_WIRE_5, c2.bits node _mac_unit_io_in_b_T_2 = bits(_mac_unit_io_in_b_WIRE_5, 31, 0) connect _mac_unit_io_in_b_WIRE_4.bits, _mac_unit_io_in_b_T_2 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_4.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_6 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_7 : UInt<32> connect _mac_unit_io_in_b_WIRE_7, c1.bits node _mac_unit_io_in_b_T_3 = bits(_mac_unit_io_in_b_WIRE_7, 31, 0) connect _mac_unit_io_in_b_WIRE_6.bits, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_6.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c.bits invalidate io.out_b.bits wire _mac_unit_io_in_b_WIRE_8 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_9 : UInt<32> connect _mac_unit_io_in_b_WIRE_9, io.in_b.bits node _mac_unit_io_in_b_T_4 = bits(_mac_unit_io_in_b_WIRE_9, 31, 0) connect _mac_unit_io_in_b_WIRE_8.bits, _mac_unit_io_in_b_T_4 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_8.bits connect mac_unit.io.in_c.bits, c2.bits node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b.bits invalidate mac_unit.io.in_c.bits

module PE_20( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [31:0] io_in_a_bits, // @[PE.scala:35:14] input [31:0] io_in_b_bits, // @[PE.scala:35:14] input [31:0] io_in_d_bits, // @[PE.scala:35:14] output [31:0] io_out_a_bits, // @[PE.scala:35:14] output [31:0] io_out_b_bits, // @[PE.scala:35:14] output [31:0] io_out_c_bits, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [3:0] io_in_id, // @[PE.scala:35:14] output [3:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30] wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30] wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7] wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15] wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7] wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37] wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37] wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7] wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7] reg [31:0] c1_bits; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38] reg [31:0] c2_bits; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] | _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29] wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34] wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34] wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] | _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T = |io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15] wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}] wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26] wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN | io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 | _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] | _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN | io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 | _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37] assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37] wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] | _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26] wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN | c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 | _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] | _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29] wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] | _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T_4 = |io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15] wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<14>(0h2000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<13>(0h1000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<18>(0h2f000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<13>(0h1000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<27>(0h4000000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_155, _T_160) node _T_192 = or(_T_191, _T_165) node _T_193 = or(_T_192, _T_170) node _T_194 = or(_T_193, _T_175) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_185) node _T_197 = or(_T_196, _T_190) node _T_198 = and(_T_150, _T_197) node _T_199 = or(UInt<1>(0h0), _T_198) node _T_200 = and(_T_149, _T_199) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_200, UInt<1>(0h1), "") : assert_2 node _T_204 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_8) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<1>(0h1)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_9) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<2>(0h2)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_10) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<2>(0h3)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_11) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_231 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_204 connect _WIRE[1], _T_210 connect _WIRE[2], _T_216 connect _WIRE[3], _T_222 connect _WIRE[4], _T_228 connect _WIRE[5], _T_229 connect _WIRE[6], _T_230 connect _WIRE[7], _T_231 connect _WIRE[8], _T_232 node _T_233 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_234 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_235 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_238 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[5], _T_233, UInt<1>(0h0)) node _T_240 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_242 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_243 = or(_T_234, _T_235) node _T_244 = or(_T_243, _T_236) node _T_245 = or(_T_244, _T_237) node _T_246 = or(_T_245, _T_238) node _T_247 = or(_T_246, _T_239) node _T_248 = or(_T_247, _T_240) node _T_249 = or(_T_248, _T_241) node _T_250 = or(_T_249, _T_242) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_250 node _T_251 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_252 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_253 = and(_T_251, _T_252) node _T_254 = or(UInt<1>(0h0), _T_253) node _T_255 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<14>(0h2000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<17>(0h10000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_271 = cvt(_T_270) node _T_272 = and(_T_271, asSInt(UInt<18>(0h2f000))) node _T_273 = asSInt(_T_272) node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) node _T_275 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_276 = cvt(_T_275) node _T_277 = and(_T_276, asSInt(UInt<17>(0h10000))) node _T_278 = asSInt(_T_277) node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) node _T_280 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<13>(0h1000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<27>(0h4000000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<13>(0h1000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_259, _T_264) node _T_296 = or(_T_295, _T_269) node _T_297 = or(_T_296, _T_274) node _T_298 = or(_T_297, _T_279) node _T_299 = or(_T_298, _T_284) node _T_300 = or(_T_299, _T_289) node _T_301 = or(_T_300, _T_294) node _T_302 = and(_T_254, _T_301) node _T_303 = or(UInt<1>(0h0), _T_302) node _T_304 = and(_WIRE_1, _T_303) node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_T_304, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_304, UInt<1>(0h1), "") : assert_3 node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(source_ok, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_311 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_311, UInt<1>(0h1), "") : assert_5 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_318 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_318, UInt<1>(0h1), "") : assert_7 node _T_322 = not(io.in.a.bits.mask) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(_T_323, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_323, UInt<1>(0h1), "") : assert_8 node _T_327 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_327, UInt<1>(0h1), "") : assert_9 node _T_331 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_331 : node _T_332 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_333 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_12) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<1>(0h1)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_13) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_348 = shr(io.in.a.bits.source, 2) node _T_349 = eq(_T_348, UInt<2>(0h2)) node _T_350 = leq(UInt<1>(0h0), uncommonBits_14) node _T_351 = and(_T_349, _T_350) node _T_352 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_353 = and(_T_351, _T_352) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_354 = shr(io.in.a.bits.source, 2) node _T_355 = eq(_T_354, UInt<2>(0h3)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_15) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_362 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_363 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_364 = or(_T_335, _T_341) node _T_365 = or(_T_364, _T_347) node _T_366 = or(_T_365, _T_353) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = and(_T_334, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<27>(0h4000000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<13>(0h1000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = or(_T_379, _T_384) node _T_416 = or(_T_415, _T_389) node _T_417 = or(_T_416, _T_394) node _T_418 = or(_T_417, _T_399) node _T_419 = or(_T_418, _T_404) node _T_420 = or(_T_419, _T_409) node _T_421 = or(_T_420, _T_414) node _T_422 = and(_T_374, _T_421) node _T_423 = or(UInt<1>(0h0), _T_422) node _T_424 = and(_T_373, _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_424, UInt<1>(0h1), "") : assert_10 node _T_428 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<1>(0h0)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_16) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_435 = shr(io.in.a.bits.source, 2) node _T_436 = eq(_T_435, UInt<1>(0h1)) node _T_437 = leq(UInt<1>(0h0), uncommonBits_17) node _T_438 = and(_T_436, _T_437) node _T_439 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_440 = and(_T_438, _T_439) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_441 = shr(io.in.a.bits.source, 2) node _T_442 = eq(_T_441, UInt<2>(0h2)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_18) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_446 = and(_T_444, _T_445) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_447 = shr(io.in.a.bits.source, 2) node _T_448 = eq(_T_447, UInt<2>(0h3)) node _T_449 = leq(UInt<1>(0h0), uncommonBits_19) node _T_450 = and(_T_448, _T_449) node _T_451 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_452 = and(_T_450, _T_451) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_456 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_428 connect _WIRE_2[1], _T_434 connect _WIRE_2[2], _T_440 connect _WIRE_2[3], _T_446 connect _WIRE_2[4], _T_452 connect _WIRE_2[5], _T_453 connect _WIRE_2[6], _T_454 connect _WIRE_2[7], _T_455 connect _WIRE_2[8], _T_456 node _T_457 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_458 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE_2[5], _T_457, UInt<1>(0h0)) node _T_464 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = or(_T_458, _T_459) node _T_468 = or(_T_467, _T_460) node _T_469 = or(_T_468, _T_461) node _T_470 = or(_T_469, _T_462) node _T_471 = or(_T_470, _T_463) node _T_472 = or(_T_471, _T_464) node _T_473 = or(_T_472, _T_465) node _T_474 = or(_T_473, _T_466) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_474 node _T_475 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_476 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_477 = and(_T_475, _T_476) node _T_478 = or(UInt<1>(0h0), _T_477) node _T_479 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<14>(0h2000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<13>(0h1000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<17>(0h10000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<18>(0h2f000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_500 = cvt(_T_499) node _T_501 = and(_T_500, asSInt(UInt<17>(0h10000))) node _T_502 = asSInt(_T_501) node _T_503 = eq(_T_502, asSInt(UInt<1>(0h0))) node _T_504 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<13>(0h1000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<27>(0h4000000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = or(_T_483, _T_488) node _T_520 = or(_T_519, _T_493) node _T_521 = or(_T_520, _T_498) node _T_522 = or(_T_521, _T_503) node _T_523 = or(_T_522, _T_508) node _T_524 = or(_T_523, _T_513) node _T_525 = or(_T_524, _T_518) node _T_526 = and(_T_478, _T_525) node _T_527 = or(UInt<1>(0h0), _T_526) node _T_528 = and(_WIRE_3, _T_527) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_528, UInt<1>(0h1), "") : assert_11 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(source_ok, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_535 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_535, UInt<1>(0h1), "") : assert_13 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(is_aligned, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_542 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_542, UInt<1>(0h1), "") : assert_15 node _T_546 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_546, UInt<1>(0h1), "") : assert_16 node _T_550 = not(io.in.a.bits.mask) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_551, UInt<1>(0h1), "") : assert_17 node _T_555 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_555, UInt<1>(0h1), "") : assert_18 node _T_559 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_559 : node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<1>(0h0)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_20) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_570 = shr(io.in.a.bits.source, 2) node _T_571 = eq(_T_570, UInt<1>(0h1)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_21) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<2>(0h2)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_22) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<2>(0h3)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_23) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_591 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_592 = or(_T_563, _T_569) node _T_593 = or(_T_592, _T_575) node _T_594 = or(_T_593, _T_581) node _T_595 = or(_T_594, _T_587) node _T_596 = or(_T_595, _T_588) node _T_597 = or(_T_596, _T_589) node _T_598 = or(_T_597, _T_590) node _T_599 = or(_T_598, _T_591) node _T_600 = and(_T_562, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_601, UInt<1>(0h1), "") : assert_19 node _T_605 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_606 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_607 = and(_T_605, _T_606) node _T_608 = or(UInt<1>(0h0), _T_607) node _T_609 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<13>(0h1000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = and(_T_608, _T_613) node _T_615 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_616 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_617 = and(_T_615, _T_616) node _T_618 = or(UInt<1>(0h0), _T_617) node _T_619 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<14>(0h2000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<18>(0h2f000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<17>(0h10000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<13>(0h1000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_645 = cvt(_T_644) node _T_646 = and(_T_645, asSInt(UInt<27>(0h4000000))) node _T_647 = asSInt(_T_646) node _T_648 = eq(_T_647, asSInt(UInt<1>(0h0))) node _T_649 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_650 = cvt(_T_649) node _T_651 = and(_T_650, asSInt(UInt<13>(0h1000))) node _T_652 = asSInt(_T_651) node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0))) node _T_654 = or(_T_623, _T_628) node _T_655 = or(_T_654, _T_633) node _T_656 = or(_T_655, _T_638) node _T_657 = or(_T_656, _T_643) node _T_658 = or(_T_657, _T_648) node _T_659 = or(_T_658, _T_653) node _T_660 = and(_T_618, _T_659) node _T_661 = or(UInt<1>(0h0), _T_614) node _T_662 = or(_T_661, _T_660) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_662, UInt<1>(0h1), "") : assert_20 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(source_ok, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_672, UInt<1>(0h1), "") : assert_23 node _T_676 = eq(io.in.a.bits.mask, mask) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_676, UInt<1>(0h1), "") : assert_24 node _T_680 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_680, UInt<1>(0h1), "") : assert_25 node _T_684 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_24) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_25) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_26) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_27) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_728 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_729 = and(_T_727, _T_728) node _T_730 = or(UInt<1>(0h0), _T_729) node _T_731 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = and(_T_730, _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<18>(0h2f000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<13>(0h1000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<27>(0h4000000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = or(_T_745, _T_750) node _T_772 = or(_T_771, _T_755) node _T_773 = or(_T_772, _T_760) node _T_774 = or(_T_773, _T_765) node _T_775 = or(_T_774, _T_770) node _T_776 = and(_T_740, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_736) node _T_785 = or(_T_784, _T_776) node _T_786 = or(_T_785, _T_783) node _T_787 = and(_T_726, _T_786) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_787, UInt<1>(0h1), "") : assert_26 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(source_ok, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(is_aligned, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_797 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(_T_797, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_797, UInt<1>(0h1), "") : assert_29 node _T_801 = eq(io.in.a.bits.mask, mask) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_801, UInt<1>(0h1), "") : assert_30 node _T_805 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_805 : node _T_806 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_807 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_808 = and(_T_806, _T_807) node _T_809 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_810 = shr(io.in.a.bits.source, 2) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = leq(UInt<1>(0h0), uncommonBits_28) node _T_813 = and(_T_811, _T_812) node _T_814 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_815 = and(_T_813, _T_814) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_816 = shr(io.in.a.bits.source, 2) node _T_817 = eq(_T_816, UInt<1>(0h1)) node _T_818 = leq(UInt<1>(0h0), uncommonBits_29) node _T_819 = and(_T_817, _T_818) node _T_820 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_821 = and(_T_819, _T_820) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_822 = shr(io.in.a.bits.source, 2) node _T_823 = eq(_T_822, UInt<2>(0h2)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_30) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_828 = shr(io.in.a.bits.source, 2) node _T_829 = eq(_T_828, UInt<2>(0h3)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_31) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_833 = and(_T_831, _T_832) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_837 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_838 = or(_T_809, _T_815) node _T_839 = or(_T_838, _T_821) node _T_840 = or(_T_839, _T_827) node _T_841 = or(_T_840, _T_833) node _T_842 = or(_T_841, _T_834) node _T_843 = or(_T_842, _T_835) node _T_844 = or(_T_843, _T_836) node _T_845 = or(_T_844, _T_837) node _T_846 = and(_T_808, _T_845) node _T_847 = or(UInt<1>(0h0), _T_846) node _T_848 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_849 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_850 = and(_T_848, _T_849) node _T_851 = or(UInt<1>(0h0), _T_850) node _T_852 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_853 = cvt(_T_852) node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000))) node _T_855 = asSInt(_T_854) node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0))) node _T_857 = and(_T_851, _T_856) node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_859 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_860 = and(_T_858, _T_859) node _T_861 = or(UInt<1>(0h0), _T_860) node _T_862 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<14>(0h2000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<18>(0h2f000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_873 = cvt(_T_872) node _T_874 = and(_T_873, asSInt(UInt<17>(0h10000))) node _T_875 = asSInt(_T_874) node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0))) node _T_877 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<13>(0h1000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<27>(0h4000000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<13>(0h1000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = or(_T_866, _T_871) node _T_893 = or(_T_892, _T_876) node _T_894 = or(_T_893, _T_881) node _T_895 = or(_T_894, _T_886) node _T_896 = or(_T_895, _T_891) node _T_897 = and(_T_861, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<17>(0h10000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = and(_T_898, _T_903) node _T_905 = or(UInt<1>(0h0), _T_857) node _T_906 = or(_T_905, _T_897) node _T_907 = or(_T_906, _T_904) node _T_908 = and(_T_847, _T_907) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_908, UInt<1>(0h1), "") : assert_31 node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(source_ok, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(is_aligned, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_918 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_918, UInt<1>(0h1), "") : assert_34 node _T_922 = not(mask) node _T_923 = and(io.in.a.bits.mask, _T_922) node _T_924 = eq(_T_923, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_924, UInt<1>(0h1), "") : assert_35 node _T_928 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_928 : node _T_929 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_930 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_931 = and(_T_929, _T_930) node _T_932 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_933 = shr(io.in.a.bits.source, 2) node _T_934 = eq(_T_933, UInt<1>(0h0)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_32) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_938 = and(_T_936, _T_937) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_939 = shr(io.in.a.bits.source, 2) node _T_940 = eq(_T_939, UInt<1>(0h1)) node _T_941 = leq(UInt<1>(0h0), uncommonBits_33) node _T_942 = and(_T_940, _T_941) node _T_943 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_944 = and(_T_942, _T_943) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_945 = shr(io.in.a.bits.source, 2) node _T_946 = eq(_T_945, UInt<2>(0h2)) node _T_947 = leq(UInt<1>(0h0), uncommonBits_34) node _T_948 = and(_T_946, _T_947) node _T_949 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<2>(0h3)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_35) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_961 = or(_T_932, _T_938) node _T_962 = or(_T_961, _T_944) node _T_963 = or(_T_962, _T_950) node _T_964 = or(_T_963, _T_956) node _T_965 = or(_T_964, _T_957) node _T_966 = or(_T_965, _T_958) node _T_967 = or(_T_966, _T_959) node _T_968 = or(_T_967, _T_960) node _T_969 = and(_T_931, _T_968) node _T_970 = or(UInt<1>(0h0), _T_969) node _T_971 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_972 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_973 = and(_T_971, _T_972) node _T_974 = or(UInt<1>(0h0), _T_973) node _T_975 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_976 = cvt(_T_975) node _T_977 = and(_T_976, asSInt(UInt<14>(0h2000))) node _T_978 = asSInt(_T_977) node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0))) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_986 = cvt(_T_985) node _T_987 = and(_T_986, asSInt(UInt<18>(0h2f000))) node _T_988 = asSInt(_T_987) node _T_989 = eq(_T_988, asSInt(UInt<1>(0h0))) node _T_990 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_991 = cvt(_T_990) node _T_992 = and(_T_991, asSInt(UInt<17>(0h10000))) node _T_993 = asSInt(_T_992) node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0))) node _T_995 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_996 = cvt(_T_995) node _T_997 = and(_T_996, asSInt(UInt<13>(0h1000))) node _T_998 = asSInt(_T_997) node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0))) node _T_1000 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<27>(0h4000000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<13>(0h1000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_979, _T_984) node _T_1011 = or(_T_1010, _T_989) node _T_1012 = or(_T_1011, _T_994) node _T_1013 = or(_T_1012, _T_999) node _T_1014 = or(_T_1013, _T_1004) node _T_1015 = or(_T_1014, _T_1009) node _T_1016 = and(_T_974, _T_1015) node _T_1017 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1018 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<17>(0h10000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = and(_T_1017, _T_1022) node _T_1024 = or(UInt<1>(0h0), _T_1016) node _T_1025 = or(_T_1024, _T_1023) node _T_1026 = and(_T_970, _T_1025) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_36 node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(is_aligned, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1036 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_39 node _T_1040 = eq(io.in.a.bits.mask, mask) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_40 node _T_1044 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1044 : node _T_1045 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1046 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1049 = shr(io.in.a.bits.source, 2) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1055 = shr(io.in.a.bits.source, 2) node _T_1056 = eq(_T_1055, UInt<1>(0h1)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1061 = shr(io.in.a.bits.source, 2) node _T_1062 = eq(_T_1061, UInt<2>(0h2)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1066 = and(_T_1064, _T_1065) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1067 = shr(io.in.a.bits.source, 2) node _T_1068 = eq(_T_1067, UInt<2>(0h3)) node _T_1069 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1077 = or(_T_1048, _T_1054) node _T_1078 = or(_T_1077, _T_1060) node _T_1079 = or(_T_1078, _T_1066) node _T_1080 = or(_T_1079, _T_1072) node _T_1081 = or(_T_1080, _T_1073) node _T_1082 = or(_T_1081, _T_1074) node _T_1083 = or(_T_1082, _T_1075) node _T_1084 = or(_T_1083, _T_1076) node _T_1085 = and(_T_1047, _T_1084) node _T_1086 = or(UInt<1>(0h0), _T_1085) node _T_1087 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1088 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = or(UInt<1>(0h0), _T_1089) node _T_1091 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1092 = cvt(_T_1091) node _T_1093 = and(_T_1092, asSInt(UInt<14>(0h2000))) node _T_1094 = asSInt(_T_1093) node _T_1095 = eq(_T_1094, asSInt(UInt<1>(0h0))) node _T_1096 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1097 = cvt(_T_1096) node _T_1098 = and(_T_1097, asSInt(UInt<13>(0h1000))) node _T_1099 = asSInt(_T_1098) node _T_1100 = eq(_T_1099, asSInt(UInt<1>(0h0))) node _T_1101 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<18>(0h2f000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<17>(0h10000))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1112 = cvt(_T_1111) node _T_1113 = and(_T_1112, asSInt(UInt<13>(0h1000))) node _T_1114 = asSInt(_T_1113) node _T_1115 = eq(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1117 = cvt(_T_1116) node _T_1118 = and(_T_1117, asSInt(UInt<27>(0h4000000))) node _T_1119 = asSInt(_T_1118) node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0))) node _T_1121 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<13>(0h1000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = or(_T_1095, _T_1100) node _T_1127 = or(_T_1126, _T_1105) node _T_1128 = or(_T_1127, _T_1110) node _T_1129 = or(_T_1128, _T_1115) node _T_1130 = or(_T_1129, _T_1120) node _T_1131 = or(_T_1130, _T_1125) node _T_1132 = and(_T_1090, _T_1131) node _T_1133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = and(_T_1133, _T_1138) node _T_1140 = or(UInt<1>(0h0), _T_1132) node _T_1141 = or(_T_1140, _T_1139) node _T_1142 = and(_T_1086, _T_1141) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_41 node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(source_ok, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(is_aligned, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1152 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_44 node _T_1156 = eq(io.in.a.bits.mask, mask) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_45 node _T_1160 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1160 : node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1162 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<1>(0h1)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1177 = shr(io.in.a.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h2)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1183 = shr(io.in.a.bits.source, 2) node _T_1184 = eq(_T_1183, UInt<2>(0h3)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1193 = or(_T_1164, _T_1170) node _T_1194 = or(_T_1193, _T_1176) node _T_1195 = or(_T_1194, _T_1182) node _T_1196 = or(_T_1195, _T_1188) node _T_1197 = or(_T_1196, _T_1189) node _T_1198 = or(_T_1197, _T_1190) node _T_1199 = or(_T_1198, _T_1191) node _T_1200 = or(_T_1199, _T_1192) node _T_1201 = and(_T_1163, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1201) node _T_1203 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1204 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = or(UInt<1>(0h0), _T_1205) node _T_1207 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1208 = cvt(_T_1207) node _T_1209 = and(_T_1208, asSInt(UInt<13>(0h1000))) node _T_1210 = asSInt(_T_1209) node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = and(_T_1206, _T_1211) node _T_1213 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1214 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<14>(0h2000))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1220 = cvt(_T_1219) node _T_1221 = and(_T_1220, asSInt(UInt<17>(0h10000))) node _T_1222 = asSInt(_T_1221) node _T_1223 = eq(_T_1222, asSInt(UInt<1>(0h0))) node _T_1224 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1225 = cvt(_T_1224) node _T_1226 = and(_T_1225, asSInt(UInt<18>(0h2f000))) node _T_1227 = asSInt(_T_1226) node _T_1228 = eq(_T_1227, asSInt(UInt<1>(0h0))) node _T_1229 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1230 = cvt(_T_1229) node _T_1231 = and(_T_1230, asSInt(UInt<17>(0h10000))) node _T_1232 = asSInt(_T_1231) node _T_1233 = eq(_T_1232, asSInt(UInt<1>(0h0))) node _T_1234 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1235 = cvt(_T_1234) node _T_1236 = and(_T_1235, asSInt(UInt<13>(0h1000))) node _T_1237 = asSInt(_T_1236) node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0))) node _T_1239 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1240 = cvt(_T_1239) node _T_1241 = and(_T_1240, asSInt(UInt<27>(0h4000000))) node _T_1242 = asSInt(_T_1241) node _T_1243 = eq(_T_1242, asSInt(UInt<1>(0h0))) node _T_1244 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1245 = cvt(_T_1244) node _T_1246 = and(_T_1245, asSInt(UInt<13>(0h1000))) node _T_1247 = asSInt(_T_1246) node _T_1248 = eq(_T_1247, asSInt(UInt<1>(0h0))) node _T_1249 = or(_T_1218, _T_1223) node _T_1250 = or(_T_1249, _T_1228) node _T_1251 = or(_T_1250, _T_1233) node _T_1252 = or(_T_1251, _T_1238) node _T_1253 = or(_T_1252, _T_1243) node _T_1254 = or(_T_1253, _T_1248) node _T_1255 = and(_T_1213, _T_1254) node _T_1256 = or(UInt<1>(0h0), _T_1212) node _T_1257 = or(_T_1256, _T_1255) node _T_1258 = and(_T_1202, _T_1257) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_46 node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(source_ok, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(is_aligned, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1268 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_49 node _T_1272 = eq(io.in.a.bits.mask, mask) node _T_1273 = asUInt(reset) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) when _T_1274 : node _T_1275 = eq(_T_1272, UInt<1>(0h0)) when _T_1275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1272, UInt<1>(0h1), "") : assert_50 node _T_1276 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1280 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1284 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1284 : node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(source_ok_1, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1288 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_54 node _T_1292 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_55 node _T_1296 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_56 node _T_1300 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_57 node _T_1304 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1304 : node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(source_ok_1, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(sink_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1311 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_60 node _T_1315 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_61 node _T_1319 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_62 node _T_1323 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_63 node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1328 = or(UInt<1>(0h1), _T_1327) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_64 node _T_1332 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1332 : node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(source_ok_1, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(sink_ok, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1339 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_67 node _T_1343 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_68 node _T_1347 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_69 node _T_1351 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1352 = or(_T_1351, io.in.d.bits.corrupt) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_70 node _T_1356 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1357 = or(UInt<1>(0h1), _T_1356) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_71 node _T_1361 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1361 : node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(source_ok_1, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1365 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_73 node _T_1369 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_74 node _T_1373 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1374 = or(UInt<1>(0h1), _T_1373) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_75 node _T_1378 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1378 : node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(source_ok_1, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1382 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1383 = asUInt(reset) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) when _T_1384 : node _T_1385 = eq(_T_1382, UInt<1>(0h0)) when _T_1385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1382, UInt<1>(0h1), "") : assert_77 node _T_1386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1387 = or(_T_1386, io.in.d.bits.corrupt) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_78 node _T_1391 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1392 = or(UInt<1>(0h1), _T_1391) node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(_T_1392, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1392, UInt<1>(0h1), "") : assert_79 node _T_1396 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1396 : node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(source_ok_1, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1400 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_81 node _T_1404 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_82 node _T_1408 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1409 = or(UInt<1>(0h1), _T_1408) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1413 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(_T_1413, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1413, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1417 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(_T_1417, UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1417, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1421 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1425 = eq(a_first, UInt<1>(0h0)) node _T_1426 = and(io.in.a.valid, _T_1425) when _T_1426 : node _T_1427 = eq(io.in.a.bits.opcode, opcode) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_87 node _T_1431 = eq(io.in.a.bits.param, param) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_88 node _T_1435 = eq(io.in.a.bits.size, size) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_89 node _T_1439 = eq(io.in.a.bits.source, source) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_90 node _T_1443 = eq(io.in.a.bits.address, address) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_91 node _T_1447 = and(io.in.a.ready, io.in.a.valid) node _T_1448 = and(_T_1447, a_first) when _T_1448 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1449 = eq(d_first, UInt<1>(0h0)) node _T_1450 = and(io.in.d.valid, _T_1449) when _T_1450 : node _T_1451 = eq(io.in.d.bits.opcode, opcode_1) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_92 node _T_1455 = eq(io.in.d.bits.param, param_1) node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(_T_1455, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1455, UInt<1>(0h1), "") : assert_93 node _T_1459 = eq(io.in.d.bits.size, size_1) node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(_T_1459, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1459, UInt<1>(0h1), "") : assert_94 node _T_1463 = eq(io.in.d.bits.source, source_1) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_95 node _T_1467 = eq(io.in.d.bits.sink, sink) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_96 node _T_1471 = eq(io.in.d.bits.denied, denied) node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(_T_1471, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1471, UInt<1>(0h1), "") : assert_97 node _T_1475 = and(io.in.d.ready, io.in.d.valid) node _T_1476 = and(_T_1475, d_first) when _T_1476 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1477 = and(io.in.a.valid, a_first_1) node _T_1478 = and(_T_1477, UInt<1>(0h1)) when _T_1478 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1479 = and(io.in.a.ready, io.in.a.valid) node _T_1480 = and(_T_1479, a_first_1) node _T_1481 = and(_T_1480, UInt<1>(0h1)) when _T_1481 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1482 = dshr(inflight, io.in.a.bits.source) node _T_1483 = bits(_T_1482, 0, 0) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1488 = and(io.in.d.valid, d_first_1) node _T_1489 = and(_T_1488, UInt<1>(0h1)) node _T_1490 = eq(d_release_ack, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1492 = and(io.in.d.ready, io.in.d.valid) node _T_1493 = and(_T_1492, d_first_1) node _T_1494 = and(_T_1493, UInt<1>(0h1)) node _T_1495 = eq(d_release_ack, UInt<1>(0h0)) node _T_1496 = and(_T_1494, _T_1495) when _T_1496 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1497 = and(io.in.d.valid, d_first_1) node _T_1498 = and(_T_1497, UInt<1>(0h1)) node _T_1499 = eq(d_release_ack, UInt<1>(0h0)) node _T_1500 = and(_T_1498, _T_1499) when _T_1500 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1501 = dshr(inflight, io.in.d.bits.source) node _T_1502 = bits(_T_1501, 0, 0) node _T_1503 = or(_T_1502, same_cycle_resp) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1507 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1508 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1509 = or(_T_1507, _T_1508) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_100 node _T_1513 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(_T_1513, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1513, UInt<1>(0h1), "") : assert_101 else : node _T_1517 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1518 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_102 node _T_1523 = eq(io.in.d.bits.size, a_size_lookup) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_103 node _T_1527 = and(io.in.d.valid, d_first_1) node _T_1528 = and(_T_1527, a_first_1) node _T_1529 = and(_T_1528, io.in.a.valid) node _T_1530 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1531 = and(_T_1529, _T_1530) node _T_1532 = eq(d_release_ack, UInt<1>(0h0)) node _T_1533 = and(_T_1531, _T_1532) when _T_1533 : node _T_1534 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1535 = or(_T_1534, io.in.a.ready) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_104 node _T_1539 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1540 = orr(a_set_wo_ready) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) node _T_1542 = or(_T_1539, _T_1541) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1546 = orr(inflight) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) node _T_1548 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1549 = or(_T_1547, _T_1548) node _T_1550 = lt(watchdog, plusarg_reader.out) node _T_1551 = or(_T_1549, _T_1550) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1555 = and(io.in.a.ready, io.in.a.valid) node _T_1556 = and(io.in.d.ready, io.in.d.valid) node _T_1557 = or(_T_1555, _T_1556) when _T_1557 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1558 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1559 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1560 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = and(_T_1558, _T_1561) when _T_1562 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1563 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1564 = and(_T_1563, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1565 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1566 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = and(_T_1564, _T_1567) when _T_1568 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1569 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1570 = bits(_T_1569, 0, 0) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1575 = and(io.in.d.valid, d_first_2) node _T_1576 = and(_T_1575, UInt<1>(0h1)) node _T_1577 = and(_T_1576, d_release_ack_1) when _T_1577 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1578 = and(io.in.d.ready, io.in.d.valid) node _T_1579 = and(_T_1578, d_first_2) node _T_1580 = and(_T_1579, UInt<1>(0h1)) node _T_1581 = and(_T_1580, d_release_ack_1) when _T_1581 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1582 = and(io.in.d.valid, d_first_2) node _T_1583 = and(_T_1582, UInt<1>(0h1)) node _T_1584 = and(_T_1583, d_release_ack_1) when _T_1584 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1585 = dshr(inflight_1, io.in.d.bits.source) node _T_1586 = bits(_T_1585, 0, 0) node _T_1587 = or(_T_1586, same_cycle_resp_1) node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(_T_1587, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1587, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1591 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_109 else : node _T_1595 = eq(io.in.d.bits.size, c_size_lookup) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_110 node _T_1599 = and(io.in.d.valid, d_first_2) node _T_1600 = and(_T_1599, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1601 = and(_T_1600, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1602 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1603 = and(_T_1601, _T_1602) node _T_1604 = and(_T_1603, d_release_ack_1) node _T_1605 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1606 = and(_T_1604, _T_1605) when _T_1606 : node _T_1607 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1608 = or(_T_1607, _WIRE_27.ready) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_111 node _T_1612 = orr(c_set_wo_ready) when _T_1612 : node _T_1613 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(_T_1613, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1613, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1617 = orr(inflight_1) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) node _T_1619 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1620 = or(_T_1618, _T_1619) node _T_1621 = lt(watchdog_1, plusarg_reader_1.out) node _T_1622 = or(_T_1620, _T_1621) node _T_1623 = asUInt(reset) node _T_1624 = eq(_T_1623, UInt<1>(0h0)) when _T_1624 : node _T_1625 = eq(_T_1622, UInt<1>(0h0)) when _T_1625 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1622, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1626 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1627 = and(io.in.d.ready, io.in.d.valid) node _T_1628 = or(_T_1626, _T_1627) when _T_1628 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1555 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1555; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1555; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1628 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1628; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1628; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1628; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1481 = _T_1555 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1481 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1481 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1481 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1481 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1481 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1527 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1527 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1496 = _T_1628 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1496 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1496 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1496 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1599 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1599 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1581 = _T_1628 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1581 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1581 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1581 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_24 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_24(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_205 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_205( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_66 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_66( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_8 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<25> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_46_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_39_2, rrd_cs_decoder_decoded_andMatrixOutputs_27_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_52_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_25_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_1_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_56_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_63_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_19) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_23_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_22_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_37_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_51_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_6_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_54_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_27) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_61_2, rrd_cs_decoder_decoded_andMatrixOutputs_48_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_7_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_30) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_53_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_32) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_35 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_34) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_14, _rrd_cs_decoder_decoded_orMatrixOutputs_T_12) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_18) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_24, _rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_29, _rrd_cs_decoder_decoded_orMatrixOutputs_T_28) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_31) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_35) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_14, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 24, 24) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 24, 21) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 20, 20) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 17, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid

module RegisterReadDecode_8( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [15:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [15:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [15:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [15:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [4:0] rrd_cs_decoder_4; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [24:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [24:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = rrd_cs_decoder_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62; // @[pla.scala:90:45, :98:70] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = rrd_cs_decoder_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_55_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_46_2, rrd_cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_39_2, rrd_cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_52_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_25_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_12_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_56_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_5_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_44_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_23_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [9:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_6_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_35_2, rrd_cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_64_2, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_12, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_61_2, rrd_cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_31 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_33 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_35 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_34; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_5, _rrd_cs_decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_10, _rrd_cs_decoder_decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_14, _rrd_cs_decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_24, _rrd_cs_decoder_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_29, _rrd_cs_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_33, _rrd_cs_decoder_decoded_orMatrixOutputs_T_31}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, 3'h0}; // @[pla.scala:102:36] wire [12:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:102:36] wire [24:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_14, rrd_cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_21; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = rrd_cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [3:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[24:21]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[20]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] assign rrd_cs_decoder_4 = rrd_cs_decoder_decoded[17:13]; // @[pla.scala:81:23] assign rrd_cs_op_fcn = rrd_cs_decoder_4; // @[Decode.scala:50:77] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T | _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T | _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 | _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 7'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_182 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_182( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_178 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_195 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_178( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_195 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_22 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_214 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_215 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_22( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_214 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_215 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_123 = shr(io.in.a.bits.source, 3) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_130 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_240 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_314 = shr(io.in.a.bits.source, 3) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_321 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_428 = shr(io.in.a.bits.source, 3) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_435 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_538 = shr(io.in.a.bits.source, 3) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_545 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_651 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_752 = shr(io.in.a.bits.source, 3) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_759 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<27>(0h4000000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<13>(0h1000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = or(_T_772, _T_777) node _T_804 = or(_T_803, _T_782) node _T_805 = or(_T_804, _T_787) node _T_806 = or(_T_805, _T_792) node _T_807 = or(_T_806, _T_797) node _T_808 = or(_T_807, _T_802) node _T_809 = and(_T_767, _T_808) node _T_810 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_811 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_812 = cvt(_T_811) node _T_813 = and(_T_812, asSInt(UInt<17>(0h10000))) node _T_814 = asSInt(_T_813) node _T_815 = eq(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = and(_T_810, _T_815) node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_818 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_819 = and(_T_817, _T_818) node _T_820 = or(UInt<1>(0h0), _T_819) node _T_821 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_822 = cvt(_T_821) node _T_823 = and(_T_822, asSInt(UInt<17>(0h10000))) node _T_824 = asSInt(_T_823) node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0))) node _T_826 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<29>(0h10000000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = or(_T_825, _T_830) node _T_832 = and(_T_820, _T_831) node _T_833 = or(UInt<1>(0h0), _T_809) node _T_834 = or(_T_833, _T_816) node _T_835 = or(_T_834, _T_832) node _T_836 = and(_T_763, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_836, UInt<1>(0h1), "") : assert_36 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(source_ok, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(is_aligned, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_846 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_846, UInt<1>(0h1), "") : assert_39 node _T_850 = eq(io.in.a.bits.mask, mask) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_850, UInt<1>(0h1), "") : assert_40 node _T_854 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_854 : node _T_855 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_856 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_858 = shr(io.in.a.bits.source, 3) node _T_859 = eq(_T_858, UInt<1>(0h0)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_9) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_863 = and(_T_861, _T_862) node _T_864 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_865 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_866 = or(_T_863, _T_864) node _T_867 = or(_T_866, _T_865) node _T_868 = and(_T_857, _T_867) node _T_869 = or(UInt<1>(0h0), _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<13>(0h1000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<17>(0h10000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = and(_T_916, _T_921) node _T_923 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_924 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_925 = and(_T_923, _T_924) node _T_926 = or(UInt<1>(0h0), _T_925) node _T_927 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<29>(0h10000000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = or(_T_931, _T_936) node _T_938 = and(_T_926, _T_937) node _T_939 = or(UInt<1>(0h0), _T_915) node _T_940 = or(_T_939, _T_922) node _T_941 = or(_T_940, _T_938) node _T_942 = and(_T_869, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_942, UInt<1>(0h1), "") : assert_41 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(is_aligned, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_952 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_952, UInt<1>(0h1), "") : assert_44 node _T_956 = eq(io.in.a.bits.mask, mask) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_956, UInt<1>(0h1), "") : assert_45 node _T_960 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_960 : node _T_961 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_962 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_964 = shr(io.in.a.bits.source, 3) node _T_965 = eq(_T_964, UInt<1>(0h0)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_10) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_971 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_972 = or(_T_969, _T_970) node _T_973 = or(_T_972, _T_971) node _T_974 = and(_T_963, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<14>(0h2000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_991, _T_996) node _T_1023 = or(_T_1022, _T_1001) node _T_1024 = or(_T_1023, _T_1006) node _T_1025 = or(_T_1024, _T_1011) node _T_1026 = or(_T_1025, _T_1016) node _T_1027 = or(_T_1026, _T_1021) node _T_1028 = and(_T_986, _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<17>(0h10000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<29>(0h10000000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _T_1044 = and(_T_1032, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_985) node _T_1046 = or(_T_1045, _T_1028) node _T_1047 = or(_T_1046, _T_1044) node _T_1048 = and(_T_975, _T_1047) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_46 node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(is_aligned, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1058 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_49 node _T_1062 = eq(io.in.a.bits.mask, mask) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_50 node _T_1066 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1070 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1074 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1074 : node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(source_ok_1, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1078 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_54 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_55 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_56 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_57 node _T_1094 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1094 : node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(source_ok_1, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(sink_ok, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1101 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_60 node _T_1105 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_61 node _T_1109 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_62 node _T_1113 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_63 node _T_1117 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1118 = or(UInt<1>(0h1), _T_1117) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_64 node _T_1122 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(source_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(sink_ok, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1129 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_67 node _T_1133 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_68 node _T_1137 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_69 node _T_1141 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.d.bits.corrupt) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_70 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h1), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_71 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_73 node _T_1159 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_74 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(UInt<1>(0h1), _T_1163) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_75 node _T_1168 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1168 : node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(source_ok_1, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1172 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_77 node _T_1176 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1177 = or(_T_1176, io.in.d.bits.corrupt) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_78 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h1), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_79 node _T_1186 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1186 : node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(source_ok_1, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1190 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_81 node _T_1194 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_82 node _T_1198 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1199 = or(UInt<1>(0h1), _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1203 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1207 = shr(io.in.b.bits.source, 3) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) node _T_1214 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1213, _T_1218) node _T_1220 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = and(_T_1219, _T_1227) node _T_1237 = and(_T_1236, _T_1235) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1241 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1241 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1242 = shr(io.in.b.bits.source, 3) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1249 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1247 connect _WIRE_4[1], _T_1248 connect _WIRE_4[2], _T_1249 node _T_1250 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1251 = mux(_WIRE_4[0], _T_1250, UInt<1>(0h0)) node _T_1252 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1253 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1254 = or(_T_1251, _T_1252) node _T_1255 = or(_T_1254, _T_1253) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1255 node _T_1256 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1257 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = or(UInt<1>(0h0), _T_1258) node _T_1260 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<14>(0h2000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<13>(0h1000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<18>(0h2f000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<17>(0h10000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<27>(0h4000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1301 = cvt(_T_1300) node _T_1302 = and(_T_1301, asSInt(UInt<13>(0h1000))) node _T_1303 = asSInt(_T_1302) node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0))) node _T_1305 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = or(_T_1264, _T_1269) node _T_1311 = or(_T_1310, _T_1274) node _T_1312 = or(_T_1311, _T_1279) node _T_1313 = or(_T_1312, _T_1284) node _T_1314 = or(_T_1313, _T_1289) node _T_1315 = or(_T_1314, _T_1294) node _T_1316 = or(_T_1315, _T_1299) node _T_1317 = or(_T_1316, _T_1304) node _T_1318 = or(_T_1317, _T_1309) node _T_1319 = and(_T_1259, _T_1318) node _T_1320 = or(UInt<1>(0h0), _T_1319) node _T_1321 = and(_WIRE_5, _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_86 node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(address_ok, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(legal_source, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1334 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_90 node _T_1338 = eq(io.in.b.bits.mask, mask_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_91 node _T_1342 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_92 node _T_1346 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1346 : node _T_1347 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1348 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1349 = and(_T_1347, _T_1348) node _T_1350 = or(UInt<1>(0h0), _T_1349) node _T_1351 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<14>(0h2000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<13>(0h1000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<18>(0h2f000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<13>(0h1000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<17>(0h10000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<27>(0h4000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<29>(0h10000000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = or(_T_1355, _T_1360) node _T_1402 = or(_T_1401, _T_1365) node _T_1403 = or(_T_1402, _T_1370) node _T_1404 = or(_T_1403, _T_1375) node _T_1405 = or(_T_1404, _T_1380) node _T_1406 = or(_T_1405, _T_1385) node _T_1407 = or(_T_1406, _T_1390) node _T_1408 = or(_T_1407, _T_1395) node _T_1409 = or(_T_1408, _T_1400) node _T_1410 = and(_T_1350, _T_1409) node _T_1411 = or(UInt<1>(0h0), _T_1410) node _T_1412 = and(UInt<1>(0h0), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_93 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(address_ok, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(legal_source, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1425 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_97 node _T_1429 = eq(io.in.b.bits.mask, mask_1) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_98 node _T_1433 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_99 node _T_1437 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1437 : node _T_1438 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1439 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1440 = and(_T_1438, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<14>(0h2000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<13>(0h1000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<18>(0h2f000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<13>(0h1000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<17>(0h10000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<27>(0h4000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<13>(0h1000))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1488 = cvt(_T_1487) node _T_1489 = and(_T_1488, asSInt(UInt<29>(0h10000000))) node _T_1490 = asSInt(_T_1489) node _T_1491 = eq(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = or(_T_1446, _T_1451) node _T_1493 = or(_T_1492, _T_1456) node _T_1494 = or(_T_1493, _T_1461) node _T_1495 = or(_T_1494, _T_1466) node _T_1496 = or(_T_1495, _T_1471) node _T_1497 = or(_T_1496, _T_1476) node _T_1498 = or(_T_1497, _T_1481) node _T_1499 = or(_T_1498, _T_1486) node _T_1500 = or(_T_1499, _T_1491) node _T_1501 = and(_T_1441, _T_1500) node _T_1502 = or(UInt<1>(0h0), _T_1501) node _T_1503 = and(UInt<1>(0h0), _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_100 node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(address_ok, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(legal_source, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1516 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_104 node _T_1520 = eq(io.in.b.bits.mask, mask_1) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_105 node _T_1524 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1524 : node _T_1525 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1526 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = or(UInt<1>(0h0), _T_1527) node _T_1529 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<14>(0h2000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<13>(0h1000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<18>(0h2f000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<27>(0h4000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<29>(0h10000000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = or(_T_1533, _T_1538) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1548) node _T_1582 = or(_T_1581, _T_1553) node _T_1583 = or(_T_1582, _T_1558) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1568) node _T_1586 = or(_T_1585, _T_1573) node _T_1587 = or(_T_1586, _T_1578) node _T_1588 = and(_T_1528, _T_1587) node _T_1589 = or(UInt<1>(0h0), _T_1588) node _T_1590 = and(UInt<1>(0h0), _T_1589) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_106 node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(address_ok, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(legal_source, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1603 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_110 node _T_1607 = not(mask_1) node _T_1608 = and(io.in.b.bits.mask, _T_1607) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_111 node _T_1613 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1613 : node _T_1614 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1615 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = or(UInt<1>(0h0), _T_1616) node _T_1618 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<14>(0h2000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<18>(0h2f000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<13>(0h1000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<17>(0h10000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<27>(0h4000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1659 = cvt(_T_1658) node _T_1660 = and(_T_1659, asSInt(UInt<13>(0h1000))) node _T_1661 = asSInt(_T_1660) node _T_1662 = eq(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1664 = cvt(_T_1663) node _T_1665 = and(_T_1664, asSInt(UInt<29>(0h10000000))) node _T_1666 = asSInt(_T_1665) node _T_1667 = eq(_T_1666, asSInt(UInt<1>(0h0))) node _T_1668 = or(_T_1622, _T_1627) node _T_1669 = or(_T_1668, _T_1632) node _T_1670 = or(_T_1669, _T_1637) node _T_1671 = or(_T_1670, _T_1642) node _T_1672 = or(_T_1671, _T_1647) node _T_1673 = or(_T_1672, _T_1652) node _T_1674 = or(_T_1673, _T_1657) node _T_1675 = or(_T_1674, _T_1662) node _T_1676 = or(_T_1675, _T_1667) node _T_1677 = and(_T_1617, _T_1676) node _T_1678 = or(UInt<1>(0h0), _T_1677) node _T_1679 = and(UInt<1>(0h0), _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_112 node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(address_ok, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(legal_source, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1689 = asUInt(reset) node _T_1690 = eq(_T_1689, UInt<1>(0h0)) when _T_1690 : node _T_1691 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1692 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_116 node _T_1696 = eq(io.in.b.bits.mask, mask_1) node _T_1697 = asUInt(reset) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) when _T_1698 : node _T_1699 = eq(_T_1696, UInt<1>(0h0)) when _T_1699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1696, UInt<1>(0h1), "") : assert_117 node _T_1700 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1700 : node _T_1701 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1702 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = or(UInt<1>(0h0), _T_1703) node _T_1705 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<14>(0h2000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<13>(0h1000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<18>(0h2f000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<13>(0h1000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<17>(0h10000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<27>(0h4000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1746 = cvt(_T_1745) node _T_1747 = and(_T_1746, asSInt(UInt<13>(0h1000))) node _T_1748 = asSInt(_T_1747) node _T_1749 = eq(_T_1748, asSInt(UInt<1>(0h0))) node _T_1750 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<29>(0h10000000))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = or(_T_1709, _T_1714) node _T_1756 = or(_T_1755, _T_1719) node _T_1757 = or(_T_1756, _T_1724) node _T_1758 = or(_T_1757, _T_1729) node _T_1759 = or(_T_1758, _T_1734) node _T_1760 = or(_T_1759, _T_1739) node _T_1761 = or(_T_1760, _T_1744) node _T_1762 = or(_T_1761, _T_1749) node _T_1763 = or(_T_1762, _T_1754) node _T_1764 = and(_T_1704, _T_1763) node _T_1765 = or(UInt<1>(0h0), _T_1764) node _T_1766 = and(UInt<1>(0h0), _T_1765) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_118 node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(address_ok, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(legal_source, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1779 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_122 node _T_1783 = eq(io.in.b.bits.mask, mask_1) node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(_T_1783, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1783, UInt<1>(0h1), "") : assert_123 node _T_1787 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1787 : node _T_1788 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1789 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1790 = and(_T_1788, _T_1789) node _T_1791 = or(UInt<1>(0h0), _T_1790) node _T_1792 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<14>(0h2000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<13>(0h1000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1796, _T_1801) node _T_1843 = or(_T_1842, _T_1806) node _T_1844 = or(_T_1843, _T_1811) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1821) node _T_1847 = or(_T_1846, _T_1826) node _T_1848 = or(_T_1847, _T_1831) node _T_1849 = or(_T_1848, _T_1836) node _T_1850 = or(_T_1849, _T_1841) node _T_1851 = and(_T_1791, _T_1850) node _T_1852 = or(UInt<1>(0h0), _T_1851) node _T_1853 = and(UInt<1>(0h0), _T_1852) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_124 node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(address_ok, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(legal_source, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1866 = eq(io.in.b.bits.mask, mask_1) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_128 node _T_1870 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1874 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1878 = shr(io.in.c.bits.source, 3) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) node _T_1885 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1892 = eq(_T_1891, UInt<1>(0h0)) node _T_1893 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = or(_T_1892, _T_1897) node _T_1899 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) node _T_1901 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1890, _T_1898) node _T_1908 = and(_T_1907, _T_1906) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_131 node _T_1912 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1912 : node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(address_ok_1, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok_2, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1919 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_134 node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1926 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_136 node _T_1930 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_137 node _T_1934 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1941 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_140 node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1948 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_142 node _T_1952 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1952 : node _T_1953 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1954 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1955 = and(_T_1953, _T_1954) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_1956 = shr(io.in.c.bits.source, 3) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) node _T_1958 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1959 = and(_T_1957, _T_1958) node _T_1960 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_1961 = and(_T_1959, _T_1960) node _T_1962 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1963 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1964 = or(_T_1961, _T_1962) node _T_1965 = or(_T_1964, _T_1963) node _T_1966 = and(_T_1955, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1966) node _T_1968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1969 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<14>(0h2000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<13>(0h1000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<18>(0h2f000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<17>(0h10000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2000 = cvt(_T_1999) node _T_2001 = and(_T_2000, asSInt(UInt<27>(0h4000000))) node _T_2002 = asSInt(_T_2001) node _T_2003 = eq(_T_2002, asSInt(UInt<1>(0h0))) node _T_2004 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2005 = cvt(_T_2004) node _T_2006 = and(_T_2005, asSInt(UInt<13>(0h1000))) node _T_2007 = asSInt(_T_2006) node _T_2008 = eq(_T_2007, asSInt(UInt<1>(0h0))) node _T_2009 = or(_T_1973, _T_1978) node _T_2010 = or(_T_2009, _T_1983) node _T_2011 = or(_T_2010, _T_1988) node _T_2012 = or(_T_2011, _T_1993) node _T_2013 = or(_T_2012, _T_1998) node _T_2014 = or(_T_2013, _T_2003) node _T_2015 = or(_T_2014, _T_2008) node _T_2016 = and(_T_1968, _T_2015) node _T_2017 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2018 = or(UInt<1>(0h0), _T_2017) node _T_2019 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2020 = cvt(_T_2019) node _T_2021 = and(_T_2020, asSInt(UInt<17>(0h10000))) node _T_2022 = asSInt(_T_2021) node _T_2023 = eq(_T_2022, asSInt(UInt<1>(0h0))) node _T_2024 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2025 = cvt(_T_2024) node _T_2026 = and(_T_2025, asSInt(UInt<29>(0h10000000))) node _T_2027 = asSInt(_T_2026) node _T_2028 = eq(_T_2027, asSInt(UInt<1>(0h0))) node _T_2029 = or(_T_2023, _T_2028) node _T_2030 = and(_T_2018, _T_2029) node _T_2031 = or(UInt<1>(0h0), _T_2016) node _T_2032 = or(_T_2031, _T_2030) node _T_2033 = and(_T_1967, _T_2032) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2037 = shr(io.in.c.bits.source, 3) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) node _T_2039 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2040 = and(_T_2038, _T_2039) node _T_2041 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2044 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2042 connect _WIRE_6[1], _T_2043 connect _WIRE_6[2], _T_2044 node _T_2045 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2046 = mux(_WIRE_6[0], _T_2045, UInt<1>(0h0)) node _T_2047 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2048 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = or(_T_2046, _T_2047) node _T_2050 = or(_T_2049, _T_2048) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2050 node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<14>(0h2000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<13>(0h1000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<18>(0h2f000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<13>(0h1000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<17>(0h10000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<29>(0h10000000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = or(_T_2059, _T_2064) node _T_2106 = or(_T_2105, _T_2069) node _T_2107 = or(_T_2106, _T_2074) node _T_2108 = or(_T_2107, _T_2079) node _T_2109 = or(_T_2108, _T_2084) node _T_2110 = or(_T_2109, _T_2089) node _T_2111 = or(_T_2110, _T_2094) node _T_2112 = or(_T_2111, _T_2099) node _T_2113 = or(_T_2112, _T_2104) node _T_2114 = and(_T_2054, _T_2113) node _T_2115 = or(UInt<1>(0h0), _T_2114) node _T_2116 = and(_WIRE_7, _T_2115) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_144 node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(source_ok_2, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2123 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_146 node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2130 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_148 node _T_2134 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2135 = asUInt(reset) node _T_2136 = eq(_T_2135, UInt<1>(0h0)) when _T_2136 : node _T_2137 = eq(_T_2134, UInt<1>(0h0)) when _T_2137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2134, UInt<1>(0h1), "") : assert_149 node _T_2138 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2138 : node _T_2139 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2140 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2141 = and(_T_2139, _T_2140) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2142 = shr(io.in.c.bits.source, 3) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) node _T_2144 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2149 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2150 = or(_T_2147, _T_2148) node _T_2151 = or(_T_2150, _T_2149) node _T_2152 = and(_T_2141, _T_2151) node _T_2153 = or(UInt<1>(0h0), _T_2152) node _T_2154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2155 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<14>(0h2000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<13>(0h1000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<18>(0h2f000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<17>(0h10000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2186 = cvt(_T_2185) node _T_2187 = and(_T_2186, asSInt(UInt<27>(0h4000000))) node _T_2188 = asSInt(_T_2187) node _T_2189 = eq(_T_2188, asSInt(UInt<1>(0h0))) node _T_2190 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<13>(0h1000))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2159, _T_2164) node _T_2196 = or(_T_2195, _T_2169) node _T_2197 = or(_T_2196, _T_2174) node _T_2198 = or(_T_2197, _T_2179) node _T_2199 = or(_T_2198, _T_2184) node _T_2200 = or(_T_2199, _T_2189) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = and(_T_2154, _T_2201) node _T_2203 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2204 = or(UInt<1>(0h0), _T_2203) node _T_2205 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2206 = cvt(_T_2205) node _T_2207 = and(_T_2206, asSInt(UInt<17>(0h10000))) node _T_2208 = asSInt(_T_2207) node _T_2209 = eq(_T_2208, asSInt(UInt<1>(0h0))) node _T_2210 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2211 = cvt(_T_2210) node _T_2212 = and(_T_2211, asSInt(UInt<29>(0h10000000))) node _T_2213 = asSInt(_T_2212) node _T_2214 = eq(_T_2213, asSInt(UInt<1>(0h0))) node _T_2215 = or(_T_2209, _T_2214) node _T_2216 = and(_T_2204, _T_2215) node _T_2217 = or(UInt<1>(0h0), _T_2202) node _T_2218 = or(_T_2217, _T_2216) node _T_2219 = and(_T_2153, _T_2218) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2223 = shr(io.in.c.bits.source, 3) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) node _T_2225 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2226 = and(_T_2224, _T_2225) node _T_2227 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2228 = and(_T_2226, _T_2227) node _T_2229 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2230 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2228 connect _WIRE_8[1], _T_2229 connect _WIRE_8[2], _T_2230 node _T_2231 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2232 = mux(_WIRE_8[0], _T_2231, UInt<1>(0h0)) node _T_2233 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2234 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2235 = or(_T_2232, _T_2233) node _T_2236 = or(_T_2235, _T_2234) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2236 node _T_2237 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2238 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2239 = and(_T_2237, _T_2238) node _T_2240 = or(UInt<1>(0h0), _T_2239) node _T_2241 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<14>(0h2000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<13>(0h1000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<18>(0h2f000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<13>(0h1000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<17>(0h10000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<27>(0h4000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2282 = cvt(_T_2281) node _T_2283 = and(_T_2282, asSInt(UInt<13>(0h1000))) node _T_2284 = asSInt(_T_2283) node _T_2285 = eq(_T_2284, asSInt(UInt<1>(0h0))) node _T_2286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2287 = cvt(_T_2286) node _T_2288 = and(_T_2287, asSInt(UInt<29>(0h10000000))) node _T_2289 = asSInt(_T_2288) node _T_2290 = eq(_T_2289, asSInt(UInt<1>(0h0))) node _T_2291 = or(_T_2245, _T_2250) node _T_2292 = or(_T_2291, _T_2255) node _T_2293 = or(_T_2292, _T_2260) node _T_2294 = or(_T_2293, _T_2265) node _T_2295 = or(_T_2294, _T_2270) node _T_2296 = or(_T_2295, _T_2275) node _T_2297 = or(_T_2296, _T_2280) node _T_2298 = or(_T_2297, _T_2285) node _T_2299 = or(_T_2298, _T_2290) node _T_2300 = and(_T_2240, _T_2299) node _T_2301 = or(UInt<1>(0h0), _T_2300) node _T_2302 = and(_WIRE_9, _T_2301) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_151 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(source_ok_2, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2309 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(_T_2309, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2309, UInt<1>(0h1), "") : assert_153 node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2316 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_155 node _T_2320 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2320 : node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(address_ok_1, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : node _T_2326 = eq(source_ok_2, UInt<1>(0h0)) when _T_2326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2330 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2331 = asUInt(reset) node _T_2332 = eq(_T_2331, UInt<1>(0h0)) when _T_2332 : node _T_2333 = eq(_T_2330, UInt<1>(0h0)) when _T_2333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2330, UInt<1>(0h1), "") : assert_159 node _T_2334 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(_T_2334, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2334, UInt<1>(0h1), "") : assert_160 node _T_2338 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2338 : node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(address_ok_1, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(source_ok_2, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2345 = asUInt(reset) node _T_2346 = eq(_T_2345, UInt<1>(0h0)) when _T_2346 : node _T_2347 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2348 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_164 node _T_2352 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2352 : node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(address_ok_1, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok_2, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2362 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_168 node _T_2366 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2373 = eq(a_first, UInt<1>(0h0)) node _T_2374 = and(io.in.a.valid, _T_2373) when _T_2374 : node _T_2375 = eq(io.in.a.bits.opcode, opcode) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_171 node _T_2379 = eq(io.in.a.bits.param, param) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_172 node _T_2383 = eq(io.in.a.bits.size, size) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_173 node _T_2387 = eq(io.in.a.bits.source, source) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_174 node _T_2391 = eq(io.in.a.bits.address, address) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_175 node _T_2395 = and(io.in.a.ready, io.in.a.valid) node _T_2396 = and(_T_2395, a_first) when _T_2396 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2397 = eq(d_first, UInt<1>(0h0)) node _T_2398 = and(io.in.d.valid, _T_2397) when _T_2398 : node _T_2399 = eq(io.in.d.bits.opcode, opcode_1) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_176 node _T_2403 = eq(io.in.d.bits.param, param_1) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_177 node _T_2407 = eq(io.in.d.bits.size, size_1) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_178 node _T_2411 = eq(io.in.d.bits.source, source_1) node _T_2412 = asUInt(reset) node _T_2413 = eq(_T_2412, UInt<1>(0h0)) when _T_2413 : node _T_2414 = eq(_T_2411, UInt<1>(0h0)) when _T_2414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2411, UInt<1>(0h1), "") : assert_179 node _T_2415 = eq(io.in.d.bits.sink, sink) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_180 node _T_2419 = eq(io.in.d.bits.denied, denied) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_181 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first) when _T_2424 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2425 = eq(b_first, UInt<1>(0h0)) node _T_2426 = and(io.in.b.valid, _T_2425) when _T_2426 : node _T_2427 = eq(io.in.b.bits.opcode, opcode_2) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_182 node _T_2431 = eq(io.in.b.bits.param, param_2) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_183 node _T_2435 = eq(io.in.b.bits.size, size_2) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_184 node _T_2439 = eq(io.in.b.bits.source, source_2) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_185 node _T_2443 = eq(io.in.b.bits.address, address_1) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_186 node _T_2447 = and(io.in.b.ready, io.in.b.valid) node _T_2448 = and(_T_2447, b_first) when _T_2448 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2449 = eq(c_first, UInt<1>(0h0)) node _T_2450 = and(io.in.c.valid, _T_2449) when _T_2450 : node _T_2451 = eq(io.in.c.bits.opcode, opcode_3) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_187 node _T_2455 = eq(io.in.c.bits.param, param_3) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_188 node _T_2459 = eq(io.in.c.bits.size, size_3) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_189 node _T_2463 = eq(io.in.c.bits.source, source_3) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_190 node _T_2467 = eq(io.in.c.bits.address, address_2) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_191 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(_T_2471, c_first) when _T_2472 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2473 = and(io.in.a.valid, a_first_1) node _T_2474 = and(_T_2473, UInt<1>(0h1)) when _T_2474 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2475 = and(io.in.a.ready, io.in.a.valid) node _T_2476 = and(_T_2475, a_first_1) node _T_2477 = and(_T_2476, UInt<1>(0h1)) when _T_2477 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2478 = dshr(inflight, io.in.a.bits.source) node _T_2479 = bits(_T_2478, 0, 0) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2484 = and(io.in.d.valid, d_first_1) node _T_2485 = and(_T_2484, UInt<1>(0h1)) node _T_2486 = eq(d_release_ack, UInt<1>(0h0)) node _T_2487 = and(_T_2485, _T_2486) when _T_2487 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2488 = and(io.in.d.ready, io.in.d.valid) node _T_2489 = and(_T_2488, d_first_1) node _T_2490 = and(_T_2489, UInt<1>(0h1)) node _T_2491 = eq(d_release_ack, UInt<1>(0h0)) node _T_2492 = and(_T_2490, _T_2491) when _T_2492 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2493 = and(io.in.d.valid, d_first_1) node _T_2494 = and(_T_2493, UInt<1>(0h1)) node _T_2495 = eq(d_release_ack, UInt<1>(0h0)) node _T_2496 = and(_T_2494, _T_2495) when _T_2496 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2497 = dshr(inflight, io.in.d.bits.source) node _T_2498 = bits(_T_2497, 0, 0) node _T_2499 = or(_T_2498, same_cycle_resp) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_194 node _T_2509 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_195 else : node _T_2513 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2514 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2515 = or(_T_2513, _T_2514) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_196 node _T_2519 = eq(io.in.d.bits.size, a_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_197 node _T_2523 = and(io.in.d.valid, d_first_1) node _T_2524 = and(_T_2523, a_first_1) node _T_2525 = and(_T_2524, io.in.a.valid) node _T_2526 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = eq(d_release_ack, UInt<1>(0h0)) node _T_2529 = and(_T_2527, _T_2528) when _T_2529 : node _T_2530 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2531 = or(_T_2530, io.in.a.ready) node _T_2532 = asUInt(reset) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) when _T_2533 : node _T_2534 = eq(_T_2531, UInt<1>(0h0)) when _T_2534 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2531, UInt<1>(0h1), "") : assert_198 node _T_2535 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2536 = orr(a_set_wo_ready) node _T_2537 = eq(_T_2536, UInt<1>(0h0)) node _T_2538 = or(_T_2535, _T_2537) node _T_2539 = asUInt(reset) node _T_2540 = eq(_T_2539, UInt<1>(0h0)) when _T_2540 : node _T_2541 = eq(_T_2538, UInt<1>(0h0)) when _T_2541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2538, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_8 node _T_2542 = orr(inflight) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) node _T_2544 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2545 = or(_T_2543, _T_2544) node _T_2546 = lt(watchdog, plusarg_reader.out) node _T_2547 = or(_T_2545, _T_2546) node _T_2548 = asUInt(reset) node _T_2549 = eq(_T_2548, UInt<1>(0h0)) when _T_2549 : node _T_2550 = eq(_T_2547, UInt<1>(0h0)) when _T_2550 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2547, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2551 = and(io.in.a.ready, io.in.a.valid) node _T_2552 = and(io.in.d.ready, io.in.d.valid) node _T_2553 = or(_T_2551, _T_2552) when _T_2553 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2554 = and(io.in.c.valid, c_first_1) node _T_2555 = bits(io.in.c.bits.opcode, 2, 2) node _T_2556 = bits(io.in.c.bits.opcode, 1, 1) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = and(_T_2554, _T_2557) when _T_2558 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2559 = and(io.in.c.ready, io.in.c.valid) node _T_2560 = and(_T_2559, c_first_1) node _T_2561 = bits(io.in.c.bits.opcode, 2, 2) node _T_2562 = bits(io.in.c.bits.opcode, 1, 1) node _T_2563 = and(_T_2561, _T_2562) node _T_2564 = and(_T_2560, _T_2563) when _T_2564 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2565 = dshr(inflight_1, io.in.c.bits.source) node _T_2566 = bits(_T_2565, 0, 0) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) node _T_2568 = asUInt(reset) node _T_2569 = eq(_T_2568, UInt<1>(0h0)) when _T_2569 : node _T_2570 = eq(_T_2567, UInt<1>(0h0)) when _T_2570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2567, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2571 = and(io.in.d.valid, d_first_2) node _T_2572 = and(_T_2571, UInt<1>(0h1)) node _T_2573 = and(_T_2572, d_release_ack_1) when _T_2573 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2574 = and(io.in.d.ready, io.in.d.valid) node _T_2575 = and(_T_2574, d_first_2) node _T_2576 = and(_T_2575, UInt<1>(0h1)) node _T_2577 = and(_T_2576, d_release_ack_1) when _T_2577 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2578 = and(io.in.d.valid, d_first_2) node _T_2579 = and(_T_2578, UInt<1>(0h1)) node _T_2580 = and(_T_2579, d_release_ack_1) when _T_2580 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2581 = dshr(inflight_1, io.in.d.bits.source) node _T_2582 = bits(_T_2581, 0, 0) node _T_2583 = or(_T_2582, same_cycle_resp_1) node _T_2584 = asUInt(reset) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) when _T_2585 : node _T_2586 = eq(_T_2583, UInt<1>(0h0)) when _T_2586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2583, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2587 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2588 = asUInt(reset) node _T_2589 = eq(_T_2588, UInt<1>(0h0)) when _T_2589 : node _T_2590 = eq(_T_2587, UInt<1>(0h0)) when _T_2590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2587, UInt<1>(0h1), "") : assert_203 else : node _T_2591 = eq(io.in.d.bits.size, c_size_lookup) node _T_2592 = asUInt(reset) node _T_2593 = eq(_T_2592, UInt<1>(0h0)) when _T_2593 : node _T_2594 = eq(_T_2591, UInt<1>(0h0)) when _T_2594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2591, UInt<1>(0h1), "") : assert_204 node _T_2595 = and(io.in.d.valid, d_first_2) node _T_2596 = and(_T_2595, c_first_1) node _T_2597 = and(_T_2596, io.in.c.valid) node _T_2598 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2599 = and(_T_2597, _T_2598) node _T_2600 = and(_T_2599, d_release_ack_1) node _T_2601 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2602 = and(_T_2600, _T_2601) when _T_2602 : node _T_2603 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2604 = or(_T_2603, io.in.c.ready) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_205 node _T_2608 = orr(c_set_wo_ready) when _T_2608 : node _T_2609 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_9 node _T_2613 = orr(inflight_1) node _T_2614 = eq(_T_2613, UInt<1>(0h0)) node _T_2615 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2616 = or(_T_2614, _T_2615) node _T_2617 = lt(watchdog_1, plusarg_reader_1.out) node _T_2618 = or(_T_2616, _T_2617) node _T_2619 = asUInt(reset) node _T_2620 = eq(_T_2619, UInt<1>(0h0)) when _T_2620 : node _T_2621 = eq(_T_2618, UInt<1>(0h0)) when _T_2621 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2618, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2622 = and(io.in.c.ready, io.in.c.valid) node _T_2623 = and(io.in.d.ready, io.in.d.valid) node _T_2624 = or(_T_2622, _T_2623) when _T_2624 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2625 = and(io.in.d.ready, io.in.d.valid) node _T_2626 = and(_T_2625, d_first_3) node _T_2627 = bits(io.in.d.bits.opcode, 2, 2) node _T_2628 = bits(io.in.d.bits.opcode, 1, 1) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) node _T_2630 = and(_T_2627, _T_2629) node _T_2631 = and(_T_2626, _T_2630) when _T_2631 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2632 = dshr(inflight_2, io.in.d.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = asUInt(reset) node _T_2636 = eq(_T_2635, UInt<1>(0h0)) when _T_2636 : node _T_2637 = eq(_T_2634, UInt<1>(0h0)) when _T_2637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2634, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2638 = and(io.in.e.ready, io.in.e.valid) node _T_2639 = and(_T_2638, UInt<1>(0h1)) node _T_2640 = and(_T_2639, UInt<1>(0h1)) when _T_2640 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2641 = or(d_set, inflight_2) node _T_2642 = dshr(_T_2641, io.in.e.bits.sink) node _T_2643 = bits(_T_2642, 0, 0) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[3]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_9 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_10 = {_legal_source_WIRE_2, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} | _legal_source_T_10; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2551 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2551; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2551; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2625 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2625; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2622 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2622; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2622; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_20 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2551 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2477 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2477 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2477 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2477 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2477 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2523 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_22 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2523 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2625 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2492 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2492 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2492 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_23 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2564 = _T_2622 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2564 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2564 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2564 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2564 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2564 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2595 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2595 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2577 = _T_2625 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2577 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2577 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2577 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2631 = _T_2625 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_24 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2631 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2640 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = _T_2640 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module Tile_53 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_309 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_53( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_309 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BoomTile : input clock : Clock input reset : Reset output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>, custom : { rob_empty : UInt<1>}}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1 inst broadcast of BundleBridgeNexus_UInt1 inst broadcast_1 of BundleBridgeNexus_UInt32 inst nexus of BundleBridgeNexus_NoOutput_6 inst nexus_1 of BundleBridgeNexus_TraceAux inst broadcast_2 of BundleBridgeNexus_NoOutput_7 inst buffer of TLBuffer_a32d64s3k3z4c connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_a32d64s2k3z4c connect buffer_1.clock, clock connect buffer_1.reset, reset inst widget of TLWidthWidget8_8 connect widget.clock, clock connect widget.reset, reset inst dcache of BoomNonBlockingDCache connect dcache.clock, clock connect dcache.reset, reset inst frontend of BoomFrontend connect frontend.clock, clock connect frontend.reset, reset inst buffer_2 of TLBuffer_a32d64s1k3z4u connect buffer_2.clock, clock connect buffer_2.reset, reset inst widget_1 of TLWidthWidget8_9 connect widget_1.clock, clock connect widget_1.reset, reset inst buffer_3 of TLBuffer_a32d64s3k3z4c_1 connect buffer_3.clock, clock connect buffer_3.reset, reset inst buffer_4 of TLBuffer_1 connect buffer_4.clock, clock connect buffer_4.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeOut.e.bits.sink invalidate tlOtherMastersNodeOut.e.valid invalidate tlOtherMastersNodeOut.e.ready invalidate tlOtherMastersNodeOut.d.bits.corrupt invalidate tlOtherMastersNodeOut.d.bits.data invalidate tlOtherMastersNodeOut.d.bits.denied invalidate tlOtherMastersNodeOut.d.bits.sink invalidate tlOtherMastersNodeOut.d.bits.source invalidate tlOtherMastersNodeOut.d.bits.size invalidate tlOtherMastersNodeOut.d.bits.param invalidate tlOtherMastersNodeOut.d.bits.opcode invalidate tlOtherMastersNodeOut.d.valid invalidate tlOtherMastersNodeOut.d.ready invalidate tlOtherMastersNodeOut.c.bits.corrupt invalidate tlOtherMastersNodeOut.c.bits.data invalidate tlOtherMastersNodeOut.c.bits.address invalidate tlOtherMastersNodeOut.c.bits.source invalidate tlOtherMastersNodeOut.c.bits.size invalidate tlOtherMastersNodeOut.c.bits.param invalidate tlOtherMastersNodeOut.c.bits.opcode invalidate tlOtherMastersNodeOut.c.valid invalidate tlOtherMastersNodeOut.c.ready invalidate tlOtherMastersNodeOut.b.bits.corrupt invalidate tlOtherMastersNodeOut.b.bits.data invalidate tlOtherMastersNodeOut.b.bits.mask invalidate tlOtherMastersNodeOut.b.bits.address invalidate tlOtherMastersNodeOut.b.bits.source invalidate tlOtherMastersNodeOut.b.bits.size invalidate tlOtherMastersNodeOut.b.bits.param invalidate tlOtherMastersNodeOut.b.bits.opcode invalidate tlOtherMastersNodeOut.b.valid invalidate tlOtherMastersNodeOut.b.ready invalidate tlOtherMastersNodeOut.a.bits.corrupt invalidate tlOtherMastersNodeOut.a.bits.data invalidate tlOtherMastersNodeOut.a.bits.mask invalidate tlOtherMastersNodeOut.a.bits.address invalidate tlOtherMastersNodeOut.a.bits.source invalidate tlOtherMastersNodeOut.a.bits.size invalidate tlOtherMastersNodeOut.a.bits.param invalidate tlOtherMastersNodeOut.a.bits.opcode invalidate tlOtherMastersNodeOut.a.valid invalidate tlOtherMastersNodeOut.a.ready wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeIn.e.bits.sink invalidate tlOtherMastersNodeIn.e.valid invalidate tlOtherMastersNodeIn.e.ready invalidate tlOtherMastersNodeIn.d.bits.corrupt invalidate tlOtherMastersNodeIn.d.bits.data invalidate tlOtherMastersNodeIn.d.bits.denied invalidate tlOtherMastersNodeIn.d.bits.sink invalidate tlOtherMastersNodeIn.d.bits.source invalidate tlOtherMastersNodeIn.d.bits.size invalidate tlOtherMastersNodeIn.d.bits.param invalidate tlOtherMastersNodeIn.d.bits.opcode invalidate tlOtherMastersNodeIn.d.valid invalidate tlOtherMastersNodeIn.d.ready invalidate tlOtherMastersNodeIn.c.bits.corrupt invalidate tlOtherMastersNodeIn.c.bits.data invalidate tlOtherMastersNodeIn.c.bits.address invalidate tlOtherMastersNodeIn.c.bits.source invalidate tlOtherMastersNodeIn.c.bits.size invalidate tlOtherMastersNodeIn.c.bits.param invalidate tlOtherMastersNodeIn.c.bits.opcode invalidate tlOtherMastersNodeIn.c.valid invalidate tlOtherMastersNodeIn.c.ready invalidate tlOtherMastersNodeIn.b.bits.corrupt invalidate tlOtherMastersNodeIn.b.bits.data invalidate tlOtherMastersNodeIn.b.bits.mask invalidate tlOtherMastersNodeIn.b.bits.address invalidate tlOtherMastersNodeIn.b.bits.source invalidate tlOtherMastersNodeIn.b.bits.size invalidate tlOtherMastersNodeIn.b.bits.param invalidate tlOtherMastersNodeIn.b.bits.opcode invalidate tlOtherMastersNodeIn.b.valid invalidate tlOtherMastersNodeIn.b.ready invalidate tlOtherMastersNodeIn.a.bits.corrupt invalidate tlOtherMastersNodeIn.a.bits.data invalidate tlOtherMastersNodeIn.a.bits.mask invalidate tlOtherMastersNodeIn.a.bits.address invalidate tlOtherMastersNodeIn.a.bits.source invalidate tlOtherMastersNodeIn.a.bits.size invalidate tlOtherMastersNodeIn.a.bits.param invalidate tlOtherMastersNodeIn.a.bits.opcode invalidate tlOtherMastersNodeIn.a.valid invalidate tlOtherMastersNodeIn.a.ready connect tlOtherMastersNodeOut, tlOtherMastersNodeIn wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>, custom : { rob_empty : UInt<1>}} invalidate traceSourceNodeOut.custom.rob_empty invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid invalidate traceSourceNodeOut.insns[1].tval invalidate traceSourceNodeOut.insns[1].cause invalidate traceSourceNodeOut.insns[1].interrupt invalidate traceSourceNodeOut.insns[1].exception invalidate traceSourceNodeOut.insns[1].priv invalidate traceSourceNodeOut.insns[1].insn invalidate traceSourceNodeOut.insns[1].iaddr invalidate traceSourceNodeOut.insns[1].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[2], rvalid : UInt<1>[2], wvalid : UInt<1>[2], ivalid : UInt<1>[2], action : UInt<3>}[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeOut.e.bits.sink invalidate masterNodeOut.e.valid invalidate masterNodeOut.e.ready invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.c.bits.corrupt invalidate masterNodeOut.c.bits.data invalidate masterNodeOut.c.bits.address invalidate masterNodeOut.c.bits.source invalidate masterNodeOut.c.bits.size invalidate masterNodeOut.c.bits.param invalidate masterNodeOut.c.bits.opcode invalidate masterNodeOut.c.valid invalidate masterNodeOut.c.ready invalidate masterNodeOut.b.bits.corrupt invalidate masterNodeOut.b.bits.data invalidate masterNodeOut.b.bits.mask invalidate masterNodeOut.b.bits.address invalidate masterNodeOut.b.bits.source invalidate masterNodeOut.b.bits.size invalidate masterNodeOut.b.bits.param invalidate masterNodeOut.b.bits.opcode invalidate masterNodeOut.b.valid invalidate masterNodeOut.b.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready wire masterNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeIn.e.bits.sink invalidate masterNodeIn.e.valid invalidate masterNodeIn.e.ready invalidate masterNodeIn.d.bits.corrupt invalidate masterNodeIn.d.bits.data invalidate masterNodeIn.d.bits.denied invalidate masterNodeIn.d.bits.sink invalidate masterNodeIn.d.bits.source invalidate masterNodeIn.d.bits.size invalidate masterNodeIn.d.bits.param invalidate masterNodeIn.d.bits.opcode invalidate masterNodeIn.d.valid invalidate masterNodeIn.d.ready invalidate masterNodeIn.c.bits.corrupt invalidate masterNodeIn.c.bits.data invalidate masterNodeIn.c.bits.address invalidate masterNodeIn.c.bits.source invalidate masterNodeIn.c.bits.size invalidate masterNodeIn.c.bits.param invalidate masterNodeIn.c.bits.opcode invalidate masterNodeIn.c.valid invalidate masterNodeIn.c.ready invalidate masterNodeIn.b.bits.corrupt invalidate masterNodeIn.b.bits.data invalidate masterNodeIn.b.bits.mask invalidate masterNodeIn.b.bits.address invalidate masterNodeIn.b.bits.source invalidate masterNodeIn.b.bits.size invalidate masterNodeIn.b.bits.param invalidate masterNodeIn.b.bits.opcode invalidate masterNodeIn.b.valid invalidate masterNodeIn.b.ready invalidate masterNodeIn.a.bits.corrupt invalidate masterNodeIn.a.bits.data invalidate masterNodeIn.a.bits.mask invalidate masterNodeIn.a.bits.address invalidate masterNodeIn.a.bits.source invalidate masterNodeIn.a.bits.size invalidate masterNodeIn.a.bits.param invalidate masterNodeIn.a.bits.opcode invalidate masterNodeIn.a.valid invalidate masterNodeIn.a.ready connect masterNodeOut, masterNodeIn wire dCacheTapOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate dCacheTapOut.e.bits.sink invalidate dCacheTapOut.e.valid invalidate dCacheTapOut.e.ready invalidate dCacheTapOut.d.bits.corrupt invalidate dCacheTapOut.d.bits.data invalidate dCacheTapOut.d.bits.denied invalidate dCacheTapOut.d.bits.sink invalidate dCacheTapOut.d.bits.source invalidate dCacheTapOut.d.bits.size invalidate dCacheTapOut.d.bits.param invalidate dCacheTapOut.d.bits.opcode invalidate dCacheTapOut.d.valid invalidate dCacheTapOut.d.ready invalidate dCacheTapOut.c.bits.corrupt invalidate dCacheTapOut.c.bits.data invalidate dCacheTapOut.c.bits.address invalidate dCacheTapOut.c.bits.source invalidate dCacheTapOut.c.bits.size invalidate dCacheTapOut.c.bits.param invalidate dCacheTapOut.c.bits.opcode invalidate dCacheTapOut.c.valid invalidate dCacheTapOut.c.ready invalidate dCacheTapOut.b.bits.corrupt invalidate dCacheTapOut.b.bits.data invalidate dCacheTapOut.b.bits.mask invalidate dCacheTapOut.b.bits.address invalidate dCacheTapOut.b.bits.source invalidate dCacheTapOut.b.bits.size invalidate dCacheTapOut.b.bits.param invalidate dCacheTapOut.b.bits.opcode invalidate dCacheTapOut.b.valid invalidate dCacheTapOut.b.ready invalidate dCacheTapOut.a.bits.corrupt invalidate dCacheTapOut.a.bits.data invalidate dCacheTapOut.a.bits.mask invalidate dCacheTapOut.a.bits.address invalidate dCacheTapOut.a.bits.source invalidate dCacheTapOut.a.bits.size invalidate dCacheTapOut.a.bits.param invalidate dCacheTapOut.a.bits.opcode invalidate dCacheTapOut.a.valid invalidate dCacheTapOut.a.ready wire dCacheTapIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate dCacheTapIn.e.bits.sink invalidate dCacheTapIn.e.valid invalidate dCacheTapIn.e.ready invalidate dCacheTapIn.d.bits.corrupt invalidate dCacheTapIn.d.bits.data invalidate dCacheTapIn.d.bits.denied invalidate dCacheTapIn.d.bits.sink invalidate dCacheTapIn.d.bits.source invalidate dCacheTapIn.d.bits.size invalidate dCacheTapIn.d.bits.param invalidate dCacheTapIn.d.bits.opcode invalidate dCacheTapIn.d.valid invalidate dCacheTapIn.d.ready invalidate dCacheTapIn.c.bits.corrupt invalidate dCacheTapIn.c.bits.data invalidate dCacheTapIn.c.bits.address invalidate dCacheTapIn.c.bits.source invalidate dCacheTapIn.c.bits.size invalidate dCacheTapIn.c.bits.param invalidate dCacheTapIn.c.bits.opcode invalidate dCacheTapIn.c.valid invalidate dCacheTapIn.c.ready invalidate dCacheTapIn.b.bits.corrupt invalidate dCacheTapIn.b.bits.data invalidate dCacheTapIn.b.bits.mask invalidate dCacheTapIn.b.bits.address invalidate dCacheTapIn.b.bits.source invalidate dCacheTapIn.b.bits.size invalidate dCacheTapIn.b.bits.param invalidate dCacheTapIn.b.bits.opcode invalidate dCacheTapIn.b.valid invalidate dCacheTapIn.b.ready invalidate dCacheTapIn.a.bits.corrupt invalidate dCacheTapIn.a.bits.data invalidate dCacheTapIn.a.bits.mask invalidate dCacheTapIn.a.bits.address invalidate dCacheTapIn.a.bits.source invalidate dCacheTapIn.a.bits.size invalidate dCacheTapIn.a.bits.param invalidate dCacheTapIn.a.bits.opcode invalidate dCacheTapIn.a.valid invalidate dCacheTapIn.a.ready connect dCacheTapOut, dCacheTapIn connect masterNodeIn, tlOtherMastersNodeOut connect buffer.auto.in, tlMasterXbar.auto.anon_out connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect buffer_3.auto.in, masterNodeOut connect tlOtherMastersNodeIn.e.bits, buffer.auto.out.e.bits connect tlOtherMastersNodeIn.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, tlOtherMastersNodeIn.e.ready connect buffer.auto.out.d, tlOtherMastersNodeIn.d connect tlOtherMastersNodeIn.c.bits, buffer.auto.out.c.bits connect tlOtherMastersNodeIn.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, tlOtherMastersNodeIn.c.ready connect buffer.auto.out.b, tlOtherMastersNodeIn.b connect tlOtherMastersNodeIn.a.bits, buffer.auto.out.a.bits connect tlOtherMastersNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, tlOtherMastersNodeIn.a.ready connect tlMasterXbar.auto.anon_in_0, dCacheTapOut connect dCacheTapIn.e.bits, buffer_1.auto.out.e.bits connect dCacheTapIn.e.valid, buffer_1.auto.out.e.valid connect buffer_1.auto.out.e.ready, dCacheTapIn.e.ready connect buffer_1.auto.out.d, dCacheTapIn.d connect dCacheTapIn.c.bits, buffer_1.auto.out.c.bits connect dCacheTapIn.c.valid, buffer_1.auto.out.c.valid connect buffer_1.auto.out.c.ready, dCacheTapIn.c.ready connect buffer_1.auto.out.b, dCacheTapIn.b connect dCacheTapIn.a.bits, buffer_1.auto.out.a.bits connect dCacheTapIn.a.valid, buffer_1.auto.out.a.valid connect buffer_1.auto.out.a.ready, dCacheTapIn.a.ready connect buffer_1.auto.in, widget.auto.anon_out connect widget.auto.anon_in, dcache.auto.out connect widget_1.auto.anon_in, frontend.auto.icache_master_out connect tlMasterXbar.auto.anon_in_1, buffer_2.auto.out connect buffer_2.auto.in, widget_1.auto.anon_out connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect auto.buffer_out.e.bits, buffer_3.auto.out.e.bits connect auto.buffer_out.e.valid, buffer_3.auto.out.e.valid connect buffer_3.auto.out.e.ready, auto.buffer_out.e.ready connect buffer_3.auto.out.d, auto.buffer_out.d connect auto.buffer_out.c.bits, buffer_3.auto.out.c.bits connect auto.buffer_out.c.valid, buffer_3.auto.out.c.valid connect buffer_3.auto.out.c.ready, auto.buffer_out.c.ready connect buffer_3.auto.out.b, auto.buffer_out.b connect auto.buffer_out.a.bits, buffer_3.auto.out.a.bits connect auto.buffer_out.a.valid, buffer_3.auto.out.a.valid connect buffer_3.auto.out.a.ready, auto.buffer_out.a.ready inst core of BoomCore connect core.clock, clock connect core.reset, reset inst lsu of LSU connect lsu.clock, clock connect lsu.reset, reset connect wfiNodeOut[0], UInt<1>(0h0) connect core.io.interrupts.debug, intSinkNodeIn[0] connect core.io.interrupts.msip, intSinkNodeIn[1] connect core.io.interrupts.mtip, intSinkNodeIn[2] connect core.io.interrupts.meip, intSinkNodeIn[3] connect core.io.interrupts.seip, intSinkNodeIn[4] connect traceSourceNodeOut, core.io.trace connect core.io.hartid, hartIdSinkNodeIn connect frontend.io.cpu, core.io.ifu connect core.io.lsu, lsu.io.core invalidate core.io.rocc.exception invalidate core.io.rocc.interrupt invalidate core.io.rocc.busy invalidate core.io.rocc.mem.clock_enabled invalidate core.io.rocc.mem.keep_clock_enabled invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad invalidate core.io.rocc.mem.perf.blocked invalidate core.io.rocc.mem.perf.tlbMiss invalidate core.io.rocc.mem.perf.grant invalidate core.io.rocc.mem.perf.release invalidate core.io.rocc.mem.perf.acquire invalidate core.io.rocc.mem.store_pending invalidate core.io.rocc.mem.ordered invalidate core.io.rocc.mem.s2_gpa_is_pte invalidate core.io.rocc.mem.s2_gpa invalidate core.io.rocc.mem.s2_xcpt.ae.st invalidate core.io.rocc.mem.s2_xcpt.ae.ld invalidate core.io.rocc.mem.s2_xcpt.gf.st invalidate core.io.rocc.mem.s2_xcpt.gf.ld invalidate core.io.rocc.mem.s2_xcpt.pf.st invalidate core.io.rocc.mem.s2_xcpt.pf.ld invalidate core.io.rocc.mem.s2_xcpt.ma.st invalidate core.io.rocc.mem.s2_xcpt.ma.ld invalidate core.io.rocc.mem.replay_next invalidate core.io.rocc.mem.resp.bits.store_data invalidate core.io.rocc.mem.resp.bits.data_raw invalidate core.io.rocc.mem.resp.bits.data_word_bypass invalidate core.io.rocc.mem.resp.bits.has_data invalidate core.io.rocc.mem.resp.bits.replay invalidate core.io.rocc.mem.resp.bits.mask invalidate core.io.rocc.mem.resp.bits.data invalidate core.io.rocc.mem.resp.bits.dv invalidate core.io.rocc.mem.resp.bits.dprv invalidate core.io.rocc.mem.resp.bits.signed invalidate core.io.rocc.mem.resp.bits.size invalidate core.io.rocc.mem.resp.bits.cmd invalidate core.io.rocc.mem.resp.bits.tag invalidate core.io.rocc.mem.resp.bits.addr invalidate core.io.rocc.mem.resp.valid invalidate core.io.rocc.mem.s2_paddr invalidate core.io.rocc.mem.s2_uncached invalidate core.io.rocc.mem.s2_kill invalidate core.io.rocc.mem.s2_nack_cause_raw invalidate core.io.rocc.mem.s2_nack invalidate core.io.rocc.mem.s1_data.mask invalidate core.io.rocc.mem.s1_data.data invalidate core.io.rocc.mem.s1_kill invalidate core.io.rocc.mem.req.bits.mask invalidate core.io.rocc.mem.req.bits.data invalidate core.io.rocc.mem.req.bits.no_xcpt invalidate core.io.rocc.mem.req.bits.no_alloc invalidate core.io.rocc.mem.req.bits.no_resp invalidate core.io.rocc.mem.req.bits.phys invalidate core.io.rocc.mem.req.bits.dv invalidate core.io.rocc.mem.req.bits.dprv invalidate core.io.rocc.mem.req.bits.signed invalidate core.io.rocc.mem.req.bits.size invalidate core.io.rocc.mem.req.bits.cmd invalidate core.io.rocc.mem.req.bits.tag invalidate core.io.rocc.mem.req.bits.addr invalidate core.io.rocc.mem.req.valid invalidate core.io.rocc.mem.req.ready invalidate core.io.rocc.resp.bits.data invalidate core.io.rocc.resp.bits.rd invalidate core.io.rocc.resp.valid invalidate core.io.rocc.resp.ready invalidate core.io.rocc.cmd.bits.status.uie invalidate core.io.rocc.cmd.bits.status.sie invalidate core.io.rocc.cmd.bits.status.hie invalidate core.io.rocc.cmd.bits.status.mie invalidate core.io.rocc.cmd.bits.status.upie invalidate core.io.rocc.cmd.bits.status.spie invalidate core.io.rocc.cmd.bits.status.ube invalidate core.io.rocc.cmd.bits.status.mpie invalidate core.io.rocc.cmd.bits.status.spp invalidate core.io.rocc.cmd.bits.status.vs invalidate core.io.rocc.cmd.bits.status.mpp invalidate core.io.rocc.cmd.bits.status.fs invalidate core.io.rocc.cmd.bits.status.xs invalidate core.io.rocc.cmd.bits.status.mprv invalidate core.io.rocc.cmd.bits.status.sum invalidate core.io.rocc.cmd.bits.status.mxr invalidate core.io.rocc.cmd.bits.status.tvm invalidate core.io.rocc.cmd.bits.status.tw invalidate core.io.rocc.cmd.bits.status.tsr invalidate core.io.rocc.cmd.bits.status.zero1 invalidate core.io.rocc.cmd.bits.status.sd_rv32 invalidate core.io.rocc.cmd.bits.status.uxl invalidate core.io.rocc.cmd.bits.status.sxl invalidate core.io.rocc.cmd.bits.status.sbe invalidate core.io.rocc.cmd.bits.status.mbe invalidate core.io.rocc.cmd.bits.status.gva invalidate core.io.rocc.cmd.bits.status.mpv invalidate core.io.rocc.cmd.bits.status.zero2 invalidate core.io.rocc.cmd.bits.status.sd invalidate core.io.rocc.cmd.bits.status.v invalidate core.io.rocc.cmd.bits.status.prv invalidate core.io.rocc.cmd.bits.status.dv invalidate core.io.rocc.cmd.bits.status.dprv invalidate core.io.rocc.cmd.bits.status.isa invalidate core.io.rocc.cmd.bits.status.wfi invalidate core.io.rocc.cmd.bits.status.cease invalidate core.io.rocc.cmd.bits.status.debug invalidate core.io.rocc.cmd.bits.rs2 invalidate core.io.rocc.cmd.bits.rs1 invalidate core.io.rocc.cmd.bits.inst.opcode invalidate core.io.rocc.cmd.bits.inst.rd invalidate core.io.rocc.cmd.bits.inst.xs2 invalidate core.io.rocc.cmd.bits.inst.xs1 invalidate core.io.rocc.cmd.bits.inst.xd invalidate core.io.rocc.cmd.bits.inst.rs1 invalidate core.io.rocc.cmd.bits.inst.rs2 invalidate core.io.rocc.cmd.bits.inst.funct invalidate core.io.rocc.cmd.valid invalidate core.io.rocc.cmd.ready inst ptw of PTW connect ptw.clock, clock connect ptw.reset, reset connect core.io.ptw, ptw.io.dpath connect ptw.io.requestor[0], lsu.io.ptw connect ptw.io.requestor[1], frontend.io.ptw connect ptw.io.requestor[2], core.io.ptw_tlb inst hellaCacheArb of HellaCacheArbiter connect hellaCacheArb.clock, clock connect hellaCacheArb.reset, reset connect hellaCacheArb.io.requestor[0], ptw.io.mem connect lsu.io.hellacache, hellaCacheArb.io.mem connect dcache.io.lsu, lsu.io.dmem

module BoomTile( // @[tile.scala:154:7] input clock, // @[tile.scala:154:7] input reset, // @[tile.scala:154:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_custom_rob_empty, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire dCacheTapOut_e_ready; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire dCacheTapOut_c_ready; // @[MixedNode.scala:542:17] wire dCacheTapOut_b_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17] wire [7:0] dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17] wire dCacheTapOut_a_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17] wire [7:0] tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire buffer_3_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_3_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_3_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_c_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_3_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_3_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_3_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _hellaCacheArb_io_requestor_0_req_ready; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_nack; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_resp_valid; // @[tile.scala:242:29] wire [39:0] _hellaCacheArb_io_requestor_0_resp_bits_addr; // @[tile.scala:242:29] wire [1:0] _hellaCacheArb_io_requestor_0_resp_bits_dprv; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_resp_bits_dv; // @[tile.scala:242:29] wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data; // @[tile.scala:242:29] wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[tile.scala:242:29] wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data_raw; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_st; // @[tile.scala:242:29] wire _hellaCacheArb_io_requestor_0_store_pending; // @[tile.scala:242:29] wire _hellaCacheArb_io_mem_req_valid; // @[tile.scala:242:29] wire [39:0] _hellaCacheArb_io_mem_req_bits_addr; // @[tile.scala:242:29] wire _hellaCacheArb_io_mem_req_bits_dv; // @[tile.scala:242:29] wire _hellaCacheArb_io_mem_s1_kill; // @[tile.scala:242:29] wire _ptw_io_requestor_0_req_ready; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_valid; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pf; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_gf; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_hr; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_hw; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_hx; // @[tile.scala:236:20] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[tile.scala:236:20] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[tile.scala:236:20] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[tile.scala:236:20] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_debug; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_cease; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_wfi; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_dv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_prv; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_v; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_sd; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mpv; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_gva; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_tsr; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_tw; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_tvm; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mxr; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_sum; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mprv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_fs; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_spp; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mpie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_spie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_mie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_status_sie; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_req_ready; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_valid; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pf; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_gf; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_hr; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_hw; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_hx; // @[tile.scala:236:20] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[tile.scala:236:20] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[tile.scala:236:20] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[tile.scala:236:20] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_debug; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_cease; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_wfi; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_dv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_prv; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_v; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_sd; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mpv; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_gva; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_tsr; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_tw; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_tvm; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mxr; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_sum; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mprv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_fs; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_spp; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mpie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_spie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_mie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_status_sie; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_req_ready; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_valid; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_ae_final; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pf; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_gf; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_hr; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_hw; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_hx; // @[tile.scala:236:20] wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_d; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_g; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_u; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_r; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_pte_v; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[tile.scala:236:20] wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[tile.scala:236:20] wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[tile.scala:236:20] wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[tile.scala:236:20] wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_debug; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_cease; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_wfi; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_dprv; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_dv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_prv; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_v; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_sd; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mpv; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_gva; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_tsr; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_tw; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_tvm; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mxr; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_sum; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mprv; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_fs; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_status_mpp; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_spp; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mpie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_spie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_mie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_status_sie; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[tile.scala:236:20] wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[tile.scala:236:20] wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[tile.scala:236:20] wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[tile.scala:236:20] wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[tile.scala:236:20] wire _ptw_io_mem_req_valid; // @[tile.scala:236:20] wire [39:0] _ptw_io_mem_req_bits_addr; // @[tile.scala:236:20] wire _ptw_io_mem_req_bits_dv; // @[tile.scala:236:20] wire _ptw_io_mem_s1_kill; // @[tile.scala:236:20] wire _ptw_io_dpath_perf_l2miss; // @[tile.scala:236:20] wire _ptw_io_dpath_perf_l2hit; // @[tile.scala:236:20] wire _ptw_io_dpath_perf_pte_miss; // @[tile.scala:236:20] wire _ptw_io_dpath_clock_enabled; // @[tile.scala:236:20] wire _lsu_io_ptw_req_valid; // @[tile.scala:159:20] wire _lsu_io_ptw_req_bits_valid; // @[tile.scala:159:20] wire [26:0] _lsu_io_ptw_req_bits_bits_addr; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iwakeups_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iwakeups_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_iwakeups_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_iwakeups_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_iwakeups_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iwakeups_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iwakeups_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_iwakeups_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iwakeups_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iwakeups_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iwakeups_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_bypassable; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iwakeups_0_bits_speculative_mask; // @[tile.scala:159:20] wire _lsu_io_core_iwakeups_0_bits_rebusy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iresp_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_iresp_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_iresp_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_iresp_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_iresp_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_iresp_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_iresp_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_iresp_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_iresp_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_iresp_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_iresp_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_iresp_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_iresp_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_iresp_0_bits_data; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_fresp_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_fresp_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_fresp_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_fresp_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_fresp_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_fresp_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_fresp_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_fresp_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_fresp_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_fresp_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_fresp_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_fresp_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_fresp_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_fresp_0_bits_data; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_ldq_idx_0; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_ldq_idx_1; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_stq_idx_0; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_dis_stq_idx_1; // @[tile.scala:159:20] wire _lsu_io_core_ldq_full_0; // @[tile.scala:159:20] wire _lsu_io_core_ldq_full_1; // @[tile.scala:159:20] wire _lsu_io_core_stq_full_0; // @[tile.scala:159:20] wire _lsu_io_core_stq_full_1; // @[tile.scala:159:20] wire _lsu_io_core_clr_bsy_0_valid; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_clr_bsy_0_bits; // @[tile.scala:159:20] wire _lsu_io_core_clr_bsy_1_valid; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_clr_bsy_1_bits; // @[tile.scala:159:20] wire _lsu_io_core_clr_unsafe_0_valid; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_clr_unsafe_0_bits; // @[tile.scala:159:20] wire _lsu_io_core_fencei_rdy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_core_lxcpt_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tile.scala:159:20] wire [39:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tile.scala:159:20] wire _lsu_io_core_perf_acquire; // @[tile.scala:159:20] wire _lsu_io_core_perf_release; // @[tile.scala:159:20] wire _lsu_io_core_perf_tlbMiss; // @[tile.scala:159:20] wire _lsu_io_dmem_req_valid; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_valid; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tile.scala:159:20] wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tile.scala:159:20] wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tile.scala:159:20] wire _lsu_io_dmem_s1_kill_0; // @[tile.scala:159:20] wire _lsu_io_dmem_ll_resp_ready; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_brupdate_b1_resolve_mask; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_brupdate_b1_mispredict_mask; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_brupdate_b2_uop_inst; // @[tile.scala:159:20] wire [31:0] _lsu_io_dmem_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_0; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_1; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_2; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iq_type_3; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_0; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_1; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_2; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_3; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_4; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_5; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_6; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_7; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_8; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fu_code_9; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_issued; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_agen; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_dgen; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_p1_speculative_child; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_p2_speculative_child; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_p1_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_p2_bypass_hint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_iw_p3_bypass_hint; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dis_col_sel; // @[tile.scala:159:20] wire [11:0] _lsu_io_dmem_brupdate_b2_uop_br_mask; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_tag; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_type; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_fence; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_sfence; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_amo; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_eret; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_rocc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_mov; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_taken; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_imm_rename; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_imm_sel; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_pimm; // @[tile.scala:159:20] wire [19:0] _lsu_io_dmem_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_op1_sel; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_op2_sel; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ldst; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wen; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren1; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren2; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren3; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap12; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap23; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fromint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_toint; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fma; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_div; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_sqrt; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wflags; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_ctrl_vec; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20] wire [3:0] _lsu_io_dmem_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_pdst; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs1; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs2; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs3; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ppred; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20] wire [6:0] _lsu_io_dmem_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_exception; // @[tile.scala:159:20] wire [63:0] _lsu_io_dmem_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_mem_size; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_is_unique; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_csr_cmd; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_ldst; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs1; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs2; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs3; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fcn_dw; // @[tile.scala:159:20] wire [4:0] _lsu_io_dmem_brupdate_b2_uop_fcn_op; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_fp_val; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_fp_rm; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_uop_fp_typ; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_mispredict; // @[tile.scala:159:20] wire _lsu_io_dmem_brupdate_b2_taken; // @[tile.scala:159:20] wire [2:0] _lsu_io_dmem_brupdate_b2_cfi_type; // @[tile.scala:159:20] wire [1:0] _lsu_io_dmem_brupdate_b2_pc_sel; // @[tile.scala:159:20] wire [39:0] _lsu_io_dmem_brupdate_b2_jalr_target; // @[tile.scala:159:20] wire [20:0] _lsu_io_dmem_brupdate_b2_target_offset; // @[tile.scala:159:20] wire _lsu_io_dmem_exception; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_rob_pnr_idx; // @[tile.scala:159:20] wire [5:0] _lsu_io_dmem_rob_head_idx; // @[tile.scala:159:20] wire _lsu_io_dmem_release_ready; // @[tile.scala:159:20] wire _lsu_io_dmem_force_order; // @[tile.scala:159:20] wire _lsu_io_hellacache_req_ready; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_nack; // @[tile.scala:159:20] wire _lsu_io_hellacache_resp_valid; // @[tile.scala:159:20] wire [39:0] _lsu_io_hellacache_resp_bits_addr; // @[tile.scala:159:20] wire [1:0] _lsu_io_hellacache_resp_bits_dprv; // @[tile.scala:159:20] wire _lsu_io_hellacache_resp_bits_dv; // @[tile.scala:159:20] wire [63:0] _lsu_io_hellacache_resp_bits_data; // @[tile.scala:159:20] wire [63:0] _lsu_io_hellacache_resp_bits_data_word_bypass; // @[tile.scala:159:20] wire [63:0] _lsu_io_hellacache_resp_bits_data_raw; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ma_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ma_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_pf_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_pf_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_gf_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_gf_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ae_ld; // @[tile.scala:159:20] wire _lsu_io_hellacache_s2_xcpt_ae_st; // @[tile.scala:159:20] wire _lsu_io_hellacache_store_pending; // @[tile.scala:159:20] wire _core_io_ifu_fetchpacket_ready; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_arb_ftq_reqs_0; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_arb_ftq_reqs_1; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_arb_ftq_reqs_2; // @[tile.scala:158:20] wire _core_io_ifu_status_debug; // @[tile.scala:158:20] wire _core_io_ifu_status_cease; // @[tile.scala:158:20] wire _core_io_ifu_status_wfi; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_dprv; // @[tile.scala:158:20] wire _core_io_ifu_status_dv; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_prv; // @[tile.scala:158:20] wire _core_io_ifu_status_v; // @[tile.scala:158:20] wire _core_io_ifu_status_sd; // @[tile.scala:158:20] wire _core_io_ifu_status_mpv; // @[tile.scala:158:20] wire _core_io_ifu_status_gva; // @[tile.scala:158:20] wire _core_io_ifu_status_tsr; // @[tile.scala:158:20] wire _core_io_ifu_status_tw; // @[tile.scala:158:20] wire _core_io_ifu_status_tvm; // @[tile.scala:158:20] wire _core_io_ifu_status_mxr; // @[tile.scala:158:20] wire _core_io_ifu_status_sum; // @[tile.scala:158:20] wire _core_io_ifu_status_mprv; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_fs; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_status_mpp; // @[tile.scala:158:20] wire _core_io_ifu_status_spp; // @[tile.scala:158:20] wire _core_io_ifu_status_mpie; // @[tile.scala:158:20] wire _core_io_ifu_status_spie; // @[tile.scala:158:20] wire _core_io_ifu_status_mie; // @[tile.scala:158:20] wire _core_io_ifu_status_sie; // @[tile.scala:158:20] wire _core_io_ifu_sfence_valid; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_rs1; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_rs2; // @[tile.scala:158:20] wire [38:0] _core_io_ifu_sfence_bits_addr; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_asid; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_hv; // @[tile.scala:158:20] wire _core_io_ifu_sfence_bits_hg; // @[tile.scala:158:20] wire [11:0] _core_io_ifu_brupdate_b1_resolve_mask; // @[tile.scala:158:20] wire [11:0] _core_io_ifu_brupdate_b1_mispredict_mask; // @[tile.scala:158:20] wire [31:0] _core_io_ifu_brupdate_b2_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_ifu_brupdate_b2_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_ifu_brupdate_b2_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_ifu_brupdate_b2_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_br_type; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_fence; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_amo; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_eret; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_taken; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_ifu_brupdate_b2_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_ifu_brupdate_b2_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_ppred; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_ifu_brupdate_b2_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_ifu_brupdate_b2_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_mem_size; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_is_unique; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_brupdate_b2_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_mispredict; // @[tile.scala:158:20] wire _core_io_ifu_brupdate_b2_taken; // @[tile.scala:158:20] wire [2:0] _core_io_ifu_brupdate_b2_cfi_type; // @[tile.scala:158:20] wire [1:0] _core_io_ifu_brupdate_b2_pc_sel; // @[tile.scala:158:20] wire [39:0] _core_io_ifu_brupdate_b2_jalr_target; // @[tile.scala:158:20] wire [20:0] _core_io_ifu_brupdate_b2_target_offset; // @[tile.scala:158:20] wire _core_io_ifu_redirect_flush; // @[tile.scala:158:20] wire _core_io_ifu_redirect_val; // @[tile.scala:158:20] wire [39:0] _core_io_ifu_redirect_pc; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_redirect_ftq_idx; // @[tile.scala:158:20] wire [63:0] _core_io_ifu_redirect_ghist_old_history; // @[tile.scala:158:20] wire _core_io_ifu_redirect_ghist_current_saw_branch_not_taken; // @[tile.scala:158:20] wire _core_io_ifu_redirect_ghist_new_saw_branch_not_taken; // @[tile.scala:158:20] wire _core_io_ifu_redirect_ghist_new_saw_branch_taken; // @[tile.scala:158:20] wire [4:0] _core_io_ifu_redirect_ghist_ras_idx; // @[tile.scala:158:20] wire _core_io_ifu_commit_valid; // @[tile.scala:158:20] wire [31:0] _core_io_ifu_commit_bits; // @[tile.scala:158:20] wire _core_io_ifu_flush_icache; // @[tile.scala:158:20] wire _core_io_ifu_enable_bpd; // @[tile.scala:158:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[tile.scala:158:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[tile.scala:158:20] wire _core_io_ptw_sfence_valid; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_rs1; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_rs2; // @[tile.scala:158:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_asid; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_hv; // @[tile.scala:158:20] wire _core_io_ptw_sfence_bits_hg; // @[tile.scala:158:20] wire _core_io_ptw_status_debug; // @[tile.scala:158:20] wire _core_io_ptw_status_cease; // @[tile.scala:158:20] wire _core_io_ptw_status_wfi; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_dprv; // @[tile.scala:158:20] wire _core_io_ptw_status_dv; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_prv; // @[tile.scala:158:20] wire _core_io_ptw_status_v; // @[tile.scala:158:20] wire _core_io_ptw_status_sd; // @[tile.scala:158:20] wire _core_io_ptw_status_mpv; // @[tile.scala:158:20] wire _core_io_ptw_status_gva; // @[tile.scala:158:20] wire _core_io_ptw_status_tsr; // @[tile.scala:158:20] wire _core_io_ptw_status_tw; // @[tile.scala:158:20] wire _core_io_ptw_status_tvm; // @[tile.scala:158:20] wire _core_io_ptw_status_mxr; // @[tile.scala:158:20] wire _core_io_ptw_status_sum; // @[tile.scala:158:20] wire _core_io_ptw_status_mprv; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_fs; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_status_mpp; // @[tile.scala:158:20] wire _core_io_ptw_status_spp; // @[tile.scala:158:20] wire _core_io_ptw_status_mpie; // @[tile.scala:158:20] wire _core_io_ptw_status_spie; // @[tile.scala:158:20] wire _core_io_ptw_status_mie; // @[tile.scala:158:20] wire _core_io_ptw_status_sie; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_0_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_1_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_2_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_3_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_4_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_5_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_6_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_l; // @[tile.scala:158:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_x; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_w; // @[tile.scala:158:20] wire _core_io_ptw_pmp_7_cfg_r; // @[tile.scala:158:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[tile.scala:158:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_agen_0_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_agen_0_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_agen_0_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_agen_0_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_agen_0_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_agen_0_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_agen_0_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_agen_0_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_agen_0_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_agen_0_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_agen_0_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_agen_0_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_agen_0_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_agen_0_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_0_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_0_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dgen_0_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dgen_0_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dgen_0_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_0_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_0_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_0_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_0_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_0_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_0_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_0_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_0_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_0_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_1_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_1_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dgen_1_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dgen_1_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dgen_1_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_1_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_1_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_1_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_1_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_1_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_1_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_1_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_1_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_1_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_2_bits_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dgen_2_bits_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dgen_2_bits_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dgen_2_bits_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dgen_2_bits_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dgen_2_bits_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dgen_2_bits_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_2_bits_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dgen_2_bits_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dgen_2_bits_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dgen_2_bits_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dgen_2_bits_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dgen_2_bits_uop_debug_tsrc; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dgen_2_bits_data; // @[tile.scala:158:20] wire _core_io_lsu_sfence_valid; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_rs1; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_rs2; // @[tile.scala:158:20] wire [38:0] _core_io_lsu_sfence_bits_addr; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_asid; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_hv; // @[tile.scala:158:20] wire _core_io_lsu_sfence_bits_hg; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_0_bits_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_0_bits_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dis_uops_0_bits_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dis_uops_0_bits_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_taken; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dis_uops_0_bits_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_0_bits_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_0_bits_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dis_uops_0_bits_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_0_bits_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_0_bits_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_0_bits_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_0_bits_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_valid; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_1_bits_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_dis_uops_1_bits_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_dis_uops_1_bits_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_dis_uops_1_bits_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_br_type; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_taken; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_dis_uops_1_bits_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_dis_uops_1_bits_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_ppred; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_dis_uops_1_bits_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_dis_uops_1_bits_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_dis_uops_1_bits_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_dis_uops_1_bits_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_dis_uops_1_bits_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_dis_uops_1_bits_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_commit_valids_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_valids_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_arch_valids_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_arch_valids_1; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_0_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_0_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_commit_uops_0_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_commit_uops_0_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_br_type; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_taken; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_commit_uops_0_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_0_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_ppred; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_0_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_uops_0_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_0_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_0_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_0_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_0_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_0_debug_tsrc; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_1_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_commit_uops_1_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_commit_uops_1_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_commit_uops_1_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_br_type; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_taken; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_commit_uops_1_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_commit_uops_1_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_ppred; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_commit_uops_1_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_uops_1_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_commit_uops_1_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_uops_1_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_commit_uops_1_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_commit_uops_1_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_commit_uops_1_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_commit_fflags_valid; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_commit_fflags_bits; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_debug_wdata_0; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_commit_debug_wdata_1; // @[tile.scala:158:20] wire _core_io_lsu_commit_load_at_rob_head; // @[tile.scala:158:20] wire _core_io_lsu_fence_dmem; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_brupdate_b1_resolve_mask; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_brupdate_b1_mispredict_mask; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_brupdate_b2_uop_inst; // @[tile.scala:158:20] wire [31:0] _core_io_lsu_brupdate_b2_uop_debug_inst; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_rvc; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_brupdate_b2_uop_debug_pc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_0; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_1; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_2; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iq_type_3; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_0; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_1; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_2; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_3; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_4; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_5; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_6; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_7; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_8; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fu_code_9; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_issued; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_issued_partial_agen; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_issued_partial_dgen; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_p1_speculative_child; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_p2_speculative_child; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_p1_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_p2_bypass_hint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_iw_p3_bypass_hint; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_dis_col_sel; // @[tile.scala:158:20] wire [11:0] _core_io_lsu_brupdate_b2_uop_br_mask; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_br_tag; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_br_type; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_sfb; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_fence; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_fencei; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_sfence; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_amo; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_eret; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_rocc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_mov; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_ftq_idx; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_edge_inst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_pc_lob; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_taken; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_imm_rename; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_imm_sel; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_pimm; // @[tile.scala:158:20] wire [19:0] _core_io_lsu_brupdate_b2_uop_imm_packed; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_op1_sel; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_op2_sel; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ldst; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_wen; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ren1; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ren2; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_ren3; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_swap12; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_swap23; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_fromint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_toint; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_fma; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_div; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_sqrt; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_wflags; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_ctrl_vec; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_rob_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_ldq_idx; // @[tile.scala:158:20] wire [3:0] _core_io_lsu_brupdate_b2_uop_stq_idx; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_rxq_idx; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_pdst; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_prs1; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_prs2; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_prs3; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_ppred; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_prs1_busy; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_prs2_busy; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_prs3_busy; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_ppred_busy; // @[tile.scala:158:20] wire [6:0] _core_io_lsu_brupdate_b2_uop_stale_pdst; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_brupdate_b2_uop_exc_cause; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_mem_cmd; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_mem_size; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_mem_signed; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_uses_ldq; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_uses_stq; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_is_unique; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_csr_cmd; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_ldst; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs1; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs2; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs3; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_dst_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_frs3_en; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fcn_dw; // @[tile.scala:158:20] wire [4:0] _core_io_lsu_brupdate_b2_uop_fcn_op; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_fp_val; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_fp_rm; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_uop_fp_typ; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_mispredict; // @[tile.scala:158:20] wire _core_io_lsu_brupdate_b2_taken; // @[tile.scala:158:20] wire [2:0] _core_io_lsu_brupdate_b2_cfi_type; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_brupdate_b2_pc_sel; // @[tile.scala:158:20] wire [39:0] _core_io_lsu_brupdate_b2_jalr_target; // @[tile.scala:158:20] wire [20:0] _core_io_lsu_brupdate_b2_target_offset; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_rob_pnr_idx; // @[tile.scala:158:20] wire [5:0] _core_io_lsu_rob_head_idx; // @[tile.scala:158:20] wire _core_io_lsu_exception; // @[tile.scala:158:20] wire [63:0] _core_io_lsu_tsc_reg; // @[tile.scala:158:20] wire _core_io_lsu_status_debug; // @[tile.scala:158:20] wire _core_io_lsu_status_cease; // @[tile.scala:158:20] wire _core_io_lsu_status_wfi; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_dprv; // @[tile.scala:158:20] wire _core_io_lsu_status_dv; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_prv; // @[tile.scala:158:20] wire _core_io_lsu_status_v; // @[tile.scala:158:20] wire _core_io_lsu_status_sd; // @[tile.scala:158:20] wire _core_io_lsu_status_mpv; // @[tile.scala:158:20] wire _core_io_lsu_status_gva; // @[tile.scala:158:20] wire _core_io_lsu_status_tsr; // @[tile.scala:158:20] wire _core_io_lsu_status_tw; // @[tile.scala:158:20] wire _core_io_lsu_status_tvm; // @[tile.scala:158:20] wire _core_io_lsu_status_mxr; // @[tile.scala:158:20] wire _core_io_lsu_status_sum; // @[tile.scala:158:20] wire _core_io_lsu_status_mprv; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_fs; // @[tile.scala:158:20] wire [1:0] _core_io_lsu_status_mpp; // @[tile.scala:158:20] wire _core_io_lsu_status_spp; // @[tile.scala:158:20] wire _core_io_lsu_status_mpie; // @[tile.scala:158:20] wire _core_io_lsu_status_spie; // @[tile.scala:158:20] wire _core_io_lsu_status_mie; // @[tile.scala:158:20] wire _core_io_lsu_status_sie; // @[tile.scala:158:20] wire _buffer_2_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_2_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_2_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire _buffer_2_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_2_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_2_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_2_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_2_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_2_auto_out_d_ready; // @[Buffer.scala:75:28] wire _frontend_io_cpu_fetchpacket_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_valid; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst; // @[tile.scala:137:28] wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_valid; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst; // @[tile.scala:137:28] wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst; // @[tile.scala:137:28] wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[tile.scala:137:28] wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid; // @[tile.scala:137:28] wire [1:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_type; // @[tile.scala:137:28] wire [3:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_br_mask; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_call; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_ras_top; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_0_entry_ras_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_entry_start_bank; // @[tile.scala:137:28] wire [63:0] _frontend_io_cpu_rrd_ftq_resps_0_ghist_old_history; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_0_ghist_ras_idx; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_0_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid; // @[tile.scala:137:28] wire [1:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_type; // @[tile.scala:137:28] wire [3:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_br_mask; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_call; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_ras_top; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_1_entry_ras_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_1_entry_start_bank; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_1_pc; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_valid; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid; // @[tile.scala:137:28] wire [1:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_taken; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted; // @[tile.scala:137:28] wire [2:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_type; // @[tile.scala:137:28] wire [3:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_br_mask; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_call; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_ras_top; // @[tile.scala:137:28] wire [4:0] _frontend_io_cpu_rrd_ftq_resps_2_entry_ras_idx; // @[tile.scala:137:28] wire _frontend_io_cpu_rrd_ftq_resps_2_entry_start_bank; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_rrd_ftq_resps_2_pc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_com_pc; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_debug_fetch_pc_0; // @[tile.scala:137:28] wire [39:0] _frontend_io_cpu_debug_fetch_pc_1; // @[tile.scala:137:28] wire _frontend_io_cpu_perf_acquire; // @[tile.scala:137:28] wire _frontend_io_cpu_perf_tlbMiss; // @[tile.scala:137:28] wire _frontend_io_ptw_req_valid; // @[tile.scala:137:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[tile.scala:137:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[tile.scala:137:28] wire _dcache_io_lsu_req_ready; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_store_ack_0_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_store_ack_0_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_store_ack_0_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_store_ack_0_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_store_ack_0_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_store_ack_0_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_store_ack_0_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_store_ack_0_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_store_ack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_store_ack_0_bits_addr; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_store_ack_0_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_store_ack_0_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_nack_0_bits_addr; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_valid; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_ll_resp_bits_uop_inst; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_ll_resp_bits_uop_debug_inst; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_rvc; // @[tile.scala:132:54] wire [39:0] _dcache_io_lsu_ll_resp_bits_uop_debug_pc; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_0; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_1; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_2; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iq_type_3; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_0; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_1; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_2; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_3; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_4; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_5; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_6; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_7; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_8; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fu_code_9; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_issued; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_agen; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_iw_p1_speculative_child; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_iw_p2_speculative_child; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_dis_col_sel; // @[tile.scala:132:54] wire [11:0] _dcache_io_lsu_ll_resp_bits_uop_br_mask; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_br_tag; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_br_type; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_sfb; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_fence; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_fencei; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_sfence; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_amo; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_eret; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_rocc; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_mov; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_ftq_idx; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_edge_inst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_pc_lob; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_taken; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_imm_rename; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_imm_sel; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_pimm; // @[tile.scala:132:54] wire [19:0] _dcache_io_lsu_ll_resp_bits_uop_imm_packed; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_op1_sel; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_op2_sel; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ldst; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wen; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren1; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren2; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren3; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap12; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap23; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fromint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_toint; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fma; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_div; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wflags; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_vec; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_rob_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_ldq_idx; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_ll_resp_bits_uop_stq_idx; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_rxq_idx; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_pdst; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_prs1; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_prs2; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_prs3; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_ppred; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_prs1_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_prs2_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_prs3_busy; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_ppred_busy; // @[tile.scala:132:54] wire [6:0] _dcache_io_lsu_ll_resp_bits_uop_stale_pdst; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_exception; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_ll_resp_bits_uop_exc_cause; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_mem_cmd; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_mem_size; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_mem_signed; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_uses_ldq; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_uses_stq; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_is_unique; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_flush_on_commit; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_csr_cmd; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_ldst_is_rs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_ldst; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_lrs1; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_lrs2; // @[tile.scala:132:54] wire [5:0] _dcache_io_lsu_ll_resp_bits_uop_lrs3; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_dst_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_lrs1_rtype; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_lrs2_rtype; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_frs3_en; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fcn_dw; // @[tile.scala:132:54] wire [4:0] _dcache_io_lsu_ll_resp_bits_uop_fcn_op; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_fp_val; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_fp_rm; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_ll_resp_bits_uop_fp_typ; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_xcpt_pf_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_xcpt_ae_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_xcpt_ma_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_bp_debug_if; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_uop_bp_xcpt_if; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_debug_fsrc; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_ll_resp_bits_uop_debug_tsrc; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_ll_resp_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_ll_resp_bits_is_hella; // @[tile.scala:132:54] wire _dcache_io_lsu_release_valid; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tile.scala:132:54] wire [2:0] _dcache_io_lsu_release_bits_param; // @[tile.scala:132:54] wire [3:0] _dcache_io_lsu_release_bits_size; // @[tile.scala:132:54] wire [1:0] _dcache_io_lsu_release_bits_source; // @[tile.scala:132:54] wire [31:0] _dcache_io_lsu_release_bits_address; // @[tile.scala:132:54] wire [63:0] _dcache_io_lsu_release_bits_data; // @[tile.scala:132:54] wire _dcache_io_lsu_ordered; // @[tile.scala:132:54] wire _dcache_io_lsu_perf_acquire; // @[tile.scala:132:54] wire _dcache_io_lsu_perf_release; // @[tile.scala:132:54] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_b_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_b_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_b_bits_size; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_b_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_auto_in_b_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_in_b_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_b_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_c_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_e_ready; // @[Buffer.scala:75:28] wire _tlMasterXbar_auto_anon_in_1_a_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_1_d_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [1:0] _tlMasterXbar_auto_anon_in_1_d_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_in_1_d_bits_size; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_in_1_d_bits_sink; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_bits_denied; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_in_1_d_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_in_1_d_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_a_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_a_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_a_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_out_a_bits_size; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_a_bits_source; // @[HierarchicalElement.scala:55:42] wire [31:0] _tlMasterXbar_auto_anon_out_a_bits_address; // @[HierarchicalElement.scala:55:42] wire [7:0] _tlMasterXbar_auto_anon_out_a_bits_mask; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_out_a_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_a_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_b_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_c_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_c_bits_opcode; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_c_bits_param; // @[HierarchicalElement.scala:55:42] wire [3:0] _tlMasterXbar_auto_anon_out_c_bits_size; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_c_bits_source; // @[HierarchicalElement.scala:55:42] wire [31:0] _tlMasterXbar_auto_anon_out_c_bits_address; // @[HierarchicalElement.scala:55:42] wire [63:0] _tlMasterXbar_auto_anon_out_c_bits_data; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_c_bits_corrupt; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_d_ready; // @[HierarchicalElement.scala:55:42] wire _tlMasterXbar_auto_anon_out_e_valid; // @[HierarchicalElement.scala:55:42] wire [2:0] _tlMasterXbar_auto_anon_out_e_bits_sink; // @[HierarchicalElement.scala:55:42] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tile.scala:154:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tile.scala:154:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tile.scala:154:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tile.scala:154:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tile.scala:154:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tile.scala:154:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tile.scala:154:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tile.scala:154:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tile.scala:154:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tile.scala:154:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tile.scala:154:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tile.scala:154:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[tile.scala:154:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[tile.scala:154:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[tile.scala:154:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[tile.scala:154:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tile.scala:154:7] wire auto_hartid_in_0 = auto_hartid_in; // @[tile.scala:154:7] wire auto_wfi_out_0 = 1'h0; // @[tile.scala:154:7] wire auto_cease_out_0 = 1'h0; // @[tile.scala:154:7] wire auto_halt_out_0 = 1'h0; // @[tile.scala:154:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tile.scala:154:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_1_valid = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_1_exception = 1'h0; // @[tile.scala:154:7] wire auto_trace_source_out_insns_1_interrupt = 1'h0; // @[tile.scala:154:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] reset_vectorOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [31:0] reset_vectorIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17] wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] auto_trace_source_out_insns_1_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] traceSourceNodeOut_insns_1_cause = 64'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_trace_source_out_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] traceSourceNodeOut_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9] wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tile.scala:154:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tile.scala:154:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tile.scala:154:7] wire [31:0] auto_trace_source_out_insns_1_insn = 32'h0; // @[tile.scala:154:7] wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire buffer_3_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_3_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_3_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_3_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_3_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_3_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_3_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_3_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[MixedNode.scala:551:17] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[MixedNode.scala:551:17] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_a_bits_source_0; // @[tile.scala:154:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[tile.scala:154:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[tile.scala:154:7] wire auto_buffer_out_a_bits_corrupt_0; // @[tile.scala:154:7] wire auto_buffer_out_a_valid_0; // @[tile.scala:154:7] wire auto_buffer_out_b_ready_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[tile.scala:154:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_c_bits_source_0; // @[tile.scala:154:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[tile.scala:154:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[tile.scala:154:7] wire auto_buffer_out_c_bits_corrupt_0; // @[tile.scala:154:7] wire auto_buffer_out_c_valid_0; // @[tile.scala:154:7] wire auto_buffer_out_d_ready_0; // @[tile.scala:154:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[tile.scala:154:7] wire auto_buffer_out_e_valid_0; // @[tile.scala:154:7] wire auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:154:7] wire [63:0] auto_trace_source_out_time_0; // @[tile.scala:154:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_source = widget_1_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_source = widget_1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_source = widget_1_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_3_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_a_ready = buffer_3_auto_in_a_ready; // @[Buffer.scala:40:9] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_a_valid = buffer_3_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_a_bits_opcode = buffer_3_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_a_bits_param = buffer_3_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_3_nodeIn_a_bits_size = buffer_3_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_a_bits_source = buffer_3_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_3_nodeIn_a_bits_address = buffer_3_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_3_nodeIn_a_bits_mask = buffer_3_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_3_nodeIn_a_bits_data = buffer_3_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_a_bits_corrupt = buffer_3_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_b_ready = buffer_3_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_3_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_b_valid = buffer_3_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_b_bits_opcode = buffer_3_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_b_bits_param = buffer_3_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_b_bits_size = buffer_3_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_b_bits_source = buffer_3_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_3_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] masterNodeOut_b_bits_address = buffer_3_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] masterNodeOut_b_bits_mask = buffer_3_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_b_bits_data = buffer_3_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_b_bits_corrupt = buffer_3_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_c_ready = buffer_3_auto_in_c_ready; // @[Buffer.scala:40:9] wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_c_valid = buffer_3_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_c_bits_opcode = buffer_3_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_c_bits_param = buffer_3_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_3_nodeIn_c_bits_size = buffer_3_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_c_bits_source = buffer_3_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_3_nodeIn_c_bits_address = buffer_3_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_3_nodeIn_c_bits_data = buffer_3_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_c_bits_corrupt = buffer_3_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_d_ready = buffer_3_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_3_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_d_valid = buffer_3_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_opcode = buffer_3_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_d_bits_param = buffer_3_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_d_bits_size = buffer_3_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_source = buffer_3_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_sink = buffer_3_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_denied = buffer_3_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_d_bits_data = buffer_3_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_corrupt = buffer_3_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_e_ready = buffer_3_auto_in_e_ready; // @[Buffer.scala:40:9] wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_3_nodeIn_e_valid = buffer_3_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_3_nodeIn_e_bits_sink = buffer_3_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_a_ready = buffer_3_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_3_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_3_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_3_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_3_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_3_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_3_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_3_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_3_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_3_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_corrupt_0 = buffer_3_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_3_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_b_valid = buffer_3_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_b_bits_opcode = buffer_3_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeOut_b_bits_param = buffer_3_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_b_bits_size = buffer_3_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_b_bits_source = buffer_3_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeOut_b_bits_address = buffer_3_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_3_nodeOut_b_bits_mask = buffer_3_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_b_bits_data = buffer_3_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_b_bits_corrupt = buffer_3_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_c_ready = buffer_3_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_3_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_3_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_3_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_3_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_3_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_3_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_3_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_3_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_corrupt_0 = buffer_3_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_3_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_valid = buffer_3_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_d_bits_opcode = buffer_3_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_3_nodeOut_d_bits_param = buffer_3_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_3_nodeOut_d_bits_size = buffer_3_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_d_bits_source = buffer_3_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_d_bits_sink = buffer_3_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_bits_denied = buffer_3_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_3_nodeOut_d_bits_data = buffer_3_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_d_bits_corrupt = buffer_3_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_e_ready = buffer_3_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_3_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_3_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_3_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_3_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_3_nodeIn_a_ready = buffer_3_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_out_a_valid = buffer_3_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_opcode = buffer_3_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_param = buffer_3_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_size = buffer_3_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_source = buffer_3_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_address = buffer_3_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_mask = buffer_3_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_data = buffer_3_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_out_a_bits_corrupt = buffer_3_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_out_b_ready = buffer_3_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeIn_b_valid = buffer_3_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_opcode = buffer_3_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_param = buffer_3_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_size = buffer_3_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_source = buffer_3_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_address = buffer_3_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_mask = buffer_3_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_data = buffer_3_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_b_bits_corrupt = buffer_3_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_c_ready = buffer_3_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_out_c_valid = buffer_3_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_opcode = buffer_3_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_param = buffer_3_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_size = buffer_3_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_source = buffer_3_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_address = buffer_3_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_data = buffer_3_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_out_c_bits_corrupt = buffer_3_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_out_d_ready = buffer_3_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeIn_d_valid = buffer_3_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_opcode = buffer_3_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_param = buffer_3_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_size = buffer_3_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_source = buffer_3_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_sink = buffer_3_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_denied = buffer_3_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_data = buffer_3_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_d_bits_corrupt = buffer_3_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeIn_e_ready = buffer_3_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_out_e_valid = buffer_3_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_out_e_bits_sink = buffer_3_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_ready = buffer_3_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeOut_a_valid = buffer_3_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_opcode = buffer_3_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_param = buffer_3_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_size = buffer_3_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_source = buffer_3_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_address = buffer_3_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_mask = buffer_3_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_data = buffer_3_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_a_bits_corrupt = buffer_3_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_b_ready = buffer_3_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_b_valid = buffer_3_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_opcode = buffer_3_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_param = buffer_3_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_size = buffer_3_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_source = buffer_3_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_address = buffer_3_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_mask = buffer_3_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_data = buffer_3_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_bits_corrupt = buffer_3_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_ready = buffer_3_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeOut_c_valid = buffer_3_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_opcode = buffer_3_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_param = buffer_3_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_size = buffer_3_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_source = buffer_3_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_address = buffer_3_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_data = buffer_3_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_c_bits_corrupt = buffer_3_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_d_ready = buffer_3_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_d_valid = buffer_3_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_opcode = buffer_3_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_param = buffer_3_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_size = buffer_3_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_source = buffer_3_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_sink = buffer_3_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_denied = buffer_3_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_data = buffer_3_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_bits_corrupt = buffer_3_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_e_ready = buffer_3_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_3_nodeOut_e_valid = buffer_3_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_nodeOut_e_bits_sink = buffer_3_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeIn_a_valid = tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeIn_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] masterNodeIn_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] masterNodeIn_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeIn_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] wire masterNodeIn_a_bits_corrupt = tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_ready = tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_valid; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] masterNodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] masterNodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [7:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeIn_c_valid = tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeIn_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] wire [2:0] masterNodeIn_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] wire [31:0] masterNodeIn_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeIn_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] wire masterNodeIn_c_bits_corrupt = tlOtherMastersNodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_ready = tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_valid; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] wire masterNodeIn_e_valid = tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_corrupt = tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_corrupt = tlOtherMastersNodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[MixedNode.scala:542:17] assign auto_trace_source_out_custom_rob_empty_0 = traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_a_bits_corrupt = masterNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9] assign masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_3_auto_in_c_bits_corrupt = masterNodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_3_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9] assign masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_3_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_3_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_ready = masterNodeIn_a_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_corrupt = masterNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_valid = masterNodeIn_b_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_opcode = masterNodeIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_param = masterNodeIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_size = masterNodeIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_source = masterNodeIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_address = masterNodeIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_mask = masterNodeIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_data = masterNodeIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_bits_corrupt = masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_ready = masterNodeIn_c_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_corrupt = masterNodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_valid = masterNodeIn_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_opcode = masterNodeIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_param = masterNodeIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_size = masterNodeIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_source = masterNodeIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_sink = masterNodeIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_denied = masterNodeIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_data = masterNodeIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_bits_corrupt = masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_ready = masterNodeIn_e_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_a_ready = dCacheTapOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_a_valid; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] dCacheTapIn_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] dCacheTapIn_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dCacheTapIn_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] dCacheTapIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] dCacheTapIn_a_bits_data; // @[MixedNode.scala:551:17] wire dCacheTapIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire dCacheTapIn_b_ready; // @[MixedNode.scala:551:17] wire dCacheTapIn_b_valid = dCacheTapOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] dCacheTapIn_b_bits_opcode = dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_b_bits_param = dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] dCacheTapIn_b_bits_size = dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_b_bits_source = dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] dCacheTapIn_b_bits_address = dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] dCacheTapIn_b_bits_mask = dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] dCacheTapIn_b_bits_data = dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_b_bits_corrupt = dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_c_ready = dCacheTapOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_c_valid; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] dCacheTapIn_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] dCacheTapIn_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dCacheTapIn_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] dCacheTapIn_c_bits_data; // @[MixedNode.scala:551:17] wire dCacheTapIn_c_bits_corrupt; // @[MixedNode.scala:551:17] wire dCacheTapIn_d_ready; // @[MixedNode.scala:551:17] wire dCacheTapIn_d_valid = dCacheTapOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] dCacheTapIn_d_bits_opcode = dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_d_bits_param = dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] dCacheTapIn_d_bits_size = dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dCacheTapIn_d_bits_source = dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] dCacheTapIn_d_bits_sink = dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_d_bits_denied = dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] dCacheTapIn_d_bits_data = dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_d_bits_corrupt = dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_e_ready = dCacheTapOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire dCacheTapIn_e_valid; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapIn_e_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] dCacheTapOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] dCacheTapOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] dCacheTapOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_a_bits_data; // @[MixedNode.scala:542:17] wire dCacheTapOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire dCacheTapOut_a_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_b_ready; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] dCacheTapOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] dCacheTapOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] dCacheTapOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] dCacheTapOut_c_bits_data; // @[MixedNode.scala:542:17] wire dCacheTapOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire dCacheTapOut_c_valid; // @[MixedNode.scala:542:17] wire dCacheTapOut_d_ready; // @[MixedNode.scala:542:17] wire [2:0] dCacheTapOut_e_bits_sink; // @[MixedNode.scala:542:17] wire dCacheTapOut_e_valid; // @[MixedNode.scala:542:17] assign dCacheTapOut_a_valid = dCacheTapIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_opcode = dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_param = dCacheTapIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_size = dCacheTapIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_source = dCacheTapIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_address = dCacheTapIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_mask = dCacheTapIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_data = dCacheTapIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_a_bits_corrupt = dCacheTapIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_b_ready = dCacheTapIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_valid = dCacheTapIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_opcode = dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_param = dCacheTapIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_size = dCacheTapIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_source = dCacheTapIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_address = dCacheTapIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_data = dCacheTapIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_c_bits_corrupt = dCacheTapIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_d_ready = dCacheTapIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_e_valid = dCacheTapIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign dCacheTapOut_e_bits_sink = dCacheTapIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (_tlMasterXbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_buffer_2_auto_out_a_valid), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_opcode (_buffer_2_auto_out_a_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_param (_buffer_2_auto_out_a_bits_param), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_size (_buffer_2_auto_out_a_bits_size), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_source (_buffer_2_auto_out_a_bits_source), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_address (_buffer_2_auto_out_a_bits_address), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_mask (_buffer_2_auto_out_a_bits_mask), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_data (_buffer_2_auto_out_a_bits_data), // @[Buffer.scala:75:28] .auto_anon_in_1_a_bits_corrupt (_buffer_2_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_in_1_d_ready (_buffer_2_auto_out_d_ready), // @[Buffer.scala:75:28] .auto_anon_in_1_d_valid (_tlMasterXbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_tlMasterXbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_tlMasterXbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_tlMasterXbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_sink (_tlMasterXbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_tlMasterXbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_tlMasterXbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_tlMasterXbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (dCacheTapOut_a_ready), .auto_anon_in_0_a_valid (dCacheTapOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_opcode (dCacheTapOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_param (dCacheTapOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_size (dCacheTapOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_source (dCacheTapOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_address (dCacheTapOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_mask (dCacheTapOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_data (dCacheTapOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_corrupt (dCacheTapOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_0_b_ready (dCacheTapOut_b_ready), // @[MixedNode.scala:542:17] .auto_anon_in_0_b_valid (dCacheTapOut_b_valid), .auto_anon_in_0_b_bits_opcode (dCacheTapOut_b_bits_opcode), .auto_anon_in_0_b_bits_param (dCacheTapOut_b_bits_param), .auto_anon_in_0_b_bits_size (dCacheTapOut_b_bits_size), .auto_anon_in_0_b_bits_source (dCacheTapOut_b_bits_source), .auto_anon_in_0_b_bits_address (dCacheTapOut_b_bits_address), .auto_anon_in_0_b_bits_mask (dCacheTapOut_b_bits_mask), .auto_anon_in_0_b_bits_data (dCacheTapOut_b_bits_data), .auto_anon_in_0_b_bits_corrupt (dCacheTapOut_b_bits_corrupt), .auto_anon_in_0_c_ready (dCacheTapOut_c_ready), .auto_anon_in_0_c_valid (dCacheTapOut_c_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_opcode (dCacheTapOut_c_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_param (dCacheTapOut_c_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_size (dCacheTapOut_c_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_source (dCacheTapOut_c_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_address (dCacheTapOut_c_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_data (dCacheTapOut_c_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_0_c_bits_corrupt (dCacheTapOut_c_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_0_d_ready (dCacheTapOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_0_d_valid (dCacheTapOut_d_valid), .auto_anon_in_0_d_bits_opcode (dCacheTapOut_d_bits_opcode), .auto_anon_in_0_d_bits_param (dCacheTapOut_d_bits_param), .auto_anon_in_0_d_bits_size (dCacheTapOut_d_bits_size), .auto_anon_in_0_d_bits_source (dCacheTapOut_d_bits_source), .auto_anon_in_0_d_bits_sink (dCacheTapOut_d_bits_sink), .auto_anon_in_0_d_bits_denied (dCacheTapOut_d_bits_denied), .auto_anon_in_0_d_bits_data (dCacheTapOut_d_bits_data), .auto_anon_in_0_d_bits_corrupt (dCacheTapOut_d_bits_corrupt), .auto_anon_in_0_e_ready (dCacheTapOut_e_ready), .auto_anon_in_0_e_valid (dCacheTapOut_e_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_e_bits_sink (dCacheTapOut_e_bits_sink), // @[MixedNode.scala:542:17] .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_tlMasterXbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_tlMasterXbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_tlMasterXbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_tlMasterXbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_tlMasterXbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_tlMasterXbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_tlMasterXbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_tlMasterXbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_tlMasterXbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_b_ready (_tlMasterXbar_auto_anon_out_b_ready), .auto_anon_out_b_valid (_buffer_auto_in_b_valid), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_opcode (_buffer_auto_in_b_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_param (_buffer_auto_in_b_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_size (_buffer_auto_in_b_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_source (_buffer_auto_in_b_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_address (_buffer_auto_in_b_bits_address), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_mask (_buffer_auto_in_b_bits_mask), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_data (_buffer_auto_in_b_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_out_c_ready (_buffer_auto_in_c_ready), // @[Buffer.scala:75:28] .auto_anon_out_c_valid (_tlMasterXbar_auto_anon_out_c_valid), .auto_anon_out_c_bits_opcode (_tlMasterXbar_auto_anon_out_c_bits_opcode), .auto_anon_out_c_bits_param (_tlMasterXbar_auto_anon_out_c_bits_param), .auto_anon_out_c_bits_size (_tlMasterXbar_auto_anon_out_c_bits_size), .auto_anon_out_c_bits_source (_tlMasterXbar_auto_anon_out_c_bits_source), .auto_anon_out_c_bits_address (_tlMasterXbar_auto_anon_out_c_bits_address), .auto_anon_out_c_bits_data (_tlMasterXbar_auto_anon_out_c_bits_data), .auto_anon_out_c_bits_corrupt (_tlMasterXbar_auto_anon_out_c_bits_corrupt), .auto_anon_out_d_ready (_tlMasterXbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_out_e_ready (_buffer_auto_in_e_ready), // @[Buffer.scala:75:28] .auto_anon_out_e_valid (_tlMasterXbar_auto_anon_out_e_valid), .auto_anon_out_e_bits_sink (_tlMasterXbar_auto_anon_out_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] TLBuffer_a32d64s3k3z4c buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_tlMasterXbar_auto_anon_out_a_valid), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_opcode (_tlMasterXbar_auto_anon_out_a_bits_opcode), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_param (_tlMasterXbar_auto_anon_out_a_bits_param), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_size (_tlMasterXbar_auto_anon_out_a_bits_size), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_source (_tlMasterXbar_auto_anon_out_a_bits_source), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_address (_tlMasterXbar_auto_anon_out_a_bits_address), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_mask (_tlMasterXbar_auto_anon_out_a_bits_mask), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_data (_tlMasterXbar_auto_anon_out_a_bits_data), // @[HierarchicalElement.scala:55:42] .auto_in_a_bits_corrupt (_tlMasterXbar_auto_anon_out_a_bits_corrupt), // @[HierarchicalElement.scala:55:42] .auto_in_b_ready (_tlMasterXbar_auto_anon_out_b_ready), // @[HierarchicalElement.scala:55:42] .auto_in_b_valid (_buffer_auto_in_b_valid), .auto_in_b_bits_opcode (_buffer_auto_in_b_bits_opcode), .auto_in_b_bits_param (_buffer_auto_in_b_bits_param), .auto_in_b_bits_size (_buffer_auto_in_b_bits_size), .auto_in_b_bits_source (_buffer_auto_in_b_bits_source), .auto_in_b_bits_address (_buffer_auto_in_b_bits_address), .auto_in_b_bits_mask (_buffer_auto_in_b_bits_mask), .auto_in_b_bits_data (_buffer_auto_in_b_bits_data), .auto_in_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), .auto_in_c_ready (_buffer_auto_in_c_ready), .auto_in_c_valid (_tlMasterXbar_auto_anon_out_c_valid), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_opcode (_tlMasterXbar_auto_anon_out_c_bits_opcode), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_param (_tlMasterXbar_auto_anon_out_c_bits_param), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_size (_tlMasterXbar_auto_anon_out_c_bits_size), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_source (_tlMasterXbar_auto_anon_out_c_bits_source), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_address (_tlMasterXbar_auto_anon_out_c_bits_address), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_data (_tlMasterXbar_auto_anon_out_c_bits_data), // @[HierarchicalElement.scala:55:42] .auto_in_c_bits_corrupt (_tlMasterXbar_auto_anon_out_c_bits_corrupt), // @[HierarchicalElement.scala:55:42] .auto_in_d_ready (_tlMasterXbar_auto_anon_out_d_ready), // @[HierarchicalElement.scala:55:42] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_in_e_ready (_buffer_auto_in_e_ready), .auto_in_e_valid (_tlMasterXbar_auto_anon_out_e_valid), // @[HierarchicalElement.scala:55:42] .auto_in_e_bits_sink (_tlMasterXbar_auto_anon_out_e_bits_sink), // @[HierarchicalElement.scala:55:42] .auto_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_out_a_bits_corrupt (tlOtherMastersNodeIn_a_bits_corrupt), .auto_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_out_c_bits_corrupt (tlOtherMastersNodeIn_c_bits_corrupt), .auto_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[Buffer.scala:75:28] TLBuffer_a32d64s2k3z4c buffer_1 ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (widget_auto_anon_out_a_ready), .auto_in_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_in_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_in_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_in_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_in_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_in_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_in_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_in_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_in_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_in_b_valid (widget_auto_anon_out_b_valid), .auto_in_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_in_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_in_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_in_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_in_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_in_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_in_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_in_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_in_c_ready (widget_auto_anon_out_c_ready), .auto_in_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_in_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_in_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_in_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_in_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_in_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_in_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_in_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_in_d_valid (widget_auto_anon_out_d_valid), .auto_in_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_in_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_in_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_in_e_ready (widget_auto_anon_out_e_ready), .auto_in_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_in_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_a_ready (dCacheTapIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (dCacheTapIn_a_valid), .auto_out_a_bits_opcode (dCacheTapIn_a_bits_opcode), .auto_out_a_bits_param (dCacheTapIn_a_bits_param), .auto_out_a_bits_size (dCacheTapIn_a_bits_size), .auto_out_a_bits_source (dCacheTapIn_a_bits_source), .auto_out_a_bits_address (dCacheTapIn_a_bits_address), .auto_out_a_bits_mask (dCacheTapIn_a_bits_mask), .auto_out_a_bits_data (dCacheTapIn_a_bits_data), .auto_out_a_bits_corrupt (dCacheTapIn_a_bits_corrupt), .auto_out_b_ready (dCacheTapIn_b_ready), .auto_out_b_valid (dCacheTapIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_opcode (dCacheTapIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (dCacheTapIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_size (dCacheTapIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (dCacheTapIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (dCacheTapIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_b_bits_mask (dCacheTapIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_out_b_bits_data (dCacheTapIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_out_b_bits_corrupt (dCacheTapIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_c_ready (dCacheTapIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (dCacheTapIn_c_valid), .auto_out_c_bits_opcode (dCacheTapIn_c_bits_opcode), .auto_out_c_bits_param (dCacheTapIn_c_bits_param), .auto_out_c_bits_size (dCacheTapIn_c_bits_size), .auto_out_c_bits_source (dCacheTapIn_c_bits_source), .auto_out_c_bits_address (dCacheTapIn_c_bits_address), .auto_out_c_bits_data (dCacheTapIn_c_bits_data), .auto_out_c_bits_corrupt (dCacheTapIn_c_bits_corrupt), .auto_out_d_ready (dCacheTapIn_d_ready), .auto_out_d_valid (dCacheTapIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (dCacheTapIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (dCacheTapIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (dCacheTapIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (dCacheTapIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (dCacheTapIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (dCacheTapIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (dCacheTapIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (dCacheTapIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (dCacheTapIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (dCacheTapIn_e_valid), .auto_out_e_bits_sink (dCacheTapIn_e_bits_sink) ); // @[Buffer.scala:75:28] BoomNonBlockingDCache dcache ( // @[tile.scala:132:54] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_lsu_req_ready (_dcache_io_lsu_req_ready), .io_lsu_req_valid (_lsu_io_dmem_req_valid), // @[tile.scala:159:20] .io_lsu_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_0 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_1 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_2 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iq_type_3 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_0 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_1 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_2 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_3 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_4 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_5 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_6 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_7 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_8 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fu_code_9 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_issued (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_dis_col_sel (_lsu_io_dmem_req_bits_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_br_type (_lsu_io_dmem_req_bits_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_sfence (_lsu_io_dmem_req_bits_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_eret (_lsu_io_dmem_req_bits_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_rocc (_lsu_io_dmem_req_bits_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_mov (_lsu_io_dmem_req_bits_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_imm_rename (_lsu_io_dmem_req_bits_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_pimm (_lsu_io_dmem_req_bits_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_wen (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_toint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_fma (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_div (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_ctrl_vec (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fcn_op (_lsu_io_dmem_req_bits_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_rm (_lsu_io_dmem_req_bits_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_fp_typ (_lsu_io_dmem_req_bits_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), // @[tile.scala:159:20] .io_lsu_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), // @[tile.scala:159:20] .io_lsu_s1_kill_0 (_lsu_io_dmem_s1_kill_0), // @[tile.scala:159:20] .io_lsu_resp_0_valid (_dcache_io_lsu_resp_0_valid), .io_lsu_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), .io_lsu_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), .io_lsu_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), .io_lsu_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), .io_lsu_resp_0_bits_uop_iq_type_0 (_dcache_io_lsu_resp_0_bits_uop_iq_type_0), .io_lsu_resp_0_bits_uop_iq_type_1 (_dcache_io_lsu_resp_0_bits_uop_iq_type_1), .io_lsu_resp_0_bits_uop_iq_type_2 (_dcache_io_lsu_resp_0_bits_uop_iq_type_2), .io_lsu_resp_0_bits_uop_iq_type_3 (_dcache_io_lsu_resp_0_bits_uop_iq_type_3), .io_lsu_resp_0_bits_uop_fu_code_0 (_dcache_io_lsu_resp_0_bits_uop_fu_code_0), .io_lsu_resp_0_bits_uop_fu_code_1 (_dcache_io_lsu_resp_0_bits_uop_fu_code_1), .io_lsu_resp_0_bits_uop_fu_code_2 (_dcache_io_lsu_resp_0_bits_uop_fu_code_2), .io_lsu_resp_0_bits_uop_fu_code_3 (_dcache_io_lsu_resp_0_bits_uop_fu_code_3), .io_lsu_resp_0_bits_uop_fu_code_4 (_dcache_io_lsu_resp_0_bits_uop_fu_code_4), .io_lsu_resp_0_bits_uop_fu_code_5 (_dcache_io_lsu_resp_0_bits_uop_fu_code_5), .io_lsu_resp_0_bits_uop_fu_code_6 (_dcache_io_lsu_resp_0_bits_uop_fu_code_6), .io_lsu_resp_0_bits_uop_fu_code_7 (_dcache_io_lsu_resp_0_bits_uop_fu_code_7), .io_lsu_resp_0_bits_uop_fu_code_8 (_dcache_io_lsu_resp_0_bits_uop_fu_code_8), .io_lsu_resp_0_bits_uop_fu_code_9 (_dcache_io_lsu_resp_0_bits_uop_fu_code_9), .io_lsu_resp_0_bits_uop_iw_issued (_dcache_io_lsu_resp_0_bits_uop_iw_issued), .io_lsu_resp_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_agen), .io_lsu_resp_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_dgen), .io_lsu_resp_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p1_speculative_child), .io_lsu_resp_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p2_speculative_child), .io_lsu_resp_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p1_bypass_hint), .io_lsu_resp_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p2_bypass_hint), .io_lsu_resp_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p3_bypass_hint), .io_lsu_resp_0_bits_uop_dis_col_sel (_dcache_io_lsu_resp_0_bits_uop_dis_col_sel), .io_lsu_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), .io_lsu_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), .io_lsu_resp_0_bits_uop_br_type (_dcache_io_lsu_resp_0_bits_uop_br_type), .io_lsu_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), .io_lsu_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), .io_lsu_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), .io_lsu_resp_0_bits_uop_is_sfence (_dcache_io_lsu_resp_0_bits_uop_is_sfence), .io_lsu_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), .io_lsu_resp_0_bits_uop_is_eret (_dcache_io_lsu_resp_0_bits_uop_is_eret), .io_lsu_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), .io_lsu_resp_0_bits_uop_is_rocc (_dcache_io_lsu_resp_0_bits_uop_is_rocc), .io_lsu_resp_0_bits_uop_is_mov (_dcache_io_lsu_resp_0_bits_uop_is_mov), .io_lsu_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), .io_lsu_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), .io_lsu_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), .io_lsu_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), .io_lsu_resp_0_bits_uop_imm_rename (_dcache_io_lsu_resp_0_bits_uop_imm_rename), .io_lsu_resp_0_bits_uop_imm_sel (_dcache_io_lsu_resp_0_bits_uop_imm_sel), .io_lsu_resp_0_bits_uop_pimm (_dcache_io_lsu_resp_0_bits_uop_pimm), .io_lsu_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), .io_lsu_resp_0_bits_uop_op1_sel (_dcache_io_lsu_resp_0_bits_uop_op1_sel), .io_lsu_resp_0_bits_uop_op2_sel (_dcache_io_lsu_resp_0_bits_uop_op2_sel), .io_lsu_resp_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ldst), .io_lsu_resp_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wen), .io_lsu_resp_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren1), .io_lsu_resp_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren2), .io_lsu_resp_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren3), .io_lsu_resp_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap12), .io_lsu_resp_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap23), .io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_resp_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fromint), .io_lsu_resp_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_toint), .io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_resp_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fma), .io_lsu_resp_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_div), .io_lsu_resp_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_sqrt), .io_lsu_resp_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wflags), .io_lsu_resp_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_vec), .io_lsu_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), .io_lsu_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), .io_lsu_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), .io_lsu_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), .io_lsu_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), .io_lsu_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), .io_lsu_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), .io_lsu_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), .io_lsu_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), .io_lsu_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), .io_lsu_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), .io_lsu_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), .io_lsu_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), .io_lsu_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), .io_lsu_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), .io_lsu_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), .io_lsu_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), .io_lsu_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), .io_lsu_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), .io_lsu_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), .io_lsu_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), .io_lsu_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), .io_lsu_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), .io_lsu_resp_0_bits_uop_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_csr_cmd), .io_lsu_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), .io_lsu_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), .io_lsu_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), .io_lsu_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), .io_lsu_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), .io_lsu_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), .io_lsu_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), .io_lsu_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), .io_lsu_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), .io_lsu_resp_0_bits_uop_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_fcn_dw), .io_lsu_resp_0_bits_uop_fcn_op (_dcache_io_lsu_resp_0_bits_uop_fcn_op), .io_lsu_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), .io_lsu_resp_0_bits_uop_fp_rm (_dcache_io_lsu_resp_0_bits_uop_fp_rm), .io_lsu_resp_0_bits_uop_fp_typ (_dcache_io_lsu_resp_0_bits_uop_fp_typ), .io_lsu_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), .io_lsu_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), .io_lsu_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), .io_lsu_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), .io_lsu_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), .io_lsu_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), .io_lsu_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), .io_lsu_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), .io_lsu_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), .io_lsu_store_ack_0_valid (_dcache_io_lsu_store_ack_0_valid), .io_lsu_store_ack_0_bits_uop_inst (_dcache_io_lsu_store_ack_0_bits_uop_inst), .io_lsu_store_ack_0_bits_uop_debug_inst (_dcache_io_lsu_store_ack_0_bits_uop_debug_inst), .io_lsu_store_ack_0_bits_uop_is_rvc (_dcache_io_lsu_store_ack_0_bits_uop_is_rvc), .io_lsu_store_ack_0_bits_uop_debug_pc (_dcache_io_lsu_store_ack_0_bits_uop_debug_pc), .io_lsu_store_ack_0_bits_uop_iq_type_0 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_0), .io_lsu_store_ack_0_bits_uop_iq_type_1 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_1), .io_lsu_store_ack_0_bits_uop_iq_type_2 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_2), .io_lsu_store_ack_0_bits_uop_iq_type_3 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_3), .io_lsu_store_ack_0_bits_uop_fu_code_0 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_0), .io_lsu_store_ack_0_bits_uop_fu_code_1 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_1), .io_lsu_store_ack_0_bits_uop_fu_code_2 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_2), .io_lsu_store_ack_0_bits_uop_fu_code_3 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_3), .io_lsu_store_ack_0_bits_uop_fu_code_4 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_4), .io_lsu_store_ack_0_bits_uop_fu_code_5 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_5), .io_lsu_store_ack_0_bits_uop_fu_code_6 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_6), .io_lsu_store_ack_0_bits_uop_fu_code_7 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_7), .io_lsu_store_ack_0_bits_uop_fu_code_8 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_8), .io_lsu_store_ack_0_bits_uop_fu_code_9 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_9), .io_lsu_store_ack_0_bits_uop_iw_issued (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued), .io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen), .io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen), .io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child), .io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child), .io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint), .io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint), .io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint), .io_lsu_store_ack_0_bits_uop_dis_col_sel (_dcache_io_lsu_store_ack_0_bits_uop_dis_col_sel), .io_lsu_store_ack_0_bits_uop_br_mask (_dcache_io_lsu_store_ack_0_bits_uop_br_mask), .io_lsu_store_ack_0_bits_uop_br_tag (_dcache_io_lsu_store_ack_0_bits_uop_br_tag), .io_lsu_store_ack_0_bits_uop_br_type (_dcache_io_lsu_store_ack_0_bits_uop_br_type), .io_lsu_store_ack_0_bits_uop_is_sfb (_dcache_io_lsu_store_ack_0_bits_uop_is_sfb), .io_lsu_store_ack_0_bits_uop_is_fence (_dcache_io_lsu_store_ack_0_bits_uop_is_fence), .io_lsu_store_ack_0_bits_uop_is_fencei (_dcache_io_lsu_store_ack_0_bits_uop_is_fencei), .io_lsu_store_ack_0_bits_uop_is_sfence (_dcache_io_lsu_store_ack_0_bits_uop_is_sfence), .io_lsu_store_ack_0_bits_uop_is_amo (_dcache_io_lsu_store_ack_0_bits_uop_is_amo), .io_lsu_store_ack_0_bits_uop_is_eret (_dcache_io_lsu_store_ack_0_bits_uop_is_eret), .io_lsu_store_ack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_store_ack_0_bits_uop_is_sys_pc2epc), .io_lsu_store_ack_0_bits_uop_is_rocc (_dcache_io_lsu_store_ack_0_bits_uop_is_rocc), .io_lsu_store_ack_0_bits_uop_is_mov (_dcache_io_lsu_store_ack_0_bits_uop_is_mov), .io_lsu_store_ack_0_bits_uop_ftq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ftq_idx), .io_lsu_store_ack_0_bits_uop_edge_inst (_dcache_io_lsu_store_ack_0_bits_uop_edge_inst), .io_lsu_store_ack_0_bits_uop_pc_lob (_dcache_io_lsu_store_ack_0_bits_uop_pc_lob), .io_lsu_store_ack_0_bits_uop_taken (_dcache_io_lsu_store_ack_0_bits_uop_taken), .io_lsu_store_ack_0_bits_uop_imm_rename (_dcache_io_lsu_store_ack_0_bits_uop_imm_rename), .io_lsu_store_ack_0_bits_uop_imm_sel (_dcache_io_lsu_store_ack_0_bits_uop_imm_sel), .io_lsu_store_ack_0_bits_uop_pimm (_dcache_io_lsu_store_ack_0_bits_uop_pimm), .io_lsu_store_ack_0_bits_uop_imm_packed (_dcache_io_lsu_store_ack_0_bits_uop_imm_packed), .io_lsu_store_ack_0_bits_uop_op1_sel (_dcache_io_lsu_store_ack_0_bits_uop_op1_sel), .io_lsu_store_ack_0_bits_uop_op2_sel (_dcache_io_lsu_store_ack_0_bits_uop_op2_sel), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst), .io_lsu_store_ack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wen), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2), .io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3), .io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12), .io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23), .io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint), .io_lsu_store_ack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_toint), .io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_store_ack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fma), .io_lsu_store_ack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_div), .io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt), .io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags), .io_lsu_store_ack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_vec), .io_lsu_store_ack_0_bits_uop_rob_idx (_dcache_io_lsu_store_ack_0_bits_uop_rob_idx), .io_lsu_store_ack_0_bits_uop_ldq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ldq_idx), .io_lsu_store_ack_0_bits_uop_stq_idx (_dcache_io_lsu_store_ack_0_bits_uop_stq_idx), .io_lsu_store_ack_0_bits_uop_rxq_idx (_dcache_io_lsu_store_ack_0_bits_uop_rxq_idx), .io_lsu_store_ack_0_bits_uop_pdst (_dcache_io_lsu_store_ack_0_bits_uop_pdst), .io_lsu_store_ack_0_bits_uop_prs1 (_dcache_io_lsu_store_ack_0_bits_uop_prs1), .io_lsu_store_ack_0_bits_uop_prs2 (_dcache_io_lsu_store_ack_0_bits_uop_prs2), .io_lsu_store_ack_0_bits_uop_prs3 (_dcache_io_lsu_store_ack_0_bits_uop_prs3), .io_lsu_store_ack_0_bits_uop_ppred (_dcache_io_lsu_store_ack_0_bits_uop_ppred), .io_lsu_store_ack_0_bits_uop_prs1_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs1_busy), .io_lsu_store_ack_0_bits_uop_prs2_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs2_busy), .io_lsu_store_ack_0_bits_uop_prs3_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs3_busy), .io_lsu_store_ack_0_bits_uop_ppred_busy (_dcache_io_lsu_store_ack_0_bits_uop_ppred_busy), .io_lsu_store_ack_0_bits_uop_stale_pdst (_dcache_io_lsu_store_ack_0_bits_uop_stale_pdst), .io_lsu_store_ack_0_bits_uop_exception (_dcache_io_lsu_store_ack_0_bits_uop_exception), .io_lsu_store_ack_0_bits_uop_exc_cause (_dcache_io_lsu_store_ack_0_bits_uop_exc_cause), .io_lsu_store_ack_0_bits_uop_mem_cmd (_dcache_io_lsu_store_ack_0_bits_uop_mem_cmd), .io_lsu_store_ack_0_bits_uop_mem_size (_dcache_io_lsu_store_ack_0_bits_uop_mem_size), .io_lsu_store_ack_0_bits_uop_mem_signed (_dcache_io_lsu_store_ack_0_bits_uop_mem_signed), .io_lsu_store_ack_0_bits_uop_uses_ldq (_dcache_io_lsu_store_ack_0_bits_uop_uses_ldq), .io_lsu_store_ack_0_bits_uop_uses_stq (_dcache_io_lsu_store_ack_0_bits_uop_uses_stq), .io_lsu_store_ack_0_bits_uop_is_unique (_dcache_io_lsu_store_ack_0_bits_uop_is_unique), .io_lsu_store_ack_0_bits_uop_flush_on_commit (_dcache_io_lsu_store_ack_0_bits_uop_flush_on_commit), .io_lsu_store_ack_0_bits_uop_csr_cmd (_dcache_io_lsu_store_ack_0_bits_uop_csr_cmd), .io_lsu_store_ack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_store_ack_0_bits_uop_ldst_is_rs1), .io_lsu_store_ack_0_bits_uop_ldst (_dcache_io_lsu_store_ack_0_bits_uop_ldst), .io_lsu_store_ack_0_bits_uop_lrs1 (_dcache_io_lsu_store_ack_0_bits_uop_lrs1), .io_lsu_store_ack_0_bits_uop_lrs2 (_dcache_io_lsu_store_ack_0_bits_uop_lrs2), .io_lsu_store_ack_0_bits_uop_lrs3 (_dcache_io_lsu_store_ack_0_bits_uop_lrs3), .io_lsu_store_ack_0_bits_uop_dst_rtype (_dcache_io_lsu_store_ack_0_bits_uop_dst_rtype), .io_lsu_store_ack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs1_rtype), .io_lsu_store_ack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs2_rtype), .io_lsu_store_ack_0_bits_uop_frs3_en (_dcache_io_lsu_store_ack_0_bits_uop_frs3_en), .io_lsu_store_ack_0_bits_uop_fcn_dw (_dcache_io_lsu_store_ack_0_bits_uop_fcn_dw), .io_lsu_store_ack_0_bits_uop_fcn_op (_dcache_io_lsu_store_ack_0_bits_uop_fcn_op), .io_lsu_store_ack_0_bits_uop_fp_val (_dcache_io_lsu_store_ack_0_bits_uop_fp_val), .io_lsu_store_ack_0_bits_uop_fp_rm (_dcache_io_lsu_store_ack_0_bits_uop_fp_rm), .io_lsu_store_ack_0_bits_uop_fp_typ (_dcache_io_lsu_store_ack_0_bits_uop_fp_typ), .io_lsu_store_ack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_pf_if), .io_lsu_store_ack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ae_if), .io_lsu_store_ack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ma_if), .io_lsu_store_ack_0_bits_uop_bp_debug_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_debug_if), .io_lsu_store_ack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_xcpt_if), .io_lsu_store_ack_0_bits_uop_debug_fsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_fsrc), .io_lsu_store_ack_0_bits_uop_debug_tsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_tsrc), .io_lsu_store_ack_0_bits_addr (_dcache_io_lsu_store_ack_0_bits_addr), .io_lsu_store_ack_0_bits_data (_dcache_io_lsu_store_ack_0_bits_data), .io_lsu_store_ack_0_bits_is_hella (_dcache_io_lsu_store_ack_0_bits_is_hella), .io_lsu_nack_0_valid (_dcache_io_lsu_nack_0_valid), .io_lsu_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), .io_lsu_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), .io_lsu_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), .io_lsu_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), .io_lsu_nack_0_bits_uop_iq_type_0 (_dcache_io_lsu_nack_0_bits_uop_iq_type_0), .io_lsu_nack_0_bits_uop_iq_type_1 (_dcache_io_lsu_nack_0_bits_uop_iq_type_1), .io_lsu_nack_0_bits_uop_iq_type_2 (_dcache_io_lsu_nack_0_bits_uop_iq_type_2), .io_lsu_nack_0_bits_uop_iq_type_3 (_dcache_io_lsu_nack_0_bits_uop_iq_type_3), .io_lsu_nack_0_bits_uop_fu_code_0 (_dcache_io_lsu_nack_0_bits_uop_fu_code_0), .io_lsu_nack_0_bits_uop_fu_code_1 (_dcache_io_lsu_nack_0_bits_uop_fu_code_1), .io_lsu_nack_0_bits_uop_fu_code_2 (_dcache_io_lsu_nack_0_bits_uop_fu_code_2), .io_lsu_nack_0_bits_uop_fu_code_3 (_dcache_io_lsu_nack_0_bits_uop_fu_code_3), .io_lsu_nack_0_bits_uop_fu_code_4 (_dcache_io_lsu_nack_0_bits_uop_fu_code_4), .io_lsu_nack_0_bits_uop_fu_code_5 (_dcache_io_lsu_nack_0_bits_uop_fu_code_5), .io_lsu_nack_0_bits_uop_fu_code_6 (_dcache_io_lsu_nack_0_bits_uop_fu_code_6), .io_lsu_nack_0_bits_uop_fu_code_7 (_dcache_io_lsu_nack_0_bits_uop_fu_code_7), .io_lsu_nack_0_bits_uop_fu_code_8 (_dcache_io_lsu_nack_0_bits_uop_fu_code_8), .io_lsu_nack_0_bits_uop_fu_code_9 (_dcache_io_lsu_nack_0_bits_uop_fu_code_9), .io_lsu_nack_0_bits_uop_iw_issued (_dcache_io_lsu_nack_0_bits_uop_iw_issued), .io_lsu_nack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_agen), .io_lsu_nack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_dgen), .io_lsu_nack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p1_speculative_child), .io_lsu_nack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p2_speculative_child), .io_lsu_nack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p1_bypass_hint), .io_lsu_nack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p2_bypass_hint), .io_lsu_nack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p3_bypass_hint), .io_lsu_nack_0_bits_uop_dis_col_sel (_dcache_io_lsu_nack_0_bits_uop_dis_col_sel), .io_lsu_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), .io_lsu_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), .io_lsu_nack_0_bits_uop_br_type (_dcache_io_lsu_nack_0_bits_uop_br_type), .io_lsu_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), .io_lsu_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), .io_lsu_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), .io_lsu_nack_0_bits_uop_is_sfence (_dcache_io_lsu_nack_0_bits_uop_is_sfence), .io_lsu_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), .io_lsu_nack_0_bits_uop_is_eret (_dcache_io_lsu_nack_0_bits_uop_is_eret), .io_lsu_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), .io_lsu_nack_0_bits_uop_is_rocc (_dcache_io_lsu_nack_0_bits_uop_is_rocc), .io_lsu_nack_0_bits_uop_is_mov (_dcache_io_lsu_nack_0_bits_uop_is_mov), .io_lsu_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), .io_lsu_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), .io_lsu_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), .io_lsu_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), .io_lsu_nack_0_bits_uop_imm_rename (_dcache_io_lsu_nack_0_bits_uop_imm_rename), .io_lsu_nack_0_bits_uop_imm_sel (_dcache_io_lsu_nack_0_bits_uop_imm_sel), .io_lsu_nack_0_bits_uop_pimm (_dcache_io_lsu_nack_0_bits_uop_pimm), .io_lsu_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), .io_lsu_nack_0_bits_uop_op1_sel (_dcache_io_lsu_nack_0_bits_uop_op1_sel), .io_lsu_nack_0_bits_uop_op2_sel (_dcache_io_lsu_nack_0_bits_uop_op2_sel), .io_lsu_nack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ldst), .io_lsu_nack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wen), .io_lsu_nack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren1), .io_lsu_nack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren2), .io_lsu_nack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren3), .io_lsu_nack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap12), .io_lsu_nack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap23), .io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_nack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fromint), .io_lsu_nack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_toint), .io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_nack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fma), .io_lsu_nack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_div), .io_lsu_nack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_sqrt), .io_lsu_nack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wflags), .io_lsu_nack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_vec), .io_lsu_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), .io_lsu_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), .io_lsu_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), .io_lsu_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), .io_lsu_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), .io_lsu_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), .io_lsu_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), .io_lsu_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), .io_lsu_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), .io_lsu_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), .io_lsu_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), .io_lsu_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), .io_lsu_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), .io_lsu_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), .io_lsu_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), .io_lsu_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), .io_lsu_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), .io_lsu_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), .io_lsu_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), .io_lsu_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), .io_lsu_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), .io_lsu_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), .io_lsu_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), .io_lsu_nack_0_bits_uop_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_csr_cmd), .io_lsu_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), .io_lsu_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), .io_lsu_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), .io_lsu_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), .io_lsu_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), .io_lsu_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), .io_lsu_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), .io_lsu_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), .io_lsu_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), .io_lsu_nack_0_bits_uop_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_fcn_dw), .io_lsu_nack_0_bits_uop_fcn_op (_dcache_io_lsu_nack_0_bits_uop_fcn_op), .io_lsu_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), .io_lsu_nack_0_bits_uop_fp_rm (_dcache_io_lsu_nack_0_bits_uop_fp_rm), .io_lsu_nack_0_bits_uop_fp_typ (_dcache_io_lsu_nack_0_bits_uop_fp_typ), .io_lsu_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), .io_lsu_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), .io_lsu_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), .io_lsu_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), .io_lsu_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), .io_lsu_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), .io_lsu_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), .io_lsu_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), .io_lsu_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), .io_lsu_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), .io_lsu_ll_resp_ready (_lsu_io_dmem_ll_resp_ready), // @[tile.scala:159:20] .io_lsu_ll_resp_valid (_dcache_io_lsu_ll_resp_valid), .io_lsu_ll_resp_bits_uop_inst (_dcache_io_lsu_ll_resp_bits_uop_inst), .io_lsu_ll_resp_bits_uop_debug_inst (_dcache_io_lsu_ll_resp_bits_uop_debug_inst), .io_lsu_ll_resp_bits_uop_is_rvc (_dcache_io_lsu_ll_resp_bits_uop_is_rvc), .io_lsu_ll_resp_bits_uop_debug_pc (_dcache_io_lsu_ll_resp_bits_uop_debug_pc), .io_lsu_ll_resp_bits_uop_iq_type_0 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_0), .io_lsu_ll_resp_bits_uop_iq_type_1 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_1), .io_lsu_ll_resp_bits_uop_iq_type_2 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_2), .io_lsu_ll_resp_bits_uop_iq_type_3 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_3), .io_lsu_ll_resp_bits_uop_fu_code_0 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_0), .io_lsu_ll_resp_bits_uop_fu_code_1 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_1), .io_lsu_ll_resp_bits_uop_fu_code_2 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_2), .io_lsu_ll_resp_bits_uop_fu_code_3 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_3), .io_lsu_ll_resp_bits_uop_fu_code_4 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_4), .io_lsu_ll_resp_bits_uop_fu_code_5 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_5), .io_lsu_ll_resp_bits_uop_fu_code_6 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_6), .io_lsu_ll_resp_bits_uop_fu_code_7 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_7), .io_lsu_ll_resp_bits_uop_fu_code_8 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_8), .io_lsu_ll_resp_bits_uop_fu_code_9 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_9), .io_lsu_ll_resp_bits_uop_iw_issued (_dcache_io_lsu_ll_resp_bits_uop_iw_issued), .io_lsu_ll_resp_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_agen), .io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen), .io_lsu_ll_resp_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_speculative_child), .io_lsu_ll_resp_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_speculative_child), .io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint), .io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint), .io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint), .io_lsu_ll_resp_bits_uop_dis_col_sel (_dcache_io_lsu_ll_resp_bits_uop_dis_col_sel), .io_lsu_ll_resp_bits_uop_br_mask (_dcache_io_lsu_ll_resp_bits_uop_br_mask), .io_lsu_ll_resp_bits_uop_br_tag (_dcache_io_lsu_ll_resp_bits_uop_br_tag), .io_lsu_ll_resp_bits_uop_br_type (_dcache_io_lsu_ll_resp_bits_uop_br_type), .io_lsu_ll_resp_bits_uop_is_sfb (_dcache_io_lsu_ll_resp_bits_uop_is_sfb), .io_lsu_ll_resp_bits_uop_is_fence (_dcache_io_lsu_ll_resp_bits_uop_is_fence), .io_lsu_ll_resp_bits_uop_is_fencei (_dcache_io_lsu_ll_resp_bits_uop_is_fencei), .io_lsu_ll_resp_bits_uop_is_sfence (_dcache_io_lsu_ll_resp_bits_uop_is_sfence), .io_lsu_ll_resp_bits_uop_is_amo (_dcache_io_lsu_ll_resp_bits_uop_is_amo), .io_lsu_ll_resp_bits_uop_is_eret (_dcache_io_lsu_ll_resp_bits_uop_is_eret), .io_lsu_ll_resp_bits_uop_is_sys_pc2epc (_dcache_io_lsu_ll_resp_bits_uop_is_sys_pc2epc), .io_lsu_ll_resp_bits_uop_is_rocc (_dcache_io_lsu_ll_resp_bits_uop_is_rocc), .io_lsu_ll_resp_bits_uop_is_mov (_dcache_io_lsu_ll_resp_bits_uop_is_mov), .io_lsu_ll_resp_bits_uop_ftq_idx (_dcache_io_lsu_ll_resp_bits_uop_ftq_idx), .io_lsu_ll_resp_bits_uop_edge_inst (_dcache_io_lsu_ll_resp_bits_uop_edge_inst), .io_lsu_ll_resp_bits_uop_pc_lob (_dcache_io_lsu_ll_resp_bits_uop_pc_lob), .io_lsu_ll_resp_bits_uop_taken (_dcache_io_lsu_ll_resp_bits_uop_taken), .io_lsu_ll_resp_bits_uop_imm_rename (_dcache_io_lsu_ll_resp_bits_uop_imm_rename), .io_lsu_ll_resp_bits_uop_imm_sel (_dcache_io_lsu_ll_resp_bits_uop_imm_sel), .io_lsu_ll_resp_bits_uop_pimm (_dcache_io_lsu_ll_resp_bits_uop_pimm), .io_lsu_ll_resp_bits_uop_imm_packed (_dcache_io_lsu_ll_resp_bits_uop_imm_packed), .io_lsu_ll_resp_bits_uop_op1_sel (_dcache_io_lsu_ll_resp_bits_uop_op1_sel), .io_lsu_ll_resp_bits_uop_op2_sel (_dcache_io_lsu_ll_resp_bits_uop_op2_sel), .io_lsu_ll_resp_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ldst), .io_lsu_ll_resp_bits_uop_fp_ctrl_wen (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wen), .io_lsu_ll_resp_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren1), .io_lsu_ll_resp_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren2), .io_lsu_ll_resp_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren3), .io_lsu_ll_resp_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap12), .io_lsu_ll_resp_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap23), .io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn), .io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut), .io_lsu_ll_resp_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fromint), .io_lsu_ll_resp_bits_uop_fp_ctrl_toint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_toint), .io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe), .io_lsu_ll_resp_bits_uop_fp_ctrl_fma (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fma), .io_lsu_ll_resp_bits_uop_fp_ctrl_div (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_div), .io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt), .io_lsu_ll_resp_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wflags), .io_lsu_ll_resp_bits_uop_fp_ctrl_vec (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_vec), .io_lsu_ll_resp_bits_uop_rob_idx (_dcache_io_lsu_ll_resp_bits_uop_rob_idx), .io_lsu_ll_resp_bits_uop_ldq_idx (_dcache_io_lsu_ll_resp_bits_uop_ldq_idx), .io_lsu_ll_resp_bits_uop_stq_idx (_dcache_io_lsu_ll_resp_bits_uop_stq_idx), .io_lsu_ll_resp_bits_uop_rxq_idx (_dcache_io_lsu_ll_resp_bits_uop_rxq_idx), .io_lsu_ll_resp_bits_uop_pdst (_dcache_io_lsu_ll_resp_bits_uop_pdst), .io_lsu_ll_resp_bits_uop_prs1 (_dcache_io_lsu_ll_resp_bits_uop_prs1), .io_lsu_ll_resp_bits_uop_prs2 (_dcache_io_lsu_ll_resp_bits_uop_prs2), .io_lsu_ll_resp_bits_uop_prs3 (_dcache_io_lsu_ll_resp_bits_uop_prs3), .io_lsu_ll_resp_bits_uop_ppred (_dcache_io_lsu_ll_resp_bits_uop_ppred), .io_lsu_ll_resp_bits_uop_prs1_busy (_dcache_io_lsu_ll_resp_bits_uop_prs1_busy), .io_lsu_ll_resp_bits_uop_prs2_busy (_dcache_io_lsu_ll_resp_bits_uop_prs2_busy), .io_lsu_ll_resp_bits_uop_prs3_busy (_dcache_io_lsu_ll_resp_bits_uop_prs3_busy), .io_lsu_ll_resp_bits_uop_ppred_busy (_dcache_io_lsu_ll_resp_bits_uop_ppred_busy), .io_lsu_ll_resp_bits_uop_stale_pdst (_dcache_io_lsu_ll_resp_bits_uop_stale_pdst), .io_lsu_ll_resp_bits_uop_exception (_dcache_io_lsu_ll_resp_bits_uop_exception), .io_lsu_ll_resp_bits_uop_exc_cause (_dcache_io_lsu_ll_resp_bits_uop_exc_cause), .io_lsu_ll_resp_bits_uop_mem_cmd (_dcache_io_lsu_ll_resp_bits_uop_mem_cmd), .io_lsu_ll_resp_bits_uop_mem_size (_dcache_io_lsu_ll_resp_bits_uop_mem_size), .io_lsu_ll_resp_bits_uop_mem_signed (_dcache_io_lsu_ll_resp_bits_uop_mem_signed), .io_lsu_ll_resp_bits_uop_uses_ldq (_dcache_io_lsu_ll_resp_bits_uop_uses_ldq), .io_lsu_ll_resp_bits_uop_uses_stq (_dcache_io_lsu_ll_resp_bits_uop_uses_stq), .io_lsu_ll_resp_bits_uop_is_unique (_dcache_io_lsu_ll_resp_bits_uop_is_unique), .io_lsu_ll_resp_bits_uop_flush_on_commit (_dcache_io_lsu_ll_resp_bits_uop_flush_on_commit), .io_lsu_ll_resp_bits_uop_csr_cmd (_dcache_io_lsu_ll_resp_bits_uop_csr_cmd), .io_lsu_ll_resp_bits_uop_ldst_is_rs1 (_dcache_io_lsu_ll_resp_bits_uop_ldst_is_rs1), .io_lsu_ll_resp_bits_uop_ldst (_dcache_io_lsu_ll_resp_bits_uop_ldst), .io_lsu_ll_resp_bits_uop_lrs1 (_dcache_io_lsu_ll_resp_bits_uop_lrs1), .io_lsu_ll_resp_bits_uop_lrs2 (_dcache_io_lsu_ll_resp_bits_uop_lrs2), .io_lsu_ll_resp_bits_uop_lrs3 (_dcache_io_lsu_ll_resp_bits_uop_lrs3), .io_lsu_ll_resp_bits_uop_dst_rtype (_dcache_io_lsu_ll_resp_bits_uop_dst_rtype), .io_lsu_ll_resp_bits_uop_lrs1_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs1_rtype), .io_lsu_ll_resp_bits_uop_lrs2_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs2_rtype), .io_lsu_ll_resp_bits_uop_frs3_en (_dcache_io_lsu_ll_resp_bits_uop_frs3_en), .io_lsu_ll_resp_bits_uop_fcn_dw (_dcache_io_lsu_ll_resp_bits_uop_fcn_dw), .io_lsu_ll_resp_bits_uop_fcn_op (_dcache_io_lsu_ll_resp_bits_uop_fcn_op), .io_lsu_ll_resp_bits_uop_fp_val (_dcache_io_lsu_ll_resp_bits_uop_fp_val), .io_lsu_ll_resp_bits_uop_fp_rm (_dcache_io_lsu_ll_resp_bits_uop_fp_rm), .io_lsu_ll_resp_bits_uop_fp_typ (_dcache_io_lsu_ll_resp_bits_uop_fp_typ), .io_lsu_ll_resp_bits_uop_xcpt_pf_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_pf_if), .io_lsu_ll_resp_bits_uop_xcpt_ae_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ae_if), .io_lsu_ll_resp_bits_uop_xcpt_ma_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ma_if), .io_lsu_ll_resp_bits_uop_bp_debug_if (_dcache_io_lsu_ll_resp_bits_uop_bp_debug_if), .io_lsu_ll_resp_bits_uop_bp_xcpt_if (_dcache_io_lsu_ll_resp_bits_uop_bp_xcpt_if), .io_lsu_ll_resp_bits_uop_debug_fsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_fsrc), .io_lsu_ll_resp_bits_uop_debug_tsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_tsrc), .io_lsu_ll_resp_bits_data (_dcache_io_lsu_ll_resp_bits_data), .io_lsu_ll_resp_bits_is_hella (_dcache_io_lsu_ll_resp_bits_is_hella), .io_lsu_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), // @[tile.scala:159:20] .io_lsu_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_0 (_lsu_io_dmem_brupdate_b2_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_1 (_lsu_io_dmem_brupdate_b2_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_2 (_lsu_io_dmem_brupdate_b2_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iq_type_3 (_lsu_io_dmem_brupdate_b2_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_0 (_lsu_io_dmem_brupdate_b2_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_1 (_lsu_io_dmem_brupdate_b2_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_2 (_lsu_io_dmem_brupdate_b2_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_3 (_lsu_io_dmem_brupdate_b2_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_4 (_lsu_io_dmem_brupdate_b2_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_5 (_lsu_io_dmem_brupdate_b2_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_6 (_lsu_io_dmem_brupdate_b2_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_7 (_lsu_io_dmem_brupdate_b2_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_8 (_lsu_io_dmem_brupdate_b2_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fu_code_9 (_lsu_io_dmem_brupdate_b2_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_issued (_lsu_io_dmem_brupdate_b2_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_issued_partial_agen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_issued_partial_dgen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p1_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p2_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p1_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p2_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_iw_p3_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_dis_col_sel (_lsu_io_dmem_brupdate_b2_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_br_type (_lsu_io_dmem_brupdate_b2_uop_br_type), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_sfence (_lsu_io_dmem_brupdate_b2_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_eret (_lsu_io_dmem_brupdate_b2_uop_is_eret), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_rocc (_lsu_io_dmem_brupdate_b2_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_mov (_lsu_io_dmem_brupdate_b2_uop_is_mov), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_imm_rename (_lsu_io_dmem_brupdate_b2_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_imm_sel (_lsu_io_dmem_brupdate_b2_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_pimm (_lsu_io_dmem_brupdate_b2_uop_pimm), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_op1_sel (_lsu_io_dmem_brupdate_b2_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_op2_sel (_lsu_io_dmem_brupdate_b2_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ldst (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_wen (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ren1 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ren2 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_ren3 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_swap12 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_swap23 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_fromint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_toint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_fma (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_div (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_sqrt (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_wflags (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_ctrl_vec (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fcn_op (_lsu_io_dmem_brupdate_b2_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_rm (_lsu_io_dmem_brupdate_b2_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_fp_typ (_lsu_io_dmem_brupdate_b2_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), // @[tile.scala:159:20] .io_lsu_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), // @[tile.scala:159:20] .io_lsu_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), // @[tile.scala:159:20] .io_lsu_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), // @[tile.scala:159:20] .io_lsu_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), // @[tile.scala:159:20] .io_lsu_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), // @[tile.scala:159:20] .io_lsu_exception (_lsu_io_dmem_exception), // @[tile.scala:159:20] .io_lsu_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), // @[tile.scala:159:20] .io_lsu_rob_head_idx (_lsu_io_dmem_rob_head_idx), // @[tile.scala:159:20] .io_lsu_release_ready (_lsu_io_dmem_release_ready), // @[tile.scala:159:20] .io_lsu_release_valid (_dcache_io_lsu_release_valid), .io_lsu_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), .io_lsu_release_bits_param (_dcache_io_lsu_release_bits_param), .io_lsu_release_bits_size (_dcache_io_lsu_release_bits_size), .io_lsu_release_bits_source (_dcache_io_lsu_release_bits_source), .io_lsu_release_bits_address (_dcache_io_lsu_release_bits_address), .io_lsu_release_bits_data (_dcache_io_lsu_release_bits_data), .io_lsu_force_order (_lsu_io_dmem_force_order), // @[tile.scala:159:20] .io_lsu_ordered (_dcache_io_lsu_ordered), .io_lsu_perf_acquire (_dcache_io_lsu_perf_acquire), .io_lsu_perf_release (_dcache_io_lsu_perf_release) ); // @[tile.scala:132:54] BoomFrontend frontend ( // @[tile.scala:137:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_source (widget_1_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), // @[tile.scala:158:20] .io_cpu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), .io_cpu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), .io_cpu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), .io_cpu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), .io_cpu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), .io_cpu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), .io_cpu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), .io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), .io_cpu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), .io_cpu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), .io_cpu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), .io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), .io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), .io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), .io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), .io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), .io_cpu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), .io_cpu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), .io_cpu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), .io_cpu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), .io_cpu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), .io_cpu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), .io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), .io_cpu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), .io_cpu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), .io_cpu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), .io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), .io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), .io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), .io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), .io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), .io_cpu_arb_ftq_reqs_0 (_core_io_ifu_arb_ftq_reqs_0), // @[tile.scala:158:20] .io_cpu_arb_ftq_reqs_1 (_core_io_ifu_arb_ftq_reqs_1), // @[tile.scala:158:20] .io_cpu_arb_ftq_reqs_2 (_core_io_ifu_arb_ftq_reqs_2), // @[tile.scala:158:20] .io_cpu_rrd_ftq_resps_0_valid (_frontend_io_cpu_rrd_ftq_resps_0_valid), .io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid), .io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits), .io_cpu_rrd_ftq_resps_0_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_taken), .io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted), .io_cpu_rrd_ftq_resps_0_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_type), .io_cpu_rrd_ftq_resps_0_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_0_entry_br_mask), .io_cpu_rrd_ftq_resps_0_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_call), .io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret), .io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4), .io_cpu_rrd_ftq_resps_0_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_top), .io_cpu_rrd_ftq_resps_0_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_idx), .io_cpu_rrd_ftq_resps_0_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_0_entry_start_bank), .io_cpu_rrd_ftq_resps_0_ghist_old_history (_frontend_io_cpu_rrd_ftq_resps_0_ghist_old_history), .io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken), .io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken), .io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken), .io_cpu_rrd_ftq_resps_0_ghist_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_ghist_ras_idx), .io_cpu_rrd_ftq_resps_0_pc (_frontend_io_cpu_rrd_ftq_resps_0_pc), .io_cpu_rrd_ftq_resps_1_valid (_frontend_io_cpu_rrd_ftq_resps_1_valid), .io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid), .io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits), .io_cpu_rrd_ftq_resps_1_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_taken), .io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted), .io_cpu_rrd_ftq_resps_1_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_type), .io_cpu_rrd_ftq_resps_1_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_1_entry_br_mask), .io_cpu_rrd_ftq_resps_1_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_call), .io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret), .io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4), .io_cpu_rrd_ftq_resps_1_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_top), .io_cpu_rrd_ftq_resps_1_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_idx), .io_cpu_rrd_ftq_resps_1_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_1_entry_start_bank), .io_cpu_rrd_ftq_resps_1_pc (_frontend_io_cpu_rrd_ftq_resps_1_pc), .io_cpu_rrd_ftq_resps_2_valid (_frontend_io_cpu_rrd_ftq_resps_2_valid), .io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid), .io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits), .io_cpu_rrd_ftq_resps_2_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_taken), .io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted), .io_cpu_rrd_ftq_resps_2_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_type), .io_cpu_rrd_ftq_resps_2_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_2_entry_br_mask), .io_cpu_rrd_ftq_resps_2_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_call), .io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret), .io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4), .io_cpu_rrd_ftq_resps_2_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_top), .io_cpu_rrd_ftq_resps_2_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_idx), .io_cpu_rrd_ftq_resps_2_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_2_entry_start_bank), .io_cpu_rrd_ftq_resps_2_pc (_frontend_io_cpu_rrd_ftq_resps_2_pc), .io_cpu_com_pc (_frontend_io_cpu_com_pc), .io_cpu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), .io_cpu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), .io_cpu_status_debug (_core_io_ifu_status_debug), // @[tile.scala:158:20] .io_cpu_status_cease (_core_io_ifu_status_cease), // @[tile.scala:158:20] .io_cpu_status_wfi (_core_io_ifu_status_wfi), // @[tile.scala:158:20] .io_cpu_status_dprv (_core_io_ifu_status_dprv), // @[tile.scala:158:20] .io_cpu_status_dv (_core_io_ifu_status_dv), // @[tile.scala:158:20] .io_cpu_status_prv (_core_io_ifu_status_prv), // @[tile.scala:158:20] .io_cpu_status_v (_core_io_ifu_status_v), // @[tile.scala:158:20] .io_cpu_status_sd (_core_io_ifu_status_sd), // @[tile.scala:158:20] .io_cpu_status_mpv (_core_io_ifu_status_mpv), // @[tile.scala:158:20] .io_cpu_status_gva (_core_io_ifu_status_gva), // @[tile.scala:158:20] .io_cpu_status_tsr (_core_io_ifu_status_tsr), // @[tile.scala:158:20] .io_cpu_status_tw (_core_io_ifu_status_tw), // @[tile.scala:158:20] .io_cpu_status_tvm (_core_io_ifu_status_tvm), // @[tile.scala:158:20] .io_cpu_status_mxr (_core_io_ifu_status_mxr), // @[tile.scala:158:20] .io_cpu_status_sum (_core_io_ifu_status_sum), // @[tile.scala:158:20] .io_cpu_status_mprv (_core_io_ifu_status_mprv), // @[tile.scala:158:20] .io_cpu_status_fs (_core_io_ifu_status_fs), // @[tile.scala:158:20] .io_cpu_status_mpp (_core_io_ifu_status_mpp), // @[tile.scala:158:20] .io_cpu_status_spp (_core_io_ifu_status_spp), // @[tile.scala:158:20] .io_cpu_status_mpie (_core_io_ifu_status_mpie), // @[tile.scala:158:20] .io_cpu_status_spie (_core_io_ifu_status_spie), // @[tile.scala:158:20] .io_cpu_status_mie (_core_io_ifu_status_mie), // @[tile.scala:158:20] .io_cpu_status_sie (_core_io_ifu_status_sie), // @[tile.scala:158:20] .io_cpu_sfence_valid (_core_io_ifu_sfence_valid), // @[tile.scala:158:20] .io_cpu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), // @[tile.scala:158:20] .io_cpu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), // @[tile.scala:158:20] .io_cpu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), // @[tile.scala:158:20] .io_cpu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), // @[tile.scala:158:20] .io_cpu_sfence_bits_hv (_core_io_ifu_sfence_bits_hv), // @[tile.scala:158:20] .io_cpu_sfence_bits_hg (_core_io_ifu_sfence_bits_hg), // @[tile.scala:158:20] .io_cpu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), // @[tile.scala:158:20] .io_cpu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_0 (_core_io_ifu_brupdate_b2_uop_iq_type_0), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_1 (_core_io_ifu_brupdate_b2_uop_iq_type_1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_2 (_core_io_ifu_brupdate_b2_uop_iq_type_2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iq_type_3 (_core_io_ifu_brupdate_b2_uop_iq_type_3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_0 (_core_io_ifu_brupdate_b2_uop_fu_code_0), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_1 (_core_io_ifu_brupdate_b2_uop_fu_code_1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_2 (_core_io_ifu_brupdate_b2_uop_fu_code_2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_3 (_core_io_ifu_brupdate_b2_uop_fu_code_3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_4 (_core_io_ifu_brupdate_b2_uop_fu_code_4), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_5 (_core_io_ifu_brupdate_b2_uop_fu_code_5), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_6 (_core_io_ifu_brupdate_b2_uop_fu_code_6), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_7 (_core_io_ifu_brupdate_b2_uop_fu_code_7), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_8 (_core_io_ifu_brupdate_b2_uop_fu_code_8), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fu_code_9 (_core_io_ifu_brupdate_b2_uop_fu_code_9), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_issued (_core_io_ifu_brupdate_b2_uop_iw_issued), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_issued_partial_agen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p1_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p2_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_dis_col_sel (_core_io_ifu_brupdate_b2_uop_dis_col_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_br_type (_core_io_ifu_brupdate_b2_uop_br_type), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_sfence (_core_io_ifu_brupdate_b2_uop_is_sfence), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_eret (_core_io_ifu_brupdate_b2_uop_is_eret), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_rocc (_core_io_ifu_brupdate_b2_uop_is_rocc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_mov (_core_io_ifu_brupdate_b2_uop_is_mov), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_imm_rename (_core_io_ifu_brupdate_b2_uop_imm_rename), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_imm_sel (_core_io_ifu_brupdate_b2_uop_imm_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_pimm (_core_io_ifu_brupdate_b2_uop_pimm), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_op1_sel (_core_io_ifu_brupdate_b2_uop_op1_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_op2_sel (_core_io_ifu_brupdate_b2_uop_op2_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ldst (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_wen (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_fromint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_toint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_fma (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_div (_core_io_ifu_brupdate_b2_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_ifu_brupdate_b2_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_wflags (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_ctrl_vec (_core_io_ifu_brupdate_b2_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_csr_cmd (_core_io_ifu_brupdate_b2_uop_csr_cmd), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fcn_dw (_core_io_ifu_brupdate_b2_uop_fcn_dw), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fcn_op (_core_io_ifu_brupdate_b2_uop_fcn_op), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_rm (_core_io_ifu_brupdate_b2_uop_fp_rm), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_fp_typ (_core_io_ifu_brupdate_b2_uop_fp_typ), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:158:20] .io_cpu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), // @[tile.scala:158:20] .io_cpu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), // @[tile.scala:158:20] .io_cpu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), // @[tile.scala:158:20] .io_cpu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), // @[tile.scala:158:20] .io_cpu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), // @[tile.scala:158:20] .io_cpu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), // @[tile.scala:158:20] .io_cpu_redirect_flush (_core_io_ifu_redirect_flush), // @[tile.scala:158:20] .io_cpu_redirect_val (_core_io_ifu_redirect_val), // @[tile.scala:158:20] .io_cpu_redirect_pc (_core_io_ifu_redirect_pc), // @[tile.scala:158:20] .io_cpu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), // @[tile.scala:158:20] .io_cpu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), // @[tile.scala:158:20] .io_cpu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), // @[tile.scala:158:20] .io_cpu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), // @[tile.scala:158:20] .io_cpu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), // @[tile.scala:158:20] .io_cpu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), // @[tile.scala:158:20] .io_cpu_commit_valid (_core_io_ifu_commit_valid), // @[tile.scala:158:20] .io_cpu_commit_bits (_core_io_ifu_commit_bits), // @[tile.scala:158:20] .io_cpu_flush_icache (_core_io_ifu_flush_icache), // @[tile.scala:158:20] .io_cpu_enable_bpd (_core_io_ifu_enable_bpd), // @[tile.scala:158:20] .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[tile.scala:236:20] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[tile.scala:236:20] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[tile.scala:236:20] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[tile.scala:236:20] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[tile.scala:236:20] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[tile.scala:236:20] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[tile.scala:236:20] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[tile.scala:236:20] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[tile.scala:236:20] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[tile.scala:236:20] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[tile.scala:236:20] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[tile.scala:236:20] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[tile.scala:236:20] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[tile.scala:236:20] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[tile.scala:236:20] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[tile.scala:236:20] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[tile.scala:236:20] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[tile.scala:236:20] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[tile.scala:236:20] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[tile.scala:236:20] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[tile.scala:236:20] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[tile.scala:236:20] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[tile.scala:236:20] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[tile.scala:236:20] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[tile.scala:236:20] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[tile.scala:236:20] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[tile.scala:236:20] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[tile.scala:236:20] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[tile.scala:236:20] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[tile.scala:236:20] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[tile.scala:236:20] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[tile.scala:236:20] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[tile.scala:236:20] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[tile.scala:236:20] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[tile.scala:236:20] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[tile.scala:236:20] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[tile.scala:236:20] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[tile.scala:236:20] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[tile.scala:236:20] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[tile.scala:236:20] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[tile.scala:236:20] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask) // @[tile.scala:236:20] ); // @[tile.scala:137:28] TLBuffer_a32d64s1k3z4u buffer_2 ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (widget_1_auto_anon_out_a_ready), .auto_in_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_in_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_in_d_valid (widget_1_auto_anon_out_d_valid), .auto_in_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_in_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_in_d_bits_source (widget_1_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_tlMasterXbar_auto_anon_in_1_a_ready), // @[HierarchicalElement.scala:55:42] .auto_out_a_valid (_buffer_2_auto_out_a_valid), .auto_out_a_bits_opcode (_buffer_2_auto_out_a_bits_opcode), .auto_out_a_bits_param (_buffer_2_auto_out_a_bits_param), .auto_out_a_bits_size (_buffer_2_auto_out_a_bits_size), .auto_out_a_bits_source (_buffer_2_auto_out_a_bits_source), .auto_out_a_bits_address (_buffer_2_auto_out_a_bits_address), .auto_out_a_bits_mask (_buffer_2_auto_out_a_bits_mask), .auto_out_a_bits_data (_buffer_2_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_buffer_2_auto_out_a_bits_corrupt), .auto_out_d_ready (_buffer_2_auto_out_d_ready), .auto_out_d_valid (_tlMasterXbar_auto_anon_in_1_d_valid), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_opcode (_tlMasterXbar_auto_anon_in_1_d_bits_opcode), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_param (_tlMasterXbar_auto_anon_in_1_d_bits_param), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_size (_tlMasterXbar_auto_anon_in_1_d_bits_size), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_sink (_tlMasterXbar_auto_anon_in_1_d_bits_sink), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_denied (_tlMasterXbar_auto_anon_in_1_d_bits_denied), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_data (_tlMasterXbar_auto_anon_in_1_d_bits_data), // @[HierarchicalElement.scala:55:42] .auto_out_d_bits_corrupt (_tlMasterXbar_auto_anon_in_1_d_bits_corrupt) // @[HierarchicalElement.scala:55:42] ); // @[Buffer.scala:75:28] BoomCore core ( // @[tile.scala:158:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_ifu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), .io_ifu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), // @[tile.scala:137:28] .io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), // @[tile.scala:137:28] .io_ifu_arb_ftq_reqs_0 (_core_io_ifu_arb_ftq_reqs_0), .io_ifu_arb_ftq_reqs_1 (_core_io_ifu_arb_ftq_reqs_1), .io_ifu_arb_ftq_reqs_2 (_core_io_ifu_arb_ftq_reqs_2), .io_ifu_rrd_ftq_resps_0_valid (_frontend_io_cpu_rrd_ftq_resps_0_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_idx_bits), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_mispredicted), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_type), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_0_entry_br_mask), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_call), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_is_ret), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_0_entry_cfi_npc_plus4), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_top), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_entry_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_0_entry_start_bank), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_old_history (_frontend_io_cpu_rrd_ftq_resps_0_ghist_old_history), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_taken (_frontend_io_cpu_rrd_ftq_resps_0_ghist_new_saw_branch_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_ghist_ras_idx (_frontend_io_cpu_rrd_ftq_resps_0_ghist_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_0_pc (_frontend_io_cpu_rrd_ftq_resps_0_pc), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_valid (_frontend_io_cpu_rrd_ftq_resps_1_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_idx_bits), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_mispredicted), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_type), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_1_entry_br_mask), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_call), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_is_ret), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_1_entry_cfi_npc_plus4), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_top), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_1_entry_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_1_entry_start_bank), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_1_pc (_frontend_io_cpu_rrd_ftq_resps_1_pc), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_valid (_frontend_io_cpu_rrd_ftq_resps_2_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_valid), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_idx_bits), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_taken (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_taken), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_mispredicted), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_type (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_type), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_br_mask (_frontend_io_cpu_rrd_ftq_resps_2_entry_br_mask), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_is_call (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_call), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_is_ret), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4 (_frontend_io_cpu_rrd_ftq_resps_2_entry_cfi_npc_plus4), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_ras_top (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_top), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_ras_idx (_frontend_io_cpu_rrd_ftq_resps_2_entry_ras_idx), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_entry_start_bank (_frontend_io_cpu_rrd_ftq_resps_2_entry_start_bank), // @[tile.scala:137:28] .io_ifu_rrd_ftq_resps_2_pc (_frontend_io_cpu_rrd_ftq_resps_2_pc), // @[tile.scala:137:28] .io_ifu_com_pc (_frontend_io_cpu_com_pc), // @[tile.scala:137:28] .io_ifu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), // @[tile.scala:137:28] .io_ifu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), // @[tile.scala:137:28] .io_ifu_status_debug (_core_io_ifu_status_debug), .io_ifu_status_cease (_core_io_ifu_status_cease), .io_ifu_status_wfi (_core_io_ifu_status_wfi), .io_ifu_status_dprv (_core_io_ifu_status_dprv), .io_ifu_status_dv (_core_io_ifu_status_dv), .io_ifu_status_prv (_core_io_ifu_status_prv), .io_ifu_status_v (_core_io_ifu_status_v), .io_ifu_status_sd (_core_io_ifu_status_sd), .io_ifu_status_mpv (_core_io_ifu_status_mpv), .io_ifu_status_gva (_core_io_ifu_status_gva), .io_ifu_status_tsr (_core_io_ifu_status_tsr), .io_ifu_status_tw (_core_io_ifu_status_tw), .io_ifu_status_tvm (_core_io_ifu_status_tvm), .io_ifu_status_mxr (_core_io_ifu_status_mxr), .io_ifu_status_sum (_core_io_ifu_status_sum), .io_ifu_status_mprv (_core_io_ifu_status_mprv), .io_ifu_status_fs (_core_io_ifu_status_fs), .io_ifu_status_mpp (_core_io_ifu_status_mpp), .io_ifu_status_spp (_core_io_ifu_status_spp), .io_ifu_status_mpie (_core_io_ifu_status_mpie), .io_ifu_status_spie (_core_io_ifu_status_spie), .io_ifu_status_mie (_core_io_ifu_status_mie), .io_ifu_status_sie (_core_io_ifu_status_sie), .io_ifu_sfence_valid (_core_io_ifu_sfence_valid), .io_ifu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), .io_ifu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), .io_ifu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), .io_ifu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), .io_ifu_sfence_bits_hv (_core_io_ifu_sfence_bits_hv), .io_ifu_sfence_bits_hg (_core_io_ifu_sfence_bits_hg), .io_ifu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), .io_ifu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), .io_ifu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), .io_ifu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), .io_ifu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), .io_ifu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), .io_ifu_brupdate_b2_uop_iq_type_0 (_core_io_ifu_brupdate_b2_uop_iq_type_0), .io_ifu_brupdate_b2_uop_iq_type_1 (_core_io_ifu_brupdate_b2_uop_iq_type_1), .io_ifu_brupdate_b2_uop_iq_type_2 (_core_io_ifu_brupdate_b2_uop_iq_type_2), .io_ifu_brupdate_b2_uop_iq_type_3 (_core_io_ifu_brupdate_b2_uop_iq_type_3), .io_ifu_brupdate_b2_uop_fu_code_0 (_core_io_ifu_brupdate_b2_uop_fu_code_0), .io_ifu_brupdate_b2_uop_fu_code_1 (_core_io_ifu_brupdate_b2_uop_fu_code_1), .io_ifu_brupdate_b2_uop_fu_code_2 (_core_io_ifu_brupdate_b2_uop_fu_code_2), .io_ifu_brupdate_b2_uop_fu_code_3 (_core_io_ifu_brupdate_b2_uop_fu_code_3), .io_ifu_brupdate_b2_uop_fu_code_4 (_core_io_ifu_brupdate_b2_uop_fu_code_4), .io_ifu_brupdate_b2_uop_fu_code_5 (_core_io_ifu_brupdate_b2_uop_fu_code_5), .io_ifu_brupdate_b2_uop_fu_code_6 (_core_io_ifu_brupdate_b2_uop_fu_code_6), .io_ifu_brupdate_b2_uop_fu_code_7 (_core_io_ifu_brupdate_b2_uop_fu_code_7), .io_ifu_brupdate_b2_uop_fu_code_8 (_core_io_ifu_brupdate_b2_uop_fu_code_8), .io_ifu_brupdate_b2_uop_fu_code_9 (_core_io_ifu_brupdate_b2_uop_fu_code_9), .io_ifu_brupdate_b2_uop_iw_issued (_core_io_ifu_brupdate_b2_uop_iw_issued), .io_ifu_brupdate_b2_uop_iw_issued_partial_agen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_agen), .io_ifu_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_ifu_brupdate_b2_uop_iw_issued_partial_dgen), .io_ifu_brupdate_b2_uop_iw_p1_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p1_speculative_child), .io_ifu_brupdate_b2_uop_iw_p2_speculative_child (_core_io_ifu_brupdate_b2_uop_iw_p2_speculative_child), .io_ifu_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p1_bypass_hint), .io_ifu_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p2_bypass_hint), .io_ifu_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_ifu_brupdate_b2_uop_iw_p3_bypass_hint), .io_ifu_brupdate_b2_uop_dis_col_sel (_core_io_ifu_brupdate_b2_uop_dis_col_sel), .io_ifu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), .io_ifu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), .io_ifu_brupdate_b2_uop_br_type (_core_io_ifu_brupdate_b2_uop_br_type), .io_ifu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), .io_ifu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), .io_ifu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), .io_ifu_brupdate_b2_uop_is_sfence (_core_io_ifu_brupdate_b2_uop_is_sfence), .io_ifu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), .io_ifu_brupdate_b2_uop_is_eret (_core_io_ifu_brupdate_b2_uop_is_eret), .io_ifu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), .io_ifu_brupdate_b2_uop_is_rocc (_core_io_ifu_brupdate_b2_uop_is_rocc), .io_ifu_brupdate_b2_uop_is_mov (_core_io_ifu_brupdate_b2_uop_is_mov), .io_ifu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), .io_ifu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), .io_ifu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), .io_ifu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), .io_ifu_brupdate_b2_uop_imm_rename (_core_io_ifu_brupdate_b2_uop_imm_rename), .io_ifu_brupdate_b2_uop_imm_sel (_core_io_ifu_brupdate_b2_uop_imm_sel), .io_ifu_brupdate_b2_uop_pimm (_core_io_ifu_brupdate_b2_uop_pimm), .io_ifu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), .io_ifu_brupdate_b2_uop_op1_sel (_core_io_ifu_brupdate_b2_uop_op1_sel), .io_ifu_brupdate_b2_uop_op2_sel (_core_io_ifu_brupdate_b2_uop_op2_sel), .io_ifu_brupdate_b2_uop_fp_ctrl_ldst (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ldst), .io_ifu_brupdate_b2_uop_fp_ctrl_wen (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wen), .io_ifu_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren1), .io_ifu_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren2), .io_ifu_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_ren3), .io_ifu_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap12), .io_ifu_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_ifu_brupdate_b2_uop_fp_ctrl_swap23), .io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn), .io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut), .io_ifu_brupdate_b2_uop_fp_ctrl_fromint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fromint), .io_ifu_brupdate_b2_uop_fp_ctrl_toint (_core_io_ifu_brupdate_b2_uop_fp_ctrl_toint), .io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe), .io_ifu_brupdate_b2_uop_fp_ctrl_fma (_core_io_ifu_brupdate_b2_uop_fp_ctrl_fma), .io_ifu_brupdate_b2_uop_fp_ctrl_div (_core_io_ifu_brupdate_b2_uop_fp_ctrl_div), .io_ifu_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_ifu_brupdate_b2_uop_fp_ctrl_sqrt), .io_ifu_brupdate_b2_uop_fp_ctrl_wflags (_core_io_ifu_brupdate_b2_uop_fp_ctrl_wflags), .io_ifu_brupdate_b2_uop_fp_ctrl_vec (_core_io_ifu_brupdate_b2_uop_fp_ctrl_vec), .io_ifu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), .io_ifu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), .io_ifu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), .io_ifu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), .io_ifu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), .io_ifu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), .io_ifu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), .io_ifu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), .io_ifu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), .io_ifu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), .io_ifu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), .io_ifu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), .io_ifu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), .io_ifu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), .io_ifu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), .io_ifu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), .io_ifu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), .io_ifu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), .io_ifu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), .io_ifu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), .io_ifu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), .io_ifu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), .io_ifu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), .io_ifu_brupdate_b2_uop_csr_cmd (_core_io_ifu_brupdate_b2_uop_csr_cmd), .io_ifu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), .io_ifu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), .io_ifu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), .io_ifu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), .io_ifu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), .io_ifu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), .io_ifu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), .io_ifu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), .io_ifu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), .io_ifu_brupdate_b2_uop_fcn_dw (_core_io_ifu_brupdate_b2_uop_fcn_dw), .io_ifu_brupdate_b2_uop_fcn_op (_core_io_ifu_brupdate_b2_uop_fcn_op), .io_ifu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), .io_ifu_brupdate_b2_uop_fp_rm (_core_io_ifu_brupdate_b2_uop_fp_rm), .io_ifu_brupdate_b2_uop_fp_typ (_core_io_ifu_brupdate_b2_uop_fp_typ), .io_ifu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), .io_ifu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), .io_ifu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), .io_ifu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), .io_ifu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), .io_ifu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), .io_ifu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), .io_ifu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), .io_ifu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), .io_ifu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), .io_ifu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), .io_ifu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), .io_ifu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), .io_ifu_redirect_flush (_core_io_ifu_redirect_flush), .io_ifu_redirect_val (_core_io_ifu_redirect_val), .io_ifu_redirect_pc (_core_io_ifu_redirect_pc), .io_ifu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), .io_ifu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), .io_ifu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), .io_ifu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), .io_ifu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), .io_ifu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), .io_ifu_commit_valid (_core_io_ifu_commit_valid), .io_ifu_commit_bits (_core_io_ifu_commit_bits), .io_ifu_flush_icache (_core_io_ifu_flush_icache), .io_ifu_enable_bpd (_core_io_ifu_enable_bpd), .io_ifu_perf_acquire (_frontend_io_cpu_perf_acquire), // @[tile.scala:137:28] .io_ifu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[tile.scala:137:28] .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_l2miss (_ptw_io_dpath_perf_l2miss), // @[tile.scala:236:20] .io_ptw_perf_l2hit (_ptw_io_dpath_perf_l2hit), // @[tile.scala:236:20] .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[tile.scala:236:20] .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[tile.scala:236:20] .io_lsu_agen_0_valid (_core_io_lsu_agen_0_valid), .io_lsu_agen_0_bits_uop_inst (_core_io_lsu_agen_0_bits_uop_inst), .io_lsu_agen_0_bits_uop_debug_inst (_core_io_lsu_agen_0_bits_uop_debug_inst), .io_lsu_agen_0_bits_uop_is_rvc (_core_io_lsu_agen_0_bits_uop_is_rvc), .io_lsu_agen_0_bits_uop_debug_pc (_core_io_lsu_agen_0_bits_uop_debug_pc), .io_lsu_agen_0_bits_uop_iq_type_0 (_core_io_lsu_agen_0_bits_uop_iq_type_0), .io_lsu_agen_0_bits_uop_iq_type_1 (_core_io_lsu_agen_0_bits_uop_iq_type_1), .io_lsu_agen_0_bits_uop_iq_type_2 (_core_io_lsu_agen_0_bits_uop_iq_type_2), .io_lsu_agen_0_bits_uop_iq_type_3 (_core_io_lsu_agen_0_bits_uop_iq_type_3), .io_lsu_agen_0_bits_uop_fu_code_0 (_core_io_lsu_agen_0_bits_uop_fu_code_0), .io_lsu_agen_0_bits_uop_fu_code_1 (_core_io_lsu_agen_0_bits_uop_fu_code_1), .io_lsu_agen_0_bits_uop_fu_code_2 (_core_io_lsu_agen_0_bits_uop_fu_code_2), .io_lsu_agen_0_bits_uop_fu_code_3 (_core_io_lsu_agen_0_bits_uop_fu_code_3), .io_lsu_agen_0_bits_uop_fu_code_4 (_core_io_lsu_agen_0_bits_uop_fu_code_4), .io_lsu_agen_0_bits_uop_fu_code_5 (_core_io_lsu_agen_0_bits_uop_fu_code_5), .io_lsu_agen_0_bits_uop_fu_code_6 (_core_io_lsu_agen_0_bits_uop_fu_code_6), .io_lsu_agen_0_bits_uop_fu_code_7 (_core_io_lsu_agen_0_bits_uop_fu_code_7), .io_lsu_agen_0_bits_uop_fu_code_8 (_core_io_lsu_agen_0_bits_uop_fu_code_8), .io_lsu_agen_0_bits_uop_fu_code_9 (_core_io_lsu_agen_0_bits_uop_fu_code_9), .io_lsu_agen_0_bits_uop_iw_issued (_core_io_lsu_agen_0_bits_uop_iw_issued), .io_lsu_agen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_agen), .io_lsu_agen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_dgen), .io_lsu_agen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p1_speculative_child), .io_lsu_agen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p2_speculative_child), .io_lsu_agen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p1_bypass_hint), .io_lsu_agen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p2_bypass_hint), .io_lsu_agen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p3_bypass_hint), .io_lsu_agen_0_bits_uop_dis_col_sel (_core_io_lsu_agen_0_bits_uop_dis_col_sel), .io_lsu_agen_0_bits_uop_br_mask (_core_io_lsu_agen_0_bits_uop_br_mask), .io_lsu_agen_0_bits_uop_br_tag (_core_io_lsu_agen_0_bits_uop_br_tag), .io_lsu_agen_0_bits_uop_br_type (_core_io_lsu_agen_0_bits_uop_br_type), .io_lsu_agen_0_bits_uop_is_sfb (_core_io_lsu_agen_0_bits_uop_is_sfb), .io_lsu_agen_0_bits_uop_is_fence (_core_io_lsu_agen_0_bits_uop_is_fence), .io_lsu_agen_0_bits_uop_is_fencei (_core_io_lsu_agen_0_bits_uop_is_fencei), .io_lsu_agen_0_bits_uop_is_sfence (_core_io_lsu_agen_0_bits_uop_is_sfence), .io_lsu_agen_0_bits_uop_is_amo (_core_io_lsu_agen_0_bits_uop_is_amo), .io_lsu_agen_0_bits_uop_is_eret (_core_io_lsu_agen_0_bits_uop_is_eret), .io_lsu_agen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_agen_0_bits_uop_is_sys_pc2epc), .io_lsu_agen_0_bits_uop_is_rocc (_core_io_lsu_agen_0_bits_uop_is_rocc), .io_lsu_agen_0_bits_uop_is_mov (_core_io_lsu_agen_0_bits_uop_is_mov), .io_lsu_agen_0_bits_uop_ftq_idx (_core_io_lsu_agen_0_bits_uop_ftq_idx), .io_lsu_agen_0_bits_uop_edge_inst (_core_io_lsu_agen_0_bits_uop_edge_inst), .io_lsu_agen_0_bits_uop_pc_lob (_core_io_lsu_agen_0_bits_uop_pc_lob), .io_lsu_agen_0_bits_uop_taken (_core_io_lsu_agen_0_bits_uop_taken), .io_lsu_agen_0_bits_uop_imm_rename (_core_io_lsu_agen_0_bits_uop_imm_rename), .io_lsu_agen_0_bits_uop_imm_sel (_core_io_lsu_agen_0_bits_uop_imm_sel), .io_lsu_agen_0_bits_uop_pimm (_core_io_lsu_agen_0_bits_uop_pimm), .io_lsu_agen_0_bits_uop_imm_packed (_core_io_lsu_agen_0_bits_uop_imm_packed), .io_lsu_agen_0_bits_uop_op1_sel (_core_io_lsu_agen_0_bits_uop_op1_sel), .io_lsu_agen_0_bits_uop_op2_sel (_core_io_lsu_agen_0_bits_uop_op2_sel), .io_lsu_agen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ldst), .io_lsu_agen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wen), .io_lsu_agen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren1), .io_lsu_agen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren2), .io_lsu_agen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren3), .io_lsu_agen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap12), .io_lsu_agen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap23), .io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_agen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fromint), .io_lsu_agen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_toint), .io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_agen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fma), .io_lsu_agen_0_bits_uop_fp_ctrl_div (_core_io_lsu_agen_0_bits_uop_fp_ctrl_div), .io_lsu_agen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_agen_0_bits_uop_fp_ctrl_sqrt), .io_lsu_agen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wflags), .io_lsu_agen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_agen_0_bits_uop_fp_ctrl_vec), .io_lsu_agen_0_bits_uop_rob_idx (_core_io_lsu_agen_0_bits_uop_rob_idx), .io_lsu_agen_0_bits_uop_ldq_idx (_core_io_lsu_agen_0_bits_uop_ldq_idx), .io_lsu_agen_0_bits_uop_stq_idx (_core_io_lsu_agen_0_bits_uop_stq_idx), .io_lsu_agen_0_bits_uop_rxq_idx (_core_io_lsu_agen_0_bits_uop_rxq_idx), .io_lsu_agen_0_bits_uop_pdst (_core_io_lsu_agen_0_bits_uop_pdst), .io_lsu_agen_0_bits_uop_prs1 (_core_io_lsu_agen_0_bits_uop_prs1), .io_lsu_agen_0_bits_uop_prs2 (_core_io_lsu_agen_0_bits_uop_prs2), .io_lsu_agen_0_bits_uop_prs3 (_core_io_lsu_agen_0_bits_uop_prs3), .io_lsu_agen_0_bits_uop_ppred (_core_io_lsu_agen_0_bits_uop_ppred), .io_lsu_agen_0_bits_uop_prs1_busy (_core_io_lsu_agen_0_bits_uop_prs1_busy), .io_lsu_agen_0_bits_uop_prs2_busy (_core_io_lsu_agen_0_bits_uop_prs2_busy), .io_lsu_agen_0_bits_uop_prs3_busy (_core_io_lsu_agen_0_bits_uop_prs3_busy), .io_lsu_agen_0_bits_uop_ppred_busy (_core_io_lsu_agen_0_bits_uop_ppred_busy), .io_lsu_agen_0_bits_uop_stale_pdst (_core_io_lsu_agen_0_bits_uop_stale_pdst), .io_lsu_agen_0_bits_uop_exception (_core_io_lsu_agen_0_bits_uop_exception), .io_lsu_agen_0_bits_uop_exc_cause (_core_io_lsu_agen_0_bits_uop_exc_cause), .io_lsu_agen_0_bits_uop_mem_cmd (_core_io_lsu_agen_0_bits_uop_mem_cmd), .io_lsu_agen_0_bits_uop_mem_size (_core_io_lsu_agen_0_bits_uop_mem_size), .io_lsu_agen_0_bits_uop_mem_signed (_core_io_lsu_agen_0_bits_uop_mem_signed), .io_lsu_agen_0_bits_uop_uses_ldq (_core_io_lsu_agen_0_bits_uop_uses_ldq), .io_lsu_agen_0_bits_uop_uses_stq (_core_io_lsu_agen_0_bits_uop_uses_stq), .io_lsu_agen_0_bits_uop_is_unique (_core_io_lsu_agen_0_bits_uop_is_unique), .io_lsu_agen_0_bits_uop_flush_on_commit (_core_io_lsu_agen_0_bits_uop_flush_on_commit), .io_lsu_agen_0_bits_uop_csr_cmd (_core_io_lsu_agen_0_bits_uop_csr_cmd), .io_lsu_agen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_agen_0_bits_uop_ldst_is_rs1), .io_lsu_agen_0_bits_uop_ldst (_core_io_lsu_agen_0_bits_uop_ldst), .io_lsu_agen_0_bits_uop_lrs1 (_core_io_lsu_agen_0_bits_uop_lrs1), .io_lsu_agen_0_bits_uop_lrs2 (_core_io_lsu_agen_0_bits_uop_lrs2), .io_lsu_agen_0_bits_uop_lrs3 (_core_io_lsu_agen_0_bits_uop_lrs3), .io_lsu_agen_0_bits_uop_dst_rtype (_core_io_lsu_agen_0_bits_uop_dst_rtype), .io_lsu_agen_0_bits_uop_lrs1_rtype (_core_io_lsu_agen_0_bits_uop_lrs1_rtype), .io_lsu_agen_0_bits_uop_lrs2_rtype (_core_io_lsu_agen_0_bits_uop_lrs2_rtype), .io_lsu_agen_0_bits_uop_frs3_en (_core_io_lsu_agen_0_bits_uop_frs3_en), .io_lsu_agen_0_bits_uop_fcn_dw (_core_io_lsu_agen_0_bits_uop_fcn_dw), .io_lsu_agen_0_bits_uop_fcn_op (_core_io_lsu_agen_0_bits_uop_fcn_op), .io_lsu_agen_0_bits_uop_fp_val (_core_io_lsu_agen_0_bits_uop_fp_val), .io_lsu_agen_0_bits_uop_fp_rm (_core_io_lsu_agen_0_bits_uop_fp_rm), .io_lsu_agen_0_bits_uop_fp_typ (_core_io_lsu_agen_0_bits_uop_fp_typ), .io_lsu_agen_0_bits_uop_xcpt_pf_if (_core_io_lsu_agen_0_bits_uop_xcpt_pf_if), .io_lsu_agen_0_bits_uop_xcpt_ae_if (_core_io_lsu_agen_0_bits_uop_xcpt_ae_if), .io_lsu_agen_0_bits_uop_xcpt_ma_if (_core_io_lsu_agen_0_bits_uop_xcpt_ma_if), .io_lsu_agen_0_bits_uop_bp_debug_if (_core_io_lsu_agen_0_bits_uop_bp_debug_if), .io_lsu_agen_0_bits_uop_bp_xcpt_if (_core_io_lsu_agen_0_bits_uop_bp_xcpt_if), .io_lsu_agen_0_bits_uop_debug_fsrc (_core_io_lsu_agen_0_bits_uop_debug_fsrc), .io_lsu_agen_0_bits_uop_debug_tsrc (_core_io_lsu_agen_0_bits_uop_debug_tsrc), .io_lsu_agen_0_bits_data (_core_io_lsu_agen_0_bits_data), .io_lsu_dgen_0_valid (_core_io_lsu_dgen_0_valid), .io_lsu_dgen_0_bits_uop_inst (_core_io_lsu_dgen_0_bits_uop_inst), .io_lsu_dgen_0_bits_uop_debug_inst (_core_io_lsu_dgen_0_bits_uop_debug_inst), .io_lsu_dgen_0_bits_uop_is_rvc (_core_io_lsu_dgen_0_bits_uop_is_rvc), .io_lsu_dgen_0_bits_uop_debug_pc (_core_io_lsu_dgen_0_bits_uop_debug_pc), .io_lsu_dgen_0_bits_uop_iq_type_0 (_core_io_lsu_dgen_0_bits_uop_iq_type_0), .io_lsu_dgen_0_bits_uop_iq_type_1 (_core_io_lsu_dgen_0_bits_uop_iq_type_1), .io_lsu_dgen_0_bits_uop_iq_type_2 (_core_io_lsu_dgen_0_bits_uop_iq_type_2), .io_lsu_dgen_0_bits_uop_iq_type_3 (_core_io_lsu_dgen_0_bits_uop_iq_type_3), .io_lsu_dgen_0_bits_uop_fu_code_0 (_core_io_lsu_dgen_0_bits_uop_fu_code_0), .io_lsu_dgen_0_bits_uop_fu_code_1 (_core_io_lsu_dgen_0_bits_uop_fu_code_1), .io_lsu_dgen_0_bits_uop_fu_code_2 (_core_io_lsu_dgen_0_bits_uop_fu_code_2), .io_lsu_dgen_0_bits_uop_fu_code_3 (_core_io_lsu_dgen_0_bits_uop_fu_code_3), .io_lsu_dgen_0_bits_uop_fu_code_4 (_core_io_lsu_dgen_0_bits_uop_fu_code_4), .io_lsu_dgen_0_bits_uop_fu_code_5 (_core_io_lsu_dgen_0_bits_uop_fu_code_5), .io_lsu_dgen_0_bits_uop_fu_code_6 (_core_io_lsu_dgen_0_bits_uop_fu_code_6), .io_lsu_dgen_0_bits_uop_fu_code_7 (_core_io_lsu_dgen_0_bits_uop_fu_code_7), .io_lsu_dgen_0_bits_uop_fu_code_8 (_core_io_lsu_dgen_0_bits_uop_fu_code_8), .io_lsu_dgen_0_bits_uop_fu_code_9 (_core_io_lsu_dgen_0_bits_uop_fu_code_9), .io_lsu_dgen_0_bits_uop_iw_issued (_core_io_lsu_dgen_0_bits_uop_iw_issued), .io_lsu_dgen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_agen), .io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen), .io_lsu_dgen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p1_speculative_child), .io_lsu_dgen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p2_speculative_child), .io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint), .io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint), .io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint), .io_lsu_dgen_0_bits_uop_dis_col_sel (_core_io_lsu_dgen_0_bits_uop_dis_col_sel), .io_lsu_dgen_0_bits_uop_br_mask (_core_io_lsu_dgen_0_bits_uop_br_mask), .io_lsu_dgen_0_bits_uop_br_tag (_core_io_lsu_dgen_0_bits_uop_br_tag), .io_lsu_dgen_0_bits_uop_br_type (_core_io_lsu_dgen_0_bits_uop_br_type), .io_lsu_dgen_0_bits_uop_is_sfb (_core_io_lsu_dgen_0_bits_uop_is_sfb), .io_lsu_dgen_0_bits_uop_is_fence (_core_io_lsu_dgen_0_bits_uop_is_fence), .io_lsu_dgen_0_bits_uop_is_fencei (_core_io_lsu_dgen_0_bits_uop_is_fencei), .io_lsu_dgen_0_bits_uop_is_sfence (_core_io_lsu_dgen_0_bits_uop_is_sfence), .io_lsu_dgen_0_bits_uop_is_amo (_core_io_lsu_dgen_0_bits_uop_is_amo), .io_lsu_dgen_0_bits_uop_is_eret (_core_io_lsu_dgen_0_bits_uop_is_eret), .io_lsu_dgen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_0_bits_uop_is_sys_pc2epc), .io_lsu_dgen_0_bits_uop_is_rocc (_core_io_lsu_dgen_0_bits_uop_is_rocc), .io_lsu_dgen_0_bits_uop_is_mov (_core_io_lsu_dgen_0_bits_uop_is_mov), .io_lsu_dgen_0_bits_uop_ftq_idx (_core_io_lsu_dgen_0_bits_uop_ftq_idx), .io_lsu_dgen_0_bits_uop_edge_inst (_core_io_lsu_dgen_0_bits_uop_edge_inst), .io_lsu_dgen_0_bits_uop_pc_lob (_core_io_lsu_dgen_0_bits_uop_pc_lob), .io_lsu_dgen_0_bits_uop_taken (_core_io_lsu_dgen_0_bits_uop_taken), .io_lsu_dgen_0_bits_uop_imm_rename (_core_io_lsu_dgen_0_bits_uop_imm_rename), .io_lsu_dgen_0_bits_uop_imm_sel (_core_io_lsu_dgen_0_bits_uop_imm_sel), .io_lsu_dgen_0_bits_uop_pimm (_core_io_lsu_dgen_0_bits_uop_pimm), .io_lsu_dgen_0_bits_uop_imm_packed (_core_io_lsu_dgen_0_bits_uop_imm_packed), .io_lsu_dgen_0_bits_uop_op1_sel (_core_io_lsu_dgen_0_bits_uop_op1_sel), .io_lsu_dgen_0_bits_uop_op2_sel (_core_io_lsu_dgen_0_bits_uop_op2_sel), .io_lsu_dgen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ldst), .io_lsu_dgen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wen), .io_lsu_dgen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren1), .io_lsu_dgen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren2), .io_lsu_dgen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren3), .io_lsu_dgen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap12), .io_lsu_dgen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap23), .io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn), .io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut), .io_lsu_dgen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fromint), .io_lsu_dgen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_toint), .io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe), .io_lsu_dgen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fma), .io_lsu_dgen_0_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_div), .io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt), .io_lsu_dgen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wflags), .io_lsu_dgen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_vec), .io_lsu_dgen_0_bits_uop_rob_idx (_core_io_lsu_dgen_0_bits_uop_rob_idx), .io_lsu_dgen_0_bits_uop_ldq_idx (_core_io_lsu_dgen_0_bits_uop_ldq_idx), .io_lsu_dgen_0_bits_uop_stq_idx (_core_io_lsu_dgen_0_bits_uop_stq_idx), .io_lsu_dgen_0_bits_uop_rxq_idx (_core_io_lsu_dgen_0_bits_uop_rxq_idx), .io_lsu_dgen_0_bits_uop_pdst (_core_io_lsu_dgen_0_bits_uop_pdst), .io_lsu_dgen_0_bits_uop_prs1 (_core_io_lsu_dgen_0_bits_uop_prs1), .io_lsu_dgen_0_bits_uop_prs2 (_core_io_lsu_dgen_0_bits_uop_prs2), .io_lsu_dgen_0_bits_uop_prs3 (_core_io_lsu_dgen_0_bits_uop_prs3), .io_lsu_dgen_0_bits_uop_ppred (_core_io_lsu_dgen_0_bits_uop_ppred), .io_lsu_dgen_0_bits_uop_prs1_busy (_core_io_lsu_dgen_0_bits_uop_prs1_busy), .io_lsu_dgen_0_bits_uop_prs2_busy (_core_io_lsu_dgen_0_bits_uop_prs2_busy), .io_lsu_dgen_0_bits_uop_prs3_busy (_core_io_lsu_dgen_0_bits_uop_prs3_busy), .io_lsu_dgen_0_bits_uop_ppred_busy (_core_io_lsu_dgen_0_bits_uop_ppred_busy), .io_lsu_dgen_0_bits_uop_stale_pdst (_core_io_lsu_dgen_0_bits_uop_stale_pdst), .io_lsu_dgen_0_bits_uop_exception (_core_io_lsu_dgen_0_bits_uop_exception), .io_lsu_dgen_0_bits_uop_exc_cause (_core_io_lsu_dgen_0_bits_uop_exc_cause), .io_lsu_dgen_0_bits_uop_mem_cmd (_core_io_lsu_dgen_0_bits_uop_mem_cmd), .io_lsu_dgen_0_bits_uop_mem_size (_core_io_lsu_dgen_0_bits_uop_mem_size), .io_lsu_dgen_0_bits_uop_mem_signed (_core_io_lsu_dgen_0_bits_uop_mem_signed), .io_lsu_dgen_0_bits_uop_uses_ldq (_core_io_lsu_dgen_0_bits_uop_uses_ldq), .io_lsu_dgen_0_bits_uop_uses_stq (_core_io_lsu_dgen_0_bits_uop_uses_stq), .io_lsu_dgen_0_bits_uop_is_unique (_core_io_lsu_dgen_0_bits_uop_is_unique), .io_lsu_dgen_0_bits_uop_flush_on_commit (_core_io_lsu_dgen_0_bits_uop_flush_on_commit), .io_lsu_dgen_0_bits_uop_csr_cmd (_core_io_lsu_dgen_0_bits_uop_csr_cmd), .io_lsu_dgen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_0_bits_uop_ldst_is_rs1), .io_lsu_dgen_0_bits_uop_ldst (_core_io_lsu_dgen_0_bits_uop_ldst), .io_lsu_dgen_0_bits_uop_lrs1 (_core_io_lsu_dgen_0_bits_uop_lrs1), .io_lsu_dgen_0_bits_uop_lrs2 (_core_io_lsu_dgen_0_bits_uop_lrs2), .io_lsu_dgen_0_bits_uop_lrs3 (_core_io_lsu_dgen_0_bits_uop_lrs3), .io_lsu_dgen_0_bits_uop_dst_rtype (_core_io_lsu_dgen_0_bits_uop_dst_rtype), .io_lsu_dgen_0_bits_uop_lrs1_rtype (_core_io_lsu_dgen_0_bits_uop_lrs1_rtype), .io_lsu_dgen_0_bits_uop_lrs2_rtype (_core_io_lsu_dgen_0_bits_uop_lrs2_rtype), .io_lsu_dgen_0_bits_uop_frs3_en (_core_io_lsu_dgen_0_bits_uop_frs3_en), .io_lsu_dgen_0_bits_uop_fcn_dw (_core_io_lsu_dgen_0_bits_uop_fcn_dw), .io_lsu_dgen_0_bits_uop_fcn_op (_core_io_lsu_dgen_0_bits_uop_fcn_op), .io_lsu_dgen_0_bits_uop_fp_val (_core_io_lsu_dgen_0_bits_uop_fp_val), .io_lsu_dgen_0_bits_uop_fp_rm (_core_io_lsu_dgen_0_bits_uop_fp_rm), .io_lsu_dgen_0_bits_uop_fp_typ (_core_io_lsu_dgen_0_bits_uop_fp_typ), .io_lsu_dgen_0_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_0_bits_uop_xcpt_pf_if), .io_lsu_dgen_0_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ae_if), .io_lsu_dgen_0_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ma_if), .io_lsu_dgen_0_bits_uop_bp_debug_if (_core_io_lsu_dgen_0_bits_uop_bp_debug_if), .io_lsu_dgen_0_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_0_bits_uop_bp_xcpt_if), .io_lsu_dgen_0_bits_uop_debug_fsrc (_core_io_lsu_dgen_0_bits_uop_debug_fsrc), .io_lsu_dgen_0_bits_uop_debug_tsrc (_core_io_lsu_dgen_0_bits_uop_debug_tsrc), .io_lsu_dgen_0_bits_data (_core_io_lsu_dgen_0_bits_data), .io_lsu_dgen_1_valid (_core_io_lsu_dgen_1_valid), .io_lsu_dgen_1_bits_uop_inst (_core_io_lsu_dgen_1_bits_uop_inst), .io_lsu_dgen_1_bits_uop_debug_inst (_core_io_lsu_dgen_1_bits_uop_debug_inst), .io_lsu_dgen_1_bits_uop_is_rvc (_core_io_lsu_dgen_1_bits_uop_is_rvc), .io_lsu_dgen_1_bits_uop_debug_pc (_core_io_lsu_dgen_1_bits_uop_debug_pc), .io_lsu_dgen_1_bits_uop_iq_type_0 (_core_io_lsu_dgen_1_bits_uop_iq_type_0), .io_lsu_dgen_1_bits_uop_iq_type_1 (_core_io_lsu_dgen_1_bits_uop_iq_type_1), .io_lsu_dgen_1_bits_uop_iq_type_2 (_core_io_lsu_dgen_1_bits_uop_iq_type_2), .io_lsu_dgen_1_bits_uop_iq_type_3 (_core_io_lsu_dgen_1_bits_uop_iq_type_3), .io_lsu_dgen_1_bits_uop_fu_code_0 (_core_io_lsu_dgen_1_bits_uop_fu_code_0), .io_lsu_dgen_1_bits_uop_fu_code_1 (_core_io_lsu_dgen_1_bits_uop_fu_code_1), .io_lsu_dgen_1_bits_uop_fu_code_2 (_core_io_lsu_dgen_1_bits_uop_fu_code_2), .io_lsu_dgen_1_bits_uop_fu_code_3 (_core_io_lsu_dgen_1_bits_uop_fu_code_3), .io_lsu_dgen_1_bits_uop_fu_code_4 (_core_io_lsu_dgen_1_bits_uop_fu_code_4), .io_lsu_dgen_1_bits_uop_fu_code_5 (_core_io_lsu_dgen_1_bits_uop_fu_code_5), .io_lsu_dgen_1_bits_uop_fu_code_6 (_core_io_lsu_dgen_1_bits_uop_fu_code_6), .io_lsu_dgen_1_bits_uop_fu_code_7 (_core_io_lsu_dgen_1_bits_uop_fu_code_7), .io_lsu_dgen_1_bits_uop_fu_code_8 (_core_io_lsu_dgen_1_bits_uop_fu_code_8), .io_lsu_dgen_1_bits_uop_fu_code_9 (_core_io_lsu_dgen_1_bits_uop_fu_code_9), .io_lsu_dgen_1_bits_uop_iw_issued (_core_io_lsu_dgen_1_bits_uop_iw_issued), .io_lsu_dgen_1_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_agen), .io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen), .io_lsu_dgen_1_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p1_speculative_child), .io_lsu_dgen_1_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p2_speculative_child), .io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint), .io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint), .io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint), .io_lsu_dgen_1_bits_uop_dis_col_sel (_core_io_lsu_dgen_1_bits_uop_dis_col_sel), .io_lsu_dgen_1_bits_uop_br_mask (_core_io_lsu_dgen_1_bits_uop_br_mask), .io_lsu_dgen_1_bits_uop_br_tag (_core_io_lsu_dgen_1_bits_uop_br_tag), .io_lsu_dgen_1_bits_uop_br_type (_core_io_lsu_dgen_1_bits_uop_br_type), .io_lsu_dgen_1_bits_uop_is_sfb (_core_io_lsu_dgen_1_bits_uop_is_sfb), .io_lsu_dgen_1_bits_uop_is_fence (_core_io_lsu_dgen_1_bits_uop_is_fence), .io_lsu_dgen_1_bits_uop_is_fencei (_core_io_lsu_dgen_1_bits_uop_is_fencei), .io_lsu_dgen_1_bits_uop_is_sfence (_core_io_lsu_dgen_1_bits_uop_is_sfence), .io_lsu_dgen_1_bits_uop_is_amo (_core_io_lsu_dgen_1_bits_uop_is_amo), .io_lsu_dgen_1_bits_uop_is_eret (_core_io_lsu_dgen_1_bits_uop_is_eret), .io_lsu_dgen_1_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_1_bits_uop_is_sys_pc2epc), .io_lsu_dgen_1_bits_uop_is_rocc (_core_io_lsu_dgen_1_bits_uop_is_rocc), .io_lsu_dgen_1_bits_uop_is_mov (_core_io_lsu_dgen_1_bits_uop_is_mov), .io_lsu_dgen_1_bits_uop_ftq_idx (_core_io_lsu_dgen_1_bits_uop_ftq_idx), .io_lsu_dgen_1_bits_uop_edge_inst (_core_io_lsu_dgen_1_bits_uop_edge_inst), .io_lsu_dgen_1_bits_uop_pc_lob (_core_io_lsu_dgen_1_bits_uop_pc_lob), .io_lsu_dgen_1_bits_uop_taken (_core_io_lsu_dgen_1_bits_uop_taken), .io_lsu_dgen_1_bits_uop_imm_rename (_core_io_lsu_dgen_1_bits_uop_imm_rename), .io_lsu_dgen_1_bits_uop_imm_sel (_core_io_lsu_dgen_1_bits_uop_imm_sel), .io_lsu_dgen_1_bits_uop_pimm (_core_io_lsu_dgen_1_bits_uop_pimm), .io_lsu_dgen_1_bits_uop_imm_packed (_core_io_lsu_dgen_1_bits_uop_imm_packed), .io_lsu_dgen_1_bits_uop_op1_sel (_core_io_lsu_dgen_1_bits_uop_op1_sel), .io_lsu_dgen_1_bits_uop_op2_sel (_core_io_lsu_dgen_1_bits_uop_op2_sel), .io_lsu_dgen_1_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ldst), .io_lsu_dgen_1_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wen), .io_lsu_dgen_1_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren1), .io_lsu_dgen_1_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren2), .io_lsu_dgen_1_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren3), .io_lsu_dgen_1_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap12), .io_lsu_dgen_1_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap23), .io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn), .io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut), .io_lsu_dgen_1_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fromint), .io_lsu_dgen_1_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_toint), .io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe), .io_lsu_dgen_1_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fma), .io_lsu_dgen_1_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_div), .io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt), .io_lsu_dgen_1_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wflags), .io_lsu_dgen_1_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_vec), .io_lsu_dgen_1_bits_uop_rob_idx (_core_io_lsu_dgen_1_bits_uop_rob_idx), .io_lsu_dgen_1_bits_uop_ldq_idx (_core_io_lsu_dgen_1_bits_uop_ldq_idx), .io_lsu_dgen_1_bits_uop_stq_idx (_core_io_lsu_dgen_1_bits_uop_stq_idx), .io_lsu_dgen_1_bits_uop_rxq_idx (_core_io_lsu_dgen_1_bits_uop_rxq_idx), .io_lsu_dgen_1_bits_uop_pdst (_core_io_lsu_dgen_1_bits_uop_pdst), .io_lsu_dgen_1_bits_uop_prs1 (_core_io_lsu_dgen_1_bits_uop_prs1), .io_lsu_dgen_1_bits_uop_prs2 (_core_io_lsu_dgen_1_bits_uop_prs2), .io_lsu_dgen_1_bits_uop_prs3 (_core_io_lsu_dgen_1_bits_uop_prs3), .io_lsu_dgen_1_bits_uop_ppred (_core_io_lsu_dgen_1_bits_uop_ppred), .io_lsu_dgen_1_bits_uop_prs1_busy (_core_io_lsu_dgen_1_bits_uop_prs1_busy), .io_lsu_dgen_1_bits_uop_prs2_busy (_core_io_lsu_dgen_1_bits_uop_prs2_busy), .io_lsu_dgen_1_bits_uop_prs3_busy (_core_io_lsu_dgen_1_bits_uop_prs3_busy), .io_lsu_dgen_1_bits_uop_ppred_busy (_core_io_lsu_dgen_1_bits_uop_ppred_busy), .io_lsu_dgen_1_bits_uop_stale_pdst (_core_io_lsu_dgen_1_bits_uop_stale_pdst), .io_lsu_dgen_1_bits_uop_exception (_core_io_lsu_dgen_1_bits_uop_exception), .io_lsu_dgen_1_bits_uop_exc_cause (_core_io_lsu_dgen_1_bits_uop_exc_cause), .io_lsu_dgen_1_bits_uop_mem_cmd (_core_io_lsu_dgen_1_bits_uop_mem_cmd), .io_lsu_dgen_1_bits_uop_mem_size (_core_io_lsu_dgen_1_bits_uop_mem_size), .io_lsu_dgen_1_bits_uop_mem_signed (_core_io_lsu_dgen_1_bits_uop_mem_signed), .io_lsu_dgen_1_bits_uop_uses_ldq (_core_io_lsu_dgen_1_bits_uop_uses_ldq), .io_lsu_dgen_1_bits_uop_uses_stq (_core_io_lsu_dgen_1_bits_uop_uses_stq), .io_lsu_dgen_1_bits_uop_is_unique (_core_io_lsu_dgen_1_bits_uop_is_unique), .io_lsu_dgen_1_bits_uop_flush_on_commit (_core_io_lsu_dgen_1_bits_uop_flush_on_commit), .io_lsu_dgen_1_bits_uop_csr_cmd (_core_io_lsu_dgen_1_bits_uop_csr_cmd), .io_lsu_dgen_1_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_1_bits_uop_ldst_is_rs1), .io_lsu_dgen_1_bits_uop_ldst (_core_io_lsu_dgen_1_bits_uop_ldst), .io_lsu_dgen_1_bits_uop_lrs1 (_core_io_lsu_dgen_1_bits_uop_lrs1), .io_lsu_dgen_1_bits_uop_lrs2 (_core_io_lsu_dgen_1_bits_uop_lrs2), .io_lsu_dgen_1_bits_uop_lrs3 (_core_io_lsu_dgen_1_bits_uop_lrs3), .io_lsu_dgen_1_bits_uop_dst_rtype (_core_io_lsu_dgen_1_bits_uop_dst_rtype), .io_lsu_dgen_1_bits_uop_lrs1_rtype (_core_io_lsu_dgen_1_bits_uop_lrs1_rtype), .io_lsu_dgen_1_bits_uop_lrs2_rtype (_core_io_lsu_dgen_1_bits_uop_lrs2_rtype), .io_lsu_dgen_1_bits_uop_frs3_en (_core_io_lsu_dgen_1_bits_uop_frs3_en), .io_lsu_dgen_1_bits_uop_fcn_dw (_core_io_lsu_dgen_1_bits_uop_fcn_dw), .io_lsu_dgen_1_bits_uop_fcn_op (_core_io_lsu_dgen_1_bits_uop_fcn_op), .io_lsu_dgen_1_bits_uop_fp_val (_core_io_lsu_dgen_1_bits_uop_fp_val), .io_lsu_dgen_1_bits_uop_fp_rm (_core_io_lsu_dgen_1_bits_uop_fp_rm), .io_lsu_dgen_1_bits_uop_fp_typ (_core_io_lsu_dgen_1_bits_uop_fp_typ), .io_lsu_dgen_1_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_1_bits_uop_xcpt_pf_if), .io_lsu_dgen_1_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ae_if), .io_lsu_dgen_1_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ma_if), .io_lsu_dgen_1_bits_uop_bp_debug_if (_core_io_lsu_dgen_1_bits_uop_bp_debug_if), .io_lsu_dgen_1_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_1_bits_uop_bp_xcpt_if), .io_lsu_dgen_1_bits_uop_debug_fsrc (_core_io_lsu_dgen_1_bits_uop_debug_fsrc), .io_lsu_dgen_1_bits_uop_debug_tsrc (_core_io_lsu_dgen_1_bits_uop_debug_tsrc), .io_lsu_dgen_1_bits_data (_core_io_lsu_dgen_1_bits_data), .io_lsu_dgen_2_valid (_core_io_lsu_dgen_2_valid), .io_lsu_dgen_2_bits_uop_inst (_core_io_lsu_dgen_2_bits_uop_inst), .io_lsu_dgen_2_bits_uop_debug_inst (_core_io_lsu_dgen_2_bits_uop_debug_inst), .io_lsu_dgen_2_bits_uop_is_rvc (_core_io_lsu_dgen_2_bits_uop_is_rvc), .io_lsu_dgen_2_bits_uop_debug_pc (_core_io_lsu_dgen_2_bits_uop_debug_pc), .io_lsu_dgen_2_bits_uop_iq_type_0 (_core_io_lsu_dgen_2_bits_uop_iq_type_0), .io_lsu_dgen_2_bits_uop_iq_type_1 (_core_io_lsu_dgen_2_bits_uop_iq_type_1), .io_lsu_dgen_2_bits_uop_iq_type_2 (_core_io_lsu_dgen_2_bits_uop_iq_type_2), .io_lsu_dgen_2_bits_uop_iq_type_3 (_core_io_lsu_dgen_2_bits_uop_iq_type_3), .io_lsu_dgen_2_bits_uop_fu_code_0 (_core_io_lsu_dgen_2_bits_uop_fu_code_0), .io_lsu_dgen_2_bits_uop_fu_code_1 (_core_io_lsu_dgen_2_bits_uop_fu_code_1), .io_lsu_dgen_2_bits_uop_fu_code_2 (_core_io_lsu_dgen_2_bits_uop_fu_code_2), .io_lsu_dgen_2_bits_uop_fu_code_3 (_core_io_lsu_dgen_2_bits_uop_fu_code_3), .io_lsu_dgen_2_bits_uop_fu_code_4 (_core_io_lsu_dgen_2_bits_uop_fu_code_4), .io_lsu_dgen_2_bits_uop_fu_code_5 (_core_io_lsu_dgen_2_bits_uop_fu_code_5), .io_lsu_dgen_2_bits_uop_fu_code_6 (_core_io_lsu_dgen_2_bits_uop_fu_code_6), .io_lsu_dgen_2_bits_uop_fu_code_7 (_core_io_lsu_dgen_2_bits_uop_fu_code_7), .io_lsu_dgen_2_bits_uop_fu_code_8 (_core_io_lsu_dgen_2_bits_uop_fu_code_8), .io_lsu_dgen_2_bits_uop_fu_code_9 (_core_io_lsu_dgen_2_bits_uop_fu_code_9), .io_lsu_dgen_2_bits_uop_iw_issued (_core_io_lsu_dgen_2_bits_uop_iw_issued), .io_lsu_dgen_2_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_agen), .io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen), .io_lsu_dgen_2_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p1_speculative_child), .io_lsu_dgen_2_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p2_speculative_child), .io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint), .io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint), .io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint), .io_lsu_dgen_2_bits_uop_dis_col_sel (_core_io_lsu_dgen_2_bits_uop_dis_col_sel), .io_lsu_dgen_2_bits_uop_br_mask (_core_io_lsu_dgen_2_bits_uop_br_mask), .io_lsu_dgen_2_bits_uop_br_tag (_core_io_lsu_dgen_2_bits_uop_br_tag), .io_lsu_dgen_2_bits_uop_br_type (_core_io_lsu_dgen_2_bits_uop_br_type), .io_lsu_dgen_2_bits_uop_is_sfb (_core_io_lsu_dgen_2_bits_uop_is_sfb), .io_lsu_dgen_2_bits_uop_is_fence (_core_io_lsu_dgen_2_bits_uop_is_fence), .io_lsu_dgen_2_bits_uop_is_fencei (_core_io_lsu_dgen_2_bits_uop_is_fencei), .io_lsu_dgen_2_bits_uop_is_sfence (_core_io_lsu_dgen_2_bits_uop_is_sfence), .io_lsu_dgen_2_bits_uop_is_amo (_core_io_lsu_dgen_2_bits_uop_is_amo), .io_lsu_dgen_2_bits_uop_is_eret (_core_io_lsu_dgen_2_bits_uop_is_eret), .io_lsu_dgen_2_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_2_bits_uop_is_sys_pc2epc), .io_lsu_dgen_2_bits_uop_is_rocc (_core_io_lsu_dgen_2_bits_uop_is_rocc), .io_lsu_dgen_2_bits_uop_is_mov (_core_io_lsu_dgen_2_bits_uop_is_mov), .io_lsu_dgen_2_bits_uop_ftq_idx (_core_io_lsu_dgen_2_bits_uop_ftq_idx), .io_lsu_dgen_2_bits_uop_edge_inst (_core_io_lsu_dgen_2_bits_uop_edge_inst), .io_lsu_dgen_2_bits_uop_pc_lob (_core_io_lsu_dgen_2_bits_uop_pc_lob), .io_lsu_dgen_2_bits_uop_taken (_core_io_lsu_dgen_2_bits_uop_taken), .io_lsu_dgen_2_bits_uop_imm_rename (_core_io_lsu_dgen_2_bits_uop_imm_rename), .io_lsu_dgen_2_bits_uop_imm_sel (_core_io_lsu_dgen_2_bits_uop_imm_sel), .io_lsu_dgen_2_bits_uop_pimm (_core_io_lsu_dgen_2_bits_uop_pimm), .io_lsu_dgen_2_bits_uop_imm_packed (_core_io_lsu_dgen_2_bits_uop_imm_packed), .io_lsu_dgen_2_bits_uop_op1_sel (_core_io_lsu_dgen_2_bits_uop_op1_sel), .io_lsu_dgen_2_bits_uop_op2_sel (_core_io_lsu_dgen_2_bits_uop_op2_sel), .io_lsu_dgen_2_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ldst), .io_lsu_dgen_2_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wen), .io_lsu_dgen_2_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren1), .io_lsu_dgen_2_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren2), .io_lsu_dgen_2_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren3), .io_lsu_dgen_2_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap12), .io_lsu_dgen_2_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap23), .io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn), .io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut), .io_lsu_dgen_2_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fromint), .io_lsu_dgen_2_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_toint), .io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe), .io_lsu_dgen_2_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fma), .io_lsu_dgen_2_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_div), .io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt), .io_lsu_dgen_2_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wflags), .io_lsu_dgen_2_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_vec), .io_lsu_dgen_2_bits_uop_rob_idx (_core_io_lsu_dgen_2_bits_uop_rob_idx), .io_lsu_dgen_2_bits_uop_ldq_idx (_core_io_lsu_dgen_2_bits_uop_ldq_idx), .io_lsu_dgen_2_bits_uop_stq_idx (_core_io_lsu_dgen_2_bits_uop_stq_idx), .io_lsu_dgen_2_bits_uop_rxq_idx (_core_io_lsu_dgen_2_bits_uop_rxq_idx), .io_lsu_dgen_2_bits_uop_pdst (_core_io_lsu_dgen_2_bits_uop_pdst), .io_lsu_dgen_2_bits_uop_prs1 (_core_io_lsu_dgen_2_bits_uop_prs1), .io_lsu_dgen_2_bits_uop_prs2 (_core_io_lsu_dgen_2_bits_uop_prs2), .io_lsu_dgen_2_bits_uop_prs3 (_core_io_lsu_dgen_2_bits_uop_prs3), .io_lsu_dgen_2_bits_uop_ppred (_core_io_lsu_dgen_2_bits_uop_ppred), .io_lsu_dgen_2_bits_uop_prs1_busy (_core_io_lsu_dgen_2_bits_uop_prs1_busy), .io_lsu_dgen_2_bits_uop_prs2_busy (_core_io_lsu_dgen_2_bits_uop_prs2_busy), .io_lsu_dgen_2_bits_uop_prs3_busy (_core_io_lsu_dgen_2_bits_uop_prs3_busy), .io_lsu_dgen_2_bits_uop_ppred_busy (_core_io_lsu_dgen_2_bits_uop_ppred_busy), .io_lsu_dgen_2_bits_uop_stale_pdst (_core_io_lsu_dgen_2_bits_uop_stale_pdst), .io_lsu_dgen_2_bits_uop_exception (_core_io_lsu_dgen_2_bits_uop_exception), .io_lsu_dgen_2_bits_uop_exc_cause (_core_io_lsu_dgen_2_bits_uop_exc_cause), .io_lsu_dgen_2_bits_uop_mem_cmd (_core_io_lsu_dgen_2_bits_uop_mem_cmd), .io_lsu_dgen_2_bits_uop_mem_size (_core_io_lsu_dgen_2_bits_uop_mem_size), .io_lsu_dgen_2_bits_uop_mem_signed (_core_io_lsu_dgen_2_bits_uop_mem_signed), .io_lsu_dgen_2_bits_uop_uses_ldq (_core_io_lsu_dgen_2_bits_uop_uses_ldq), .io_lsu_dgen_2_bits_uop_uses_stq (_core_io_lsu_dgen_2_bits_uop_uses_stq), .io_lsu_dgen_2_bits_uop_is_unique (_core_io_lsu_dgen_2_bits_uop_is_unique), .io_lsu_dgen_2_bits_uop_flush_on_commit (_core_io_lsu_dgen_2_bits_uop_flush_on_commit), .io_lsu_dgen_2_bits_uop_csr_cmd (_core_io_lsu_dgen_2_bits_uop_csr_cmd), .io_lsu_dgen_2_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_2_bits_uop_ldst_is_rs1), .io_lsu_dgen_2_bits_uop_ldst (_core_io_lsu_dgen_2_bits_uop_ldst), .io_lsu_dgen_2_bits_uop_lrs1 (_core_io_lsu_dgen_2_bits_uop_lrs1), .io_lsu_dgen_2_bits_uop_lrs2 (_core_io_lsu_dgen_2_bits_uop_lrs2), .io_lsu_dgen_2_bits_uop_lrs3 (_core_io_lsu_dgen_2_bits_uop_lrs3), .io_lsu_dgen_2_bits_uop_dst_rtype (_core_io_lsu_dgen_2_bits_uop_dst_rtype), .io_lsu_dgen_2_bits_uop_lrs1_rtype (_core_io_lsu_dgen_2_bits_uop_lrs1_rtype), .io_lsu_dgen_2_bits_uop_lrs2_rtype (_core_io_lsu_dgen_2_bits_uop_lrs2_rtype), .io_lsu_dgen_2_bits_uop_frs3_en (_core_io_lsu_dgen_2_bits_uop_frs3_en), .io_lsu_dgen_2_bits_uop_fcn_dw (_core_io_lsu_dgen_2_bits_uop_fcn_dw), .io_lsu_dgen_2_bits_uop_fcn_op (_core_io_lsu_dgen_2_bits_uop_fcn_op), .io_lsu_dgen_2_bits_uop_fp_val (_core_io_lsu_dgen_2_bits_uop_fp_val), .io_lsu_dgen_2_bits_uop_fp_rm (_core_io_lsu_dgen_2_bits_uop_fp_rm), .io_lsu_dgen_2_bits_uop_fp_typ (_core_io_lsu_dgen_2_bits_uop_fp_typ), .io_lsu_dgen_2_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_2_bits_uop_xcpt_pf_if), .io_lsu_dgen_2_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ae_if), .io_lsu_dgen_2_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ma_if), .io_lsu_dgen_2_bits_uop_bp_debug_if (_core_io_lsu_dgen_2_bits_uop_bp_debug_if), .io_lsu_dgen_2_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_2_bits_uop_bp_xcpt_if), .io_lsu_dgen_2_bits_uop_debug_fsrc (_core_io_lsu_dgen_2_bits_uop_debug_fsrc), .io_lsu_dgen_2_bits_uop_debug_tsrc (_core_io_lsu_dgen_2_bits_uop_debug_tsrc), .io_lsu_dgen_2_bits_data (_core_io_lsu_dgen_2_bits_data), .io_lsu_iwakeups_0_valid (_lsu_io_core_iwakeups_0_valid), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_inst (_lsu_io_core_iwakeups_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_inst (_lsu_io_core_iwakeups_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_rvc (_lsu_io_core_iwakeups_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_pc (_lsu_io_core_iwakeups_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_0 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_1 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_2 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iq_type_3 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_0 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_1 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_2 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_3 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_4 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_5 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_6 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_7 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_8 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fu_code_9 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_issued (_lsu_io_core_iwakeups_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_dis_col_sel (_lsu_io_core_iwakeups_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_br_mask (_lsu_io_core_iwakeups_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_br_tag (_lsu_io_core_iwakeups_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_br_type (_lsu_io_core_iwakeups_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_sfb (_lsu_io_core_iwakeups_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_fence (_lsu_io_core_iwakeups_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_fencei (_lsu_io_core_iwakeups_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_sfence (_lsu_io_core_iwakeups_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_amo (_lsu_io_core_iwakeups_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_eret (_lsu_io_core_iwakeups_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iwakeups_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_rocc (_lsu_io_core_iwakeups_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_mov (_lsu_io_core_iwakeups_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ftq_idx (_lsu_io_core_iwakeups_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_edge_inst (_lsu_io_core_iwakeups_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_pc_lob (_lsu_io_core_iwakeups_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_taken (_lsu_io_core_iwakeups_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_imm_rename (_lsu_io_core_iwakeups_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_imm_sel (_lsu_io_core_iwakeups_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_pimm (_lsu_io_core_iwakeups_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_imm_packed (_lsu_io_core_iwakeups_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_op1_sel (_lsu_io_core_iwakeups_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_op2_sel (_lsu_io_core_iwakeups_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_div (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_rob_idx (_lsu_io_core_iwakeups_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ldq_idx (_lsu_io_core_iwakeups_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_stq_idx (_lsu_io_core_iwakeups_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_rxq_idx (_lsu_io_core_iwakeups_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_pdst (_lsu_io_core_iwakeups_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs1 (_lsu_io_core_iwakeups_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs2 (_lsu_io_core_iwakeups_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs3 (_lsu_io_core_iwakeups_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ppred (_lsu_io_core_iwakeups_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs1_busy (_lsu_io_core_iwakeups_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs2_busy (_lsu_io_core_iwakeups_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_prs3_busy (_lsu_io_core_iwakeups_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ppred_busy (_lsu_io_core_iwakeups_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_stale_pdst (_lsu_io_core_iwakeups_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_exception (_lsu_io_core_iwakeups_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_exc_cause (_lsu_io_core_iwakeups_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_mem_cmd (_lsu_io_core_iwakeups_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_mem_size (_lsu_io_core_iwakeups_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_mem_signed (_lsu_io_core_iwakeups_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_uses_ldq (_lsu_io_core_iwakeups_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_uses_stq (_lsu_io_core_iwakeups_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_is_unique (_lsu_io_core_iwakeups_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_flush_on_commit (_lsu_io_core_iwakeups_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_csr_cmd (_lsu_io_core_iwakeups_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iwakeups_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_ldst (_lsu_io_core_iwakeups_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs1 (_lsu_io_core_iwakeups_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs2 (_lsu_io_core_iwakeups_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs3 (_lsu_io_core_iwakeups_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_dst_rtype (_lsu_io_core_iwakeups_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs1_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_lrs2_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_frs3_en (_lsu_io_core_iwakeups_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fcn_dw (_lsu_io_core_iwakeups_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fcn_op (_lsu_io_core_iwakeups_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_val (_lsu_io_core_iwakeups_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_rm (_lsu_io_core_iwakeups_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_fp_typ (_lsu_io_core_iwakeups_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_xcpt_pf_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_xcpt_ae_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_xcpt_ma_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_bp_debug_if (_lsu_io_core_iwakeups_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_bp_xcpt_if (_lsu_io_core_iwakeups_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_fsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_uop_debug_tsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_bypassable (_lsu_io_core_iwakeups_0_bits_bypassable), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_speculative_mask (_lsu_io_core_iwakeups_0_bits_speculative_mask), // @[tile.scala:159:20] .io_lsu_iwakeups_0_bits_rebusy (_lsu_io_core_iwakeups_0_bits_rebusy), // @[tile.scala:159:20] .io_lsu_iresp_0_valid (_lsu_io_core_iresp_0_valid), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_inst (_lsu_io_core_iresp_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_inst (_lsu_io_core_iresp_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_rvc (_lsu_io_core_iresp_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_pc (_lsu_io_core_iresp_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_0 (_lsu_io_core_iresp_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_1 (_lsu_io_core_iresp_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_2 (_lsu_io_core_iresp_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iq_type_3 (_lsu_io_core_iresp_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_0 (_lsu_io_core_iresp_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_1 (_lsu_io_core_iresp_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_2 (_lsu_io_core_iresp_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_3 (_lsu_io_core_iresp_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_4 (_lsu_io_core_iresp_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_5 (_lsu_io_core_iresp_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_6 (_lsu_io_core_iresp_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_7 (_lsu_io_core_iresp_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_8 (_lsu_io_core_iresp_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fu_code_9 (_lsu_io_core_iresp_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_issued (_lsu_io_core_iresp_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_dis_col_sel (_lsu_io_core_iresp_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_br_mask (_lsu_io_core_iresp_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_br_tag (_lsu_io_core_iresp_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_br_type (_lsu_io_core_iresp_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_sfb (_lsu_io_core_iresp_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_fence (_lsu_io_core_iresp_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_fencei (_lsu_io_core_iresp_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_sfence (_lsu_io_core_iresp_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_amo (_lsu_io_core_iresp_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_eret (_lsu_io_core_iresp_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iresp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_rocc (_lsu_io_core_iresp_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_mov (_lsu_io_core_iresp_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ftq_idx (_lsu_io_core_iresp_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_edge_inst (_lsu_io_core_iresp_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_pc_lob (_lsu_io_core_iresp_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_taken (_lsu_io_core_iresp_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_imm_rename (_lsu_io_core_iresp_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_imm_sel (_lsu_io_core_iresp_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_pimm (_lsu_io_core_iresp_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_imm_packed (_lsu_io_core_iresp_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_op1_sel (_lsu_io_core_iresp_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_op2_sel (_lsu_io_core_iresp_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_rob_idx (_lsu_io_core_iresp_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ldq_idx (_lsu_io_core_iresp_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_stq_idx (_lsu_io_core_iresp_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_rxq_idx (_lsu_io_core_iresp_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_pdst (_lsu_io_core_iresp_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs1 (_lsu_io_core_iresp_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs2 (_lsu_io_core_iresp_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs3 (_lsu_io_core_iresp_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ppred (_lsu_io_core_iresp_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs1_busy (_lsu_io_core_iresp_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs2_busy (_lsu_io_core_iresp_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_prs3_busy (_lsu_io_core_iresp_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ppred_busy (_lsu_io_core_iresp_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_stale_pdst (_lsu_io_core_iresp_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_exception (_lsu_io_core_iresp_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_exc_cause (_lsu_io_core_iresp_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_mem_cmd (_lsu_io_core_iresp_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_mem_size (_lsu_io_core_iresp_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_mem_signed (_lsu_io_core_iresp_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_uses_ldq (_lsu_io_core_iresp_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_uses_stq (_lsu_io_core_iresp_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_is_unique (_lsu_io_core_iresp_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_flush_on_commit (_lsu_io_core_iresp_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_csr_cmd (_lsu_io_core_iresp_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iresp_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_ldst (_lsu_io_core_iresp_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs1 (_lsu_io_core_iresp_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs2 (_lsu_io_core_iresp_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs3 (_lsu_io_core_iresp_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_dst_rtype (_lsu_io_core_iresp_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs1_rtype (_lsu_io_core_iresp_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_lrs2_rtype (_lsu_io_core_iresp_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_frs3_en (_lsu_io_core_iresp_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fcn_dw (_lsu_io_core_iresp_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fcn_op (_lsu_io_core_iresp_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_val (_lsu_io_core_iresp_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_rm (_lsu_io_core_iresp_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_fp_typ (_lsu_io_core_iresp_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_iresp_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_bp_debug_if (_lsu_io_core_iresp_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_iresp_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_fsrc (_lsu_io_core_iresp_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_uop_debug_tsrc (_lsu_io_core_iresp_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_iresp_0_bits_data (_lsu_io_core_iresp_0_bits_data), // @[tile.scala:159:20] .io_lsu_fresp_0_valid (_lsu_io_core_fresp_0_valid), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_inst (_lsu_io_core_fresp_0_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_inst (_lsu_io_core_fresp_0_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_rvc (_lsu_io_core_fresp_0_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_pc (_lsu_io_core_fresp_0_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_0 (_lsu_io_core_fresp_0_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_1 (_lsu_io_core_fresp_0_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_2 (_lsu_io_core_fresp_0_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iq_type_3 (_lsu_io_core_fresp_0_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_0 (_lsu_io_core_fresp_0_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_1 (_lsu_io_core_fresp_0_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_2 (_lsu_io_core_fresp_0_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_3 (_lsu_io_core_fresp_0_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_4 (_lsu_io_core_fresp_0_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_5 (_lsu_io_core_fresp_0_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_6 (_lsu_io_core_fresp_0_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_7 (_lsu_io_core_fresp_0_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_8 (_lsu_io_core_fresp_0_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fu_code_9 (_lsu_io_core_fresp_0_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_issued (_lsu_io_core_fresp_0_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_dis_col_sel (_lsu_io_core_fresp_0_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_br_mask (_lsu_io_core_fresp_0_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_br_tag (_lsu_io_core_fresp_0_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_br_type (_lsu_io_core_fresp_0_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_sfb (_lsu_io_core_fresp_0_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_fence (_lsu_io_core_fresp_0_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_fencei (_lsu_io_core_fresp_0_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_sfence (_lsu_io_core_fresp_0_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_amo (_lsu_io_core_fresp_0_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_eret (_lsu_io_core_fresp_0_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_fresp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_rocc (_lsu_io_core_fresp_0_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_mov (_lsu_io_core_fresp_0_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ftq_idx (_lsu_io_core_fresp_0_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_edge_inst (_lsu_io_core_fresp_0_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_pc_lob (_lsu_io_core_fresp_0_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_taken (_lsu_io_core_fresp_0_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_imm_rename (_lsu_io_core_fresp_0_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_imm_sel (_lsu_io_core_fresp_0_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_pimm (_lsu_io_core_fresp_0_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_imm_packed (_lsu_io_core_fresp_0_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_op1_sel (_lsu_io_core_fresp_0_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_op2_sel (_lsu_io_core_fresp_0_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_rob_idx (_lsu_io_core_fresp_0_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ldq_idx (_lsu_io_core_fresp_0_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_stq_idx (_lsu_io_core_fresp_0_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_rxq_idx (_lsu_io_core_fresp_0_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_pdst (_lsu_io_core_fresp_0_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs1 (_lsu_io_core_fresp_0_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs2 (_lsu_io_core_fresp_0_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs3 (_lsu_io_core_fresp_0_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ppred (_lsu_io_core_fresp_0_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs1_busy (_lsu_io_core_fresp_0_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs2_busy (_lsu_io_core_fresp_0_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_prs3_busy (_lsu_io_core_fresp_0_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ppred_busy (_lsu_io_core_fresp_0_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_stale_pdst (_lsu_io_core_fresp_0_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_exception (_lsu_io_core_fresp_0_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_exc_cause (_lsu_io_core_fresp_0_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_mem_cmd (_lsu_io_core_fresp_0_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_mem_size (_lsu_io_core_fresp_0_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_mem_signed (_lsu_io_core_fresp_0_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_uses_ldq (_lsu_io_core_fresp_0_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_uses_stq (_lsu_io_core_fresp_0_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_is_unique (_lsu_io_core_fresp_0_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_flush_on_commit (_lsu_io_core_fresp_0_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_csr_cmd (_lsu_io_core_fresp_0_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_fresp_0_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_ldst (_lsu_io_core_fresp_0_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs1 (_lsu_io_core_fresp_0_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs2 (_lsu_io_core_fresp_0_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs3 (_lsu_io_core_fresp_0_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_dst_rtype (_lsu_io_core_fresp_0_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs1_rtype (_lsu_io_core_fresp_0_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_lrs2_rtype (_lsu_io_core_fresp_0_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_frs3_en (_lsu_io_core_fresp_0_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fcn_dw (_lsu_io_core_fresp_0_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fcn_op (_lsu_io_core_fresp_0_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_val (_lsu_io_core_fresp_0_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_rm (_lsu_io_core_fresp_0_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_fp_typ (_lsu_io_core_fresp_0_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_fresp_0_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_bp_debug_if (_lsu_io_core_fresp_0_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_fresp_0_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_fsrc (_lsu_io_core_fresp_0_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_uop_debug_tsrc (_lsu_io_core_fresp_0_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_fresp_0_bits_data (_lsu_io_core_fresp_0_bits_data), // @[tile.scala:159:20] .io_lsu_sfence_valid (_core_io_lsu_sfence_valid), .io_lsu_sfence_bits_rs1 (_core_io_lsu_sfence_bits_rs1), .io_lsu_sfence_bits_rs2 (_core_io_lsu_sfence_bits_rs2), .io_lsu_sfence_bits_addr (_core_io_lsu_sfence_bits_addr), .io_lsu_sfence_bits_asid (_core_io_lsu_sfence_bits_asid), .io_lsu_sfence_bits_hv (_core_io_lsu_sfence_bits_hv), .io_lsu_sfence_bits_hg (_core_io_lsu_sfence_bits_hg), .io_lsu_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), .io_lsu_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), .io_lsu_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), .io_lsu_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), .io_lsu_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), .io_lsu_dis_uops_0_bits_iq_type_0 (_core_io_lsu_dis_uops_0_bits_iq_type_0), .io_lsu_dis_uops_0_bits_iq_type_1 (_core_io_lsu_dis_uops_0_bits_iq_type_1), .io_lsu_dis_uops_0_bits_iq_type_2 (_core_io_lsu_dis_uops_0_bits_iq_type_2), .io_lsu_dis_uops_0_bits_iq_type_3 (_core_io_lsu_dis_uops_0_bits_iq_type_3), .io_lsu_dis_uops_0_bits_fu_code_0 (_core_io_lsu_dis_uops_0_bits_fu_code_0), .io_lsu_dis_uops_0_bits_fu_code_1 (_core_io_lsu_dis_uops_0_bits_fu_code_1), .io_lsu_dis_uops_0_bits_fu_code_2 (_core_io_lsu_dis_uops_0_bits_fu_code_2), .io_lsu_dis_uops_0_bits_fu_code_3 (_core_io_lsu_dis_uops_0_bits_fu_code_3), .io_lsu_dis_uops_0_bits_fu_code_4 (_core_io_lsu_dis_uops_0_bits_fu_code_4), .io_lsu_dis_uops_0_bits_fu_code_5 (_core_io_lsu_dis_uops_0_bits_fu_code_5), .io_lsu_dis_uops_0_bits_fu_code_6 (_core_io_lsu_dis_uops_0_bits_fu_code_6), .io_lsu_dis_uops_0_bits_fu_code_7 (_core_io_lsu_dis_uops_0_bits_fu_code_7), .io_lsu_dis_uops_0_bits_fu_code_8 (_core_io_lsu_dis_uops_0_bits_fu_code_8), .io_lsu_dis_uops_0_bits_fu_code_9 (_core_io_lsu_dis_uops_0_bits_fu_code_9), .io_lsu_dis_uops_0_bits_iw_issued (_core_io_lsu_dis_uops_0_bits_iw_issued), .io_lsu_dis_uops_0_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_agen), .io_lsu_dis_uops_0_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_dgen), .io_lsu_dis_uops_0_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p1_speculative_child), .io_lsu_dis_uops_0_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p2_speculative_child), .io_lsu_dis_uops_0_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p1_bypass_hint), .io_lsu_dis_uops_0_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p2_bypass_hint), .io_lsu_dis_uops_0_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p3_bypass_hint), .io_lsu_dis_uops_0_bits_dis_col_sel (_core_io_lsu_dis_uops_0_bits_dis_col_sel), .io_lsu_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), .io_lsu_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), .io_lsu_dis_uops_0_bits_br_type (_core_io_lsu_dis_uops_0_bits_br_type), .io_lsu_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), .io_lsu_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), .io_lsu_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), .io_lsu_dis_uops_0_bits_is_sfence (_core_io_lsu_dis_uops_0_bits_is_sfence), .io_lsu_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), .io_lsu_dis_uops_0_bits_is_eret (_core_io_lsu_dis_uops_0_bits_is_eret), .io_lsu_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), .io_lsu_dis_uops_0_bits_is_rocc (_core_io_lsu_dis_uops_0_bits_is_rocc), .io_lsu_dis_uops_0_bits_is_mov (_core_io_lsu_dis_uops_0_bits_is_mov), .io_lsu_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), .io_lsu_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), .io_lsu_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), .io_lsu_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), .io_lsu_dis_uops_0_bits_imm_rename (_core_io_lsu_dis_uops_0_bits_imm_rename), .io_lsu_dis_uops_0_bits_imm_sel (_core_io_lsu_dis_uops_0_bits_imm_sel), .io_lsu_dis_uops_0_bits_pimm (_core_io_lsu_dis_uops_0_bits_pimm), .io_lsu_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), .io_lsu_dis_uops_0_bits_op1_sel (_core_io_lsu_dis_uops_0_bits_op1_sel), .io_lsu_dis_uops_0_bits_op2_sel (_core_io_lsu_dis_uops_0_bits_op2_sel), .io_lsu_dis_uops_0_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ldst), .io_lsu_dis_uops_0_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wen), .io_lsu_dis_uops_0_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren1), .io_lsu_dis_uops_0_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren2), .io_lsu_dis_uops_0_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren3), .io_lsu_dis_uops_0_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap12), .io_lsu_dis_uops_0_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap23), .io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn), .io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut), .io_lsu_dis_uops_0_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fromint), .io_lsu_dis_uops_0_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_toint), .io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe), .io_lsu_dis_uops_0_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fma), .io_lsu_dis_uops_0_bits_fp_ctrl_div (_core_io_lsu_dis_uops_0_bits_fp_ctrl_div), .io_lsu_dis_uops_0_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_0_bits_fp_ctrl_sqrt), .io_lsu_dis_uops_0_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wflags), .io_lsu_dis_uops_0_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_0_bits_fp_ctrl_vec), .io_lsu_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), .io_lsu_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), .io_lsu_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), .io_lsu_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), .io_lsu_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), .io_lsu_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), .io_lsu_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), .io_lsu_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), .io_lsu_dis_uops_0_bits_ppred (_core_io_lsu_dis_uops_0_bits_ppred), .io_lsu_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), .io_lsu_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), .io_lsu_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), .io_lsu_dis_uops_0_bits_ppred_busy (_core_io_lsu_dis_uops_0_bits_ppred_busy), .io_lsu_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), .io_lsu_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), .io_lsu_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), .io_lsu_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), .io_lsu_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), .io_lsu_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), .io_lsu_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), .io_lsu_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), .io_lsu_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), .io_lsu_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), .io_lsu_dis_uops_0_bits_csr_cmd (_core_io_lsu_dis_uops_0_bits_csr_cmd), .io_lsu_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), .io_lsu_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), .io_lsu_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), .io_lsu_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), .io_lsu_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), .io_lsu_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), .io_lsu_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), .io_lsu_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), .io_lsu_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), .io_lsu_dis_uops_0_bits_fcn_dw (_core_io_lsu_dis_uops_0_bits_fcn_dw), .io_lsu_dis_uops_0_bits_fcn_op (_core_io_lsu_dis_uops_0_bits_fcn_op), .io_lsu_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), .io_lsu_dis_uops_0_bits_fp_rm (_core_io_lsu_dis_uops_0_bits_fp_rm), .io_lsu_dis_uops_0_bits_fp_typ (_core_io_lsu_dis_uops_0_bits_fp_typ), .io_lsu_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), .io_lsu_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), .io_lsu_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), .io_lsu_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), .io_lsu_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), .io_lsu_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), .io_lsu_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), .io_lsu_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), .io_lsu_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), .io_lsu_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), .io_lsu_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), .io_lsu_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), .io_lsu_dis_uops_1_bits_iq_type_0 (_core_io_lsu_dis_uops_1_bits_iq_type_0), .io_lsu_dis_uops_1_bits_iq_type_1 (_core_io_lsu_dis_uops_1_bits_iq_type_1), .io_lsu_dis_uops_1_bits_iq_type_2 (_core_io_lsu_dis_uops_1_bits_iq_type_2), .io_lsu_dis_uops_1_bits_iq_type_3 (_core_io_lsu_dis_uops_1_bits_iq_type_3), .io_lsu_dis_uops_1_bits_fu_code_0 (_core_io_lsu_dis_uops_1_bits_fu_code_0), .io_lsu_dis_uops_1_bits_fu_code_1 (_core_io_lsu_dis_uops_1_bits_fu_code_1), .io_lsu_dis_uops_1_bits_fu_code_2 (_core_io_lsu_dis_uops_1_bits_fu_code_2), .io_lsu_dis_uops_1_bits_fu_code_3 (_core_io_lsu_dis_uops_1_bits_fu_code_3), .io_lsu_dis_uops_1_bits_fu_code_4 (_core_io_lsu_dis_uops_1_bits_fu_code_4), .io_lsu_dis_uops_1_bits_fu_code_5 (_core_io_lsu_dis_uops_1_bits_fu_code_5), .io_lsu_dis_uops_1_bits_fu_code_6 (_core_io_lsu_dis_uops_1_bits_fu_code_6), .io_lsu_dis_uops_1_bits_fu_code_7 (_core_io_lsu_dis_uops_1_bits_fu_code_7), .io_lsu_dis_uops_1_bits_fu_code_8 (_core_io_lsu_dis_uops_1_bits_fu_code_8), .io_lsu_dis_uops_1_bits_fu_code_9 (_core_io_lsu_dis_uops_1_bits_fu_code_9), .io_lsu_dis_uops_1_bits_iw_issued (_core_io_lsu_dis_uops_1_bits_iw_issued), .io_lsu_dis_uops_1_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_agen), .io_lsu_dis_uops_1_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_dgen), .io_lsu_dis_uops_1_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p1_speculative_child), .io_lsu_dis_uops_1_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p2_speculative_child), .io_lsu_dis_uops_1_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p1_bypass_hint), .io_lsu_dis_uops_1_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p2_bypass_hint), .io_lsu_dis_uops_1_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p3_bypass_hint), .io_lsu_dis_uops_1_bits_dis_col_sel (_core_io_lsu_dis_uops_1_bits_dis_col_sel), .io_lsu_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), .io_lsu_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), .io_lsu_dis_uops_1_bits_br_type (_core_io_lsu_dis_uops_1_bits_br_type), .io_lsu_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), .io_lsu_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), .io_lsu_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), .io_lsu_dis_uops_1_bits_is_sfence (_core_io_lsu_dis_uops_1_bits_is_sfence), .io_lsu_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), .io_lsu_dis_uops_1_bits_is_eret (_core_io_lsu_dis_uops_1_bits_is_eret), .io_lsu_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), .io_lsu_dis_uops_1_bits_is_rocc (_core_io_lsu_dis_uops_1_bits_is_rocc), .io_lsu_dis_uops_1_bits_is_mov (_core_io_lsu_dis_uops_1_bits_is_mov), .io_lsu_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), .io_lsu_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), .io_lsu_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), .io_lsu_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), .io_lsu_dis_uops_1_bits_imm_rename (_core_io_lsu_dis_uops_1_bits_imm_rename), .io_lsu_dis_uops_1_bits_imm_sel (_core_io_lsu_dis_uops_1_bits_imm_sel), .io_lsu_dis_uops_1_bits_pimm (_core_io_lsu_dis_uops_1_bits_pimm), .io_lsu_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), .io_lsu_dis_uops_1_bits_op1_sel (_core_io_lsu_dis_uops_1_bits_op1_sel), .io_lsu_dis_uops_1_bits_op2_sel (_core_io_lsu_dis_uops_1_bits_op2_sel), .io_lsu_dis_uops_1_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ldst), .io_lsu_dis_uops_1_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wen), .io_lsu_dis_uops_1_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren1), .io_lsu_dis_uops_1_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren2), .io_lsu_dis_uops_1_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren3), .io_lsu_dis_uops_1_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap12), .io_lsu_dis_uops_1_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap23), .io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn), .io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut), .io_lsu_dis_uops_1_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fromint), .io_lsu_dis_uops_1_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_toint), .io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe), .io_lsu_dis_uops_1_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fma), .io_lsu_dis_uops_1_bits_fp_ctrl_div (_core_io_lsu_dis_uops_1_bits_fp_ctrl_div), .io_lsu_dis_uops_1_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_1_bits_fp_ctrl_sqrt), .io_lsu_dis_uops_1_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wflags), .io_lsu_dis_uops_1_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_1_bits_fp_ctrl_vec), .io_lsu_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), .io_lsu_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), .io_lsu_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), .io_lsu_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), .io_lsu_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), .io_lsu_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), .io_lsu_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), .io_lsu_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), .io_lsu_dis_uops_1_bits_ppred (_core_io_lsu_dis_uops_1_bits_ppred), .io_lsu_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), .io_lsu_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), .io_lsu_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), .io_lsu_dis_uops_1_bits_ppred_busy (_core_io_lsu_dis_uops_1_bits_ppred_busy), .io_lsu_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), .io_lsu_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), .io_lsu_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), .io_lsu_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), .io_lsu_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), .io_lsu_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), .io_lsu_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), .io_lsu_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), .io_lsu_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), .io_lsu_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), .io_lsu_dis_uops_1_bits_csr_cmd (_core_io_lsu_dis_uops_1_bits_csr_cmd), .io_lsu_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), .io_lsu_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), .io_lsu_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), .io_lsu_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), .io_lsu_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), .io_lsu_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), .io_lsu_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), .io_lsu_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), .io_lsu_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), .io_lsu_dis_uops_1_bits_fcn_dw (_core_io_lsu_dis_uops_1_bits_fcn_dw), .io_lsu_dis_uops_1_bits_fcn_op (_core_io_lsu_dis_uops_1_bits_fcn_op), .io_lsu_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), .io_lsu_dis_uops_1_bits_fp_rm (_core_io_lsu_dis_uops_1_bits_fp_rm), .io_lsu_dis_uops_1_bits_fp_typ (_core_io_lsu_dis_uops_1_bits_fp_typ), .io_lsu_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), .io_lsu_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), .io_lsu_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), .io_lsu_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), .io_lsu_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), .io_lsu_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), .io_lsu_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), .io_lsu_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), // @[tile.scala:159:20] .io_lsu_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), // @[tile.scala:159:20] .io_lsu_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), // @[tile.scala:159:20] .io_lsu_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), // @[tile.scala:159:20] .io_lsu_ldq_full_0 (_lsu_io_core_ldq_full_0), // @[tile.scala:159:20] .io_lsu_ldq_full_1 (_lsu_io_core_ldq_full_1), // @[tile.scala:159:20] .io_lsu_stq_full_0 (_lsu_io_core_stq_full_0), // @[tile.scala:159:20] .io_lsu_stq_full_1 (_lsu_io_core_stq_full_1), // @[tile.scala:159:20] .io_lsu_commit_valids_0 (_core_io_lsu_commit_valids_0), .io_lsu_commit_valids_1 (_core_io_lsu_commit_valids_1), .io_lsu_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), .io_lsu_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), .io_lsu_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), .io_lsu_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), .io_lsu_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), .io_lsu_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), .io_lsu_commit_uops_0_iq_type_0 (_core_io_lsu_commit_uops_0_iq_type_0), .io_lsu_commit_uops_0_iq_type_1 (_core_io_lsu_commit_uops_0_iq_type_1), .io_lsu_commit_uops_0_iq_type_2 (_core_io_lsu_commit_uops_0_iq_type_2), .io_lsu_commit_uops_0_iq_type_3 (_core_io_lsu_commit_uops_0_iq_type_3), .io_lsu_commit_uops_0_fu_code_0 (_core_io_lsu_commit_uops_0_fu_code_0), .io_lsu_commit_uops_0_fu_code_1 (_core_io_lsu_commit_uops_0_fu_code_1), .io_lsu_commit_uops_0_fu_code_2 (_core_io_lsu_commit_uops_0_fu_code_2), .io_lsu_commit_uops_0_fu_code_3 (_core_io_lsu_commit_uops_0_fu_code_3), .io_lsu_commit_uops_0_fu_code_4 (_core_io_lsu_commit_uops_0_fu_code_4), .io_lsu_commit_uops_0_fu_code_5 (_core_io_lsu_commit_uops_0_fu_code_5), .io_lsu_commit_uops_0_fu_code_6 (_core_io_lsu_commit_uops_0_fu_code_6), .io_lsu_commit_uops_0_fu_code_7 (_core_io_lsu_commit_uops_0_fu_code_7), .io_lsu_commit_uops_0_fu_code_8 (_core_io_lsu_commit_uops_0_fu_code_8), .io_lsu_commit_uops_0_fu_code_9 (_core_io_lsu_commit_uops_0_fu_code_9), .io_lsu_commit_uops_0_iw_issued (_core_io_lsu_commit_uops_0_iw_issued), .io_lsu_commit_uops_0_iw_issued_partial_agen (_core_io_lsu_commit_uops_0_iw_issued_partial_agen), .io_lsu_commit_uops_0_iw_issued_partial_dgen (_core_io_lsu_commit_uops_0_iw_issued_partial_dgen), .io_lsu_commit_uops_0_iw_p1_speculative_child (_core_io_lsu_commit_uops_0_iw_p1_speculative_child), .io_lsu_commit_uops_0_iw_p2_speculative_child (_core_io_lsu_commit_uops_0_iw_p2_speculative_child), .io_lsu_commit_uops_0_iw_p1_bypass_hint (_core_io_lsu_commit_uops_0_iw_p1_bypass_hint), .io_lsu_commit_uops_0_iw_p2_bypass_hint (_core_io_lsu_commit_uops_0_iw_p2_bypass_hint), .io_lsu_commit_uops_0_iw_p3_bypass_hint (_core_io_lsu_commit_uops_0_iw_p3_bypass_hint), .io_lsu_commit_uops_0_dis_col_sel (_core_io_lsu_commit_uops_0_dis_col_sel), .io_lsu_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), .io_lsu_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), .io_lsu_commit_uops_0_br_type (_core_io_lsu_commit_uops_0_br_type), .io_lsu_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), .io_lsu_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), .io_lsu_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), .io_lsu_commit_uops_0_is_sfence (_core_io_lsu_commit_uops_0_is_sfence), .io_lsu_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), .io_lsu_commit_uops_0_is_eret (_core_io_lsu_commit_uops_0_is_eret), .io_lsu_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), .io_lsu_commit_uops_0_is_rocc (_core_io_lsu_commit_uops_0_is_rocc), .io_lsu_commit_uops_0_is_mov (_core_io_lsu_commit_uops_0_is_mov), .io_lsu_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), .io_lsu_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), .io_lsu_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), .io_lsu_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), .io_lsu_commit_uops_0_imm_rename (_core_io_lsu_commit_uops_0_imm_rename), .io_lsu_commit_uops_0_imm_sel (_core_io_lsu_commit_uops_0_imm_sel), .io_lsu_commit_uops_0_pimm (_core_io_lsu_commit_uops_0_pimm), .io_lsu_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), .io_lsu_commit_uops_0_op1_sel (_core_io_lsu_commit_uops_0_op1_sel), .io_lsu_commit_uops_0_op2_sel (_core_io_lsu_commit_uops_0_op2_sel), .io_lsu_commit_uops_0_fp_ctrl_ldst (_core_io_lsu_commit_uops_0_fp_ctrl_ldst), .io_lsu_commit_uops_0_fp_ctrl_wen (_core_io_lsu_commit_uops_0_fp_ctrl_wen), .io_lsu_commit_uops_0_fp_ctrl_ren1 (_core_io_lsu_commit_uops_0_fp_ctrl_ren1), .io_lsu_commit_uops_0_fp_ctrl_ren2 (_core_io_lsu_commit_uops_0_fp_ctrl_ren2), .io_lsu_commit_uops_0_fp_ctrl_ren3 (_core_io_lsu_commit_uops_0_fp_ctrl_ren3), .io_lsu_commit_uops_0_fp_ctrl_swap12 (_core_io_lsu_commit_uops_0_fp_ctrl_swap12), .io_lsu_commit_uops_0_fp_ctrl_swap23 (_core_io_lsu_commit_uops_0_fp_ctrl_swap23), .io_lsu_commit_uops_0_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagIn), .io_lsu_commit_uops_0_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagOut), .io_lsu_commit_uops_0_fp_ctrl_fromint (_core_io_lsu_commit_uops_0_fp_ctrl_fromint), .io_lsu_commit_uops_0_fp_ctrl_toint (_core_io_lsu_commit_uops_0_fp_ctrl_toint), .io_lsu_commit_uops_0_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_0_fp_ctrl_fastpipe), .io_lsu_commit_uops_0_fp_ctrl_fma (_core_io_lsu_commit_uops_0_fp_ctrl_fma), .io_lsu_commit_uops_0_fp_ctrl_div (_core_io_lsu_commit_uops_0_fp_ctrl_div), .io_lsu_commit_uops_0_fp_ctrl_sqrt (_core_io_lsu_commit_uops_0_fp_ctrl_sqrt), .io_lsu_commit_uops_0_fp_ctrl_wflags (_core_io_lsu_commit_uops_0_fp_ctrl_wflags), .io_lsu_commit_uops_0_fp_ctrl_vec (_core_io_lsu_commit_uops_0_fp_ctrl_vec), .io_lsu_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), .io_lsu_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), .io_lsu_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), .io_lsu_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), .io_lsu_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), .io_lsu_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), .io_lsu_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), .io_lsu_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), .io_lsu_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), .io_lsu_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), .io_lsu_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), .io_lsu_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), .io_lsu_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), .io_lsu_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), .io_lsu_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), .io_lsu_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), .io_lsu_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), .io_lsu_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), .io_lsu_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), .io_lsu_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), .io_lsu_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), .io_lsu_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), .io_lsu_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), .io_lsu_commit_uops_0_csr_cmd (_core_io_lsu_commit_uops_0_csr_cmd), .io_lsu_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), .io_lsu_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), .io_lsu_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), .io_lsu_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), .io_lsu_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), .io_lsu_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), .io_lsu_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), .io_lsu_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), .io_lsu_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), .io_lsu_commit_uops_0_fcn_dw (_core_io_lsu_commit_uops_0_fcn_dw), .io_lsu_commit_uops_0_fcn_op (_core_io_lsu_commit_uops_0_fcn_op), .io_lsu_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), .io_lsu_commit_uops_0_fp_rm (_core_io_lsu_commit_uops_0_fp_rm), .io_lsu_commit_uops_0_fp_typ (_core_io_lsu_commit_uops_0_fp_typ), .io_lsu_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), .io_lsu_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), .io_lsu_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), .io_lsu_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), .io_lsu_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), .io_lsu_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), .io_lsu_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), .io_lsu_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), .io_lsu_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), .io_lsu_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), .io_lsu_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), .io_lsu_commit_uops_1_iq_type_0 (_core_io_lsu_commit_uops_1_iq_type_0), .io_lsu_commit_uops_1_iq_type_1 (_core_io_lsu_commit_uops_1_iq_type_1), .io_lsu_commit_uops_1_iq_type_2 (_core_io_lsu_commit_uops_1_iq_type_2), .io_lsu_commit_uops_1_iq_type_3 (_core_io_lsu_commit_uops_1_iq_type_3), .io_lsu_commit_uops_1_fu_code_0 (_core_io_lsu_commit_uops_1_fu_code_0), .io_lsu_commit_uops_1_fu_code_1 (_core_io_lsu_commit_uops_1_fu_code_1), .io_lsu_commit_uops_1_fu_code_2 (_core_io_lsu_commit_uops_1_fu_code_2), .io_lsu_commit_uops_1_fu_code_3 (_core_io_lsu_commit_uops_1_fu_code_3), .io_lsu_commit_uops_1_fu_code_4 (_core_io_lsu_commit_uops_1_fu_code_4), .io_lsu_commit_uops_1_fu_code_5 (_core_io_lsu_commit_uops_1_fu_code_5), .io_lsu_commit_uops_1_fu_code_6 (_core_io_lsu_commit_uops_1_fu_code_6), .io_lsu_commit_uops_1_fu_code_7 (_core_io_lsu_commit_uops_1_fu_code_7), .io_lsu_commit_uops_1_fu_code_8 (_core_io_lsu_commit_uops_1_fu_code_8), .io_lsu_commit_uops_1_fu_code_9 (_core_io_lsu_commit_uops_1_fu_code_9), .io_lsu_commit_uops_1_iw_issued (_core_io_lsu_commit_uops_1_iw_issued), .io_lsu_commit_uops_1_iw_issued_partial_agen (_core_io_lsu_commit_uops_1_iw_issued_partial_agen), .io_lsu_commit_uops_1_iw_issued_partial_dgen (_core_io_lsu_commit_uops_1_iw_issued_partial_dgen), .io_lsu_commit_uops_1_iw_p1_speculative_child (_core_io_lsu_commit_uops_1_iw_p1_speculative_child), .io_lsu_commit_uops_1_iw_p2_speculative_child (_core_io_lsu_commit_uops_1_iw_p2_speculative_child), .io_lsu_commit_uops_1_iw_p1_bypass_hint (_core_io_lsu_commit_uops_1_iw_p1_bypass_hint), .io_lsu_commit_uops_1_iw_p2_bypass_hint (_core_io_lsu_commit_uops_1_iw_p2_bypass_hint), .io_lsu_commit_uops_1_iw_p3_bypass_hint (_core_io_lsu_commit_uops_1_iw_p3_bypass_hint), .io_lsu_commit_uops_1_dis_col_sel (_core_io_lsu_commit_uops_1_dis_col_sel), .io_lsu_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), .io_lsu_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), .io_lsu_commit_uops_1_br_type (_core_io_lsu_commit_uops_1_br_type), .io_lsu_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), .io_lsu_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), .io_lsu_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), .io_lsu_commit_uops_1_is_sfence (_core_io_lsu_commit_uops_1_is_sfence), .io_lsu_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), .io_lsu_commit_uops_1_is_eret (_core_io_lsu_commit_uops_1_is_eret), .io_lsu_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), .io_lsu_commit_uops_1_is_rocc (_core_io_lsu_commit_uops_1_is_rocc), .io_lsu_commit_uops_1_is_mov (_core_io_lsu_commit_uops_1_is_mov), .io_lsu_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), .io_lsu_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), .io_lsu_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), .io_lsu_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), .io_lsu_commit_uops_1_imm_rename (_core_io_lsu_commit_uops_1_imm_rename), .io_lsu_commit_uops_1_imm_sel (_core_io_lsu_commit_uops_1_imm_sel), .io_lsu_commit_uops_1_pimm (_core_io_lsu_commit_uops_1_pimm), .io_lsu_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), .io_lsu_commit_uops_1_op1_sel (_core_io_lsu_commit_uops_1_op1_sel), .io_lsu_commit_uops_1_op2_sel (_core_io_lsu_commit_uops_1_op2_sel), .io_lsu_commit_uops_1_fp_ctrl_ldst (_core_io_lsu_commit_uops_1_fp_ctrl_ldst), .io_lsu_commit_uops_1_fp_ctrl_wen (_core_io_lsu_commit_uops_1_fp_ctrl_wen), .io_lsu_commit_uops_1_fp_ctrl_ren1 (_core_io_lsu_commit_uops_1_fp_ctrl_ren1), .io_lsu_commit_uops_1_fp_ctrl_ren2 (_core_io_lsu_commit_uops_1_fp_ctrl_ren2), .io_lsu_commit_uops_1_fp_ctrl_ren3 (_core_io_lsu_commit_uops_1_fp_ctrl_ren3), .io_lsu_commit_uops_1_fp_ctrl_swap12 (_core_io_lsu_commit_uops_1_fp_ctrl_swap12), .io_lsu_commit_uops_1_fp_ctrl_swap23 (_core_io_lsu_commit_uops_1_fp_ctrl_swap23), .io_lsu_commit_uops_1_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagIn), .io_lsu_commit_uops_1_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagOut), .io_lsu_commit_uops_1_fp_ctrl_fromint (_core_io_lsu_commit_uops_1_fp_ctrl_fromint), .io_lsu_commit_uops_1_fp_ctrl_toint (_core_io_lsu_commit_uops_1_fp_ctrl_toint), .io_lsu_commit_uops_1_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_1_fp_ctrl_fastpipe), .io_lsu_commit_uops_1_fp_ctrl_fma (_core_io_lsu_commit_uops_1_fp_ctrl_fma), .io_lsu_commit_uops_1_fp_ctrl_div (_core_io_lsu_commit_uops_1_fp_ctrl_div), .io_lsu_commit_uops_1_fp_ctrl_sqrt (_core_io_lsu_commit_uops_1_fp_ctrl_sqrt), .io_lsu_commit_uops_1_fp_ctrl_wflags (_core_io_lsu_commit_uops_1_fp_ctrl_wflags), .io_lsu_commit_uops_1_fp_ctrl_vec (_core_io_lsu_commit_uops_1_fp_ctrl_vec), .io_lsu_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), .io_lsu_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), .io_lsu_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), .io_lsu_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), .io_lsu_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), .io_lsu_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), .io_lsu_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), .io_lsu_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), .io_lsu_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), .io_lsu_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), .io_lsu_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), .io_lsu_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), .io_lsu_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), .io_lsu_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), .io_lsu_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), .io_lsu_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), .io_lsu_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), .io_lsu_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), .io_lsu_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), .io_lsu_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), .io_lsu_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), .io_lsu_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), .io_lsu_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), .io_lsu_commit_uops_1_csr_cmd (_core_io_lsu_commit_uops_1_csr_cmd), .io_lsu_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), .io_lsu_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), .io_lsu_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), .io_lsu_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), .io_lsu_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), .io_lsu_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), .io_lsu_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), .io_lsu_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), .io_lsu_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), .io_lsu_commit_uops_1_fcn_dw (_core_io_lsu_commit_uops_1_fcn_dw), .io_lsu_commit_uops_1_fcn_op (_core_io_lsu_commit_uops_1_fcn_op), .io_lsu_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), .io_lsu_commit_uops_1_fp_rm (_core_io_lsu_commit_uops_1_fp_rm), .io_lsu_commit_uops_1_fp_typ (_core_io_lsu_commit_uops_1_fp_typ), .io_lsu_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), .io_lsu_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), .io_lsu_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), .io_lsu_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), .io_lsu_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), .io_lsu_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), .io_lsu_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), .io_lsu_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), .io_lsu_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), .io_lsu_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), .io_lsu_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), .io_lsu_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), .io_lsu_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), // @[tile.scala:159:20] .io_lsu_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), // @[tile.scala:159:20] .io_lsu_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), // @[tile.scala:159:20] .io_lsu_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), // @[tile.scala:159:20] .io_lsu_clr_unsafe_0_valid (_lsu_io_core_clr_unsafe_0_valid), // @[tile.scala:159:20] .io_lsu_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), // @[tile.scala:159:20] .io_lsu_fence_dmem (_core_io_lsu_fence_dmem), .io_lsu_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), .io_lsu_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), .io_lsu_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), .io_lsu_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), .io_lsu_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), .io_lsu_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), .io_lsu_brupdate_b2_uop_iq_type_0 (_core_io_lsu_brupdate_b2_uop_iq_type_0), .io_lsu_brupdate_b2_uop_iq_type_1 (_core_io_lsu_brupdate_b2_uop_iq_type_1), .io_lsu_brupdate_b2_uop_iq_type_2 (_core_io_lsu_brupdate_b2_uop_iq_type_2), .io_lsu_brupdate_b2_uop_iq_type_3 (_core_io_lsu_brupdate_b2_uop_iq_type_3), .io_lsu_brupdate_b2_uop_fu_code_0 (_core_io_lsu_brupdate_b2_uop_fu_code_0), .io_lsu_brupdate_b2_uop_fu_code_1 (_core_io_lsu_brupdate_b2_uop_fu_code_1), .io_lsu_brupdate_b2_uop_fu_code_2 (_core_io_lsu_brupdate_b2_uop_fu_code_2), .io_lsu_brupdate_b2_uop_fu_code_3 (_core_io_lsu_brupdate_b2_uop_fu_code_3), .io_lsu_brupdate_b2_uop_fu_code_4 (_core_io_lsu_brupdate_b2_uop_fu_code_4), .io_lsu_brupdate_b2_uop_fu_code_5 (_core_io_lsu_brupdate_b2_uop_fu_code_5), .io_lsu_brupdate_b2_uop_fu_code_6 (_core_io_lsu_brupdate_b2_uop_fu_code_6), .io_lsu_brupdate_b2_uop_fu_code_7 (_core_io_lsu_brupdate_b2_uop_fu_code_7), .io_lsu_brupdate_b2_uop_fu_code_8 (_core_io_lsu_brupdate_b2_uop_fu_code_8), .io_lsu_brupdate_b2_uop_fu_code_9 (_core_io_lsu_brupdate_b2_uop_fu_code_9), .io_lsu_brupdate_b2_uop_iw_issued (_core_io_lsu_brupdate_b2_uop_iw_issued), .io_lsu_brupdate_b2_uop_iw_issued_partial_agen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_agen), .io_lsu_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_dgen), .io_lsu_brupdate_b2_uop_iw_p1_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p1_speculative_child), .io_lsu_brupdate_b2_uop_iw_p2_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p2_speculative_child), .io_lsu_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p1_bypass_hint), .io_lsu_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p2_bypass_hint), .io_lsu_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p3_bypass_hint), .io_lsu_brupdate_b2_uop_dis_col_sel (_core_io_lsu_brupdate_b2_uop_dis_col_sel), .io_lsu_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), .io_lsu_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), .io_lsu_brupdate_b2_uop_br_type (_core_io_lsu_brupdate_b2_uop_br_type), .io_lsu_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), .io_lsu_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), .io_lsu_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), .io_lsu_brupdate_b2_uop_is_sfence (_core_io_lsu_brupdate_b2_uop_is_sfence), .io_lsu_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), .io_lsu_brupdate_b2_uop_is_eret (_core_io_lsu_brupdate_b2_uop_is_eret), .io_lsu_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), .io_lsu_brupdate_b2_uop_is_rocc (_core_io_lsu_brupdate_b2_uop_is_rocc), .io_lsu_brupdate_b2_uop_is_mov (_core_io_lsu_brupdate_b2_uop_is_mov), .io_lsu_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), .io_lsu_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), .io_lsu_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), .io_lsu_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), .io_lsu_brupdate_b2_uop_imm_rename (_core_io_lsu_brupdate_b2_uop_imm_rename), .io_lsu_brupdate_b2_uop_imm_sel (_core_io_lsu_brupdate_b2_uop_imm_sel), .io_lsu_brupdate_b2_uop_pimm (_core_io_lsu_brupdate_b2_uop_pimm), .io_lsu_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), .io_lsu_brupdate_b2_uop_op1_sel (_core_io_lsu_brupdate_b2_uop_op1_sel), .io_lsu_brupdate_b2_uop_op2_sel (_core_io_lsu_brupdate_b2_uop_op2_sel), .io_lsu_brupdate_b2_uop_fp_ctrl_ldst (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ldst), .io_lsu_brupdate_b2_uop_fp_ctrl_wen (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wen), .io_lsu_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren1), .io_lsu_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren2), .io_lsu_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren3), .io_lsu_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap12), .io_lsu_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap23), .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn), .io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut), .io_lsu_brupdate_b2_uop_fp_ctrl_fromint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fromint), .io_lsu_brupdate_b2_uop_fp_ctrl_toint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_toint), .io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe), .io_lsu_brupdate_b2_uop_fp_ctrl_fma (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fma), .io_lsu_brupdate_b2_uop_fp_ctrl_div (_core_io_lsu_brupdate_b2_uop_fp_ctrl_div), .io_lsu_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_lsu_brupdate_b2_uop_fp_ctrl_sqrt), .io_lsu_brupdate_b2_uop_fp_ctrl_wflags (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wflags), .io_lsu_brupdate_b2_uop_fp_ctrl_vec (_core_io_lsu_brupdate_b2_uop_fp_ctrl_vec), .io_lsu_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), .io_lsu_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), .io_lsu_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), .io_lsu_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), .io_lsu_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), .io_lsu_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), .io_lsu_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), .io_lsu_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), .io_lsu_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), .io_lsu_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), .io_lsu_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), .io_lsu_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), .io_lsu_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), .io_lsu_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), .io_lsu_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), .io_lsu_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), .io_lsu_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), .io_lsu_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), .io_lsu_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), .io_lsu_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), .io_lsu_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), .io_lsu_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), .io_lsu_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), .io_lsu_brupdate_b2_uop_csr_cmd (_core_io_lsu_brupdate_b2_uop_csr_cmd), .io_lsu_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), .io_lsu_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), .io_lsu_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), .io_lsu_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), .io_lsu_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), .io_lsu_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), .io_lsu_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), .io_lsu_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), .io_lsu_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), .io_lsu_brupdate_b2_uop_fcn_dw (_core_io_lsu_brupdate_b2_uop_fcn_dw), .io_lsu_brupdate_b2_uop_fcn_op (_core_io_lsu_brupdate_b2_uop_fcn_op), .io_lsu_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), .io_lsu_brupdate_b2_uop_fp_rm (_core_io_lsu_brupdate_b2_uop_fp_rm), .io_lsu_brupdate_b2_uop_fp_typ (_core_io_lsu_brupdate_b2_uop_fp_typ), .io_lsu_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), .io_lsu_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), .io_lsu_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), .io_lsu_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), .io_lsu_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), .io_lsu_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), .io_lsu_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), .io_lsu_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), .io_lsu_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), .io_lsu_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), .io_lsu_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), .io_lsu_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), .io_lsu_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), .io_lsu_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), .io_lsu_rob_head_idx (_core_io_lsu_rob_head_idx), .io_lsu_exception (_core_io_lsu_exception), .io_lsu_fencei_rdy (_lsu_io_core_fencei_rdy), // @[tile.scala:159:20] .io_lsu_lxcpt_valid (_lsu_io_core_lxcpt_valid), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_0 (_lsu_io_core_lxcpt_bits_uop_iq_type_0), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_1 (_lsu_io_core_lxcpt_bits_uop_iq_type_1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_2 (_lsu_io_core_lxcpt_bits_uop_iq_type_2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iq_type_3 (_lsu_io_core_lxcpt_bits_uop_iq_type_3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_0 (_lsu_io_core_lxcpt_bits_uop_fu_code_0), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_1 (_lsu_io_core_lxcpt_bits_uop_fu_code_1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_2 (_lsu_io_core_lxcpt_bits_uop_fu_code_2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_3 (_lsu_io_core_lxcpt_bits_uop_fu_code_3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_4 (_lsu_io_core_lxcpt_bits_uop_fu_code_4), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_5 (_lsu_io_core_lxcpt_bits_uop_fu_code_5), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_6 (_lsu_io_core_lxcpt_bits_uop_fu_code_6), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_7 (_lsu_io_core_lxcpt_bits_uop_fu_code_7), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_8 (_lsu_io_core_lxcpt_bits_uop_fu_code_8), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fu_code_9 (_lsu_io_core_lxcpt_bits_uop_fu_code_9), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_issued (_lsu_io_core_lxcpt_bits_uop_iw_issued), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_issued_partial_agen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_agen), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_dgen), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p1_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p1_speculative_child), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p2_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p2_speculative_child), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p1_bypass_hint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p2_bypass_hint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p3_bypass_hint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_dis_col_sel (_lsu_io_core_lxcpt_bits_uop_dis_col_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_br_type (_lsu_io_core_lxcpt_bits_uop_br_type), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_sfence (_lsu_io_core_lxcpt_bits_uop_is_sfence), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_eret (_lsu_io_core_lxcpt_bits_uop_is_eret), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_rocc (_lsu_io_core_lxcpt_bits_uop_is_rocc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_mov (_lsu_io_core_lxcpt_bits_uop_is_mov), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_imm_rename (_lsu_io_core_lxcpt_bits_uop_imm_rename), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_imm_sel (_lsu_io_core_lxcpt_bits_uop_imm_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_pimm (_lsu_io_core_lxcpt_bits_uop_pimm), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_op1_sel (_lsu_io_core_lxcpt_bits_uop_op1_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_op2_sel (_lsu_io_core_lxcpt_bits_uop_op2_sel), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ldst (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ldst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_wen (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wen), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ren1 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ren2 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_ren3 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_swap12 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap12), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_swap23 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap23), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_fromint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fromint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_toint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_toint), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_fma (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fma), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_div (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_div), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_sqrt), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_wflags (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wflags), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_ctrl_vec (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_vec), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_csr_cmd (_lsu_io_core_lxcpt_bits_uop_csr_cmd), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fcn_dw (_lsu_io_core_lxcpt_bits_uop_fcn_dw), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fcn_op (_lsu_io_core_lxcpt_bits_uop_fcn_op), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_rm (_lsu_io_core_lxcpt_bits_uop_fp_rm), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_fp_typ (_lsu_io_core_lxcpt_bits_uop_fp_typ), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), // @[tile.scala:159:20] .io_lsu_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), // @[tile.scala:159:20] .io_lsu_tsc_reg (_core_io_lsu_tsc_reg), .io_lsu_status_debug (_core_io_lsu_status_debug), .io_lsu_status_cease (_core_io_lsu_status_cease), .io_lsu_status_wfi (_core_io_lsu_status_wfi), .io_lsu_status_dprv (_core_io_lsu_status_dprv), .io_lsu_status_dv (_core_io_lsu_status_dv), .io_lsu_status_prv (_core_io_lsu_status_prv), .io_lsu_status_v (_core_io_lsu_status_v), .io_lsu_status_sd (_core_io_lsu_status_sd), .io_lsu_status_mpv (_core_io_lsu_status_mpv), .io_lsu_status_gva (_core_io_lsu_status_gva), .io_lsu_status_tsr (_core_io_lsu_status_tsr), .io_lsu_status_tw (_core_io_lsu_status_tw), .io_lsu_status_tvm (_core_io_lsu_status_tvm), .io_lsu_status_mxr (_core_io_lsu_status_mxr), .io_lsu_status_sum (_core_io_lsu_status_sum), .io_lsu_status_mprv (_core_io_lsu_status_mprv), .io_lsu_status_fs (_core_io_lsu_status_fs), .io_lsu_status_mpp (_core_io_lsu_status_mpp), .io_lsu_status_spp (_core_io_lsu_status_spp), .io_lsu_status_mpie (_core_io_lsu_status_mpie), .io_lsu_status_spie (_core_io_lsu_status_spie), .io_lsu_status_mie (_core_io_lsu_status_mie), .io_lsu_status_sie (_core_io_lsu_status_sie), .io_lsu_perf_acquire (_lsu_io_core_perf_acquire), // @[tile.scala:159:20] .io_lsu_perf_release (_lsu_io_core_perf_release), // @[tile.scala:159:20] .io_lsu_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), // @[tile.scala:159:20] .io_ptw_tlb_req_ready (_ptw_io_requestor_2_req_ready), // @[tile.scala:236:20] .io_ptw_tlb_resp_valid (_ptw_io_requestor_2_resp_valid), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[tile.scala:236:20] .io_ptw_tlb_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[tile.scala:236:20] .io_ptw_tlb_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[tile.scala:236:20] .io_ptw_tlb_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[tile.scala:236:20] .io_ptw_tlb_status_debug (_ptw_io_requestor_2_status_debug), // @[tile.scala:236:20] .io_ptw_tlb_status_cease (_ptw_io_requestor_2_status_cease), // @[tile.scala:236:20] .io_ptw_tlb_status_wfi (_ptw_io_requestor_2_status_wfi), // @[tile.scala:236:20] .io_ptw_tlb_status_dprv (_ptw_io_requestor_2_status_dprv), // @[tile.scala:236:20] .io_ptw_tlb_status_dv (_ptw_io_requestor_2_status_dv), // @[tile.scala:236:20] .io_ptw_tlb_status_prv (_ptw_io_requestor_2_status_prv), // @[tile.scala:236:20] .io_ptw_tlb_status_v (_ptw_io_requestor_2_status_v), // @[tile.scala:236:20] .io_ptw_tlb_status_sd (_ptw_io_requestor_2_status_sd), // @[tile.scala:236:20] .io_ptw_tlb_status_mpv (_ptw_io_requestor_2_status_mpv), // @[tile.scala:236:20] .io_ptw_tlb_status_gva (_ptw_io_requestor_2_status_gva), // @[tile.scala:236:20] .io_ptw_tlb_status_tsr (_ptw_io_requestor_2_status_tsr), // @[tile.scala:236:20] .io_ptw_tlb_status_tw (_ptw_io_requestor_2_status_tw), // @[tile.scala:236:20] .io_ptw_tlb_status_tvm (_ptw_io_requestor_2_status_tvm), // @[tile.scala:236:20] .io_ptw_tlb_status_mxr (_ptw_io_requestor_2_status_mxr), // @[tile.scala:236:20] .io_ptw_tlb_status_sum (_ptw_io_requestor_2_status_sum), // @[tile.scala:236:20] .io_ptw_tlb_status_mprv (_ptw_io_requestor_2_status_mprv), // @[tile.scala:236:20] .io_ptw_tlb_status_fs (_ptw_io_requestor_2_status_fs), // @[tile.scala:236:20] .io_ptw_tlb_status_mpp (_ptw_io_requestor_2_status_mpp), // @[tile.scala:236:20] .io_ptw_tlb_status_spp (_ptw_io_requestor_2_status_spp), // @[tile.scala:236:20] .io_ptw_tlb_status_mpie (_ptw_io_requestor_2_status_mpie), // @[tile.scala:236:20] .io_ptw_tlb_status_spie (_ptw_io_requestor_2_status_spie), // @[tile.scala:236:20] .io_ptw_tlb_status_mie (_ptw_io_requestor_2_status_mie), // @[tile.scala:236:20] .io_ptw_tlb_status_sie (_ptw_io_requestor_2_status_sie), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[tile.scala:236:20] .io_ptw_tlb_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[tile.scala:236:20] .io_trace_time (traceSourceNodeOut_time), .io_trace_custom_rob_empty (traceSourceNodeOut_custom_rob_empty) ); // @[tile.scala:158:20] LSU lsu ( // @[tile.scala:159:20] .clock (clock), .reset (reset), .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[tile.scala:236:20] .io_ptw_req_valid (_lsu_io_ptw_req_valid), .io_ptw_req_bits_valid (_lsu_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[tile.scala:236:20] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[tile.scala:236:20] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[tile.scala:236:20] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[tile.scala:236:20] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[tile.scala:236:20] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[tile.scala:236:20] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[tile.scala:236:20] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[tile.scala:236:20] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[tile.scala:236:20] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[tile.scala:236:20] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[tile.scala:236:20] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[tile.scala:236:20] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[tile.scala:236:20] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[tile.scala:236:20] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[tile.scala:236:20] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[tile.scala:236:20] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[tile.scala:236:20] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[tile.scala:236:20] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[tile.scala:236:20] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[tile.scala:236:20] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[tile.scala:236:20] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[tile.scala:236:20] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[tile.scala:236:20] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[tile.scala:236:20] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[tile.scala:236:20] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[tile.scala:236:20] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[tile.scala:236:20] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[tile.scala:236:20] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[tile.scala:236:20] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[tile.scala:236:20] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[tile.scala:236:20] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[tile.scala:236:20] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[tile.scala:236:20] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[tile.scala:236:20] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[tile.scala:236:20] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[tile.scala:236:20] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[tile.scala:236:20] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[tile.scala:236:20] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[tile.scala:236:20] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[tile.scala:236:20] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[tile.scala:236:20] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[tile.scala:236:20] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[tile.scala:236:20] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[tile.scala:236:20] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[tile.scala:236:20] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[tile.scala:236:20] .io_core_agen_0_valid (_core_io_lsu_agen_0_valid), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_inst (_core_io_lsu_agen_0_bits_uop_inst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_inst (_core_io_lsu_agen_0_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_rvc (_core_io_lsu_agen_0_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_pc (_core_io_lsu_agen_0_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_0 (_core_io_lsu_agen_0_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_1 (_core_io_lsu_agen_0_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_2 (_core_io_lsu_agen_0_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iq_type_3 (_core_io_lsu_agen_0_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_0 (_core_io_lsu_agen_0_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_1 (_core_io_lsu_agen_0_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_2 (_core_io_lsu_agen_0_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_3 (_core_io_lsu_agen_0_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_4 (_core_io_lsu_agen_0_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_5 (_core_io_lsu_agen_0_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_6 (_core_io_lsu_agen_0_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_7 (_core_io_lsu_agen_0_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_8 (_core_io_lsu_agen_0_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fu_code_9 (_core_io_lsu_agen_0_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_issued (_core_io_lsu_agen_0_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_agen_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_agen_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_agen_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_dis_col_sel (_core_io_lsu_agen_0_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_br_mask (_core_io_lsu_agen_0_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_br_tag (_core_io_lsu_agen_0_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_br_type (_core_io_lsu_agen_0_bits_uop_br_type), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_sfb (_core_io_lsu_agen_0_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_fence (_core_io_lsu_agen_0_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_fencei (_core_io_lsu_agen_0_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_sfence (_core_io_lsu_agen_0_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_amo (_core_io_lsu_agen_0_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_eret (_core_io_lsu_agen_0_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_agen_0_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_rocc (_core_io_lsu_agen_0_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_mov (_core_io_lsu_agen_0_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ftq_idx (_core_io_lsu_agen_0_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_edge_inst (_core_io_lsu_agen_0_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_pc_lob (_core_io_lsu_agen_0_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_taken (_core_io_lsu_agen_0_bits_uop_taken), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_imm_rename (_core_io_lsu_agen_0_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_imm_sel (_core_io_lsu_agen_0_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_pimm (_core_io_lsu_agen_0_bits_uop_pimm), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_imm_packed (_core_io_lsu_agen_0_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_op1_sel (_core_io_lsu_agen_0_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_op2_sel (_core_io_lsu_agen_0_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_agen_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_agen_0_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_agen_0_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_div (_core_io_lsu_agen_0_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_agen_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_agen_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_agen_0_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_rob_idx (_core_io_lsu_agen_0_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ldq_idx (_core_io_lsu_agen_0_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_stq_idx (_core_io_lsu_agen_0_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_rxq_idx (_core_io_lsu_agen_0_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_pdst (_core_io_lsu_agen_0_bits_uop_pdst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs1 (_core_io_lsu_agen_0_bits_uop_prs1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs2 (_core_io_lsu_agen_0_bits_uop_prs2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs3 (_core_io_lsu_agen_0_bits_uop_prs3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ppred (_core_io_lsu_agen_0_bits_uop_ppred), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs1_busy (_core_io_lsu_agen_0_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs2_busy (_core_io_lsu_agen_0_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_prs3_busy (_core_io_lsu_agen_0_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ppred_busy (_core_io_lsu_agen_0_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_stale_pdst (_core_io_lsu_agen_0_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_exception (_core_io_lsu_agen_0_bits_uop_exception), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_exc_cause (_core_io_lsu_agen_0_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_mem_cmd (_core_io_lsu_agen_0_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_mem_size (_core_io_lsu_agen_0_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_mem_signed (_core_io_lsu_agen_0_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_uses_ldq (_core_io_lsu_agen_0_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_uses_stq (_core_io_lsu_agen_0_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_is_unique (_core_io_lsu_agen_0_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_flush_on_commit (_core_io_lsu_agen_0_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_csr_cmd (_core_io_lsu_agen_0_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_agen_0_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_ldst (_core_io_lsu_agen_0_bits_uop_ldst), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs1 (_core_io_lsu_agen_0_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs2 (_core_io_lsu_agen_0_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs3 (_core_io_lsu_agen_0_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_dst_rtype (_core_io_lsu_agen_0_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs1_rtype (_core_io_lsu_agen_0_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_lrs2_rtype (_core_io_lsu_agen_0_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_frs3_en (_core_io_lsu_agen_0_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fcn_dw (_core_io_lsu_agen_0_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fcn_op (_core_io_lsu_agen_0_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_val (_core_io_lsu_agen_0_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_rm (_core_io_lsu_agen_0_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_fp_typ (_core_io_lsu_agen_0_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_xcpt_pf_if (_core_io_lsu_agen_0_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_xcpt_ae_if (_core_io_lsu_agen_0_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_xcpt_ma_if (_core_io_lsu_agen_0_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_bp_debug_if (_core_io_lsu_agen_0_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_bp_xcpt_if (_core_io_lsu_agen_0_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_fsrc (_core_io_lsu_agen_0_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_agen_0_bits_uop_debug_tsrc (_core_io_lsu_agen_0_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_agen_0_bits_data (_core_io_lsu_agen_0_bits_data), // @[tile.scala:158:20] .io_core_dgen_0_valid (_core_io_lsu_dgen_0_valid), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_inst (_core_io_lsu_dgen_0_bits_uop_inst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_inst (_core_io_lsu_dgen_0_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_rvc (_core_io_lsu_dgen_0_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_pc (_core_io_lsu_dgen_0_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_0 (_core_io_lsu_dgen_0_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_1 (_core_io_lsu_dgen_0_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_2 (_core_io_lsu_dgen_0_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iq_type_3 (_core_io_lsu_dgen_0_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_0 (_core_io_lsu_dgen_0_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_1 (_core_io_lsu_dgen_0_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_2 (_core_io_lsu_dgen_0_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_3 (_core_io_lsu_dgen_0_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_4 (_core_io_lsu_dgen_0_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_5 (_core_io_lsu_dgen_0_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_6 (_core_io_lsu_dgen_0_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_7 (_core_io_lsu_dgen_0_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_8 (_core_io_lsu_dgen_0_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fu_code_9 (_core_io_lsu_dgen_0_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_issued (_core_io_lsu_dgen_0_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_dis_col_sel (_core_io_lsu_dgen_0_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_br_mask (_core_io_lsu_dgen_0_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_br_tag (_core_io_lsu_dgen_0_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_br_type (_core_io_lsu_dgen_0_bits_uop_br_type), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_sfb (_core_io_lsu_dgen_0_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_fence (_core_io_lsu_dgen_0_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_fencei (_core_io_lsu_dgen_0_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_sfence (_core_io_lsu_dgen_0_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_amo (_core_io_lsu_dgen_0_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_eret (_core_io_lsu_dgen_0_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_0_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_rocc (_core_io_lsu_dgen_0_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_mov (_core_io_lsu_dgen_0_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ftq_idx (_core_io_lsu_dgen_0_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_edge_inst (_core_io_lsu_dgen_0_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_pc_lob (_core_io_lsu_dgen_0_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_taken (_core_io_lsu_dgen_0_bits_uop_taken), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_imm_rename (_core_io_lsu_dgen_0_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_imm_sel (_core_io_lsu_dgen_0_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_pimm (_core_io_lsu_dgen_0_bits_uop_pimm), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_imm_packed (_core_io_lsu_dgen_0_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_op1_sel (_core_io_lsu_dgen_0_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_op2_sel (_core_io_lsu_dgen_0_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_0_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_rob_idx (_core_io_lsu_dgen_0_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ldq_idx (_core_io_lsu_dgen_0_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_stq_idx (_core_io_lsu_dgen_0_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_rxq_idx (_core_io_lsu_dgen_0_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_pdst (_core_io_lsu_dgen_0_bits_uop_pdst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs1 (_core_io_lsu_dgen_0_bits_uop_prs1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs2 (_core_io_lsu_dgen_0_bits_uop_prs2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs3 (_core_io_lsu_dgen_0_bits_uop_prs3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ppred (_core_io_lsu_dgen_0_bits_uop_ppred), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs1_busy (_core_io_lsu_dgen_0_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs2_busy (_core_io_lsu_dgen_0_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_prs3_busy (_core_io_lsu_dgen_0_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ppred_busy (_core_io_lsu_dgen_0_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_stale_pdst (_core_io_lsu_dgen_0_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_exception (_core_io_lsu_dgen_0_bits_uop_exception), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_exc_cause (_core_io_lsu_dgen_0_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_mem_cmd (_core_io_lsu_dgen_0_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_mem_size (_core_io_lsu_dgen_0_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_mem_signed (_core_io_lsu_dgen_0_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_uses_ldq (_core_io_lsu_dgen_0_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_uses_stq (_core_io_lsu_dgen_0_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_is_unique (_core_io_lsu_dgen_0_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_flush_on_commit (_core_io_lsu_dgen_0_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_csr_cmd (_core_io_lsu_dgen_0_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_0_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_ldst (_core_io_lsu_dgen_0_bits_uop_ldst), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs1 (_core_io_lsu_dgen_0_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs2 (_core_io_lsu_dgen_0_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs3 (_core_io_lsu_dgen_0_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_dst_rtype (_core_io_lsu_dgen_0_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs1_rtype (_core_io_lsu_dgen_0_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_lrs2_rtype (_core_io_lsu_dgen_0_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_frs3_en (_core_io_lsu_dgen_0_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fcn_dw (_core_io_lsu_dgen_0_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fcn_op (_core_io_lsu_dgen_0_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_val (_core_io_lsu_dgen_0_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_rm (_core_io_lsu_dgen_0_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_fp_typ (_core_io_lsu_dgen_0_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_0_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_0_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_bp_debug_if (_core_io_lsu_dgen_0_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_0_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_fsrc (_core_io_lsu_dgen_0_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_dgen_0_bits_uop_debug_tsrc (_core_io_lsu_dgen_0_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_dgen_0_bits_data (_core_io_lsu_dgen_0_bits_data), // @[tile.scala:158:20] .io_core_dgen_1_valid (_core_io_lsu_dgen_1_valid), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_inst (_core_io_lsu_dgen_1_bits_uop_inst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_inst (_core_io_lsu_dgen_1_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_rvc (_core_io_lsu_dgen_1_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_pc (_core_io_lsu_dgen_1_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_0 (_core_io_lsu_dgen_1_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_1 (_core_io_lsu_dgen_1_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_2 (_core_io_lsu_dgen_1_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iq_type_3 (_core_io_lsu_dgen_1_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_0 (_core_io_lsu_dgen_1_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_1 (_core_io_lsu_dgen_1_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_2 (_core_io_lsu_dgen_1_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_3 (_core_io_lsu_dgen_1_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_4 (_core_io_lsu_dgen_1_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_5 (_core_io_lsu_dgen_1_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_6 (_core_io_lsu_dgen_1_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_7 (_core_io_lsu_dgen_1_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_8 (_core_io_lsu_dgen_1_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fu_code_9 (_core_io_lsu_dgen_1_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_issued (_core_io_lsu_dgen_1_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_1_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_dis_col_sel (_core_io_lsu_dgen_1_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_br_mask (_core_io_lsu_dgen_1_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_br_tag (_core_io_lsu_dgen_1_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_br_type (_core_io_lsu_dgen_1_bits_uop_br_type), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_sfb (_core_io_lsu_dgen_1_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_fence (_core_io_lsu_dgen_1_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_fencei (_core_io_lsu_dgen_1_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_sfence (_core_io_lsu_dgen_1_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_amo (_core_io_lsu_dgen_1_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_eret (_core_io_lsu_dgen_1_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_1_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_rocc (_core_io_lsu_dgen_1_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_mov (_core_io_lsu_dgen_1_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ftq_idx (_core_io_lsu_dgen_1_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_edge_inst (_core_io_lsu_dgen_1_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_pc_lob (_core_io_lsu_dgen_1_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_taken (_core_io_lsu_dgen_1_bits_uop_taken), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_imm_rename (_core_io_lsu_dgen_1_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_imm_sel (_core_io_lsu_dgen_1_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_pimm (_core_io_lsu_dgen_1_bits_uop_pimm), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_imm_packed (_core_io_lsu_dgen_1_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_op1_sel (_core_io_lsu_dgen_1_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_op2_sel (_core_io_lsu_dgen_1_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_1_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_rob_idx (_core_io_lsu_dgen_1_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ldq_idx (_core_io_lsu_dgen_1_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_stq_idx (_core_io_lsu_dgen_1_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_rxq_idx (_core_io_lsu_dgen_1_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_pdst (_core_io_lsu_dgen_1_bits_uop_pdst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs1 (_core_io_lsu_dgen_1_bits_uop_prs1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs2 (_core_io_lsu_dgen_1_bits_uop_prs2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs3 (_core_io_lsu_dgen_1_bits_uop_prs3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ppred (_core_io_lsu_dgen_1_bits_uop_ppred), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs1_busy (_core_io_lsu_dgen_1_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs2_busy (_core_io_lsu_dgen_1_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_prs3_busy (_core_io_lsu_dgen_1_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ppred_busy (_core_io_lsu_dgen_1_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_stale_pdst (_core_io_lsu_dgen_1_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_exception (_core_io_lsu_dgen_1_bits_uop_exception), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_exc_cause (_core_io_lsu_dgen_1_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_mem_cmd (_core_io_lsu_dgen_1_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_mem_size (_core_io_lsu_dgen_1_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_mem_signed (_core_io_lsu_dgen_1_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_uses_ldq (_core_io_lsu_dgen_1_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_uses_stq (_core_io_lsu_dgen_1_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_is_unique (_core_io_lsu_dgen_1_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_flush_on_commit (_core_io_lsu_dgen_1_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_csr_cmd (_core_io_lsu_dgen_1_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_1_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_ldst (_core_io_lsu_dgen_1_bits_uop_ldst), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs1 (_core_io_lsu_dgen_1_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs2 (_core_io_lsu_dgen_1_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs3 (_core_io_lsu_dgen_1_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_dst_rtype (_core_io_lsu_dgen_1_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs1_rtype (_core_io_lsu_dgen_1_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_lrs2_rtype (_core_io_lsu_dgen_1_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_frs3_en (_core_io_lsu_dgen_1_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fcn_dw (_core_io_lsu_dgen_1_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fcn_op (_core_io_lsu_dgen_1_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_val (_core_io_lsu_dgen_1_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_rm (_core_io_lsu_dgen_1_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_fp_typ (_core_io_lsu_dgen_1_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_1_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_1_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_bp_debug_if (_core_io_lsu_dgen_1_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_1_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_fsrc (_core_io_lsu_dgen_1_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_dgen_1_bits_uop_debug_tsrc (_core_io_lsu_dgen_1_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_dgen_1_bits_data (_core_io_lsu_dgen_1_bits_data), // @[tile.scala:158:20] .io_core_dgen_2_valid (_core_io_lsu_dgen_2_valid), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_inst (_core_io_lsu_dgen_2_bits_uop_inst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_inst (_core_io_lsu_dgen_2_bits_uop_debug_inst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_rvc (_core_io_lsu_dgen_2_bits_uop_is_rvc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_pc (_core_io_lsu_dgen_2_bits_uop_debug_pc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_0 (_core_io_lsu_dgen_2_bits_uop_iq_type_0), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_1 (_core_io_lsu_dgen_2_bits_uop_iq_type_1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_2 (_core_io_lsu_dgen_2_bits_uop_iq_type_2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iq_type_3 (_core_io_lsu_dgen_2_bits_uop_iq_type_3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_0 (_core_io_lsu_dgen_2_bits_uop_fu_code_0), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_1 (_core_io_lsu_dgen_2_bits_uop_fu_code_1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_2 (_core_io_lsu_dgen_2_bits_uop_fu_code_2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_3 (_core_io_lsu_dgen_2_bits_uop_fu_code_3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_4 (_core_io_lsu_dgen_2_bits_uop_fu_code_4), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_5 (_core_io_lsu_dgen_2_bits_uop_fu_code_5), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_6 (_core_io_lsu_dgen_2_bits_uop_fu_code_6), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_7 (_core_io_lsu_dgen_2_bits_uop_fu_code_7), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_8 (_core_io_lsu_dgen_2_bits_uop_fu_code_8), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fu_code_9 (_core_io_lsu_dgen_2_bits_uop_fu_code_9), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_issued (_core_io_lsu_dgen_2_bits_uop_iw_issued), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_issued_partial_agen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_issued_partial_dgen (_core_io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p1_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p2_speculative_child (_core_io_lsu_dgen_2_bits_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p1_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p2_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_iw_p3_bypass_hint (_core_io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_dis_col_sel (_core_io_lsu_dgen_2_bits_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_br_mask (_core_io_lsu_dgen_2_bits_uop_br_mask), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_br_tag (_core_io_lsu_dgen_2_bits_uop_br_tag), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_br_type (_core_io_lsu_dgen_2_bits_uop_br_type), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_sfb (_core_io_lsu_dgen_2_bits_uop_is_sfb), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_fence (_core_io_lsu_dgen_2_bits_uop_is_fence), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_fencei (_core_io_lsu_dgen_2_bits_uop_is_fencei), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_sfence (_core_io_lsu_dgen_2_bits_uop_is_sfence), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_amo (_core_io_lsu_dgen_2_bits_uop_is_amo), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_eret (_core_io_lsu_dgen_2_bits_uop_is_eret), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_sys_pc2epc (_core_io_lsu_dgen_2_bits_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_rocc (_core_io_lsu_dgen_2_bits_uop_is_rocc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_mov (_core_io_lsu_dgen_2_bits_uop_is_mov), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ftq_idx (_core_io_lsu_dgen_2_bits_uop_ftq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_edge_inst (_core_io_lsu_dgen_2_bits_uop_edge_inst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_pc_lob (_core_io_lsu_dgen_2_bits_uop_pc_lob), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_taken (_core_io_lsu_dgen_2_bits_uop_taken), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_imm_rename (_core_io_lsu_dgen_2_bits_uop_imm_rename), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_imm_sel (_core_io_lsu_dgen_2_bits_uop_imm_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_pimm (_core_io_lsu_dgen_2_bits_uop_pimm), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_imm_packed (_core_io_lsu_dgen_2_bits_uop_imm_packed), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_op1_sel (_core_io_lsu_dgen_2_bits_uop_op1_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_op2_sel (_core_io_lsu_dgen_2_bits_uop_op2_sel), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ldst (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_wen (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ren1 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ren2 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_ren3 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_swap12 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_swap23 (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_fromint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_toint (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_fastpipe (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_fma (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_div (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_sqrt (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_wflags (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_ctrl_vec (_core_io_lsu_dgen_2_bits_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_rob_idx (_core_io_lsu_dgen_2_bits_uop_rob_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ldq_idx (_core_io_lsu_dgen_2_bits_uop_ldq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_stq_idx (_core_io_lsu_dgen_2_bits_uop_stq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_rxq_idx (_core_io_lsu_dgen_2_bits_uop_rxq_idx), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_pdst (_core_io_lsu_dgen_2_bits_uop_pdst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs1 (_core_io_lsu_dgen_2_bits_uop_prs1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs2 (_core_io_lsu_dgen_2_bits_uop_prs2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs3 (_core_io_lsu_dgen_2_bits_uop_prs3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ppred (_core_io_lsu_dgen_2_bits_uop_ppred), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs1_busy (_core_io_lsu_dgen_2_bits_uop_prs1_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs2_busy (_core_io_lsu_dgen_2_bits_uop_prs2_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_prs3_busy (_core_io_lsu_dgen_2_bits_uop_prs3_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ppred_busy (_core_io_lsu_dgen_2_bits_uop_ppred_busy), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_stale_pdst (_core_io_lsu_dgen_2_bits_uop_stale_pdst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_exception (_core_io_lsu_dgen_2_bits_uop_exception), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_exc_cause (_core_io_lsu_dgen_2_bits_uop_exc_cause), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_mem_cmd (_core_io_lsu_dgen_2_bits_uop_mem_cmd), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_mem_size (_core_io_lsu_dgen_2_bits_uop_mem_size), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_mem_signed (_core_io_lsu_dgen_2_bits_uop_mem_signed), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_uses_ldq (_core_io_lsu_dgen_2_bits_uop_uses_ldq), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_uses_stq (_core_io_lsu_dgen_2_bits_uop_uses_stq), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_is_unique (_core_io_lsu_dgen_2_bits_uop_is_unique), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_flush_on_commit (_core_io_lsu_dgen_2_bits_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_csr_cmd (_core_io_lsu_dgen_2_bits_uop_csr_cmd), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ldst_is_rs1 (_core_io_lsu_dgen_2_bits_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_ldst (_core_io_lsu_dgen_2_bits_uop_ldst), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs1 (_core_io_lsu_dgen_2_bits_uop_lrs1), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs2 (_core_io_lsu_dgen_2_bits_uop_lrs2), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs3 (_core_io_lsu_dgen_2_bits_uop_lrs3), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_dst_rtype (_core_io_lsu_dgen_2_bits_uop_dst_rtype), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs1_rtype (_core_io_lsu_dgen_2_bits_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_lrs2_rtype (_core_io_lsu_dgen_2_bits_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_frs3_en (_core_io_lsu_dgen_2_bits_uop_frs3_en), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fcn_dw (_core_io_lsu_dgen_2_bits_uop_fcn_dw), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fcn_op (_core_io_lsu_dgen_2_bits_uop_fcn_op), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_val (_core_io_lsu_dgen_2_bits_uop_fp_val), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_rm (_core_io_lsu_dgen_2_bits_uop_fp_rm), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_fp_typ (_core_io_lsu_dgen_2_bits_uop_fp_typ), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_xcpt_pf_if (_core_io_lsu_dgen_2_bits_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_xcpt_ae_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_xcpt_ma_if (_core_io_lsu_dgen_2_bits_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_bp_debug_if (_core_io_lsu_dgen_2_bits_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_bp_xcpt_if (_core_io_lsu_dgen_2_bits_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_fsrc (_core_io_lsu_dgen_2_bits_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_dgen_2_bits_uop_debug_tsrc (_core_io_lsu_dgen_2_bits_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_dgen_2_bits_data (_core_io_lsu_dgen_2_bits_data), // @[tile.scala:158:20] .io_core_iwakeups_0_valid (_lsu_io_core_iwakeups_0_valid), .io_core_iwakeups_0_bits_uop_inst (_lsu_io_core_iwakeups_0_bits_uop_inst), .io_core_iwakeups_0_bits_uop_debug_inst (_lsu_io_core_iwakeups_0_bits_uop_debug_inst), .io_core_iwakeups_0_bits_uop_is_rvc (_lsu_io_core_iwakeups_0_bits_uop_is_rvc), .io_core_iwakeups_0_bits_uop_debug_pc (_lsu_io_core_iwakeups_0_bits_uop_debug_pc), .io_core_iwakeups_0_bits_uop_iq_type_0 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_0), .io_core_iwakeups_0_bits_uop_iq_type_1 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_1), .io_core_iwakeups_0_bits_uop_iq_type_2 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_2), .io_core_iwakeups_0_bits_uop_iq_type_3 (_lsu_io_core_iwakeups_0_bits_uop_iq_type_3), .io_core_iwakeups_0_bits_uop_fu_code_0 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_0), .io_core_iwakeups_0_bits_uop_fu_code_1 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_1), .io_core_iwakeups_0_bits_uop_fu_code_2 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_2), .io_core_iwakeups_0_bits_uop_fu_code_3 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_3), .io_core_iwakeups_0_bits_uop_fu_code_4 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_4), .io_core_iwakeups_0_bits_uop_fu_code_5 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_5), .io_core_iwakeups_0_bits_uop_fu_code_6 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_6), .io_core_iwakeups_0_bits_uop_fu_code_7 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_7), .io_core_iwakeups_0_bits_uop_fu_code_8 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_8), .io_core_iwakeups_0_bits_uop_fu_code_9 (_lsu_io_core_iwakeups_0_bits_uop_fu_code_9), .io_core_iwakeups_0_bits_uop_iw_issued (_lsu_io_core_iwakeups_0_bits_uop_iw_issued), .io_core_iwakeups_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_agen), .io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen), .io_core_iwakeups_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_speculative_child), .io_core_iwakeups_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_speculative_child), .io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint), .io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint), .io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint), .io_core_iwakeups_0_bits_uop_dis_col_sel (_lsu_io_core_iwakeups_0_bits_uop_dis_col_sel), .io_core_iwakeups_0_bits_uop_br_mask (_lsu_io_core_iwakeups_0_bits_uop_br_mask), .io_core_iwakeups_0_bits_uop_br_tag (_lsu_io_core_iwakeups_0_bits_uop_br_tag), .io_core_iwakeups_0_bits_uop_br_type (_lsu_io_core_iwakeups_0_bits_uop_br_type), .io_core_iwakeups_0_bits_uop_is_sfb (_lsu_io_core_iwakeups_0_bits_uop_is_sfb), .io_core_iwakeups_0_bits_uop_is_fence (_lsu_io_core_iwakeups_0_bits_uop_is_fence), .io_core_iwakeups_0_bits_uop_is_fencei (_lsu_io_core_iwakeups_0_bits_uop_is_fencei), .io_core_iwakeups_0_bits_uop_is_sfence (_lsu_io_core_iwakeups_0_bits_uop_is_sfence), .io_core_iwakeups_0_bits_uop_is_amo (_lsu_io_core_iwakeups_0_bits_uop_is_amo), .io_core_iwakeups_0_bits_uop_is_eret (_lsu_io_core_iwakeups_0_bits_uop_is_eret), .io_core_iwakeups_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iwakeups_0_bits_uop_is_sys_pc2epc), .io_core_iwakeups_0_bits_uop_is_rocc (_lsu_io_core_iwakeups_0_bits_uop_is_rocc), .io_core_iwakeups_0_bits_uop_is_mov (_lsu_io_core_iwakeups_0_bits_uop_is_mov), .io_core_iwakeups_0_bits_uop_ftq_idx (_lsu_io_core_iwakeups_0_bits_uop_ftq_idx), .io_core_iwakeups_0_bits_uop_edge_inst (_lsu_io_core_iwakeups_0_bits_uop_edge_inst), .io_core_iwakeups_0_bits_uop_pc_lob (_lsu_io_core_iwakeups_0_bits_uop_pc_lob), .io_core_iwakeups_0_bits_uop_taken (_lsu_io_core_iwakeups_0_bits_uop_taken), .io_core_iwakeups_0_bits_uop_imm_rename (_lsu_io_core_iwakeups_0_bits_uop_imm_rename), .io_core_iwakeups_0_bits_uop_imm_sel (_lsu_io_core_iwakeups_0_bits_uop_imm_sel), .io_core_iwakeups_0_bits_uop_pimm (_lsu_io_core_iwakeups_0_bits_uop_pimm), .io_core_iwakeups_0_bits_uop_imm_packed (_lsu_io_core_iwakeups_0_bits_uop_imm_packed), .io_core_iwakeups_0_bits_uop_op1_sel (_lsu_io_core_iwakeups_0_bits_uop_op1_sel), .io_core_iwakeups_0_bits_uop_op2_sel (_lsu_io_core_iwakeups_0_bits_uop_op2_sel), .io_core_iwakeups_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ldst), .io_core_iwakeups_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wen), .io_core_iwakeups_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren1), .io_core_iwakeups_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren2), .io_core_iwakeups_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_ren3), .io_core_iwakeups_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap12), .io_core_iwakeups_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_swap23), .io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn), .io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut), .io_core_iwakeups_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fromint), .io_core_iwakeups_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_toint), .io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe), .io_core_iwakeups_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_fma), .io_core_iwakeups_0_bits_uop_fp_ctrl_div (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_div), .io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt), .io_core_iwakeups_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_wflags), .io_core_iwakeups_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iwakeups_0_bits_uop_fp_ctrl_vec), .io_core_iwakeups_0_bits_uop_rob_idx (_lsu_io_core_iwakeups_0_bits_uop_rob_idx), .io_core_iwakeups_0_bits_uop_ldq_idx (_lsu_io_core_iwakeups_0_bits_uop_ldq_idx), .io_core_iwakeups_0_bits_uop_stq_idx (_lsu_io_core_iwakeups_0_bits_uop_stq_idx), .io_core_iwakeups_0_bits_uop_rxq_idx (_lsu_io_core_iwakeups_0_bits_uop_rxq_idx), .io_core_iwakeups_0_bits_uop_pdst (_lsu_io_core_iwakeups_0_bits_uop_pdst), .io_core_iwakeups_0_bits_uop_prs1 (_lsu_io_core_iwakeups_0_bits_uop_prs1), .io_core_iwakeups_0_bits_uop_prs2 (_lsu_io_core_iwakeups_0_bits_uop_prs2), .io_core_iwakeups_0_bits_uop_prs3 (_lsu_io_core_iwakeups_0_bits_uop_prs3), .io_core_iwakeups_0_bits_uop_ppred (_lsu_io_core_iwakeups_0_bits_uop_ppred), .io_core_iwakeups_0_bits_uop_prs1_busy (_lsu_io_core_iwakeups_0_bits_uop_prs1_busy), .io_core_iwakeups_0_bits_uop_prs2_busy (_lsu_io_core_iwakeups_0_bits_uop_prs2_busy), .io_core_iwakeups_0_bits_uop_prs3_busy (_lsu_io_core_iwakeups_0_bits_uop_prs3_busy), .io_core_iwakeups_0_bits_uop_ppred_busy (_lsu_io_core_iwakeups_0_bits_uop_ppred_busy), .io_core_iwakeups_0_bits_uop_stale_pdst (_lsu_io_core_iwakeups_0_bits_uop_stale_pdst), .io_core_iwakeups_0_bits_uop_exception (_lsu_io_core_iwakeups_0_bits_uop_exception), .io_core_iwakeups_0_bits_uop_exc_cause (_lsu_io_core_iwakeups_0_bits_uop_exc_cause), .io_core_iwakeups_0_bits_uop_mem_cmd (_lsu_io_core_iwakeups_0_bits_uop_mem_cmd), .io_core_iwakeups_0_bits_uop_mem_size (_lsu_io_core_iwakeups_0_bits_uop_mem_size), .io_core_iwakeups_0_bits_uop_mem_signed (_lsu_io_core_iwakeups_0_bits_uop_mem_signed), .io_core_iwakeups_0_bits_uop_uses_ldq (_lsu_io_core_iwakeups_0_bits_uop_uses_ldq), .io_core_iwakeups_0_bits_uop_uses_stq (_lsu_io_core_iwakeups_0_bits_uop_uses_stq), .io_core_iwakeups_0_bits_uop_is_unique (_lsu_io_core_iwakeups_0_bits_uop_is_unique), .io_core_iwakeups_0_bits_uop_flush_on_commit (_lsu_io_core_iwakeups_0_bits_uop_flush_on_commit), .io_core_iwakeups_0_bits_uop_csr_cmd (_lsu_io_core_iwakeups_0_bits_uop_csr_cmd), .io_core_iwakeups_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iwakeups_0_bits_uop_ldst_is_rs1), .io_core_iwakeups_0_bits_uop_ldst (_lsu_io_core_iwakeups_0_bits_uop_ldst), .io_core_iwakeups_0_bits_uop_lrs1 (_lsu_io_core_iwakeups_0_bits_uop_lrs1), .io_core_iwakeups_0_bits_uop_lrs2 (_lsu_io_core_iwakeups_0_bits_uop_lrs2), .io_core_iwakeups_0_bits_uop_lrs3 (_lsu_io_core_iwakeups_0_bits_uop_lrs3), .io_core_iwakeups_0_bits_uop_dst_rtype (_lsu_io_core_iwakeups_0_bits_uop_dst_rtype), .io_core_iwakeups_0_bits_uop_lrs1_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs1_rtype), .io_core_iwakeups_0_bits_uop_lrs2_rtype (_lsu_io_core_iwakeups_0_bits_uop_lrs2_rtype), .io_core_iwakeups_0_bits_uop_frs3_en (_lsu_io_core_iwakeups_0_bits_uop_frs3_en), .io_core_iwakeups_0_bits_uop_fcn_dw (_lsu_io_core_iwakeups_0_bits_uop_fcn_dw), .io_core_iwakeups_0_bits_uop_fcn_op (_lsu_io_core_iwakeups_0_bits_uop_fcn_op), .io_core_iwakeups_0_bits_uop_fp_val (_lsu_io_core_iwakeups_0_bits_uop_fp_val), .io_core_iwakeups_0_bits_uop_fp_rm (_lsu_io_core_iwakeups_0_bits_uop_fp_rm), .io_core_iwakeups_0_bits_uop_fp_typ (_lsu_io_core_iwakeups_0_bits_uop_fp_typ), .io_core_iwakeups_0_bits_uop_xcpt_pf_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_pf_if), .io_core_iwakeups_0_bits_uop_xcpt_ae_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ae_if), .io_core_iwakeups_0_bits_uop_xcpt_ma_if (_lsu_io_core_iwakeups_0_bits_uop_xcpt_ma_if), .io_core_iwakeups_0_bits_uop_bp_debug_if (_lsu_io_core_iwakeups_0_bits_uop_bp_debug_if), .io_core_iwakeups_0_bits_uop_bp_xcpt_if (_lsu_io_core_iwakeups_0_bits_uop_bp_xcpt_if), .io_core_iwakeups_0_bits_uop_debug_fsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_fsrc), .io_core_iwakeups_0_bits_uop_debug_tsrc (_lsu_io_core_iwakeups_0_bits_uop_debug_tsrc), .io_core_iwakeups_0_bits_bypassable (_lsu_io_core_iwakeups_0_bits_bypassable), .io_core_iwakeups_0_bits_speculative_mask (_lsu_io_core_iwakeups_0_bits_speculative_mask), .io_core_iwakeups_0_bits_rebusy (_lsu_io_core_iwakeups_0_bits_rebusy), .io_core_iresp_0_valid (_lsu_io_core_iresp_0_valid), .io_core_iresp_0_bits_uop_inst (_lsu_io_core_iresp_0_bits_uop_inst), .io_core_iresp_0_bits_uop_debug_inst (_lsu_io_core_iresp_0_bits_uop_debug_inst), .io_core_iresp_0_bits_uop_is_rvc (_lsu_io_core_iresp_0_bits_uop_is_rvc), .io_core_iresp_0_bits_uop_debug_pc (_lsu_io_core_iresp_0_bits_uop_debug_pc), .io_core_iresp_0_bits_uop_iq_type_0 (_lsu_io_core_iresp_0_bits_uop_iq_type_0), .io_core_iresp_0_bits_uop_iq_type_1 (_lsu_io_core_iresp_0_bits_uop_iq_type_1), .io_core_iresp_0_bits_uop_iq_type_2 (_lsu_io_core_iresp_0_bits_uop_iq_type_2), .io_core_iresp_0_bits_uop_iq_type_3 (_lsu_io_core_iresp_0_bits_uop_iq_type_3), .io_core_iresp_0_bits_uop_fu_code_0 (_lsu_io_core_iresp_0_bits_uop_fu_code_0), .io_core_iresp_0_bits_uop_fu_code_1 (_lsu_io_core_iresp_0_bits_uop_fu_code_1), .io_core_iresp_0_bits_uop_fu_code_2 (_lsu_io_core_iresp_0_bits_uop_fu_code_2), .io_core_iresp_0_bits_uop_fu_code_3 (_lsu_io_core_iresp_0_bits_uop_fu_code_3), .io_core_iresp_0_bits_uop_fu_code_4 (_lsu_io_core_iresp_0_bits_uop_fu_code_4), .io_core_iresp_0_bits_uop_fu_code_5 (_lsu_io_core_iresp_0_bits_uop_fu_code_5), .io_core_iresp_0_bits_uop_fu_code_6 (_lsu_io_core_iresp_0_bits_uop_fu_code_6), .io_core_iresp_0_bits_uop_fu_code_7 (_lsu_io_core_iresp_0_bits_uop_fu_code_7), .io_core_iresp_0_bits_uop_fu_code_8 (_lsu_io_core_iresp_0_bits_uop_fu_code_8), .io_core_iresp_0_bits_uop_fu_code_9 (_lsu_io_core_iresp_0_bits_uop_fu_code_9), .io_core_iresp_0_bits_uop_iw_issued (_lsu_io_core_iresp_0_bits_uop_iw_issued), .io_core_iresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_agen), .io_core_iresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_iresp_0_bits_uop_iw_issued_partial_dgen), .io_core_iresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p1_speculative_child), .io_core_iresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_iresp_0_bits_uop_iw_p2_speculative_child), .io_core_iresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p1_bypass_hint), .io_core_iresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p2_bypass_hint), .io_core_iresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_iresp_0_bits_uop_iw_p3_bypass_hint), .io_core_iresp_0_bits_uop_dis_col_sel (_lsu_io_core_iresp_0_bits_uop_dis_col_sel), .io_core_iresp_0_bits_uop_br_mask (_lsu_io_core_iresp_0_bits_uop_br_mask), .io_core_iresp_0_bits_uop_br_tag (_lsu_io_core_iresp_0_bits_uop_br_tag), .io_core_iresp_0_bits_uop_br_type (_lsu_io_core_iresp_0_bits_uop_br_type), .io_core_iresp_0_bits_uop_is_sfb (_lsu_io_core_iresp_0_bits_uop_is_sfb), .io_core_iresp_0_bits_uop_is_fence (_lsu_io_core_iresp_0_bits_uop_is_fence), .io_core_iresp_0_bits_uop_is_fencei (_lsu_io_core_iresp_0_bits_uop_is_fencei), .io_core_iresp_0_bits_uop_is_sfence (_lsu_io_core_iresp_0_bits_uop_is_sfence), .io_core_iresp_0_bits_uop_is_amo (_lsu_io_core_iresp_0_bits_uop_is_amo), .io_core_iresp_0_bits_uop_is_eret (_lsu_io_core_iresp_0_bits_uop_is_eret), .io_core_iresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_iresp_0_bits_uop_is_sys_pc2epc), .io_core_iresp_0_bits_uop_is_rocc (_lsu_io_core_iresp_0_bits_uop_is_rocc), .io_core_iresp_0_bits_uop_is_mov (_lsu_io_core_iresp_0_bits_uop_is_mov), .io_core_iresp_0_bits_uop_ftq_idx (_lsu_io_core_iresp_0_bits_uop_ftq_idx), .io_core_iresp_0_bits_uop_edge_inst (_lsu_io_core_iresp_0_bits_uop_edge_inst), .io_core_iresp_0_bits_uop_pc_lob (_lsu_io_core_iresp_0_bits_uop_pc_lob), .io_core_iresp_0_bits_uop_taken (_lsu_io_core_iresp_0_bits_uop_taken), .io_core_iresp_0_bits_uop_imm_rename (_lsu_io_core_iresp_0_bits_uop_imm_rename), .io_core_iresp_0_bits_uop_imm_sel (_lsu_io_core_iresp_0_bits_uop_imm_sel), .io_core_iresp_0_bits_uop_pimm (_lsu_io_core_iresp_0_bits_uop_pimm), .io_core_iresp_0_bits_uop_imm_packed (_lsu_io_core_iresp_0_bits_uop_imm_packed), .io_core_iresp_0_bits_uop_op1_sel (_lsu_io_core_iresp_0_bits_uop_op1_sel), .io_core_iresp_0_bits_uop_op2_sel (_lsu_io_core_iresp_0_bits_uop_op2_sel), .io_core_iresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ldst), .io_core_iresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wen), .io_core_iresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren1), .io_core_iresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren2), .io_core_iresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_ren3), .io_core_iresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap12), .io_core_iresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_swap23), .io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn), .io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut), .io_core_iresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fromint), .io_core_iresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_toint), .io_core_iresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fastpipe), .io_core_iresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_fma), .io_core_iresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_div), .io_core_iresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_sqrt), .io_core_iresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_wflags), .io_core_iresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_iresp_0_bits_uop_fp_ctrl_vec), .io_core_iresp_0_bits_uop_rob_idx (_lsu_io_core_iresp_0_bits_uop_rob_idx), .io_core_iresp_0_bits_uop_ldq_idx (_lsu_io_core_iresp_0_bits_uop_ldq_idx), .io_core_iresp_0_bits_uop_stq_idx (_lsu_io_core_iresp_0_bits_uop_stq_idx), .io_core_iresp_0_bits_uop_rxq_idx (_lsu_io_core_iresp_0_bits_uop_rxq_idx), .io_core_iresp_0_bits_uop_pdst (_lsu_io_core_iresp_0_bits_uop_pdst), .io_core_iresp_0_bits_uop_prs1 (_lsu_io_core_iresp_0_bits_uop_prs1), .io_core_iresp_0_bits_uop_prs2 (_lsu_io_core_iresp_0_bits_uop_prs2), .io_core_iresp_0_bits_uop_prs3 (_lsu_io_core_iresp_0_bits_uop_prs3), .io_core_iresp_0_bits_uop_ppred (_lsu_io_core_iresp_0_bits_uop_ppred), .io_core_iresp_0_bits_uop_prs1_busy (_lsu_io_core_iresp_0_bits_uop_prs1_busy), .io_core_iresp_0_bits_uop_prs2_busy (_lsu_io_core_iresp_0_bits_uop_prs2_busy), .io_core_iresp_0_bits_uop_prs3_busy (_lsu_io_core_iresp_0_bits_uop_prs3_busy), .io_core_iresp_0_bits_uop_ppred_busy (_lsu_io_core_iresp_0_bits_uop_ppred_busy), .io_core_iresp_0_bits_uop_stale_pdst (_lsu_io_core_iresp_0_bits_uop_stale_pdst), .io_core_iresp_0_bits_uop_exception (_lsu_io_core_iresp_0_bits_uop_exception), .io_core_iresp_0_bits_uop_exc_cause (_lsu_io_core_iresp_0_bits_uop_exc_cause), .io_core_iresp_0_bits_uop_mem_cmd (_lsu_io_core_iresp_0_bits_uop_mem_cmd), .io_core_iresp_0_bits_uop_mem_size (_lsu_io_core_iresp_0_bits_uop_mem_size), .io_core_iresp_0_bits_uop_mem_signed (_lsu_io_core_iresp_0_bits_uop_mem_signed), .io_core_iresp_0_bits_uop_uses_ldq (_lsu_io_core_iresp_0_bits_uop_uses_ldq), .io_core_iresp_0_bits_uop_uses_stq (_lsu_io_core_iresp_0_bits_uop_uses_stq), .io_core_iresp_0_bits_uop_is_unique (_lsu_io_core_iresp_0_bits_uop_is_unique), .io_core_iresp_0_bits_uop_flush_on_commit (_lsu_io_core_iresp_0_bits_uop_flush_on_commit), .io_core_iresp_0_bits_uop_csr_cmd (_lsu_io_core_iresp_0_bits_uop_csr_cmd), .io_core_iresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_iresp_0_bits_uop_ldst_is_rs1), .io_core_iresp_0_bits_uop_ldst (_lsu_io_core_iresp_0_bits_uop_ldst), .io_core_iresp_0_bits_uop_lrs1 (_lsu_io_core_iresp_0_bits_uop_lrs1), .io_core_iresp_0_bits_uop_lrs2 (_lsu_io_core_iresp_0_bits_uop_lrs2), .io_core_iresp_0_bits_uop_lrs3 (_lsu_io_core_iresp_0_bits_uop_lrs3), .io_core_iresp_0_bits_uop_dst_rtype (_lsu_io_core_iresp_0_bits_uop_dst_rtype), .io_core_iresp_0_bits_uop_lrs1_rtype (_lsu_io_core_iresp_0_bits_uop_lrs1_rtype), .io_core_iresp_0_bits_uop_lrs2_rtype (_lsu_io_core_iresp_0_bits_uop_lrs2_rtype), .io_core_iresp_0_bits_uop_frs3_en (_lsu_io_core_iresp_0_bits_uop_frs3_en), .io_core_iresp_0_bits_uop_fcn_dw (_lsu_io_core_iresp_0_bits_uop_fcn_dw), .io_core_iresp_0_bits_uop_fcn_op (_lsu_io_core_iresp_0_bits_uop_fcn_op), .io_core_iresp_0_bits_uop_fp_val (_lsu_io_core_iresp_0_bits_uop_fp_val), .io_core_iresp_0_bits_uop_fp_rm (_lsu_io_core_iresp_0_bits_uop_fp_rm), .io_core_iresp_0_bits_uop_fp_typ (_lsu_io_core_iresp_0_bits_uop_fp_typ), .io_core_iresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_iresp_0_bits_uop_xcpt_pf_if), .io_core_iresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ae_if), .io_core_iresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_iresp_0_bits_uop_xcpt_ma_if), .io_core_iresp_0_bits_uop_bp_debug_if (_lsu_io_core_iresp_0_bits_uop_bp_debug_if), .io_core_iresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_iresp_0_bits_uop_bp_xcpt_if), .io_core_iresp_0_bits_uop_debug_fsrc (_lsu_io_core_iresp_0_bits_uop_debug_fsrc), .io_core_iresp_0_bits_uop_debug_tsrc (_lsu_io_core_iresp_0_bits_uop_debug_tsrc), .io_core_iresp_0_bits_data (_lsu_io_core_iresp_0_bits_data), .io_core_fresp_0_valid (_lsu_io_core_fresp_0_valid), .io_core_fresp_0_bits_uop_inst (_lsu_io_core_fresp_0_bits_uop_inst), .io_core_fresp_0_bits_uop_debug_inst (_lsu_io_core_fresp_0_bits_uop_debug_inst), .io_core_fresp_0_bits_uop_is_rvc (_lsu_io_core_fresp_0_bits_uop_is_rvc), .io_core_fresp_0_bits_uop_debug_pc (_lsu_io_core_fresp_0_bits_uop_debug_pc), .io_core_fresp_0_bits_uop_iq_type_0 (_lsu_io_core_fresp_0_bits_uop_iq_type_0), .io_core_fresp_0_bits_uop_iq_type_1 (_lsu_io_core_fresp_0_bits_uop_iq_type_1), .io_core_fresp_0_bits_uop_iq_type_2 (_lsu_io_core_fresp_0_bits_uop_iq_type_2), .io_core_fresp_0_bits_uop_iq_type_3 (_lsu_io_core_fresp_0_bits_uop_iq_type_3), .io_core_fresp_0_bits_uop_fu_code_0 (_lsu_io_core_fresp_0_bits_uop_fu_code_0), .io_core_fresp_0_bits_uop_fu_code_1 (_lsu_io_core_fresp_0_bits_uop_fu_code_1), .io_core_fresp_0_bits_uop_fu_code_2 (_lsu_io_core_fresp_0_bits_uop_fu_code_2), .io_core_fresp_0_bits_uop_fu_code_3 (_lsu_io_core_fresp_0_bits_uop_fu_code_3), .io_core_fresp_0_bits_uop_fu_code_4 (_lsu_io_core_fresp_0_bits_uop_fu_code_4), .io_core_fresp_0_bits_uop_fu_code_5 (_lsu_io_core_fresp_0_bits_uop_fu_code_5), .io_core_fresp_0_bits_uop_fu_code_6 (_lsu_io_core_fresp_0_bits_uop_fu_code_6), .io_core_fresp_0_bits_uop_fu_code_7 (_lsu_io_core_fresp_0_bits_uop_fu_code_7), .io_core_fresp_0_bits_uop_fu_code_8 (_lsu_io_core_fresp_0_bits_uop_fu_code_8), .io_core_fresp_0_bits_uop_fu_code_9 (_lsu_io_core_fresp_0_bits_uop_fu_code_9), .io_core_fresp_0_bits_uop_iw_issued (_lsu_io_core_fresp_0_bits_uop_iw_issued), .io_core_fresp_0_bits_uop_iw_issued_partial_agen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_agen), .io_core_fresp_0_bits_uop_iw_issued_partial_dgen (_lsu_io_core_fresp_0_bits_uop_iw_issued_partial_dgen), .io_core_fresp_0_bits_uop_iw_p1_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p1_speculative_child), .io_core_fresp_0_bits_uop_iw_p2_speculative_child (_lsu_io_core_fresp_0_bits_uop_iw_p2_speculative_child), .io_core_fresp_0_bits_uop_iw_p1_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p1_bypass_hint), .io_core_fresp_0_bits_uop_iw_p2_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p2_bypass_hint), .io_core_fresp_0_bits_uop_iw_p3_bypass_hint (_lsu_io_core_fresp_0_bits_uop_iw_p3_bypass_hint), .io_core_fresp_0_bits_uop_dis_col_sel (_lsu_io_core_fresp_0_bits_uop_dis_col_sel), .io_core_fresp_0_bits_uop_br_mask (_lsu_io_core_fresp_0_bits_uop_br_mask), .io_core_fresp_0_bits_uop_br_tag (_lsu_io_core_fresp_0_bits_uop_br_tag), .io_core_fresp_0_bits_uop_br_type (_lsu_io_core_fresp_0_bits_uop_br_type), .io_core_fresp_0_bits_uop_is_sfb (_lsu_io_core_fresp_0_bits_uop_is_sfb), .io_core_fresp_0_bits_uop_is_fence (_lsu_io_core_fresp_0_bits_uop_is_fence), .io_core_fresp_0_bits_uop_is_fencei (_lsu_io_core_fresp_0_bits_uop_is_fencei), .io_core_fresp_0_bits_uop_is_sfence (_lsu_io_core_fresp_0_bits_uop_is_sfence), .io_core_fresp_0_bits_uop_is_amo (_lsu_io_core_fresp_0_bits_uop_is_amo), .io_core_fresp_0_bits_uop_is_eret (_lsu_io_core_fresp_0_bits_uop_is_eret), .io_core_fresp_0_bits_uop_is_sys_pc2epc (_lsu_io_core_fresp_0_bits_uop_is_sys_pc2epc), .io_core_fresp_0_bits_uop_is_rocc (_lsu_io_core_fresp_0_bits_uop_is_rocc), .io_core_fresp_0_bits_uop_is_mov (_lsu_io_core_fresp_0_bits_uop_is_mov), .io_core_fresp_0_bits_uop_ftq_idx (_lsu_io_core_fresp_0_bits_uop_ftq_idx), .io_core_fresp_0_bits_uop_edge_inst (_lsu_io_core_fresp_0_bits_uop_edge_inst), .io_core_fresp_0_bits_uop_pc_lob (_lsu_io_core_fresp_0_bits_uop_pc_lob), .io_core_fresp_0_bits_uop_taken (_lsu_io_core_fresp_0_bits_uop_taken), .io_core_fresp_0_bits_uop_imm_rename (_lsu_io_core_fresp_0_bits_uop_imm_rename), .io_core_fresp_0_bits_uop_imm_sel (_lsu_io_core_fresp_0_bits_uop_imm_sel), .io_core_fresp_0_bits_uop_pimm (_lsu_io_core_fresp_0_bits_uop_pimm), .io_core_fresp_0_bits_uop_imm_packed (_lsu_io_core_fresp_0_bits_uop_imm_packed), .io_core_fresp_0_bits_uop_op1_sel (_lsu_io_core_fresp_0_bits_uop_op1_sel), .io_core_fresp_0_bits_uop_op2_sel (_lsu_io_core_fresp_0_bits_uop_op2_sel), .io_core_fresp_0_bits_uop_fp_ctrl_ldst (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ldst), .io_core_fresp_0_bits_uop_fp_ctrl_wen (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wen), .io_core_fresp_0_bits_uop_fp_ctrl_ren1 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren1), .io_core_fresp_0_bits_uop_fp_ctrl_ren2 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren2), .io_core_fresp_0_bits_uop_fp_ctrl_ren3 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_ren3), .io_core_fresp_0_bits_uop_fp_ctrl_swap12 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap12), .io_core_fresp_0_bits_uop_fp_ctrl_swap23 (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_swap23), .io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn), .io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut), .io_core_fresp_0_bits_uop_fp_ctrl_fromint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fromint), .io_core_fresp_0_bits_uop_fp_ctrl_toint (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_toint), .io_core_fresp_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fastpipe), .io_core_fresp_0_bits_uop_fp_ctrl_fma (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_fma), .io_core_fresp_0_bits_uop_fp_ctrl_div (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_div), .io_core_fresp_0_bits_uop_fp_ctrl_sqrt (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_sqrt), .io_core_fresp_0_bits_uop_fp_ctrl_wflags (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_wflags), .io_core_fresp_0_bits_uop_fp_ctrl_vec (_lsu_io_core_fresp_0_bits_uop_fp_ctrl_vec), .io_core_fresp_0_bits_uop_rob_idx (_lsu_io_core_fresp_0_bits_uop_rob_idx), .io_core_fresp_0_bits_uop_ldq_idx (_lsu_io_core_fresp_0_bits_uop_ldq_idx), .io_core_fresp_0_bits_uop_stq_idx (_lsu_io_core_fresp_0_bits_uop_stq_idx), .io_core_fresp_0_bits_uop_rxq_idx (_lsu_io_core_fresp_0_bits_uop_rxq_idx), .io_core_fresp_0_bits_uop_pdst (_lsu_io_core_fresp_0_bits_uop_pdst), .io_core_fresp_0_bits_uop_prs1 (_lsu_io_core_fresp_0_bits_uop_prs1), .io_core_fresp_0_bits_uop_prs2 (_lsu_io_core_fresp_0_bits_uop_prs2), .io_core_fresp_0_bits_uop_prs3 (_lsu_io_core_fresp_0_bits_uop_prs3), .io_core_fresp_0_bits_uop_ppred (_lsu_io_core_fresp_0_bits_uop_ppred), .io_core_fresp_0_bits_uop_prs1_busy (_lsu_io_core_fresp_0_bits_uop_prs1_busy), .io_core_fresp_0_bits_uop_prs2_busy (_lsu_io_core_fresp_0_bits_uop_prs2_busy), .io_core_fresp_0_bits_uop_prs3_busy (_lsu_io_core_fresp_0_bits_uop_prs3_busy), .io_core_fresp_0_bits_uop_ppred_busy (_lsu_io_core_fresp_0_bits_uop_ppred_busy), .io_core_fresp_0_bits_uop_stale_pdst (_lsu_io_core_fresp_0_bits_uop_stale_pdst), .io_core_fresp_0_bits_uop_exception (_lsu_io_core_fresp_0_bits_uop_exception), .io_core_fresp_0_bits_uop_exc_cause (_lsu_io_core_fresp_0_bits_uop_exc_cause), .io_core_fresp_0_bits_uop_mem_cmd (_lsu_io_core_fresp_0_bits_uop_mem_cmd), .io_core_fresp_0_bits_uop_mem_size (_lsu_io_core_fresp_0_bits_uop_mem_size), .io_core_fresp_0_bits_uop_mem_signed (_lsu_io_core_fresp_0_bits_uop_mem_signed), .io_core_fresp_0_bits_uop_uses_ldq (_lsu_io_core_fresp_0_bits_uop_uses_ldq), .io_core_fresp_0_bits_uop_uses_stq (_lsu_io_core_fresp_0_bits_uop_uses_stq), .io_core_fresp_0_bits_uop_is_unique (_lsu_io_core_fresp_0_bits_uop_is_unique), .io_core_fresp_0_bits_uop_flush_on_commit (_lsu_io_core_fresp_0_bits_uop_flush_on_commit), .io_core_fresp_0_bits_uop_csr_cmd (_lsu_io_core_fresp_0_bits_uop_csr_cmd), .io_core_fresp_0_bits_uop_ldst_is_rs1 (_lsu_io_core_fresp_0_bits_uop_ldst_is_rs1), .io_core_fresp_0_bits_uop_ldst (_lsu_io_core_fresp_0_bits_uop_ldst), .io_core_fresp_0_bits_uop_lrs1 (_lsu_io_core_fresp_0_bits_uop_lrs1), .io_core_fresp_0_bits_uop_lrs2 (_lsu_io_core_fresp_0_bits_uop_lrs2), .io_core_fresp_0_bits_uop_lrs3 (_lsu_io_core_fresp_0_bits_uop_lrs3), .io_core_fresp_0_bits_uop_dst_rtype (_lsu_io_core_fresp_0_bits_uop_dst_rtype), .io_core_fresp_0_bits_uop_lrs1_rtype (_lsu_io_core_fresp_0_bits_uop_lrs1_rtype), .io_core_fresp_0_bits_uop_lrs2_rtype (_lsu_io_core_fresp_0_bits_uop_lrs2_rtype), .io_core_fresp_0_bits_uop_frs3_en (_lsu_io_core_fresp_0_bits_uop_frs3_en), .io_core_fresp_0_bits_uop_fcn_dw (_lsu_io_core_fresp_0_bits_uop_fcn_dw), .io_core_fresp_0_bits_uop_fcn_op (_lsu_io_core_fresp_0_bits_uop_fcn_op), .io_core_fresp_0_bits_uop_fp_val (_lsu_io_core_fresp_0_bits_uop_fp_val), .io_core_fresp_0_bits_uop_fp_rm (_lsu_io_core_fresp_0_bits_uop_fp_rm), .io_core_fresp_0_bits_uop_fp_typ (_lsu_io_core_fresp_0_bits_uop_fp_typ), .io_core_fresp_0_bits_uop_xcpt_pf_if (_lsu_io_core_fresp_0_bits_uop_xcpt_pf_if), .io_core_fresp_0_bits_uop_xcpt_ae_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ae_if), .io_core_fresp_0_bits_uop_xcpt_ma_if (_lsu_io_core_fresp_0_bits_uop_xcpt_ma_if), .io_core_fresp_0_bits_uop_bp_debug_if (_lsu_io_core_fresp_0_bits_uop_bp_debug_if), .io_core_fresp_0_bits_uop_bp_xcpt_if (_lsu_io_core_fresp_0_bits_uop_bp_xcpt_if), .io_core_fresp_0_bits_uop_debug_fsrc (_lsu_io_core_fresp_0_bits_uop_debug_fsrc), .io_core_fresp_0_bits_uop_debug_tsrc (_lsu_io_core_fresp_0_bits_uop_debug_tsrc), .io_core_fresp_0_bits_data (_lsu_io_core_fresp_0_bits_data), .io_core_sfence_valid (_core_io_lsu_sfence_valid), // @[tile.scala:158:20] .io_core_sfence_bits_rs1 (_core_io_lsu_sfence_bits_rs1), // @[tile.scala:158:20] .io_core_sfence_bits_rs2 (_core_io_lsu_sfence_bits_rs2), // @[tile.scala:158:20] .io_core_sfence_bits_addr (_core_io_lsu_sfence_bits_addr), // @[tile.scala:158:20] .io_core_sfence_bits_asid (_core_io_lsu_sfence_bits_asid), // @[tile.scala:158:20] .io_core_sfence_bits_hv (_core_io_lsu_sfence_bits_hv), // @[tile.scala:158:20] .io_core_sfence_bits_hg (_core_io_lsu_sfence_bits_hg), // @[tile.scala:158:20] .io_core_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_0 (_core_io_lsu_dis_uops_0_bits_iq_type_0), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_1 (_core_io_lsu_dis_uops_0_bits_iq_type_1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_2 (_core_io_lsu_dis_uops_0_bits_iq_type_2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iq_type_3 (_core_io_lsu_dis_uops_0_bits_iq_type_3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_0 (_core_io_lsu_dis_uops_0_bits_fu_code_0), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_1 (_core_io_lsu_dis_uops_0_bits_fu_code_1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_2 (_core_io_lsu_dis_uops_0_bits_fu_code_2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_3 (_core_io_lsu_dis_uops_0_bits_fu_code_3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_4 (_core_io_lsu_dis_uops_0_bits_fu_code_4), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_5 (_core_io_lsu_dis_uops_0_bits_fu_code_5), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_6 (_core_io_lsu_dis_uops_0_bits_fu_code_6), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_7 (_core_io_lsu_dis_uops_0_bits_fu_code_7), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_8 (_core_io_lsu_dis_uops_0_bits_fu_code_8), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fu_code_9 (_core_io_lsu_dis_uops_0_bits_fu_code_9), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_issued (_core_io_lsu_dis_uops_0_bits_iw_issued), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_0_bits_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_0_bits_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_0_bits_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_dis_col_sel (_core_io_lsu_dis_uops_0_bits_dis_col_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_br_type (_core_io_lsu_dis_uops_0_bits_br_type), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_sfence (_core_io_lsu_dis_uops_0_bits_is_sfence), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_eret (_core_io_lsu_dis_uops_0_bits_is_eret), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_rocc (_core_io_lsu_dis_uops_0_bits_is_rocc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_mov (_core_io_lsu_dis_uops_0_bits_is_mov), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_imm_rename (_core_io_lsu_dis_uops_0_bits_imm_rename), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_imm_sel (_core_io_lsu_dis_uops_0_bits_imm_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_pimm (_core_io_lsu_dis_uops_0_bits_pimm), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_op1_sel (_core_io_lsu_dis_uops_0_bits_op1_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_op2_sel (_core_io_lsu_dis_uops_0_bits_op2_sel), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_0_bits_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_0_bits_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_0_bits_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_div (_core_io_lsu_dis_uops_0_bits_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_0_bits_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_0_bits_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_0_bits_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ppred (_core_io_lsu_dis_uops_0_bits_ppred), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ppred_busy (_core_io_lsu_dis_uops_0_bits_ppred_busy), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_csr_cmd (_core_io_lsu_dis_uops_0_bits_csr_cmd), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fcn_dw (_core_io_lsu_dis_uops_0_bits_fcn_dw), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fcn_op (_core_io_lsu_dis_uops_0_bits_fcn_op), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_rm (_core_io_lsu_dis_uops_0_bits_fp_rm), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_fp_typ (_core_io_lsu_dis_uops_0_bits_fp_typ), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), // @[tile.scala:158:20] .io_core_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), // @[tile.scala:158:20] .io_core_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_0 (_core_io_lsu_dis_uops_1_bits_iq_type_0), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_1 (_core_io_lsu_dis_uops_1_bits_iq_type_1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_2 (_core_io_lsu_dis_uops_1_bits_iq_type_2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iq_type_3 (_core_io_lsu_dis_uops_1_bits_iq_type_3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_0 (_core_io_lsu_dis_uops_1_bits_fu_code_0), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_1 (_core_io_lsu_dis_uops_1_bits_fu_code_1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_2 (_core_io_lsu_dis_uops_1_bits_fu_code_2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_3 (_core_io_lsu_dis_uops_1_bits_fu_code_3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_4 (_core_io_lsu_dis_uops_1_bits_fu_code_4), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_5 (_core_io_lsu_dis_uops_1_bits_fu_code_5), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_6 (_core_io_lsu_dis_uops_1_bits_fu_code_6), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_7 (_core_io_lsu_dis_uops_1_bits_fu_code_7), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_8 (_core_io_lsu_dis_uops_1_bits_fu_code_8), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fu_code_9 (_core_io_lsu_dis_uops_1_bits_fu_code_9), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_issued (_core_io_lsu_dis_uops_1_bits_iw_issued), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_issued_partial_agen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_issued_partial_dgen (_core_io_lsu_dis_uops_1_bits_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p1_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p2_speculative_child (_core_io_lsu_dis_uops_1_bits_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p1_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p2_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_iw_p3_bypass_hint (_core_io_lsu_dis_uops_1_bits_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_dis_col_sel (_core_io_lsu_dis_uops_1_bits_dis_col_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_br_type (_core_io_lsu_dis_uops_1_bits_br_type), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_sfence (_core_io_lsu_dis_uops_1_bits_is_sfence), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_eret (_core_io_lsu_dis_uops_1_bits_is_eret), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_rocc (_core_io_lsu_dis_uops_1_bits_is_rocc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_mov (_core_io_lsu_dis_uops_1_bits_is_mov), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_imm_rename (_core_io_lsu_dis_uops_1_bits_imm_rename), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_imm_sel (_core_io_lsu_dis_uops_1_bits_imm_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_pimm (_core_io_lsu_dis_uops_1_bits_pimm), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_op1_sel (_core_io_lsu_dis_uops_1_bits_op1_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_op2_sel (_core_io_lsu_dis_uops_1_bits_op2_sel), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ldst (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_wen (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ren1 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ren2 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_ren3 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_swap12 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_swap23 (_core_io_lsu_dis_uops_1_bits_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_typeTagIn (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_typeTagOut (_core_io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_fromint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_toint (_core_io_lsu_dis_uops_1_bits_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_fastpipe (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_fma (_core_io_lsu_dis_uops_1_bits_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_div (_core_io_lsu_dis_uops_1_bits_fp_ctrl_div), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_sqrt (_core_io_lsu_dis_uops_1_bits_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_wflags (_core_io_lsu_dis_uops_1_bits_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_ctrl_vec (_core_io_lsu_dis_uops_1_bits_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ppred (_core_io_lsu_dis_uops_1_bits_ppred), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ppred_busy (_core_io_lsu_dis_uops_1_bits_ppred_busy), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_csr_cmd (_core_io_lsu_dis_uops_1_bits_csr_cmd), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fcn_dw (_core_io_lsu_dis_uops_1_bits_fcn_dw), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fcn_op (_core_io_lsu_dis_uops_1_bits_fcn_op), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_rm (_core_io_lsu_dis_uops_1_bits_fp_rm), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_fp_typ (_core_io_lsu_dis_uops_1_bits_fp_typ), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), // @[tile.scala:158:20] .io_core_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), // @[tile.scala:158:20] .io_core_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), .io_core_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), .io_core_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), .io_core_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), .io_core_ldq_full_0 (_lsu_io_core_ldq_full_0), .io_core_ldq_full_1 (_lsu_io_core_ldq_full_1), .io_core_stq_full_0 (_lsu_io_core_stq_full_0), .io_core_stq_full_1 (_lsu_io_core_stq_full_1), .io_core_commit_valids_0 (_core_io_lsu_commit_valids_0), // @[tile.scala:158:20] .io_core_commit_valids_1 (_core_io_lsu_commit_valids_1), // @[tile.scala:158:20] .io_core_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), // @[tile.scala:158:20] .io_core_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), // @[tile.scala:158:20] .io_core_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), // @[tile.scala:158:20] .io_core_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_0 (_core_io_lsu_commit_uops_0_iq_type_0), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_1 (_core_io_lsu_commit_uops_0_iq_type_1), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_2 (_core_io_lsu_commit_uops_0_iq_type_2), // @[tile.scala:158:20] .io_core_commit_uops_0_iq_type_3 (_core_io_lsu_commit_uops_0_iq_type_3), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_0 (_core_io_lsu_commit_uops_0_fu_code_0), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_1 (_core_io_lsu_commit_uops_0_fu_code_1), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_2 (_core_io_lsu_commit_uops_0_fu_code_2), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_3 (_core_io_lsu_commit_uops_0_fu_code_3), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_4 (_core_io_lsu_commit_uops_0_fu_code_4), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_5 (_core_io_lsu_commit_uops_0_fu_code_5), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_6 (_core_io_lsu_commit_uops_0_fu_code_6), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_7 (_core_io_lsu_commit_uops_0_fu_code_7), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_8 (_core_io_lsu_commit_uops_0_fu_code_8), // @[tile.scala:158:20] .io_core_commit_uops_0_fu_code_9 (_core_io_lsu_commit_uops_0_fu_code_9), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_issued (_core_io_lsu_commit_uops_0_iw_issued), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_issued_partial_agen (_core_io_lsu_commit_uops_0_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_issued_partial_dgen (_core_io_lsu_commit_uops_0_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p1_speculative_child (_core_io_lsu_commit_uops_0_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p2_speculative_child (_core_io_lsu_commit_uops_0_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p1_bypass_hint (_core_io_lsu_commit_uops_0_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p2_bypass_hint (_core_io_lsu_commit_uops_0_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_0_iw_p3_bypass_hint (_core_io_lsu_commit_uops_0_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_0_dis_col_sel (_core_io_lsu_commit_uops_0_dis_col_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), // @[tile.scala:158:20] .io_core_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), // @[tile.scala:158:20] .io_core_commit_uops_0_br_type (_core_io_lsu_commit_uops_0_br_type), // @[tile.scala:158:20] .io_core_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), // @[tile.scala:158:20] .io_core_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), // @[tile.scala:158:20] .io_core_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), // @[tile.scala:158:20] .io_core_commit_uops_0_is_sfence (_core_io_lsu_commit_uops_0_is_sfence), // @[tile.scala:158:20] .io_core_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), // @[tile.scala:158:20] .io_core_commit_uops_0_is_eret (_core_io_lsu_commit_uops_0_is_eret), // @[tile.scala:158:20] .io_core_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_commit_uops_0_is_rocc (_core_io_lsu_commit_uops_0_is_rocc), // @[tile.scala:158:20] .io_core_commit_uops_0_is_mov (_core_io_lsu_commit_uops_0_is_mov), // @[tile.scala:158:20] .io_core_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), // @[tile.scala:158:20] .io_core_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), // @[tile.scala:158:20] .io_core_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), // @[tile.scala:158:20] .io_core_commit_uops_0_imm_rename (_core_io_lsu_commit_uops_0_imm_rename), // @[tile.scala:158:20] .io_core_commit_uops_0_imm_sel (_core_io_lsu_commit_uops_0_imm_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_pimm (_core_io_lsu_commit_uops_0_pimm), // @[tile.scala:158:20] .io_core_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), // @[tile.scala:158:20] .io_core_commit_uops_0_op1_sel (_core_io_lsu_commit_uops_0_op1_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_op2_sel (_core_io_lsu_commit_uops_0_op2_sel), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ldst (_core_io_lsu_commit_uops_0_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_wen (_core_io_lsu_commit_uops_0_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ren1 (_core_io_lsu_commit_uops_0_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ren2 (_core_io_lsu_commit_uops_0_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_ren3 (_core_io_lsu_commit_uops_0_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_swap12 (_core_io_lsu_commit_uops_0_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_swap23 (_core_io_lsu_commit_uops_0_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_0_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_fromint (_core_io_lsu_commit_uops_0_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_toint (_core_io_lsu_commit_uops_0_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_0_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_fma (_core_io_lsu_commit_uops_0_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_div (_core_io_lsu_commit_uops_0_fp_ctrl_div), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_sqrt (_core_io_lsu_commit_uops_0_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_wflags (_core_io_lsu_commit_uops_0_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_ctrl_vec (_core_io_lsu_commit_uops_0_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), // @[tile.scala:158:20] .io_core_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), // @[tile.scala:158:20] .io_core_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), // @[tile.scala:158:20] .io_core_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), // @[tile.scala:158:20] .io_core_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), // @[tile.scala:158:20] .io_core_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), // @[tile.scala:158:20] .io_core_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), // @[tile.scala:158:20] .io_core_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), // @[tile.scala:158:20] .io_core_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), // @[tile.scala:158:20] .io_core_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), // @[tile.scala:158:20] .io_core_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), // @[tile.scala:158:20] .io_core_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), // @[tile.scala:158:20] .io_core_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), // @[tile.scala:158:20] .io_core_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), // @[tile.scala:158:20] .io_core_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), // @[tile.scala:158:20] .io_core_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), // @[tile.scala:158:20] .io_core_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), // @[tile.scala:158:20] .io_core_commit_uops_0_csr_cmd (_core_io_lsu_commit_uops_0_csr_cmd), // @[tile.scala:158:20] .io_core_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), // @[tile.scala:158:20] .io_core_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), // @[tile.scala:158:20] .io_core_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), // @[tile.scala:158:20] .io_core_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), // @[tile.scala:158:20] .io_core_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), // @[tile.scala:158:20] .io_core_commit_uops_0_fcn_dw (_core_io_lsu_commit_uops_0_fcn_dw), // @[tile.scala:158:20] .io_core_commit_uops_0_fcn_op (_core_io_lsu_commit_uops_0_fcn_op), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_rm (_core_io_lsu_commit_uops_0_fp_rm), // @[tile.scala:158:20] .io_core_commit_uops_0_fp_typ (_core_io_lsu_commit_uops_0_fp_typ), // @[tile.scala:158:20] .io_core_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), // @[tile.scala:158:20] .io_core_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), // @[tile.scala:158:20] .io_core_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), // @[tile.scala:158:20] .io_core_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), // @[tile.scala:158:20] .io_core_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), // @[tile.scala:158:20] .io_core_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), // @[tile.scala:158:20] .io_core_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), // @[tile.scala:158:20] .io_core_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_0 (_core_io_lsu_commit_uops_1_iq_type_0), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_1 (_core_io_lsu_commit_uops_1_iq_type_1), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_2 (_core_io_lsu_commit_uops_1_iq_type_2), // @[tile.scala:158:20] .io_core_commit_uops_1_iq_type_3 (_core_io_lsu_commit_uops_1_iq_type_3), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_0 (_core_io_lsu_commit_uops_1_fu_code_0), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_1 (_core_io_lsu_commit_uops_1_fu_code_1), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_2 (_core_io_lsu_commit_uops_1_fu_code_2), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_3 (_core_io_lsu_commit_uops_1_fu_code_3), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_4 (_core_io_lsu_commit_uops_1_fu_code_4), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_5 (_core_io_lsu_commit_uops_1_fu_code_5), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_6 (_core_io_lsu_commit_uops_1_fu_code_6), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_7 (_core_io_lsu_commit_uops_1_fu_code_7), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_8 (_core_io_lsu_commit_uops_1_fu_code_8), // @[tile.scala:158:20] .io_core_commit_uops_1_fu_code_9 (_core_io_lsu_commit_uops_1_fu_code_9), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_issued (_core_io_lsu_commit_uops_1_iw_issued), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_issued_partial_agen (_core_io_lsu_commit_uops_1_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_issued_partial_dgen (_core_io_lsu_commit_uops_1_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p1_speculative_child (_core_io_lsu_commit_uops_1_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p2_speculative_child (_core_io_lsu_commit_uops_1_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p1_bypass_hint (_core_io_lsu_commit_uops_1_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p2_bypass_hint (_core_io_lsu_commit_uops_1_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_1_iw_p3_bypass_hint (_core_io_lsu_commit_uops_1_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_commit_uops_1_dis_col_sel (_core_io_lsu_commit_uops_1_dis_col_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), // @[tile.scala:158:20] .io_core_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), // @[tile.scala:158:20] .io_core_commit_uops_1_br_type (_core_io_lsu_commit_uops_1_br_type), // @[tile.scala:158:20] .io_core_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), // @[tile.scala:158:20] .io_core_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), // @[tile.scala:158:20] .io_core_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), // @[tile.scala:158:20] .io_core_commit_uops_1_is_sfence (_core_io_lsu_commit_uops_1_is_sfence), // @[tile.scala:158:20] .io_core_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), // @[tile.scala:158:20] .io_core_commit_uops_1_is_eret (_core_io_lsu_commit_uops_1_is_eret), // @[tile.scala:158:20] .io_core_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_commit_uops_1_is_rocc (_core_io_lsu_commit_uops_1_is_rocc), // @[tile.scala:158:20] .io_core_commit_uops_1_is_mov (_core_io_lsu_commit_uops_1_is_mov), // @[tile.scala:158:20] .io_core_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), // @[tile.scala:158:20] .io_core_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), // @[tile.scala:158:20] .io_core_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), // @[tile.scala:158:20] .io_core_commit_uops_1_imm_rename (_core_io_lsu_commit_uops_1_imm_rename), // @[tile.scala:158:20] .io_core_commit_uops_1_imm_sel (_core_io_lsu_commit_uops_1_imm_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_pimm (_core_io_lsu_commit_uops_1_pimm), // @[tile.scala:158:20] .io_core_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), // @[tile.scala:158:20] .io_core_commit_uops_1_op1_sel (_core_io_lsu_commit_uops_1_op1_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_op2_sel (_core_io_lsu_commit_uops_1_op2_sel), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ldst (_core_io_lsu_commit_uops_1_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_wen (_core_io_lsu_commit_uops_1_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ren1 (_core_io_lsu_commit_uops_1_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ren2 (_core_io_lsu_commit_uops_1_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_ren3 (_core_io_lsu_commit_uops_1_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_swap12 (_core_io_lsu_commit_uops_1_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_swap23 (_core_io_lsu_commit_uops_1_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_typeTagIn (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_typeTagOut (_core_io_lsu_commit_uops_1_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_fromint (_core_io_lsu_commit_uops_1_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_toint (_core_io_lsu_commit_uops_1_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_fastpipe (_core_io_lsu_commit_uops_1_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_fma (_core_io_lsu_commit_uops_1_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_div (_core_io_lsu_commit_uops_1_fp_ctrl_div), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_sqrt (_core_io_lsu_commit_uops_1_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_wflags (_core_io_lsu_commit_uops_1_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_ctrl_vec (_core_io_lsu_commit_uops_1_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), // @[tile.scala:158:20] .io_core_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), // @[tile.scala:158:20] .io_core_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), // @[tile.scala:158:20] .io_core_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), // @[tile.scala:158:20] .io_core_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), // @[tile.scala:158:20] .io_core_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), // @[tile.scala:158:20] .io_core_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), // @[tile.scala:158:20] .io_core_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), // @[tile.scala:158:20] .io_core_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), // @[tile.scala:158:20] .io_core_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), // @[tile.scala:158:20] .io_core_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), // @[tile.scala:158:20] .io_core_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), // @[tile.scala:158:20] .io_core_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), // @[tile.scala:158:20] .io_core_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), // @[tile.scala:158:20] .io_core_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), // @[tile.scala:158:20] .io_core_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), // @[tile.scala:158:20] .io_core_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), // @[tile.scala:158:20] .io_core_commit_uops_1_csr_cmd (_core_io_lsu_commit_uops_1_csr_cmd), // @[tile.scala:158:20] .io_core_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), // @[tile.scala:158:20] .io_core_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), // @[tile.scala:158:20] .io_core_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), // @[tile.scala:158:20] .io_core_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), // @[tile.scala:158:20] .io_core_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), // @[tile.scala:158:20] .io_core_commit_uops_1_fcn_dw (_core_io_lsu_commit_uops_1_fcn_dw), // @[tile.scala:158:20] .io_core_commit_uops_1_fcn_op (_core_io_lsu_commit_uops_1_fcn_op), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_rm (_core_io_lsu_commit_uops_1_fp_rm), // @[tile.scala:158:20] .io_core_commit_uops_1_fp_typ (_core_io_lsu_commit_uops_1_fp_typ), // @[tile.scala:158:20] .io_core_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), // @[tile.scala:158:20] .io_core_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), // @[tile.scala:158:20] .io_core_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), // @[tile.scala:158:20] .io_core_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), // @[tile.scala:158:20] .io_core_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), // @[tile.scala:158:20] .io_core_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), // @[tile.scala:158:20] .io_core_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), // @[tile.scala:158:20] .io_core_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), // @[tile.scala:158:20] .io_core_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), // @[tile.scala:158:20] .io_core_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), // @[tile.scala:158:20] .io_core_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), // @[tile.scala:158:20] .io_core_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), .io_core_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), .io_core_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), .io_core_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), .io_core_clr_unsafe_0_valid (_lsu_io_core_clr_unsafe_0_valid), .io_core_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), .io_core_fence_dmem (_core_io_lsu_fence_dmem), // @[tile.scala:158:20] .io_core_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), // @[tile.scala:158:20] .io_core_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_0 (_core_io_lsu_brupdate_b2_uop_iq_type_0), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_1 (_core_io_lsu_brupdate_b2_uop_iq_type_1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_2 (_core_io_lsu_brupdate_b2_uop_iq_type_2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iq_type_3 (_core_io_lsu_brupdate_b2_uop_iq_type_3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_0 (_core_io_lsu_brupdate_b2_uop_fu_code_0), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_1 (_core_io_lsu_brupdate_b2_uop_fu_code_1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_2 (_core_io_lsu_brupdate_b2_uop_fu_code_2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_3 (_core_io_lsu_brupdate_b2_uop_fu_code_3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_4 (_core_io_lsu_brupdate_b2_uop_fu_code_4), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_5 (_core_io_lsu_brupdate_b2_uop_fu_code_5), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_6 (_core_io_lsu_brupdate_b2_uop_fu_code_6), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_7 (_core_io_lsu_brupdate_b2_uop_fu_code_7), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_8 (_core_io_lsu_brupdate_b2_uop_fu_code_8), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fu_code_9 (_core_io_lsu_brupdate_b2_uop_fu_code_9), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_issued (_core_io_lsu_brupdate_b2_uop_iw_issued), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_issued_partial_agen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_agen), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_issued_partial_dgen (_core_io_lsu_brupdate_b2_uop_iw_issued_partial_dgen), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p1_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p1_speculative_child), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p2_speculative_child (_core_io_lsu_brupdate_b2_uop_iw_p2_speculative_child), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p1_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p1_bypass_hint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p2_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p2_bypass_hint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_iw_p3_bypass_hint (_core_io_lsu_brupdate_b2_uop_iw_p3_bypass_hint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_dis_col_sel (_core_io_lsu_brupdate_b2_uop_dis_col_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_br_type (_core_io_lsu_brupdate_b2_uop_br_type), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_sfence (_core_io_lsu_brupdate_b2_uop_is_sfence), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_eret (_core_io_lsu_brupdate_b2_uop_is_eret), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_rocc (_core_io_lsu_brupdate_b2_uop_is_rocc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_mov (_core_io_lsu_brupdate_b2_uop_is_mov), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_imm_rename (_core_io_lsu_brupdate_b2_uop_imm_rename), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_imm_sel (_core_io_lsu_brupdate_b2_uop_imm_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_pimm (_core_io_lsu_brupdate_b2_uop_pimm), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_op1_sel (_core_io_lsu_brupdate_b2_uop_op1_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_op2_sel (_core_io_lsu_brupdate_b2_uop_op2_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ldst (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ldst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_wen (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wen), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ren1 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ren2 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_ren3 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_ren3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_swap12 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap12), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_swap23 (_core_io_lsu_brupdate_b2_uop_fp_ctrl_swap23), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_typeTagIn (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_typeTagOut (_core_io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_fromint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fromint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_toint (_core_io_lsu_brupdate_b2_uop_fp_ctrl_toint), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_fastpipe (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_fma (_core_io_lsu_brupdate_b2_uop_fp_ctrl_fma), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_div (_core_io_lsu_brupdate_b2_uop_fp_ctrl_div), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_sqrt (_core_io_lsu_brupdate_b2_uop_fp_ctrl_sqrt), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_wflags (_core_io_lsu_brupdate_b2_uop_fp_ctrl_wflags), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_ctrl_vec (_core_io_lsu_brupdate_b2_uop_fp_ctrl_vec), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_csr_cmd (_core_io_lsu_brupdate_b2_uop_csr_cmd), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fcn_dw (_core_io_lsu_brupdate_b2_uop_fcn_dw), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fcn_op (_core_io_lsu_brupdate_b2_uop_fcn_op), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_rm (_core_io_lsu_brupdate_b2_uop_fp_rm), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_fp_typ (_core_io_lsu_brupdate_b2_uop_fp_typ), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:158:20] .io_core_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:158:20] .io_core_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), // @[tile.scala:158:20] .io_core_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), // @[tile.scala:158:20] .io_core_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), // @[tile.scala:158:20] .io_core_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), // @[tile.scala:158:20] .io_core_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), // @[tile.scala:158:20] .io_core_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), // @[tile.scala:158:20] .io_core_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), // @[tile.scala:158:20] .io_core_rob_head_idx (_core_io_lsu_rob_head_idx), // @[tile.scala:158:20] .io_core_exception (_core_io_lsu_exception), // @[tile.scala:158:20] .io_core_fencei_rdy (_lsu_io_core_fencei_rdy), .io_core_lxcpt_valid (_lsu_io_core_lxcpt_valid), .io_core_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), .io_core_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), .io_core_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), .io_core_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), .io_core_lxcpt_bits_uop_iq_type_0 (_lsu_io_core_lxcpt_bits_uop_iq_type_0), .io_core_lxcpt_bits_uop_iq_type_1 (_lsu_io_core_lxcpt_bits_uop_iq_type_1), .io_core_lxcpt_bits_uop_iq_type_2 (_lsu_io_core_lxcpt_bits_uop_iq_type_2), .io_core_lxcpt_bits_uop_iq_type_3 (_lsu_io_core_lxcpt_bits_uop_iq_type_3), .io_core_lxcpt_bits_uop_fu_code_0 (_lsu_io_core_lxcpt_bits_uop_fu_code_0), .io_core_lxcpt_bits_uop_fu_code_1 (_lsu_io_core_lxcpt_bits_uop_fu_code_1), .io_core_lxcpt_bits_uop_fu_code_2 (_lsu_io_core_lxcpt_bits_uop_fu_code_2), .io_core_lxcpt_bits_uop_fu_code_3 (_lsu_io_core_lxcpt_bits_uop_fu_code_3), .io_core_lxcpt_bits_uop_fu_code_4 (_lsu_io_core_lxcpt_bits_uop_fu_code_4), .io_core_lxcpt_bits_uop_fu_code_5 (_lsu_io_core_lxcpt_bits_uop_fu_code_5), .io_core_lxcpt_bits_uop_fu_code_6 (_lsu_io_core_lxcpt_bits_uop_fu_code_6), .io_core_lxcpt_bits_uop_fu_code_7 (_lsu_io_core_lxcpt_bits_uop_fu_code_7), .io_core_lxcpt_bits_uop_fu_code_8 (_lsu_io_core_lxcpt_bits_uop_fu_code_8), .io_core_lxcpt_bits_uop_fu_code_9 (_lsu_io_core_lxcpt_bits_uop_fu_code_9), .io_core_lxcpt_bits_uop_iw_issued (_lsu_io_core_lxcpt_bits_uop_iw_issued), .io_core_lxcpt_bits_uop_iw_issued_partial_agen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_agen), .io_core_lxcpt_bits_uop_iw_issued_partial_dgen (_lsu_io_core_lxcpt_bits_uop_iw_issued_partial_dgen), .io_core_lxcpt_bits_uop_iw_p1_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p1_speculative_child), .io_core_lxcpt_bits_uop_iw_p2_speculative_child (_lsu_io_core_lxcpt_bits_uop_iw_p2_speculative_child), .io_core_lxcpt_bits_uop_iw_p1_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p1_bypass_hint), .io_core_lxcpt_bits_uop_iw_p2_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p2_bypass_hint), .io_core_lxcpt_bits_uop_iw_p3_bypass_hint (_lsu_io_core_lxcpt_bits_uop_iw_p3_bypass_hint), .io_core_lxcpt_bits_uop_dis_col_sel (_lsu_io_core_lxcpt_bits_uop_dis_col_sel), .io_core_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), .io_core_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), .io_core_lxcpt_bits_uop_br_type (_lsu_io_core_lxcpt_bits_uop_br_type), .io_core_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), .io_core_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), .io_core_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), .io_core_lxcpt_bits_uop_is_sfence (_lsu_io_core_lxcpt_bits_uop_is_sfence), .io_core_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), .io_core_lxcpt_bits_uop_is_eret (_lsu_io_core_lxcpt_bits_uop_is_eret), .io_core_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), .io_core_lxcpt_bits_uop_is_rocc (_lsu_io_core_lxcpt_bits_uop_is_rocc), .io_core_lxcpt_bits_uop_is_mov (_lsu_io_core_lxcpt_bits_uop_is_mov), .io_core_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), .io_core_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), .io_core_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), .io_core_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), .io_core_lxcpt_bits_uop_imm_rename (_lsu_io_core_lxcpt_bits_uop_imm_rename), .io_core_lxcpt_bits_uop_imm_sel (_lsu_io_core_lxcpt_bits_uop_imm_sel), .io_core_lxcpt_bits_uop_pimm (_lsu_io_core_lxcpt_bits_uop_pimm), .io_core_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), .io_core_lxcpt_bits_uop_op1_sel (_lsu_io_core_lxcpt_bits_uop_op1_sel), .io_core_lxcpt_bits_uop_op2_sel (_lsu_io_core_lxcpt_bits_uop_op2_sel), .io_core_lxcpt_bits_uop_fp_ctrl_ldst (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ldst), .io_core_lxcpt_bits_uop_fp_ctrl_wen (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wen), .io_core_lxcpt_bits_uop_fp_ctrl_ren1 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren1), .io_core_lxcpt_bits_uop_fp_ctrl_ren2 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren2), .io_core_lxcpt_bits_uop_fp_ctrl_ren3 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_ren3), .io_core_lxcpt_bits_uop_fp_ctrl_swap12 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap12), .io_core_lxcpt_bits_uop_fp_ctrl_swap23 (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_swap23), .io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn), .io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut), .io_core_lxcpt_bits_uop_fp_ctrl_fromint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fromint), .io_core_lxcpt_bits_uop_fp_ctrl_toint (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_toint), .io_core_lxcpt_bits_uop_fp_ctrl_fastpipe (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fastpipe), .io_core_lxcpt_bits_uop_fp_ctrl_fma (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_fma), .io_core_lxcpt_bits_uop_fp_ctrl_div (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_div), .io_core_lxcpt_bits_uop_fp_ctrl_sqrt (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_sqrt), .io_core_lxcpt_bits_uop_fp_ctrl_wflags (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_wflags), .io_core_lxcpt_bits_uop_fp_ctrl_vec (_lsu_io_core_lxcpt_bits_uop_fp_ctrl_vec), .io_core_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), .io_core_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), .io_core_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), .io_core_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), .io_core_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), .io_core_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), .io_core_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), .io_core_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), .io_core_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), .io_core_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), .io_core_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), .io_core_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), .io_core_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), .io_core_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), .io_core_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), .io_core_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), .io_core_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), .io_core_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), .io_core_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), .io_core_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), .io_core_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), .io_core_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), .io_core_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), .io_core_lxcpt_bits_uop_csr_cmd (_lsu_io_core_lxcpt_bits_uop_csr_cmd), .io_core_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), .io_core_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), .io_core_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), .io_core_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), .io_core_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), .io_core_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), .io_core_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), .io_core_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), .io_core_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), .io_core_lxcpt_bits_uop_fcn_dw (_lsu_io_core_lxcpt_bits_uop_fcn_dw), .io_core_lxcpt_bits_uop_fcn_op (_lsu_io_core_lxcpt_bits_uop_fcn_op), .io_core_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), .io_core_lxcpt_bits_uop_fp_rm (_lsu_io_core_lxcpt_bits_uop_fp_rm), .io_core_lxcpt_bits_uop_fp_typ (_lsu_io_core_lxcpt_bits_uop_fp_typ), .io_core_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), .io_core_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), .io_core_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), .io_core_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), .io_core_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), .io_core_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), .io_core_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), .io_core_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), .io_core_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), .io_core_tsc_reg (_core_io_lsu_tsc_reg), // @[tile.scala:158:20] .io_core_status_debug (_core_io_lsu_status_debug), // @[tile.scala:158:20] .io_core_status_cease (_core_io_lsu_status_cease), // @[tile.scala:158:20] .io_core_status_wfi (_core_io_lsu_status_wfi), // @[tile.scala:158:20] .io_core_status_dprv (_core_io_lsu_status_dprv), // @[tile.scala:158:20] .io_core_status_dv (_core_io_lsu_status_dv), // @[tile.scala:158:20] .io_core_status_prv (_core_io_lsu_status_prv), // @[tile.scala:158:20] .io_core_status_v (_core_io_lsu_status_v), // @[tile.scala:158:20] .io_core_status_sd (_core_io_lsu_status_sd), // @[tile.scala:158:20] .io_core_status_mpv (_core_io_lsu_status_mpv), // @[tile.scala:158:20] .io_core_status_gva (_core_io_lsu_status_gva), // @[tile.scala:158:20] .io_core_status_tsr (_core_io_lsu_status_tsr), // @[tile.scala:158:20] .io_core_status_tw (_core_io_lsu_status_tw), // @[tile.scala:158:20] .io_core_status_tvm (_core_io_lsu_status_tvm), // @[tile.scala:158:20] .io_core_status_mxr (_core_io_lsu_status_mxr), // @[tile.scala:158:20] .io_core_status_sum (_core_io_lsu_status_sum), // @[tile.scala:158:20] .io_core_status_mprv (_core_io_lsu_status_mprv), // @[tile.scala:158:20] .io_core_status_fs (_core_io_lsu_status_fs), // @[tile.scala:158:20] .io_core_status_mpp (_core_io_lsu_status_mpp), // @[tile.scala:158:20] .io_core_status_spp (_core_io_lsu_status_spp), // @[tile.scala:158:20] .io_core_status_mpie (_core_io_lsu_status_mpie), // @[tile.scala:158:20] .io_core_status_spie (_core_io_lsu_status_spie), // @[tile.scala:158:20] .io_core_status_mie (_core_io_lsu_status_mie), // @[tile.scala:158:20] .io_core_status_sie (_core_io_lsu_status_sie), // @[tile.scala:158:20] .io_core_perf_acquire (_lsu_io_core_perf_acquire), .io_core_perf_release (_lsu_io_core_perf_release), .io_core_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), .io_dmem_req_ready (_dcache_io_lsu_req_ready), // @[tile.scala:132:54] .io_dmem_req_valid (_lsu_io_dmem_req_valid), .io_dmem_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), .io_dmem_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), .io_dmem_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), .io_dmem_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), .io_dmem_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), .io_dmem_req_bits_0_bits_uop_iq_type_0 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_0), .io_dmem_req_bits_0_bits_uop_iq_type_1 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_1), .io_dmem_req_bits_0_bits_uop_iq_type_2 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_2), .io_dmem_req_bits_0_bits_uop_iq_type_3 (_lsu_io_dmem_req_bits_0_bits_uop_iq_type_3), .io_dmem_req_bits_0_bits_uop_fu_code_0 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_0), .io_dmem_req_bits_0_bits_uop_fu_code_1 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_1), .io_dmem_req_bits_0_bits_uop_fu_code_2 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_2), .io_dmem_req_bits_0_bits_uop_fu_code_3 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_3), .io_dmem_req_bits_0_bits_uop_fu_code_4 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_4), .io_dmem_req_bits_0_bits_uop_fu_code_5 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_5), .io_dmem_req_bits_0_bits_uop_fu_code_6 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_6), .io_dmem_req_bits_0_bits_uop_fu_code_7 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_7), .io_dmem_req_bits_0_bits_uop_fu_code_8 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_8), .io_dmem_req_bits_0_bits_uop_fu_code_9 (_lsu_io_dmem_req_bits_0_bits_uop_fu_code_9), .io_dmem_req_bits_0_bits_uop_iw_issued (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued), .io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen), .io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen (_lsu_io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen), .io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child), .io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child), .io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint), .io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint), .io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint (_lsu_io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint), .io_dmem_req_bits_0_bits_uop_dis_col_sel (_lsu_io_dmem_req_bits_0_bits_uop_dis_col_sel), .io_dmem_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), .io_dmem_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), .io_dmem_req_bits_0_bits_uop_br_type (_lsu_io_dmem_req_bits_0_bits_uop_br_type), .io_dmem_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), .io_dmem_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), .io_dmem_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), .io_dmem_req_bits_0_bits_uop_is_sfence (_lsu_io_dmem_req_bits_0_bits_uop_is_sfence), .io_dmem_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), .io_dmem_req_bits_0_bits_uop_is_eret (_lsu_io_dmem_req_bits_0_bits_uop_is_eret), .io_dmem_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), .io_dmem_req_bits_0_bits_uop_is_rocc (_lsu_io_dmem_req_bits_0_bits_uop_is_rocc), .io_dmem_req_bits_0_bits_uop_is_mov (_lsu_io_dmem_req_bits_0_bits_uop_is_mov), .io_dmem_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), .io_dmem_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), .io_dmem_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), .io_dmem_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), .io_dmem_req_bits_0_bits_uop_imm_rename (_lsu_io_dmem_req_bits_0_bits_uop_imm_rename), .io_dmem_req_bits_0_bits_uop_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_imm_sel), .io_dmem_req_bits_0_bits_uop_pimm (_lsu_io_dmem_req_bits_0_bits_uop_pimm), .io_dmem_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), .io_dmem_req_bits_0_bits_uop_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_op1_sel), .io_dmem_req_bits_0_bits_uop_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_op2_sel), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst), .io_dmem_req_bits_0_bits_uop_fp_ctrl_wen (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wen), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2), .io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3), .io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12), .io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23 (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23), .io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn), .io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut), .io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint), .io_dmem_req_bits_0_bits_uop_fp_ctrl_toint (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_toint), .io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe), .io_dmem_req_bits_0_bits_uop_fp_ctrl_fma (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_fma), .io_dmem_req_bits_0_bits_uop_fp_ctrl_div (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_div), .io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt), .io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags), .io_dmem_req_bits_0_bits_uop_fp_ctrl_vec (_lsu_io_dmem_req_bits_0_bits_uop_fp_ctrl_vec), .io_dmem_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), .io_dmem_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), .io_dmem_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), .io_dmem_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), .io_dmem_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), .io_dmem_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), .io_dmem_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), .io_dmem_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), .io_dmem_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), .io_dmem_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), .io_dmem_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), .io_dmem_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), .io_dmem_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), .io_dmem_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), .io_dmem_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), .io_dmem_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), .io_dmem_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), .io_dmem_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), .io_dmem_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), .io_dmem_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), .io_dmem_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), .io_dmem_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), .io_dmem_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), .io_dmem_req_bits_0_bits_uop_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_csr_cmd), .io_dmem_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), .io_dmem_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), .io_dmem_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), .io_dmem_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), .io_dmem_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), .io_dmem_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), .io_dmem_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), .io_dmem_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), .io_dmem_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), .io_dmem_req_bits_0_bits_uop_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_fcn_dw), .io_dmem_req_bits_0_bits_uop_fcn_op (_lsu_io_dmem_req_bits_0_bits_uop_fcn_op), .io_dmem_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), .io_dmem_req_bits_0_bits_uop_fp_rm (_lsu_io_dmem_req_bits_0_bits_uop_fp_rm), .io_dmem_req_bits_0_bits_uop_fp_typ (_lsu_io_dmem_req_bits_0_bits_uop_fp_typ), .io_dmem_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), .io_dmem_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), .io_dmem_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), .io_dmem_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), .io_dmem_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), .io_dmem_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), .io_dmem_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), .io_dmem_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), .io_dmem_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), .io_dmem_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), .io_dmem_s1_kill_0 (_lsu_io_dmem_s1_kill_0), .io_dmem_resp_0_valid (_dcache_io_lsu_resp_0_valid), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_0 (_dcache_io_lsu_resp_0_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_1 (_dcache_io_lsu_resp_0_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_2 (_dcache_io_lsu_resp_0_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iq_type_3 (_dcache_io_lsu_resp_0_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_0 (_dcache_io_lsu_resp_0_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_1 (_dcache_io_lsu_resp_0_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_2 (_dcache_io_lsu_resp_0_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_3 (_dcache_io_lsu_resp_0_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_4 (_dcache_io_lsu_resp_0_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_5 (_dcache_io_lsu_resp_0_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_6 (_dcache_io_lsu_resp_0_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_7 (_dcache_io_lsu_resp_0_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_8 (_dcache_io_lsu_resp_0_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fu_code_9 (_dcache_io_lsu_resp_0_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_issued (_dcache_io_lsu_resp_0_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_resp_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_resp_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_resp_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_dis_col_sel (_dcache_io_lsu_resp_0_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_br_type (_dcache_io_lsu_resp_0_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_sfence (_dcache_io_lsu_resp_0_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_eret (_dcache_io_lsu_resp_0_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_rocc (_dcache_io_lsu_resp_0_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_mov (_dcache_io_lsu_resp_0_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_imm_rename (_dcache_io_lsu_resp_0_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_imm_sel (_dcache_io_lsu_resp_0_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_pimm (_dcache_io_lsu_resp_0_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_op1_sel (_dcache_io_lsu_resp_0_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_op2_sel (_dcache_io_lsu_resp_0_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_resp_0_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fcn_op (_dcache_io_lsu_resp_0_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_rm (_dcache_io_lsu_resp_0_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_fp_typ (_dcache_io_lsu_resp_0_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), // @[tile.scala:132:54] .io_dmem_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), // @[tile.scala:132:54] .io_dmem_store_ack_0_valid (_dcache_io_lsu_store_ack_0_valid), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_inst (_dcache_io_lsu_store_ack_0_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_inst (_dcache_io_lsu_store_ack_0_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_rvc (_dcache_io_lsu_store_ack_0_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_pc (_dcache_io_lsu_store_ack_0_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_0 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_1 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_2 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iq_type_3 (_dcache_io_lsu_store_ack_0_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_0 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_1 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_2 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_3 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_4 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_5 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_6 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_7 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_8 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fu_code_9 (_dcache_io_lsu_store_ack_0_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_issued (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_dis_col_sel (_dcache_io_lsu_store_ack_0_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_br_mask (_dcache_io_lsu_store_ack_0_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_br_tag (_dcache_io_lsu_store_ack_0_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_br_type (_dcache_io_lsu_store_ack_0_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_sfb (_dcache_io_lsu_store_ack_0_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_fence (_dcache_io_lsu_store_ack_0_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_fencei (_dcache_io_lsu_store_ack_0_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_sfence (_dcache_io_lsu_store_ack_0_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_amo (_dcache_io_lsu_store_ack_0_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_eret (_dcache_io_lsu_store_ack_0_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_store_ack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_rocc (_dcache_io_lsu_store_ack_0_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_mov (_dcache_io_lsu_store_ack_0_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ftq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_edge_inst (_dcache_io_lsu_store_ack_0_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_pc_lob (_dcache_io_lsu_store_ack_0_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_taken (_dcache_io_lsu_store_ack_0_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_imm_rename (_dcache_io_lsu_store_ack_0_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_imm_sel (_dcache_io_lsu_store_ack_0_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_pimm (_dcache_io_lsu_store_ack_0_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_imm_packed (_dcache_io_lsu_store_ack_0_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_op1_sel (_dcache_io_lsu_store_ack_0_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_op2_sel (_dcache_io_lsu_store_ack_0_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_store_ack_0_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_rob_idx (_dcache_io_lsu_store_ack_0_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ldq_idx (_dcache_io_lsu_store_ack_0_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_stq_idx (_dcache_io_lsu_store_ack_0_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_rxq_idx (_dcache_io_lsu_store_ack_0_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_pdst (_dcache_io_lsu_store_ack_0_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs1 (_dcache_io_lsu_store_ack_0_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs2 (_dcache_io_lsu_store_ack_0_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs3 (_dcache_io_lsu_store_ack_0_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ppred (_dcache_io_lsu_store_ack_0_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs1_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs2_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_prs3_busy (_dcache_io_lsu_store_ack_0_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ppred_busy (_dcache_io_lsu_store_ack_0_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_stale_pdst (_dcache_io_lsu_store_ack_0_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_exception (_dcache_io_lsu_store_ack_0_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_exc_cause (_dcache_io_lsu_store_ack_0_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_mem_cmd (_dcache_io_lsu_store_ack_0_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_mem_size (_dcache_io_lsu_store_ack_0_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_mem_signed (_dcache_io_lsu_store_ack_0_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_uses_ldq (_dcache_io_lsu_store_ack_0_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_uses_stq (_dcache_io_lsu_store_ack_0_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_is_unique (_dcache_io_lsu_store_ack_0_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_flush_on_commit (_dcache_io_lsu_store_ack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_csr_cmd (_dcache_io_lsu_store_ack_0_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_store_ack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_ldst (_dcache_io_lsu_store_ack_0_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs1 (_dcache_io_lsu_store_ack_0_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs2 (_dcache_io_lsu_store_ack_0_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs3 (_dcache_io_lsu_store_ack_0_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_dst_rtype (_dcache_io_lsu_store_ack_0_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_store_ack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_frs3_en (_dcache_io_lsu_store_ack_0_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fcn_dw (_dcache_io_lsu_store_ack_0_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fcn_op (_dcache_io_lsu_store_ack_0_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_val (_dcache_io_lsu_store_ack_0_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_rm (_dcache_io_lsu_store_ack_0_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_fp_typ (_dcache_io_lsu_store_ack_0_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_store_ack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_bp_debug_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_store_ack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_fsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_uop_debug_tsrc (_dcache_io_lsu_store_ack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_addr (_dcache_io_lsu_store_ack_0_bits_addr), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_data (_dcache_io_lsu_store_ack_0_bits_data), // @[tile.scala:132:54] .io_dmem_store_ack_0_bits_is_hella (_dcache_io_lsu_store_ack_0_bits_is_hella), // @[tile.scala:132:54] .io_dmem_nack_0_valid (_dcache_io_lsu_nack_0_valid), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_0 (_dcache_io_lsu_nack_0_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_1 (_dcache_io_lsu_nack_0_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_2 (_dcache_io_lsu_nack_0_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iq_type_3 (_dcache_io_lsu_nack_0_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_0 (_dcache_io_lsu_nack_0_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_1 (_dcache_io_lsu_nack_0_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_2 (_dcache_io_lsu_nack_0_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_3 (_dcache_io_lsu_nack_0_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_4 (_dcache_io_lsu_nack_0_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_5 (_dcache_io_lsu_nack_0_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_6 (_dcache_io_lsu_nack_0_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_7 (_dcache_io_lsu_nack_0_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_8 (_dcache_io_lsu_nack_0_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fu_code_9 (_dcache_io_lsu_nack_0_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_issued (_dcache_io_lsu_nack_0_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_nack_0_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_nack_0_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_nack_0_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_dis_col_sel (_dcache_io_lsu_nack_0_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_br_type (_dcache_io_lsu_nack_0_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_sfence (_dcache_io_lsu_nack_0_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_eret (_dcache_io_lsu_nack_0_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_rocc (_dcache_io_lsu_nack_0_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_mov (_dcache_io_lsu_nack_0_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_imm_rename (_dcache_io_lsu_nack_0_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_imm_sel (_dcache_io_lsu_nack_0_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_pimm (_dcache_io_lsu_nack_0_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_op1_sel (_dcache_io_lsu_nack_0_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_op2_sel (_dcache_io_lsu_nack_0_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_wen (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_toint (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_fma (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_div (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_ctrl_vec (_dcache_io_lsu_nack_0_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fcn_op (_dcache_io_lsu_nack_0_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_rm (_dcache_io_lsu_nack_0_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_fp_typ (_dcache_io_lsu_nack_0_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), // @[tile.scala:132:54] .io_dmem_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), // @[tile.scala:132:54] .io_dmem_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), // @[tile.scala:132:54] .io_dmem_ll_resp_ready (_lsu_io_dmem_ll_resp_ready), .io_dmem_ll_resp_valid (_dcache_io_lsu_ll_resp_valid), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_inst (_dcache_io_lsu_ll_resp_bits_uop_inst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_inst (_dcache_io_lsu_ll_resp_bits_uop_debug_inst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_rvc (_dcache_io_lsu_ll_resp_bits_uop_is_rvc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_pc (_dcache_io_lsu_ll_resp_bits_uop_debug_pc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_0 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_0), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_1 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_2 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iq_type_3 (_dcache_io_lsu_ll_resp_bits_uop_iq_type_3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_0 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_0), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_1 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_2 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_3 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_4 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_4), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_5 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_5), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_6 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_6), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_7 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_7), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_8 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_8), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fu_code_9 (_dcache_io_lsu_ll_resp_bits_uop_fu_code_9), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_issued (_dcache_io_lsu_ll_resp_bits_uop_iw_issued), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_issued_partial_agen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_agen), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen (_dcache_io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p1_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_speculative_child), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p2_speculative_child (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_speculative_child), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint (_dcache_io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_dis_col_sel (_dcache_io_lsu_ll_resp_bits_uop_dis_col_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_br_mask (_dcache_io_lsu_ll_resp_bits_uop_br_mask), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_br_tag (_dcache_io_lsu_ll_resp_bits_uop_br_tag), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_br_type (_dcache_io_lsu_ll_resp_bits_uop_br_type), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_sfb (_dcache_io_lsu_ll_resp_bits_uop_is_sfb), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_fence (_dcache_io_lsu_ll_resp_bits_uop_is_fence), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_fencei (_dcache_io_lsu_ll_resp_bits_uop_is_fencei), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_sfence (_dcache_io_lsu_ll_resp_bits_uop_is_sfence), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_amo (_dcache_io_lsu_ll_resp_bits_uop_is_amo), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_eret (_dcache_io_lsu_ll_resp_bits_uop_is_eret), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_sys_pc2epc (_dcache_io_lsu_ll_resp_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_rocc (_dcache_io_lsu_ll_resp_bits_uop_is_rocc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_mov (_dcache_io_lsu_ll_resp_bits_uop_is_mov), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ftq_idx (_dcache_io_lsu_ll_resp_bits_uop_ftq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_edge_inst (_dcache_io_lsu_ll_resp_bits_uop_edge_inst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_pc_lob (_dcache_io_lsu_ll_resp_bits_uop_pc_lob), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_taken (_dcache_io_lsu_ll_resp_bits_uop_taken), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_imm_rename (_dcache_io_lsu_ll_resp_bits_uop_imm_rename), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_imm_sel (_dcache_io_lsu_ll_resp_bits_uop_imm_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_pimm (_dcache_io_lsu_ll_resp_bits_uop_pimm), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_imm_packed (_dcache_io_lsu_ll_resp_bits_uop_imm_packed), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_op1_sel (_dcache_io_lsu_ll_resp_bits_uop_op1_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_op2_sel (_dcache_io_lsu_ll_resp_bits_uop_op2_sel), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ldst (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ldst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_wen (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wen), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ren1 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ren2 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_ren3 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_ren3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_swap12 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap12), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_swap23 (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_swap23), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_fromint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fromint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_toint (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_toint), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_fma (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_fma), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_div (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_div), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_wflags (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_wflags), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_ctrl_vec (_dcache_io_lsu_ll_resp_bits_uop_fp_ctrl_vec), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_rob_idx (_dcache_io_lsu_ll_resp_bits_uop_rob_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ldq_idx (_dcache_io_lsu_ll_resp_bits_uop_ldq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_stq_idx (_dcache_io_lsu_ll_resp_bits_uop_stq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_rxq_idx (_dcache_io_lsu_ll_resp_bits_uop_rxq_idx), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_pdst (_dcache_io_lsu_ll_resp_bits_uop_pdst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs1 (_dcache_io_lsu_ll_resp_bits_uop_prs1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs2 (_dcache_io_lsu_ll_resp_bits_uop_prs2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs3 (_dcache_io_lsu_ll_resp_bits_uop_prs3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ppred (_dcache_io_lsu_ll_resp_bits_uop_ppred), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs1_busy (_dcache_io_lsu_ll_resp_bits_uop_prs1_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs2_busy (_dcache_io_lsu_ll_resp_bits_uop_prs2_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_prs3_busy (_dcache_io_lsu_ll_resp_bits_uop_prs3_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ppred_busy (_dcache_io_lsu_ll_resp_bits_uop_ppred_busy), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_stale_pdst (_dcache_io_lsu_ll_resp_bits_uop_stale_pdst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_exception (_dcache_io_lsu_ll_resp_bits_uop_exception), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_exc_cause (_dcache_io_lsu_ll_resp_bits_uop_exc_cause), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_mem_cmd (_dcache_io_lsu_ll_resp_bits_uop_mem_cmd), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_mem_size (_dcache_io_lsu_ll_resp_bits_uop_mem_size), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_mem_signed (_dcache_io_lsu_ll_resp_bits_uop_mem_signed), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_uses_ldq (_dcache_io_lsu_ll_resp_bits_uop_uses_ldq), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_uses_stq (_dcache_io_lsu_ll_resp_bits_uop_uses_stq), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_is_unique (_dcache_io_lsu_ll_resp_bits_uop_is_unique), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_flush_on_commit (_dcache_io_lsu_ll_resp_bits_uop_flush_on_commit), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_csr_cmd (_dcache_io_lsu_ll_resp_bits_uop_csr_cmd), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ldst_is_rs1 (_dcache_io_lsu_ll_resp_bits_uop_ldst_is_rs1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_ldst (_dcache_io_lsu_ll_resp_bits_uop_ldst), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs1 (_dcache_io_lsu_ll_resp_bits_uop_lrs1), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs2 (_dcache_io_lsu_ll_resp_bits_uop_lrs2), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs3 (_dcache_io_lsu_ll_resp_bits_uop_lrs3), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_dst_rtype (_dcache_io_lsu_ll_resp_bits_uop_dst_rtype), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs1_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs1_rtype), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_lrs2_rtype (_dcache_io_lsu_ll_resp_bits_uop_lrs2_rtype), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_frs3_en (_dcache_io_lsu_ll_resp_bits_uop_frs3_en), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fcn_dw (_dcache_io_lsu_ll_resp_bits_uop_fcn_dw), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fcn_op (_dcache_io_lsu_ll_resp_bits_uop_fcn_op), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_val (_dcache_io_lsu_ll_resp_bits_uop_fp_val), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_rm (_dcache_io_lsu_ll_resp_bits_uop_fp_rm), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_fp_typ (_dcache_io_lsu_ll_resp_bits_uop_fp_typ), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_xcpt_pf_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_pf_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_xcpt_ae_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ae_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_xcpt_ma_if (_dcache_io_lsu_ll_resp_bits_uop_xcpt_ma_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_bp_debug_if (_dcache_io_lsu_ll_resp_bits_uop_bp_debug_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_bp_xcpt_if (_dcache_io_lsu_ll_resp_bits_uop_bp_xcpt_if), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_fsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_fsrc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_uop_debug_tsrc (_dcache_io_lsu_ll_resp_bits_uop_debug_tsrc), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_data (_dcache_io_lsu_ll_resp_bits_data), // @[tile.scala:132:54] .io_dmem_ll_resp_bits_is_hella (_dcache_io_lsu_ll_resp_bits_is_hella), // @[tile.scala:132:54] .io_dmem_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), .io_dmem_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), .io_dmem_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), .io_dmem_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), .io_dmem_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), .io_dmem_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), .io_dmem_brupdate_b2_uop_iq_type_0 (_lsu_io_dmem_brupdate_b2_uop_iq_type_0), .io_dmem_brupdate_b2_uop_iq_type_1 (_lsu_io_dmem_brupdate_b2_uop_iq_type_1), .io_dmem_brupdate_b2_uop_iq_type_2 (_lsu_io_dmem_brupdate_b2_uop_iq_type_2), .io_dmem_brupdate_b2_uop_iq_type_3 (_lsu_io_dmem_brupdate_b2_uop_iq_type_3), .io_dmem_brupdate_b2_uop_fu_code_0 (_lsu_io_dmem_brupdate_b2_uop_fu_code_0), .io_dmem_brupdate_b2_uop_fu_code_1 (_lsu_io_dmem_brupdate_b2_uop_fu_code_1), .io_dmem_brupdate_b2_uop_fu_code_2 (_lsu_io_dmem_brupdate_b2_uop_fu_code_2), .io_dmem_brupdate_b2_uop_fu_code_3 (_lsu_io_dmem_brupdate_b2_uop_fu_code_3), .io_dmem_brupdate_b2_uop_fu_code_4 (_lsu_io_dmem_brupdate_b2_uop_fu_code_4), .io_dmem_brupdate_b2_uop_fu_code_5 (_lsu_io_dmem_brupdate_b2_uop_fu_code_5), .io_dmem_brupdate_b2_uop_fu_code_6 (_lsu_io_dmem_brupdate_b2_uop_fu_code_6), .io_dmem_brupdate_b2_uop_fu_code_7 (_lsu_io_dmem_brupdate_b2_uop_fu_code_7), .io_dmem_brupdate_b2_uop_fu_code_8 (_lsu_io_dmem_brupdate_b2_uop_fu_code_8), .io_dmem_brupdate_b2_uop_fu_code_9 (_lsu_io_dmem_brupdate_b2_uop_fu_code_9), .io_dmem_brupdate_b2_uop_iw_issued (_lsu_io_dmem_brupdate_b2_uop_iw_issued), .io_dmem_brupdate_b2_uop_iw_issued_partial_agen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_agen), .io_dmem_brupdate_b2_uop_iw_issued_partial_dgen (_lsu_io_dmem_brupdate_b2_uop_iw_issued_partial_dgen), .io_dmem_brupdate_b2_uop_iw_p1_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p1_speculative_child), .io_dmem_brupdate_b2_uop_iw_p2_speculative_child (_lsu_io_dmem_brupdate_b2_uop_iw_p2_speculative_child), .io_dmem_brupdate_b2_uop_iw_p1_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p1_bypass_hint), .io_dmem_brupdate_b2_uop_iw_p2_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p2_bypass_hint), .io_dmem_brupdate_b2_uop_iw_p3_bypass_hint (_lsu_io_dmem_brupdate_b2_uop_iw_p3_bypass_hint), .io_dmem_brupdate_b2_uop_dis_col_sel (_lsu_io_dmem_brupdate_b2_uop_dis_col_sel), .io_dmem_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), .io_dmem_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), .io_dmem_brupdate_b2_uop_br_type (_lsu_io_dmem_brupdate_b2_uop_br_type), .io_dmem_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), .io_dmem_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), .io_dmem_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), .io_dmem_brupdate_b2_uop_is_sfence (_lsu_io_dmem_brupdate_b2_uop_is_sfence), .io_dmem_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), .io_dmem_brupdate_b2_uop_is_eret (_lsu_io_dmem_brupdate_b2_uop_is_eret), .io_dmem_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), .io_dmem_brupdate_b2_uop_is_rocc (_lsu_io_dmem_brupdate_b2_uop_is_rocc), .io_dmem_brupdate_b2_uop_is_mov (_lsu_io_dmem_brupdate_b2_uop_is_mov), .io_dmem_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), .io_dmem_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), .io_dmem_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), .io_dmem_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), .io_dmem_brupdate_b2_uop_imm_rename (_lsu_io_dmem_brupdate_b2_uop_imm_rename), .io_dmem_brupdate_b2_uop_imm_sel (_lsu_io_dmem_brupdate_b2_uop_imm_sel), .io_dmem_brupdate_b2_uop_pimm (_lsu_io_dmem_brupdate_b2_uop_pimm), .io_dmem_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), .io_dmem_brupdate_b2_uop_op1_sel (_lsu_io_dmem_brupdate_b2_uop_op1_sel), .io_dmem_brupdate_b2_uop_op2_sel (_lsu_io_dmem_brupdate_b2_uop_op2_sel), .io_dmem_brupdate_b2_uop_fp_ctrl_ldst (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ldst), .io_dmem_brupdate_b2_uop_fp_ctrl_wen (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wen), .io_dmem_brupdate_b2_uop_fp_ctrl_ren1 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren1), .io_dmem_brupdate_b2_uop_fp_ctrl_ren2 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren2), .io_dmem_brupdate_b2_uop_fp_ctrl_ren3 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_ren3), .io_dmem_brupdate_b2_uop_fp_ctrl_swap12 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap12), .io_dmem_brupdate_b2_uop_fp_ctrl_swap23 (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_swap23), .io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn), .io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut), .io_dmem_brupdate_b2_uop_fp_ctrl_fromint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fromint), .io_dmem_brupdate_b2_uop_fp_ctrl_toint (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_toint), .io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe), .io_dmem_brupdate_b2_uop_fp_ctrl_fma (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_fma), .io_dmem_brupdate_b2_uop_fp_ctrl_div (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_div), .io_dmem_brupdate_b2_uop_fp_ctrl_sqrt (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_sqrt), .io_dmem_brupdate_b2_uop_fp_ctrl_wflags (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_wflags), .io_dmem_brupdate_b2_uop_fp_ctrl_vec (_lsu_io_dmem_brupdate_b2_uop_fp_ctrl_vec), .io_dmem_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), .io_dmem_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), .io_dmem_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), .io_dmem_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), .io_dmem_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), .io_dmem_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), .io_dmem_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), .io_dmem_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), .io_dmem_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), .io_dmem_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), .io_dmem_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), .io_dmem_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), .io_dmem_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), .io_dmem_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), .io_dmem_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), .io_dmem_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), .io_dmem_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), .io_dmem_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), .io_dmem_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), .io_dmem_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), .io_dmem_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), .io_dmem_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), .io_dmem_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), .io_dmem_brupdate_b2_uop_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_csr_cmd), .io_dmem_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), .io_dmem_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), .io_dmem_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), .io_dmem_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), .io_dmem_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), .io_dmem_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), .io_dmem_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), .io_dmem_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), .io_dmem_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), .io_dmem_brupdate_b2_uop_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_fcn_dw), .io_dmem_brupdate_b2_uop_fcn_op (_lsu_io_dmem_brupdate_b2_uop_fcn_op), .io_dmem_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), .io_dmem_brupdate_b2_uop_fp_rm (_lsu_io_dmem_brupdate_b2_uop_fp_rm), .io_dmem_brupdate_b2_uop_fp_typ (_lsu_io_dmem_brupdate_b2_uop_fp_typ), .io_dmem_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), .io_dmem_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), .io_dmem_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), .io_dmem_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), .io_dmem_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), .io_dmem_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), .io_dmem_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), .io_dmem_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), .io_dmem_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), .io_dmem_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), .io_dmem_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), .io_dmem_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), .io_dmem_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), .io_dmem_exception (_lsu_io_dmem_exception), .io_dmem_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), .io_dmem_rob_head_idx (_lsu_io_dmem_rob_head_idx), .io_dmem_release_ready (_lsu_io_dmem_release_ready), .io_dmem_release_valid (_dcache_io_lsu_release_valid), // @[tile.scala:132:54] .io_dmem_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), // @[tile.scala:132:54] .io_dmem_release_bits_param (_dcache_io_lsu_release_bits_param), // @[tile.scala:132:54] .io_dmem_release_bits_size (_dcache_io_lsu_release_bits_size), // @[tile.scala:132:54] .io_dmem_release_bits_source (_dcache_io_lsu_release_bits_source), // @[tile.scala:132:54] .io_dmem_release_bits_address (_dcache_io_lsu_release_bits_address), // @[tile.scala:132:54] .io_dmem_release_bits_data (_dcache_io_lsu_release_bits_data), // @[tile.scala:132:54] .io_dmem_force_order (_lsu_io_dmem_force_order), .io_dmem_ordered (_dcache_io_lsu_ordered), // @[tile.scala:132:54] .io_dmem_perf_acquire (_dcache_io_lsu_perf_acquire), // @[tile.scala:132:54] .io_dmem_perf_release (_dcache_io_lsu_perf_release), // @[tile.scala:132:54] .io_hellacache_req_ready (_lsu_io_hellacache_req_ready), .io_hellacache_req_valid (_hellaCacheArb_io_mem_req_valid), // @[tile.scala:242:29] .io_hellacache_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), // @[tile.scala:242:29] .io_hellacache_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), // @[tile.scala:242:29] .io_hellacache_s1_kill (_hellaCacheArb_io_mem_s1_kill), // @[tile.scala:242:29] .io_hellacache_s2_nack (_lsu_io_hellacache_s2_nack), .io_hellacache_resp_valid (_lsu_io_hellacache_resp_valid), .io_hellacache_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), .io_hellacache_resp_bits_dprv (_lsu_io_hellacache_resp_bits_dprv), .io_hellacache_resp_bits_dv (_lsu_io_hellacache_resp_bits_dv), .io_hellacache_resp_bits_data (_lsu_io_hellacache_resp_bits_data), .io_hellacache_resp_bits_data_word_bypass (_lsu_io_hellacache_resp_bits_data_word_bypass), .io_hellacache_resp_bits_data_raw (_lsu_io_hellacache_resp_bits_data_raw), .io_hellacache_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), .io_hellacache_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), .io_hellacache_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), .io_hellacache_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), .io_hellacache_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), .io_hellacache_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), .io_hellacache_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), .io_hellacache_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), .io_hellacache_store_pending (_lsu_io_hellacache_store_pending) ); // @[tile.scala:159:20] PTW ptw ( // @[tile.scala:236:20] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_lsu_io_ptw_req_valid), // @[tile.scala:159:20] .io_requestor_0_req_bits_valid (_lsu_io_ptw_req_bits_valid), // @[tile.scala:159:20] .io_requestor_0_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), // @[tile.scala:159:20] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[tile.scala:137:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[tile.scala:137:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[tile.scala:137:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready), .io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid), .io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), .io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), .io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), .io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), .io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), .io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), .io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), .io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), .io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), .io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), .io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), .io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), .io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), .io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), .io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), .io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), .io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), .io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), .io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), .io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), .io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), .io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), .io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), .io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), .io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), .io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug), .io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease), .io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi), .io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv), .io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv), .io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv), .io_requestor_2_status_v (_ptw_io_requestor_2_status_v), .io_requestor_2_status_sd (_ptw_io_requestor_2_status_sd), .io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv), .io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva), .io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr), .io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw), .io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm), .io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr), .io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum), .io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv), .io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs), .io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp), .io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp), .io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie), .io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie), .io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie), .io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie), .io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), .io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), .io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), .io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), .io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), .io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), .io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), .io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), .io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), .io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), .io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), .io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), .io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), .io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), .io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), .io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), .io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), .io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), .io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), .io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), .io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), .io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), .io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), .io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), .io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), .io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), .io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), .io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), .io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), .io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), .io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), .io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), .io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), .io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), .io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), .io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), .io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), .io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), .io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), .io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), .io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), .io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), .io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), .io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), .io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), .io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), .io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), .io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), .io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), .io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), .io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), .io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), .io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), .io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), .io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), .io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), .io_mem_req_ready (_hellaCacheArb_io_requestor_0_req_ready), // @[tile.scala:242:29] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), // @[tile.scala:242:29] .io_mem_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), // @[tile.scala:242:29] .io_mem_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), // @[tile.scala:242:29] .io_mem_resp_bits_dprv (_hellaCacheArb_io_requestor_0_resp_bits_dprv), // @[tile.scala:242:29] .io_mem_resp_bits_dv (_hellaCacheArb_io_requestor_0_resp_bits_dv), // @[tile.scala:242:29] .io_mem_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), // @[tile.scala:242:29] .io_mem_resp_bits_data_word_bypass (_hellaCacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[tile.scala:242:29] .io_mem_resp_bits_data_raw (_hellaCacheArb_io_requestor_0_resp_bits_data_raw), // @[tile.scala:242:29] .io_mem_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), // @[tile.scala:242:29] .io_mem_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), // @[tile.scala:242:29] .io_mem_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), // @[tile.scala:242:29] .io_mem_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[tile.scala:242:29] .io_mem_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), // @[tile.scala:242:29] .io_mem_store_pending (_hellaCacheArb_io_requestor_0_store_pending), // @[tile.scala:242:29] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[tile.scala:158:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[tile.scala:158:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[tile.scala:158:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[tile.scala:158:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[tile.scala:158:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[tile.scala:158:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[tile.scala:158:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[tile.scala:158:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[tile.scala:158:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[tile.scala:158:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[tile.scala:158:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[tile.scala:158:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[tile.scala:158:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[tile.scala:158:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[tile.scala:158:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[tile.scala:158:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[tile.scala:158:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[tile.scala:158:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[tile.scala:158:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[tile.scala:158:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[tile.scala:158:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[tile.scala:158:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[tile.scala:158:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[tile.scala:158:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[tile.scala:158:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[tile.scala:158:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[tile.scala:158:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[tile.scala:158:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[tile.scala:158:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[tile.scala:158:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[tile.scala:158:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[tile.scala:158:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[tile.scala:158:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[tile.scala:158:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[tile.scala:158:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[tile.scala:158:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[tile.scala:158:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[tile.scala:158:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[tile.scala:158:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[tile.scala:158:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[tile.scala:158:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[tile.scala:158:20] .io_dpath_perf_l2miss (_ptw_io_dpath_perf_l2miss), .io_dpath_perf_l2hit (_ptw_io_dpath_perf_l2hit), .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[tile.scala:236:20] HellaCacheArbiter hellaCacheArb ( // @[tile.scala:242:29] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_hellaCacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[tile.scala:236:20] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[tile.scala:236:20] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[tile.scala:236:20] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[tile.scala:236:20] .io_requestor_0_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), .io_requestor_0_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_dprv (_hellaCacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_hellaCacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_data_word_bypass (_hellaCacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_hellaCacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), .io_requestor_0_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), .io_requestor_0_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_store_pending (_hellaCacheArb_io_requestor_0_store_pending), .io_mem_req_ready (_lsu_io_hellacache_req_ready), // @[tile.scala:159:20] .io_mem_req_valid (_hellaCacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), .io_mem_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), .io_mem_s1_kill (_hellaCacheArb_io_mem_s1_kill), .io_mem_s2_nack (_lsu_io_hellacache_s2_nack), // @[tile.scala:159:20] .io_mem_resp_valid (_lsu_io_hellacache_resp_valid), // @[tile.scala:159:20] .io_mem_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), // @[tile.scala:159:20] .io_mem_resp_bits_dprv (_lsu_io_hellacache_resp_bits_dprv), // @[tile.scala:159:20] .io_mem_resp_bits_dv (_lsu_io_hellacache_resp_bits_dv), // @[tile.scala:159:20] .io_mem_resp_bits_data (_lsu_io_hellacache_resp_bits_data), // @[tile.scala:159:20] .io_mem_resp_bits_data_word_bypass (_lsu_io_hellacache_resp_bits_data_word_bypass), // @[tile.scala:159:20] .io_mem_resp_bits_data_raw (_lsu_io_hellacache_resp_bits_data_raw), // @[tile.scala:159:20] .io_mem_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), // @[tile.scala:159:20] .io_mem_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), // @[tile.scala:159:20] .io_mem_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), // @[tile.scala:159:20] .io_mem_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), // @[tile.scala:159:20] .io_mem_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), // @[tile.scala:159:20] .io_mem_store_pending (_lsu_io_hellacache_store_pending) // @[tile.scala:159:20] ); // @[tile.scala:242:29] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[tile.scala:154:7] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[tile.scala:154:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[tile.scala:154:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[tile.scala:154:7] assign auto_buffer_out_c_bits_corrupt = auto_buffer_out_c_bits_corrupt_0; // @[tile.scala:154:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[tile.scala:154:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[tile.scala:154:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[tile.scala:154:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[tile.scala:154:7] assign auto_trace_source_out_custom_rob_empty = auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:154:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_1 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_1 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h14), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h18), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h12), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow

module EgressUnit_1( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to this FIRRTL code module DTLB_5 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) node memIdx = bits(vpn, 1, 0) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4][4], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[1], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<0>, clock reg r_sectored_repl_addr : UInt<2>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<0>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_49 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_5 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_5 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _sector_hits_T_1 = shr(_sector_hits_T, 0) node _sector_hits_T_2 = eq(_sector_hits_T_1, UInt<1>(0h0)) node _sector_hits_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _sector_hits_T_4 = and(_sector_hits_T_2, _sector_hits_T_3) node sector_hits_0 = and(sectored_entries[memIdx][0].valid[0], _sector_hits_T_4) node _sector_hits_T_5 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _sector_hits_T_6 = shr(_sector_hits_T_5, 0) node _sector_hits_T_7 = eq(_sector_hits_T_6, UInt<1>(0h0)) node _sector_hits_T_8 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _sector_hits_T_9 = and(_sector_hits_T_7, _sector_hits_T_8) node sector_hits_1 = and(sectored_entries[memIdx][1].valid[0], _sector_hits_T_9) node _sector_hits_T_10 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _sector_hits_T_11 = shr(_sector_hits_T_10, 0) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _sector_hits_T_14 = and(_sector_hits_T_12, _sector_hits_T_13) node sector_hits_2 = and(sectored_entries[memIdx][2].valid[0], _sector_hits_T_14) node _sector_hits_T_15 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _sector_hits_T_16 = shr(_sector_hits_T_15, 0) node _sector_hits_T_17 = eq(_sector_hits_T_16, UInt<1>(0h0)) node _sector_hits_T_18 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _sector_hits_T_19 = and(_sector_hits_T_17, _sector_hits_T_18) node sector_hits_3 = and(sectored_entries[memIdx][3].valid[0], _sector_hits_T_19) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _hitsVec_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 0) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[memIdx][0].valid[0], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node _hitsVec_T_6 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[memIdx][1].valid[0], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node _hitsVec_T_12 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[memIdx][2].valid[0], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node _hitsVec_T_18 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[memIdx][3].valid[0], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_24 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_25 = bits(_hitsVec_T_24, 26, 18) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = or(hitsVec_ignore, _hitsVec_T_26) node _hitsVec_T_28 = and(hitsVec_tagMatch, _hitsVec_T_27) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_29 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_30 = bits(_hitsVec_T_29, 17, 9) node _hitsVec_T_31 = eq(_hitsVec_T_30, UInt<1>(0h0)) node _hitsVec_T_32 = or(hitsVec_ignore_1, _hitsVec_T_31) node _hitsVec_T_33 = and(_hitsVec_T_28, _hitsVec_T_32) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_34 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_35 = bits(_hitsVec_T_34, 8, 0) node _hitsVec_T_36 = eq(_hitsVec_T_35, UInt<1>(0h0)) node _hitsVec_T_37 = or(hitsVec_ignore_2, _hitsVec_T_36) node _hitsVec_T_38 = and(_hitsVec_T_33, _hitsVec_T_37) node hitsVec_4 = and(vm_enabled, _hitsVec_T_38) node _hitsVec_tagMatch_T_1 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_1 = and(special_entry.valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_39 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_40 = bits(_hitsVec_T_39, 26, 18) node _hitsVec_T_41 = eq(_hitsVec_T_40, UInt<1>(0h0)) node _hitsVec_T_42 = or(hitsVec_ignore_3, _hitsVec_T_41) node _hitsVec_T_43 = and(hitsVec_tagMatch_1, _hitsVec_T_42) node _hitsVec_ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_44 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_45 = bits(_hitsVec_T_44, 17, 9) node _hitsVec_T_46 = eq(_hitsVec_T_45, UInt<1>(0h0)) node _hitsVec_T_47 = or(hitsVec_ignore_4, _hitsVec_T_46) node _hitsVec_T_48 = and(_hitsVec_T_43, _hitsVec_T_47) node _hitsVec_ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h0)) node _hitsVec_T_49 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_50 = bits(_hitsVec_T_49, 8, 0) node _hitsVec_T_51 = eq(_hitsVec_T_50, UInt<1>(0h0)) node _hitsVec_T_52 = or(hitsVec_ignore_5, _hitsVec_T_51) node _hitsVec_T_53 = and(_hitsVec_T_48, _hitsVec_T_52) node hitsVec_5 = and(vm_enabled, _hitsVec_T_53) node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node r_memIdx = bits(r_refill_tag, 1, 0) node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_4 = eq(waddr_1, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_5 : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][0].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][0].tag_v, refill_v connect sectored_entries[r_memIdx][0].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h1) node sectored_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_0_lo_lo_hi = cat(sectored_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_data_0_lo_lo = cat(sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo) node sectored_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_0_lo_hi_lo = cat(sectored_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_data_0_lo_hi_hi = cat(sectored_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_data_0_lo_hi = cat(sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo) node sectored_entries_0_data_0_lo = cat(sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo) node sectored_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_data_0_hi_lo_lo = cat(sectored_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_data_0_hi_lo_hi = cat(sectored_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_data_0_hi_lo = cat(sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo) node sectored_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_data_0_hi_hi_lo = cat(sectored_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_0_hi_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_data_0_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo) node sectored_entries_0_data_0_hi = cat(sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo) node _sectored_entries_0_data_0_T = cat(sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo) connect sectored_entries[r_memIdx][0].data[0], _sectored_entries_0_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) node _T_6 = eq(waddr_1, UInt<1>(0h1)) when _T_6 : node _T_7 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_7 : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][1].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][1].tag_v, refill_v connect sectored_entries[r_memIdx][1].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h1) node sectored_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_0_lo_lo_hi = cat(sectored_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_1_data_0_lo_lo = cat(sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo) node sectored_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_0_lo_hi_lo = cat(sectored_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_1_data_0_lo_hi_hi = cat(sectored_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_1_data_0_lo_hi = cat(sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo) node sectored_entries_1_data_0_lo = cat(sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo) node sectored_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_1_data_0_hi_lo_lo = cat(sectored_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_1_data_0_hi_lo_hi = cat(sectored_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_1_data_0_hi_lo = cat(sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo) node sectored_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_1_data_0_hi_hi_lo = cat(sectored_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_0_hi_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_1_data_0_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo) node sectored_entries_1_data_0_hi = cat(sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo) node _sectored_entries_1_data_0_T = cat(sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo) connect sectored_entries[r_memIdx][1].data[0], _sectored_entries_1_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) node _T_8 = eq(waddr_1, UInt<2>(0h2)) when _T_8 : node _T_9 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_9 : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][2].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][2].tag_v, refill_v connect sectored_entries[r_memIdx][2].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h1) node sectored_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_0_lo_lo_hi = cat(sectored_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_2_data_0_lo_lo = cat(sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo) node sectored_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_0_lo_hi_lo = cat(sectored_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_2_data_0_lo_hi_hi = cat(sectored_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_2_data_0_lo_hi = cat(sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo) node sectored_entries_2_data_0_lo = cat(sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo) node sectored_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_2_data_0_hi_lo_lo = cat(sectored_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_2_data_0_hi_lo_hi = cat(sectored_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_2_data_0_hi_lo = cat(sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo) node sectored_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_2_data_0_hi_hi_lo = cat(sectored_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_0_hi_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_2_data_0_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo) node sectored_entries_2_data_0_hi = cat(sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo) node _sectored_entries_2_data_0_T = cat(sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo) connect sectored_entries[r_memIdx][2].data[0], _sectored_entries_2_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) node _T_10 = eq(waddr_1, UInt<2>(0h3)) when _T_10 : node _T_11 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_11 : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][3].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][3].tag_v, refill_v connect sectored_entries[r_memIdx][3].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h1) node sectored_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_0_lo_lo_hi = cat(sectored_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_3_data_0_lo_lo = cat(sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo) node sectored_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_0_lo_hi_lo = cat(sectored_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_3_data_0_lo_hi_hi = cat(sectored_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_3_data_0_lo_hi = cat(sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo) node sectored_entries_3_data_0_lo = cat(sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo) node sectored_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_3_data_0_hi_lo_lo = cat(sectored_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_3_data_0_hi_lo_hi = cat(sectored_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_3_data_0_hi_lo = cat(sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo) node sectored_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_3_data_0_hi_hi_lo = cat(sectored_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_0_hi_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_3_data_0_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo) node sectored_entries_3_data_0_hi = cat(sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo) node _sectored_entries_3_data_0_T = cat(sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo) connect sectored_entries[r_memIdx][3].data[0], _sectored_entries_3_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[memIdx][0].data[0] node _entries_T = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T node _entries_T_1 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_22 inst entries_barrier of OptimizationBarrier_TLBEntryData_50 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[memIdx][1].data[0] node _entries_T_23 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_45 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_51 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[memIdx][2].data[0] node _entries_T_46 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_68 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_52 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[memIdx][3].data[0] node _entries_T_69 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_91 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_53 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, superpage_entries[0].data[0] node _entries_T_92 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_114 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_54 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, special_entry.data[0] node _entries_T_115 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_137 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_55 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_4.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_4.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_4.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_5.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h0)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_5.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node _ppn_T_17 = bits(vpn, 19, 0) node _ppn_T_18 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_19 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_20 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_21 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_22 = mux(hitsVec_4, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_23 = mux(hitsVec_5, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_24 = mux(_ppn_T, _ppn_T_17, UInt<1>(0h0)) node _ppn_T_25 = or(_ppn_T_18, _ppn_T_19) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_20) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_21) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_22) node _ppn_T_29 = or(_ppn_T_28, _ppn_T_23) node _ppn_T_30 = or(_ppn_T_29, _ppn_T_24) wire ppn : UInt<20> connect ppn, _ppn_T_30 node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<7>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<3>, clock, reset, UInt<3>(0h0) wire _state_vec_WIRE : UInt<3>[4] connect _state_vec_WIRE[0], UInt<3>(0h0) connect _state_vec_WIRE[1], UInt<3>(0h0) connect _state_vec_WIRE[2], UInt<3>(0h0) connect _state_vec_WIRE[3], UInt<3>(0h0) regreset state_vec : UInt<3>[4], clock, reset, _state_vec_WIRE reg state_reg_1 : UInt<0>, clock node _T_12 = and(io.req.valid, vm_enabled) when _T_12 : node _T_13 = or(sector_hits_0, sector_hits_1) node _T_14 = or(_T_13, sector_hits_2) node _T_15 = or(_T_14, sector_hits_3) when _T_15 : node lo = cat(sector_hits_1, sector_hits_0) node hi = cat(sector_hits_3, sector_hits_2) node _T_16 = cat(hi, lo) node hi_1 = bits(_T_16, 3, 2) node lo_1 = bits(_T_16, 1, 0) node _T_17 = orr(hi_1) node _T_18 = or(hi_1, lo_1) node _T_19 = bits(_T_18, 1, 1) node _T_20 = cat(_T_17, _T_19) node state_vec_touch_way_sized = bits(_T_20, 1, 0) node _state_vec_set_left_older_T = bits(state_vec_touch_way_sized, 1, 1) node state_vec_set_left_older = eq(_state_vec_set_left_older_T, UInt<1>(0h0)) node state_vec_left_subtree_state = bits(state_vec[memIdx], 1, 1) node state_vec_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _state_vec_T = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_1 = bits(_state_vec_T, 0, 0) node _state_vec_T_2 = eq(_state_vec_T_1, UInt<1>(0h0)) node _state_vec_T_3 = mux(state_vec_set_left_older, state_vec_left_subtree_state, _state_vec_T_2) node _state_vec_T_4 = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_5 = bits(_state_vec_T_4, 0, 0) node _state_vec_T_6 = eq(_state_vec_T_5, UInt<1>(0h0)) node _state_vec_T_7 = mux(state_vec_set_left_older, _state_vec_T_6, state_vec_right_subtree_state) node state_vec_hi = cat(state_vec_set_left_older, _state_vec_T_3) node _state_vec_T_8 = cat(state_vec_hi, _state_vec_T_7) connect state_vec[memIdx], _state_vec_T_8 when superpage_hits_0 : connect state_reg_1, UInt<1>(0h0) node _multipleHits_T = bits(real_hits, 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits, 5, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_21 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_22 = and(_T_21, io.ptw.req.bits.valid) when _T_22 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_23 = and(io.req.ready, io.req.valid) node _T_24 = and(_T_23, tlb_miss) when _T_24 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node _r_superpage_repl_addr_T = andr(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_1 = not(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_2 = bits(_r_superpage_repl_addr_T_1, 0, 0) node _r_superpage_repl_addr_T_3 = mux(_r_superpage_repl_addr_T, UInt<1>(0h0), UInt<1>(0h0)) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_3 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[memIdx], 2, 2) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[memIdx], 1, 1) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_valids_lo = cat(sectored_entries[memIdx][1].valid[0], sectored_entries[memIdx][0].valid[0]) node r_sectored_repl_addr_valids_hi = cat(sectored_entries[memIdx][3].valid[0], sectored_entries[memIdx][2].valid[0]) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_4 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_5 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_6 = bits(_r_sectored_repl_addr_T_5, 0, 0) node _r_sectored_repl_addr_T_7 = bits(_r_sectored_repl_addr_T_5, 1, 1) node _r_sectored_repl_addr_T_8 = bits(_r_sectored_repl_addr_T_5, 2, 2) node _r_sectored_repl_addr_T_9 = bits(_r_sectored_repl_addr_T_5, 3, 3) node _r_sectored_repl_addr_T_10 = mux(_r_sectored_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_sectored_repl_addr_T_11 = mux(_r_sectored_repl_addr_T_7, UInt<1>(0h1), _r_sectored_repl_addr_T_10) node _r_sectored_repl_addr_T_12 = mux(_r_sectored_repl_addr_T_6, UInt<1>(0h0), _r_sectored_repl_addr_T_11) node _r_sectored_repl_addr_T_13 = mux(_r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_12) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_13 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_2 node r_sectored_hit_bits_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_hi = cat(sector_hits_3, sector_hits_2) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 3, 2) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 1, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node _r_sectored_hit_bits_T_3 = bits(_r_sectored_hit_bits_T_2, 1, 1) node _r_sectored_hit_bits_T_4 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_4 connect r_superpage_hit.valid, superpage_hits_0 connect r_superpage_hit.bits, UInt<1>(0h0) node _T_25 = eq(state, UInt<2>(0h1)) when _T_25 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_26 = eq(state, UInt<2>(0h2)) node _T_27 = and(_T_26, io.sfence.valid) when _T_27 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_28 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_29 = shr(io.sfence.bits.addr, 12) node _T_30 = eq(_T_29, vpn) node _T_31 = or(_T_28, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_31, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_35 = eq(hg, UInt<1>(0h0)) node _T_36 = and(_T_35, io.sfence.bits.rs1) when _T_36 : node _T_37 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_38 = shr(_T_37, 0) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = eq(sectored_entries[0][0].tag_v, hv) node _T_41 = and(_T_39, _T_40) when _T_41 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_42 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_42 node _T_43 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_43 node _T_44 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_44 node _T_45 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_45 node _T_46 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_46 node _T_47 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_47 node _T_48 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_48 node _T_49 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_49 node _T_50 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_50 node _T_51 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_51 node _T_52 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_52 node _T_53 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_53 node _T_54 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_54 node _T_55 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_55 node _T_56 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_56 node _T_57 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_57 node _T_58 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_58 node _T_59 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_59 node _T_60 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_60 node _T_61 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_61 node _T_62 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_62 node _T_63 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_63 node _T_64 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_64 node _T_65 = eq(sectored_entries[0][0].tag_v, hv) node _T_66 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_68 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_69 = shr(_T_68, 18) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[0] node _T_71 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_71 node _T_72 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_72 node _T_73 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_73 node _T_74 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_74 node _T_75 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_75 node _T_76 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_76 node _T_77 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_77 node _T_78 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_78 node _T_79 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_79 node _T_80 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_80 node _T_81 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_81 node _T_82 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_82 node _T_83 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_83 node _T_84 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_84 node _T_85 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_85 node _T_86 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_86 node _T_87 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_87 node _T_88 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_88 node _T_89 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_89 node _T_90 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_90 node _T_91 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_91 node _T_92 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_92 node _T_93 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_93 node _T_94 = eq(sectored_entries[0][0].tag_v, hv) node _T_95 = and(_T_94, _WIRE_2.fragmented_superpage) when _T_95 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_96 = eq(hg, UInt<1>(0h0)) node _T_97 = and(_T_96, io.sfence.bits.rs2) when _T_97 : wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[0] node _T_98 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_98 node _T_99 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_99 node _T_100 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_100 node _T_101 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_101 node _T_102 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_102 node _T_103 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_103 node _T_104 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_104 node _T_105 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_105 node _T_106 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_106 node _T_107 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_107 node _T_108 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_108 node _T_109 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_109 node _T_110 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_110 node _T_111 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_111 node _T_112 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_112 node _T_113 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_113 node _T_114 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_114 node _T_115 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_115 node _T_116 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_116 node _T_117 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_117 node _T_118 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_118 node _T_119 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_119 node _T_120 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_120 node _T_121 = eq(sectored_entries[0][0].tag_v, hv) node _T_122 = eq(_WIRE_4.g, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) when _T_123 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_124 = or(hv, hg) wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[0] node _T_125 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_125 node _T_126 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_126 node _T_127 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_127 node _T_128 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_128 node _T_129 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_129 node _T_130 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_130 node _T_131 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_131 node _T_132 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_132 node _T_133 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_133 node _T_134 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_134 node _T_135 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_135 node _T_136 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_136 node _T_137 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_137 node _T_138 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_138 node _T_139 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_139 node _T_140 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_140 node _T_141 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_141 node _T_142 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_142 node _T_143 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_143 node _T_144 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_144 node _T_145 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_145 node _T_146 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_146 node _T_147 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_147 node _T_148 = eq(sectored_entries[0][0].tag_v, _T_124) when _T_148 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_149 = eq(hg_1, UInt<1>(0h0)) node _T_150 = and(_T_149, io.sfence.bits.rs1) when _T_150 : node _T_151 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_152 = shr(_T_151, 0) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_155 = and(_T_153, _T_154) when _T_155 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][1].data[0] node _T_156 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_156 node _T_157 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_157 node _T_158 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_158 node _T_159 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_159 node _T_160 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_160 node _T_161 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_161 node _T_162 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_162 node _T_163 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_163 node _T_164 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_164 node _T_165 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_165 node _T_166 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_166 node _T_167 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_167 node _T_168 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_168 node _T_169 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_169 node _T_170 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_170 node _T_171 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_171 node _T_172 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_172 node _T_173 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_173 node _T_174 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_174 node _T_175 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_175 node _T_176 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_176 node _T_177 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_177 node _T_178 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_178 node _T_179 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_180 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_181 = and(_T_179, _T_180) when _T_181 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_182 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_183 = shr(_T_182, 18) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][1].data[0] node _T_185 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_185 node _T_186 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_186 node _T_187 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_187 node _T_188 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_188 node _T_189 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_189 node _T_190 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_190 node _T_191 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_191 node _T_192 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_192 node _T_193 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_193 node _T_194 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_194 node _T_195 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_195 node _T_196 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_196 node _T_197 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_197 node _T_198 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_198 node _T_199 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_199 node _T_200 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_200 node _T_201 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_201 node _T_202 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_202 node _T_203 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_203 node _T_204 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_204 node _T_205 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_205 node _T_206 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_206 node _T_207 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_207 node _T_208 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_209 = and(_T_208, _WIRE_10.fragmented_superpage) when _T_209 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_210 = eq(hg_1, UInt<1>(0h0)) node _T_211 = and(_T_210, io.sfence.bits.rs2) when _T_211 : wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][1].data[0] node _T_212 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_212 node _T_213 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_213 node _T_214 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_214 node _T_215 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_215 node _T_216 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_216 node _T_217 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_217 node _T_218 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_218 node _T_219 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_219 node _T_220 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_220 node _T_221 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_221 node _T_222 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_222 node _T_223 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_223 node _T_224 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_224 node _T_225 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_225 node _T_226 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_226 node _T_227 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_227 node _T_228 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_228 node _T_229 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_229 node _T_230 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_230 node _T_231 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_231 node _T_232 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_232 node _T_233 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_233 node _T_234 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_234 node _T_235 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_236 = eq(_WIRE_12.g, UInt<1>(0h0)) node _T_237 = and(_T_235, _T_236) when _T_237 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_238 = or(hv_1, hg_1) wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][1].data[0] node _T_239 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_239 node _T_240 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_240 node _T_241 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_241 node _T_242 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_242 node _T_243 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_243 node _T_244 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_244 node _T_245 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_245 node _T_246 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_246 node _T_247 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_247 node _T_248 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_248 node _T_249 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_249 node _T_250 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_250 node _T_251 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_251 node _T_252 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_252 node _T_253 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_253 node _T_254 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_254 node _T_255 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_255 node _T_256 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_256 node _T_257 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_257 node _T_258 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_258 node _T_259 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_259 node _T_260 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_260 node _T_261 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_261 node _T_262 = eq(sectored_entries[0][1].tag_v, _T_238) when _T_262 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_263 = eq(hg_2, UInt<1>(0h0)) node _T_264 = and(_T_263, io.sfence.bits.rs1) when _T_264 : node _T_265 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_266 = shr(_T_265, 0) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_269 = and(_T_267, _T_268) when _T_269 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][2].data[0] node _T_270 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_270 node _T_271 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_271 node _T_272 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_272 node _T_273 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_273 node _T_274 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_274 node _T_275 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_275 node _T_276 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_276 node _T_277 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_277 node _T_278 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_278 node _T_279 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_279 node _T_280 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_280 node _T_281 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_281 node _T_282 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_282 node _T_283 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_283 node _T_284 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_284 node _T_285 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_285 node _T_286 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_286 node _T_287 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_287 node _T_288 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_288 node _T_289 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_289 node _T_290 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_290 node _T_291 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_291 node _T_292 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_292 node _T_293 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_294 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) when _T_295 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_296 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_297 = shr(_T_296, 18) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][2].data[0] node _T_299 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_299 node _T_300 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_300 node _T_301 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_301 node _T_302 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_302 node _T_303 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_303 node _T_304 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_304 node _T_305 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_305 node _T_306 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_306 node _T_307 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_307 node _T_308 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_308 node _T_309 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_309 node _T_310 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_310 node _T_311 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_311 node _T_312 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_312 node _T_313 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_313 node _T_314 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_314 node _T_315 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_315 node _T_316 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_316 node _T_317 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_317 node _T_318 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_318 node _T_319 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_319 node _T_320 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_320 node _T_321 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_321 node _T_322 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_323 = and(_T_322, _WIRE_18.fragmented_superpage) when _T_323 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_324 = eq(hg_2, UInt<1>(0h0)) node _T_325 = and(_T_324, io.sfence.bits.rs2) when _T_325 : wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][2].data[0] node _T_326 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_326 node _T_327 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_327 node _T_328 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_328 node _T_329 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_329 node _T_330 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_330 node _T_331 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_331 node _T_332 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_332 node _T_333 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_333 node _T_334 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_334 node _T_335 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_335 node _T_336 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_336 node _T_337 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_337 node _T_338 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_338 node _T_339 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_339 node _T_340 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_340 node _T_341 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_341 node _T_342 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_342 node _T_343 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_343 node _T_344 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_344 node _T_345 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_345 node _T_346 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_346 node _T_347 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_347 node _T_348 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_348 node _T_349 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_350 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) when _T_351 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_352 = or(hv_2, hg_2) wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][2].data[0] node _T_353 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_353 node _T_354 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_354 node _T_355 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_355 node _T_356 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_356 node _T_357 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_357 node _T_358 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_358 node _T_359 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_359 node _T_360 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_360 node _T_361 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_361 node _T_362 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_362 node _T_363 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_363 node _T_364 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_364 node _T_365 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_365 node _T_366 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_366 node _T_367 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_367 node _T_368 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_368 node _T_369 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_369 node _T_370 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_370 node _T_371 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_371 node _T_372 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_372 node _T_373 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_373 node _T_374 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_374 node _T_375 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_375 node _T_376 = eq(sectored_entries[0][2].tag_v, _T_352) when _T_376 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_377 = eq(hg_3, UInt<1>(0h0)) node _T_378 = and(_T_377, io.sfence.bits.rs1) when _T_378 : node _T_379 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_380 = shr(_T_379, 0) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_383 = and(_T_381, _T_382) when _T_383 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][3].data[0] node _T_384 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_384 node _T_385 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_385 node _T_386 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_386 node _T_387 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_387 node _T_388 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_388 node _T_389 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_389 node _T_390 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_390 node _T_391 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_391 node _T_392 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_392 node _T_393 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_393 node _T_394 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_394 node _T_395 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_395 node _T_396 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_396 node _T_397 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_397 node _T_398 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_398 node _T_399 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_399 node _T_400 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_400 node _T_401 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_401 node _T_402 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_402 node _T_403 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_403 node _T_404 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_404 node _T_405 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_405 node _T_406 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_406 node _T_407 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_408 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = and(_T_407, _T_408) when _T_409 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_410 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_411 = shr(_T_410, 18) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][3].data[0] node _T_413 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_413 node _T_414 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_414 node _T_415 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_415 node _T_416 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_416 node _T_417 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_417 node _T_418 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_418 node _T_419 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_419 node _T_420 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_420 node _T_421 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_421 node _T_422 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_422 node _T_423 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_423 node _T_424 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_424 node _T_425 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_425 node _T_426 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_426 node _T_427 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_427 node _T_428 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_428 node _T_429 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_429 node _T_430 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_430 node _T_431 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_431 node _T_432 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_432 node _T_433 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_433 node _T_434 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_434 node _T_435 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_435 node _T_436 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_437 = and(_T_436, _WIRE_26.fragmented_superpage) when _T_437 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_438 = eq(hg_3, UInt<1>(0h0)) node _T_439 = and(_T_438, io.sfence.bits.rs2) when _T_439 : wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][3].data[0] node _T_440 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_440 node _T_441 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_441 node _T_442 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_442 node _T_443 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_443 node _T_444 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_444 node _T_445 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_445 node _T_446 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_446 node _T_447 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_447 node _T_448 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_448 node _T_449 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_449 node _T_450 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_450 node _T_451 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_451 node _T_452 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_452 node _T_453 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_453 node _T_454 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_454 node _T_455 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_455 node _T_456 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_456 node _T_457 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_457 node _T_458 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_458 node _T_459 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_459 node _T_460 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_460 node _T_461 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_461 node _T_462 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_462 node _T_463 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_464 = eq(_WIRE_28.g, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) when _T_465 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_466 = or(hv_3, hg_3) wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][3].data[0] node _T_467 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_467 node _T_468 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_468 node _T_469 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_469 node _T_470 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_470 node _T_471 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_471 node _T_472 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_472 node _T_473 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_473 node _T_474 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_474 node _T_475 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_475 node _T_476 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_476 node _T_477 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_477 node _T_478 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_478 node _T_479 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_479 node _T_480 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_480 node _T_481 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_481 node _T_482 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_482 node _T_483 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_483 node _T_484 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_484 node _T_485 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_485 node _T_486 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_486 node _T_487 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_487 node _T_488 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_488 node _T_489 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_489 node _T_490 = eq(sectored_entries[0][3].tag_v, _T_466) when _T_490 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_491 = eq(hg_4, UInt<1>(0h0)) node _T_492 = and(_T_491, io.sfence.bits.rs1) when _T_492 : node _T_493 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_494 = shr(_T_493, 0) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_497 = and(_T_495, _T_496) when _T_497 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[1][0].data[0] node _T_498 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_498 node _T_499 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_499 node _T_500 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_500 node _T_501 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_501 node _T_502 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_502 node _T_503 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_503 node _T_504 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_504 node _T_505 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_505 node _T_506 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_506 node _T_507 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_507 node _T_508 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_508 node _T_509 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_509 node _T_510 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_510 node _T_511 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_511 node _T_512 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_512 node _T_513 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_513 node _T_514 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_514 node _T_515 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_515 node _T_516 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_516 node _T_517 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_517 node _T_518 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_518 node _T_519 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_519 node _T_520 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_520 node _T_521 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = and(_T_521, _T_522) when _T_523 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node _T_524 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_525 = shr(_T_524, 18) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[1][0].data[0] node _T_527 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_527 node _T_528 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_528 node _T_529 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_529 node _T_530 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_530 node _T_531 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_531 node _T_532 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_532 node _T_533 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_533 node _T_534 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_534 node _T_535 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_535 node _T_536 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_536 node _T_537 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_537 node _T_538 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_538 node _T_539 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_539 node _T_540 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_540 node _T_541 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_541 node _T_542 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_542 node _T_543 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_543 node _T_544 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_544 node _T_545 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_545 node _T_546 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_546 node _T_547 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_547 node _T_548 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_548 node _T_549 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_549 node _T_550 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_551 = and(_T_550, _WIRE_34.fragmented_superpage) when _T_551 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_552 = eq(hg_4, UInt<1>(0h0)) node _T_553 = and(_T_552, io.sfence.bits.rs2) when _T_553 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[1][0].data[0] node _T_554 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_554 node _T_555 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_555 node _T_556 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_556 node _T_557 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_557 node _T_558 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_558 node _T_559 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_559 node _T_560 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_560 node _T_561 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_561 node _T_562 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_562 node _T_563 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_563 node _T_564 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_564 node _T_565 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_565 node _T_566 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_566 node _T_567 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_567 node _T_568 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_568 node _T_569 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_569 node _T_570 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_570 node _T_571 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_571 node _T_572 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_572 node _T_573 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_573 node _T_574 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_574 node _T_575 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_575 node _T_576 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_576 node _T_577 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_578 = eq(_WIRE_36.g, UInt<1>(0h0)) node _T_579 = and(_T_577, _T_578) when _T_579 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_580 = or(hv_4, hg_4) wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[1][0].data[0] node _T_581 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_581 node _T_582 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_582 node _T_583 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_583 node _T_584 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_584 node _T_585 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_585 node _T_586 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_586 node _T_587 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_587 node _T_588 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_588 node _T_589 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_589 node _T_590 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_590 node _T_591 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_591 node _T_592 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_592 node _T_593 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_593 node _T_594 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_594 node _T_595 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_595 node _T_596 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_596 node _T_597 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_597 node _T_598 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_598 node _T_599 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_599 node _T_600 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_600 node _T_601 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_601 node _T_602 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_602 node _T_603 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_603 node _T_604 = eq(sectored_entries[1][0].tag_v, _T_580) when _T_604 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_605 = eq(hg_5, UInt<1>(0h0)) node _T_606 = and(_T_605, io.sfence.bits.rs1) when _T_606 : node _T_607 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_608 = shr(_T_607, 0) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_611 = and(_T_609, _T_610) when _T_611 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[1][1].data[0] node _T_612 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_612 node _T_613 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_613 node _T_614 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_614 node _T_615 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_615 node _T_616 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_616 node _T_617 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_617 node _T_618 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_618 node _T_619 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_619 node _T_620 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_620 node _T_621 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_621 node _T_622 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_622 node _T_623 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_623 node _T_624 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_624 node _T_625 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_625 node _T_626 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_626 node _T_627 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_627 node _T_628 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_628 node _T_629 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_629 node _T_630 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_630 node _T_631 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_631 node _T_632 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_632 node _T_633 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_633 node _T_634 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_634 node _T_635 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_636 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = and(_T_635, _T_636) when _T_637 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node _T_638 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_639 = shr(_T_638, 18) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[1][1].data[0] node _T_641 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_641 node _T_642 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_642 node _T_643 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_643 node _T_644 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_644 node _T_645 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_645 node _T_646 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_646 node _T_647 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_647 node _T_648 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_648 node _T_649 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_649 node _T_650 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_650 node _T_651 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_651 node _T_652 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_652 node _T_653 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_653 node _T_654 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_654 node _T_655 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_655 node _T_656 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_656 node _T_657 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_657 node _T_658 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_658 node _T_659 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_659 node _T_660 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_660 node _T_661 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_661 node _T_662 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_662 node _T_663 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_663 node _T_664 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_665 = and(_T_664, _WIRE_42.fragmented_superpage) when _T_665 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_666 = eq(hg_5, UInt<1>(0h0)) node _T_667 = and(_T_666, io.sfence.bits.rs2) when _T_667 : wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[1][1].data[0] node _T_668 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_668 node _T_669 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_669 node _T_670 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_670 node _T_671 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_671 node _T_672 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_672 node _T_673 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_673 node _T_674 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_674 node _T_675 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_675 node _T_676 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_676 node _T_677 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_677 node _T_678 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_678 node _T_679 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_679 node _T_680 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_680 node _T_681 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_681 node _T_682 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_682 node _T_683 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_683 node _T_684 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_684 node _T_685 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_685 node _T_686 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_686 node _T_687 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_687 node _T_688 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_688 node _T_689 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_689 node _T_690 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_690 node _T_691 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_692 = eq(_WIRE_44.g, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) when _T_693 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_694 = or(hv_5, hg_5) wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[1][1].data[0] node _T_695 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_695 node _T_696 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_696 node _T_697 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_697 node _T_698 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_698 node _T_699 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_699 node _T_700 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_700 node _T_701 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_701 node _T_702 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_702 node _T_703 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_703 node _T_704 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_704 node _T_705 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_705 node _T_706 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_706 node _T_707 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_707 node _T_708 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_708 node _T_709 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_709 node _T_710 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_710 node _T_711 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_711 node _T_712 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_712 node _T_713 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_713 node _T_714 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_714 node _T_715 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_715 node _T_716 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_716 node _T_717 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_717 node _T_718 = eq(sectored_entries[1][1].tag_v, _T_694) when _T_718 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_719 = eq(hg_6, UInt<1>(0h0)) node _T_720 = and(_T_719, io.sfence.bits.rs1) when _T_720 : node _T_721 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_722 = shr(_T_721, 0) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_725 = and(_T_723, _T_724) when _T_725 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[1][2].data[0] node _T_726 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_726 node _T_727 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_727 node _T_728 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_728 node _T_729 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_729 node _T_730 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_730 node _T_731 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_731 node _T_732 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_732 node _T_733 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_733 node _T_734 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_734 node _T_735 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_735 node _T_736 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_736 node _T_737 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_737 node _T_738 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_738 node _T_739 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_739 node _T_740 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_740 node _T_741 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_741 node _T_742 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_742 node _T_743 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_743 node _T_744 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_744 node _T_745 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_745 node _T_746 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_746 node _T_747 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_747 node _T_748 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_748 node _T_749 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_750 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = and(_T_749, _T_750) when _T_751 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node _T_752 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_753 = shr(_T_752, 18) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[1][2].data[0] node _T_755 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_755 node _T_756 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_756 node _T_757 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_757 node _T_758 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_758 node _T_759 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_759 node _T_760 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_760 node _T_761 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_761 node _T_762 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_762 node _T_763 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_763 node _T_764 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_764 node _T_765 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_765 node _T_766 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_766 node _T_767 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_767 node _T_768 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_768 node _T_769 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_769 node _T_770 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_770 node _T_771 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_771 node _T_772 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_772 node _T_773 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_773 node _T_774 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_774 node _T_775 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_775 node _T_776 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_776 node _T_777 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_777 node _T_778 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_779 = and(_T_778, _WIRE_50.fragmented_superpage) when _T_779 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_780 = eq(hg_6, UInt<1>(0h0)) node _T_781 = and(_T_780, io.sfence.bits.rs2) when _T_781 : wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[1][2].data[0] node _T_782 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_782 node _T_783 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_783 node _T_784 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_784 node _T_785 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_785 node _T_786 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_786 node _T_787 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_787 node _T_788 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_788 node _T_789 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_789 node _T_790 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_790 node _T_791 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_791 node _T_792 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_792 node _T_793 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_793 node _T_794 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_794 node _T_795 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_795 node _T_796 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_796 node _T_797 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_797 node _T_798 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_798 node _T_799 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_799 node _T_800 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_800 node _T_801 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_801 node _T_802 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_802 node _T_803 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_803 node _T_804 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_804 node _T_805 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_806 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_807 = and(_T_805, _T_806) when _T_807 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_808 = or(hv_6, hg_6) wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[1][2].data[0] node _T_809 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_809 node _T_810 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_810 node _T_811 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_811 node _T_812 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_812 node _T_813 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_813 node _T_814 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_814 node _T_815 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_815 node _T_816 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_816 node _T_817 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_817 node _T_818 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_818 node _T_819 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_819 node _T_820 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_820 node _T_821 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_821 node _T_822 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_822 node _T_823 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_823 node _T_824 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_824 node _T_825 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_825 node _T_826 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_826 node _T_827 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_827 node _T_828 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_828 node _T_829 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_829 node _T_830 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_830 node _T_831 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_831 node _T_832 = eq(sectored_entries[1][2].tag_v, _T_808) when _T_832 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_833 = eq(hg_7, UInt<1>(0h0)) node _T_834 = and(_T_833, io.sfence.bits.rs1) when _T_834 : node _T_835 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_836 = shr(_T_835, 0) node _T_837 = eq(_T_836, UInt<1>(0h0)) node _T_838 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_839 = and(_T_837, _T_838) when _T_839 : wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[1][3].data[0] node _T_840 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_840 node _T_841 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_841 node _T_842 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_842 node _T_843 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_843 node _T_844 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_844 node _T_845 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_845 node _T_846 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_846 node _T_847 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_847 node _T_848 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_848 node _T_849 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_849 node _T_850 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_850 node _T_851 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_851 node _T_852 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_852 node _T_853 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_853 node _T_854 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_854 node _T_855 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_855 node _T_856 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_856 node _T_857 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_857 node _T_858 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_858 node _T_859 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_859 node _T_860 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_860 node _T_861 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_861 node _T_862 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_862 node _T_863 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_864 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_865 = and(_T_863, _T_864) when _T_865 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node _T_866 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_867 = shr(_T_866, 18) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[1][3].data[0] node _T_869 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_869 node _T_870 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_870 node _T_871 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_871 node _T_872 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_872 node _T_873 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_873 node _T_874 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_874 node _T_875 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_875 node _T_876 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_876 node _T_877 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_877 node _T_878 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_878 node _T_879 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_879 node _T_880 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_880 node _T_881 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_881 node _T_882 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_882 node _T_883 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_883 node _T_884 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_884 node _T_885 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_885 node _T_886 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_886 node _T_887 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_887 node _T_888 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_888 node _T_889 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_889 node _T_890 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_890 node _T_891 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_891 node _T_892 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_893 = and(_T_892, _WIRE_58.fragmented_superpage) when _T_893 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_894 = eq(hg_7, UInt<1>(0h0)) node _T_895 = and(_T_894, io.sfence.bits.rs2) when _T_895 : wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[1][3].data[0] node _T_896 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_896 node _T_897 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_897 node _T_898 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_898 node _T_899 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_899 node _T_900 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_900 node _T_901 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_901 node _T_902 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_902 node _T_903 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_903 node _T_904 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_904 node _T_905 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_905 node _T_906 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_906 node _T_907 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_907 node _T_908 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_908 node _T_909 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_909 node _T_910 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_910 node _T_911 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_911 node _T_912 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_912 node _T_913 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_913 node _T_914 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_914 node _T_915 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_915 node _T_916 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_916 node _T_917 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_917 node _T_918 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_918 node _T_919 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_920 = eq(_WIRE_60.g, UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) when _T_921 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_922 = or(hv_7, hg_7) wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[1][3].data[0] node _T_923 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_923 node _T_924 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_924 node _T_925 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_925 node _T_926 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_926 node _T_927 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_927 node _T_928 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_928 node _T_929 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_929 node _T_930 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_930 node _T_931 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_931 node _T_932 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_932 node _T_933 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_933 node _T_934 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_934 node _T_935 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_935 node _T_936 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_936 node _T_937 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_937 node _T_938 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_938 node _T_939 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_939 node _T_940 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_940 node _T_941 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_941 node _T_942 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_942 node _T_943 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_943 node _T_944 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_944 node _T_945 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_945 node _T_946 = eq(sectored_entries[1][3].tag_v, _T_922) when _T_946 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_947 = eq(hg_8, UInt<1>(0h0)) node _T_948 = and(_T_947, io.sfence.bits.rs1) when _T_948 : node _T_949 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_950 = shr(_T_949, 0) node _T_951 = eq(_T_950, UInt<1>(0h0)) node _T_952 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_953 = and(_T_951, _T_952) when _T_953 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[2][0].data[0] node _T_954 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_954 node _T_955 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_955 node _T_956 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_956 node _T_957 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_957 node _T_958 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_958 node _T_959 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_959 node _T_960 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_960 node _T_961 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_961 node _T_962 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_962 node _T_963 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_963 node _T_964 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_964 node _T_965 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_965 node _T_966 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_966 node _T_967 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_967 node _T_968 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_968 node _T_969 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_969 node _T_970 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_970 node _T_971 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_971 node _T_972 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_972 node _T_973 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_973 node _T_974 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_974 node _T_975 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_975 node _T_976 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_976 node _T_977 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_978 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_979 = and(_T_977, _T_978) when _T_979 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node _T_980 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_981 = shr(_T_980, 18) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[2][0].data[0] node _T_983 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_983 node _T_984 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_984 node _T_985 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_985 node _T_986 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_986 node _T_987 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_987 node _T_988 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_988 node _T_989 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_989 node _T_990 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_990 node _T_991 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_991 node _T_992 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_992 node _T_993 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_993 node _T_994 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_994 node _T_995 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_995 node _T_996 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_996 node _T_997 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_997 node _T_998 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_998 node _T_999 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_999 node _T_1000 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_1000 node _T_1001 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_1001 node _T_1002 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_1002 node _T_1003 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_1003 node _T_1004 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_1004 node _T_1005 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_1005 node _T_1006 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1007 = and(_T_1006, _WIRE_66.fragmented_superpage) when _T_1007 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1008 = eq(hg_8, UInt<1>(0h0)) node _T_1009 = and(_T_1008, io.sfence.bits.rs2) when _T_1009 : wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[2][0].data[0] node _T_1010 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_1010 node _T_1011 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_1011 node _T_1012 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_1012 node _T_1013 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_1013 node _T_1014 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_1014 node _T_1015 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_1015 node _T_1016 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_1016 node _T_1017 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_1017 node _T_1018 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_1018 node _T_1019 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_1019 node _T_1020 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_1020 node _T_1021 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_1021 node _T_1022 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_1022 node _T_1023 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_1023 node _T_1024 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_1024 node _T_1025 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_1025 node _T_1026 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_1026 node _T_1027 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_1027 node _T_1028 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_1028 node _T_1029 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_1029 node _T_1030 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_1030 node _T_1031 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_1031 node _T_1032 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_1032 node _T_1033 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1034 = eq(_WIRE_68.g, UInt<1>(0h0)) node _T_1035 = and(_T_1033, _T_1034) when _T_1035 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1036 = or(hv_8, hg_8) wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[2][0].data[0] node _T_1037 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_1037 node _T_1038 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_1038 node _T_1039 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_1039 node _T_1040 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_1040 node _T_1041 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_1041 node _T_1042 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_1042 node _T_1043 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_1043 node _T_1044 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_1044 node _T_1045 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_1045 node _T_1046 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_1046 node _T_1047 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_1047 node _T_1048 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_1048 node _T_1049 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_1049 node _T_1050 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_1050 node _T_1051 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_1051 node _T_1052 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_1052 node _T_1053 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_1053 node _T_1054 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_1054 node _T_1055 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_1055 node _T_1056 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_1056 node _T_1057 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_1057 node _T_1058 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1058 node _T_1059 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1059 node _T_1060 = eq(sectored_entries[2][0].tag_v, _T_1036) when _T_1060 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1061 = eq(hg_9, UInt<1>(0h0)) node _T_1062 = and(_T_1061, io.sfence.bits.rs1) when _T_1062 : node _T_1063 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1064 = shr(_T_1063, 0) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1067 = and(_T_1065, _T_1066) when _T_1067 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[2][1].data[0] node _T_1068 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1068 node _T_1069 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1069 node _T_1070 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1070 node _T_1071 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1071 node _T_1072 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1072 node _T_1073 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1073 node _T_1074 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1074 node _T_1075 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1075 node _T_1076 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1076 node _T_1077 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1077 node _T_1078 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1078 node _T_1079 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1079 node _T_1080 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1080 node _T_1081 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1081 node _T_1082 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1082 node _T_1083 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1083 node _T_1084 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1084 node _T_1085 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1085 node _T_1086 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1086 node _T_1087 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1087 node _T_1088 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1088 node _T_1089 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1089 node _T_1090 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1090 node _T_1091 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1092 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = and(_T_1091, _T_1092) when _T_1093 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node _T_1094 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1095 = shr(_T_1094, 18) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[2][1].data[0] node _T_1097 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1097 node _T_1098 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1098 node _T_1099 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1099 node _T_1100 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1100 node _T_1101 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1101 node _T_1102 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1102 node _T_1103 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1103 node _T_1104 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1104 node _T_1105 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1105 node _T_1106 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1106 node _T_1107 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1107 node _T_1108 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1108 node _T_1109 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1109 node _T_1110 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1110 node _T_1111 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1111 node _T_1112 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1112 node _T_1113 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1113 node _T_1114 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1114 node _T_1115 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1115 node _T_1116 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1116 node _T_1117 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1117 node _T_1118 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1118 node _T_1119 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1119 node _T_1120 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1121 = and(_T_1120, _WIRE_74.fragmented_superpage) when _T_1121 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1122 = eq(hg_9, UInt<1>(0h0)) node _T_1123 = and(_T_1122, io.sfence.bits.rs2) when _T_1123 : wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[2][1].data[0] node _T_1124 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1124 node _T_1125 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1125 node _T_1126 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1126 node _T_1127 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1127 node _T_1128 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1128 node _T_1129 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1129 node _T_1130 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1130 node _T_1131 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1131 node _T_1132 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1132 node _T_1133 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1133 node _T_1134 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1134 node _T_1135 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1135 node _T_1136 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1136 node _T_1137 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1137 node _T_1138 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1138 node _T_1139 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1139 node _T_1140 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1140 node _T_1141 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1141 node _T_1142 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1142 node _T_1143 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1143 node _T_1144 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1144 node _T_1145 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1145 node _T_1146 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1146 node _T_1147 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1148 = eq(_WIRE_76.g, UInt<1>(0h0)) node _T_1149 = and(_T_1147, _T_1148) when _T_1149 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1150 = or(hv_9, hg_9) wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[2][1].data[0] node _T_1151 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1151 node _T_1152 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1152 node _T_1153 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1153 node _T_1154 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1154 node _T_1155 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1155 node _T_1156 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1156 node _T_1157 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1157 node _T_1158 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1158 node _T_1159 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1159 node _T_1160 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1160 node _T_1161 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1161 node _T_1162 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1162 node _T_1163 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1163 node _T_1164 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1164 node _T_1165 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1165 node _T_1166 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1166 node _T_1167 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1167 node _T_1168 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1168 node _T_1169 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1169 node _T_1170 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1170 node _T_1171 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1171 node _T_1172 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1172 node _T_1173 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1173 node _T_1174 = eq(sectored_entries[2][1].tag_v, _T_1150) when _T_1174 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1175 = eq(hg_10, UInt<1>(0h0)) node _T_1176 = and(_T_1175, io.sfence.bits.rs1) when _T_1176 : node _T_1177 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1178 = shr(_T_1177, 0) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1181 = and(_T_1179, _T_1180) when _T_1181 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[2][2].data[0] node _T_1182 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1182 node _T_1183 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1183 node _T_1184 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1184 node _T_1185 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1185 node _T_1186 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1186 node _T_1187 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1187 node _T_1188 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1188 node _T_1189 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1189 node _T_1190 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1190 node _T_1191 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1191 node _T_1192 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1192 node _T_1193 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1193 node _T_1194 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1194 node _T_1195 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1195 node _T_1196 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1196 node _T_1197 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1197 node _T_1198 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1198 node _T_1199 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1199 node _T_1200 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1200 node _T_1201 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1201 node _T_1202 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1202 node _T_1203 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1203 node _T_1204 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1204 node _T_1205 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1206 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node _T_1208 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1209 = shr(_T_1208, 18) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[2][2].data[0] node _T_1211 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1211 node _T_1212 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1212 node _T_1213 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1213 node _T_1214 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1214 node _T_1215 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1215 node _T_1216 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1216 node _T_1217 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1217 node _T_1218 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1218 node _T_1219 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1219 node _T_1220 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1220 node _T_1221 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1221 node _T_1222 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1222 node _T_1223 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1223 node _T_1224 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1224 node _T_1225 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1225 node _T_1226 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1226 node _T_1227 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1227 node _T_1228 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1228 node _T_1229 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1229 node _T_1230 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1230 node _T_1231 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1231 node _T_1232 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1232 node _T_1233 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1233 node _T_1234 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1235 = and(_T_1234, _WIRE_82.fragmented_superpage) when _T_1235 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1236 = eq(hg_10, UInt<1>(0h0)) node _T_1237 = and(_T_1236, io.sfence.bits.rs2) when _T_1237 : wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[2][2].data[0] node _T_1238 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1238 node _T_1239 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1239 node _T_1240 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1240 node _T_1241 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1241 node _T_1242 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1242 node _T_1243 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1243 node _T_1244 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1244 node _T_1245 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1245 node _T_1246 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1246 node _T_1247 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1247 node _T_1248 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1248 node _T_1249 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1249 node _T_1250 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1250 node _T_1251 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1251 node _T_1252 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1252 node _T_1253 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1253 node _T_1254 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1254 node _T_1255 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1255 node _T_1256 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1256 node _T_1257 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1257 node _T_1258 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1258 node _T_1259 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1259 node _T_1260 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1260 node _T_1261 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1262 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1264 = or(hv_10, hg_10) wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[2][2].data[0] node _T_1265 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1265 node _T_1266 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1266 node _T_1267 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1267 node _T_1268 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1268 node _T_1269 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1269 node _T_1270 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1270 node _T_1271 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1271 node _T_1272 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1272 node _T_1273 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1273 node _T_1274 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1274 node _T_1275 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1275 node _T_1276 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1276 node _T_1277 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1277 node _T_1278 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1278 node _T_1279 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1279 node _T_1280 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1280 node _T_1281 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1281 node _T_1282 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1282 node _T_1283 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1283 node _T_1284 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1284 node _T_1285 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1285 node _T_1286 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1286 node _T_1287 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1287 node _T_1288 = eq(sectored_entries[2][2].tag_v, _T_1264) when _T_1288 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1289 = eq(hg_11, UInt<1>(0h0)) node _T_1290 = and(_T_1289, io.sfence.bits.rs1) when _T_1290 : node _T_1291 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1292 = shr(_T_1291, 0) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) node _T_1294 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1295 = and(_T_1293, _T_1294) when _T_1295 : wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[2][3].data[0] node _T_1296 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1296 node _T_1297 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1297 node _T_1298 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1298 node _T_1299 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1299 node _T_1300 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1300 node _T_1301 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1301 node _T_1302 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1302 node _T_1303 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1303 node _T_1304 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1304 node _T_1305 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1305 node _T_1306 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1306 node _T_1307 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1307 node _T_1308 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1308 node _T_1309 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1309 node _T_1310 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1310 node _T_1311 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1311 node _T_1312 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1312 node _T_1313 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1313 node _T_1314 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1314 node _T_1315 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1315 node _T_1316 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1316 node _T_1317 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1317 node _T_1318 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1318 node _T_1319 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1320 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1321 = and(_T_1319, _T_1320) when _T_1321 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node _T_1322 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1323 = shr(_T_1322, 18) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[2][3].data[0] node _T_1325 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1325 node _T_1326 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1326 node _T_1327 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1327 node _T_1328 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1328 node _T_1329 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1329 node _T_1330 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1330 node _T_1331 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1331 node _T_1332 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1332 node _T_1333 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1333 node _T_1334 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1334 node _T_1335 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1335 node _T_1336 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1336 node _T_1337 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1337 node _T_1338 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1338 node _T_1339 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1339 node _T_1340 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1340 node _T_1341 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1341 node _T_1342 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1342 node _T_1343 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1343 node _T_1344 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1344 node _T_1345 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1345 node _T_1346 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1346 node _T_1347 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1347 node _T_1348 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1349 = and(_T_1348, _WIRE_90.fragmented_superpage) when _T_1349 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1350 = eq(hg_11, UInt<1>(0h0)) node _T_1351 = and(_T_1350, io.sfence.bits.rs2) when _T_1351 : wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[2][3].data[0] node _T_1352 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1352 node _T_1353 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1353 node _T_1354 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1354 node _T_1355 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1355 node _T_1356 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1356 node _T_1357 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1357 node _T_1358 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1358 node _T_1359 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1359 node _T_1360 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1360 node _T_1361 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1361 node _T_1362 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1362 node _T_1363 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1363 node _T_1364 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1364 node _T_1365 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1365 node _T_1366 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1366 node _T_1367 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1367 node _T_1368 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1368 node _T_1369 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1369 node _T_1370 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1370 node _T_1371 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1371 node _T_1372 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1372 node _T_1373 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1373 node _T_1374 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1374 node _T_1375 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1376 = eq(_WIRE_92.g, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1378 = or(hv_11, hg_11) wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[2][3].data[0] node _T_1379 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1379 node _T_1380 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1380 node _T_1381 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1381 node _T_1382 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1382 node _T_1383 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1383 node _T_1384 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1384 node _T_1385 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1385 node _T_1386 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1386 node _T_1387 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1387 node _T_1388 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1388 node _T_1389 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1389 node _T_1390 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1390 node _T_1391 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1391 node _T_1392 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1392 node _T_1393 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1393 node _T_1394 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1394 node _T_1395 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1395 node _T_1396 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1396 node _T_1397 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1397 node _T_1398 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1398 node _T_1399 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1399 node _T_1400 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1400 node _T_1401 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1401 node _T_1402 = eq(sectored_entries[2][3].tag_v, _T_1378) when _T_1402 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1403 = eq(hg_12, UInt<1>(0h0)) node _T_1404 = and(_T_1403, io.sfence.bits.rs1) when _T_1404 : node _T_1405 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1406 = shr(_T_1405, 0) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) node _T_1408 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1409 = and(_T_1407, _T_1408) when _T_1409 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[3][0].data[0] node _T_1410 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1410 node _T_1411 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1411 node _T_1412 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1412 node _T_1413 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1413 node _T_1414 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1414 node _T_1415 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1415 node _T_1416 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1416 node _T_1417 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1417 node _T_1418 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1418 node _T_1419 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1419 node _T_1420 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1420 node _T_1421 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1421 node _T_1422 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1422 node _T_1423 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1423 node _T_1424 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1424 node _T_1425 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1425 node _T_1426 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1426 node _T_1427 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1427 node _T_1428 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1428 node _T_1429 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1429 node _T_1430 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1430 node _T_1431 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1431 node _T_1432 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1432 node _T_1433 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1434 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1435 = and(_T_1433, _T_1434) when _T_1435 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node _T_1436 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1437 = shr(_T_1436, 18) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[3][0].data[0] node _T_1439 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1439 node _T_1440 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1440 node _T_1441 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1441 node _T_1442 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1442 node _T_1443 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1443 node _T_1444 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1444 node _T_1445 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1445 node _T_1446 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1446 node _T_1447 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1447 node _T_1448 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1448 node _T_1449 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1449 node _T_1450 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1450 node _T_1451 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1451 node _T_1452 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1452 node _T_1453 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1453 node _T_1454 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1454 node _T_1455 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1455 node _T_1456 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1456 node _T_1457 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1457 node _T_1458 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1458 node _T_1459 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1459 node _T_1460 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1460 node _T_1461 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1461 node _T_1462 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1463 = and(_T_1462, _WIRE_98.fragmented_superpage) when _T_1463 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1464 = eq(hg_12, UInt<1>(0h0)) node _T_1465 = and(_T_1464, io.sfence.bits.rs2) when _T_1465 : wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[3][0].data[0] node _T_1466 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1466 node _T_1467 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1467 node _T_1468 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1468 node _T_1469 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1469 node _T_1470 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1470 node _T_1471 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1471 node _T_1472 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1472 node _T_1473 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1473 node _T_1474 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1474 node _T_1475 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1475 node _T_1476 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1476 node _T_1477 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1477 node _T_1478 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1478 node _T_1479 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1479 node _T_1480 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1480 node _T_1481 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1481 node _T_1482 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1482 node _T_1483 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1483 node _T_1484 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1484 node _T_1485 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1485 node _T_1486 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1486 node _T_1487 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1487 node _T_1488 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1488 node _T_1489 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1490 = eq(_WIRE_100.g, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1492 = or(hv_12, hg_12) wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[3][0].data[0] node _T_1493 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1493 node _T_1494 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1494 node _T_1495 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1495 node _T_1496 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1496 node _T_1497 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1497 node _T_1498 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1498 node _T_1499 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1499 node _T_1500 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1500 node _T_1501 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1501 node _T_1502 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1502 node _T_1503 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1503 node _T_1504 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1504 node _T_1505 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1505 node _T_1506 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1506 node _T_1507 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1507 node _T_1508 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1508 node _T_1509 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1509 node _T_1510 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1510 node _T_1511 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1511 node _T_1512 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1512 node _T_1513 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1513 node _T_1514 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1514 node _T_1515 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1515 node _T_1516 = eq(sectored_entries[3][0].tag_v, _T_1492) when _T_1516 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node hv_13 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_13 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1517 = eq(hg_13, UInt<1>(0h0)) node _T_1518 = and(_T_1517, io.sfence.bits.rs1) when _T_1518 : node _T_1519 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1520 = shr(_T_1519, 0) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1523 = and(_T_1521, _T_1522) when _T_1523 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[3][1].data[0] node _T_1524 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1524 node _T_1525 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1525 node _T_1526 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1526 node _T_1527 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1527 node _T_1528 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1528 node _T_1529 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1529 node _T_1530 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1530 node _T_1531 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1531 node _T_1532 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1532 node _T_1533 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1533 node _T_1534 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1534 node _T_1535 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1535 node _T_1536 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1536 node _T_1537 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1537 node _T_1538 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1538 node _T_1539 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1539 node _T_1540 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1540 node _T_1541 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1541 node _T_1542 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1542 node _T_1543 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1543 node _T_1544 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1544 node _T_1545 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1545 node _T_1546 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1546 node _T_1547 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1548 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1549 = and(_T_1547, _T_1548) when _T_1549 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node _T_1550 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1551 = shr(_T_1550, 18) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[3][1].data[0] node _T_1553 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1553 node _T_1554 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1554 node _T_1555 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1555 node _T_1556 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1556 node _T_1557 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1557 node _T_1558 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1558 node _T_1559 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1559 node _T_1560 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1560 node _T_1561 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1561 node _T_1562 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1562 node _T_1563 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1563 node _T_1564 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1564 node _T_1565 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1565 node _T_1566 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1566 node _T_1567 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1567 node _T_1568 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1568 node _T_1569 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1569 node _T_1570 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1570 node _T_1571 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1571 node _T_1572 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1572 node _T_1573 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1573 node _T_1574 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1574 node _T_1575 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1575 node _T_1576 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1577 = and(_T_1576, _WIRE_106.fragmented_superpage) when _T_1577 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1578 = eq(hg_13, UInt<1>(0h0)) node _T_1579 = and(_T_1578, io.sfence.bits.rs2) when _T_1579 : wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[3][1].data[0] node _T_1580 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1580 node _T_1581 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1581 node _T_1582 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1582 node _T_1583 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1583 node _T_1584 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1584 node _T_1585 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1585 node _T_1586 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1586 node _T_1587 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1587 node _T_1588 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1588 node _T_1589 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1589 node _T_1590 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1590 node _T_1591 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1591 node _T_1592 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1592 node _T_1593 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1593 node _T_1594 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1594 node _T_1595 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1595 node _T_1596 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1596 node _T_1597 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1597 node _T_1598 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1598 node _T_1599 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1599 node _T_1600 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1600 node _T_1601 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1601 node _T_1602 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1602 node _T_1603 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1604 = eq(_WIRE_108.g, UInt<1>(0h0)) node _T_1605 = and(_T_1603, _T_1604) when _T_1605 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1606 = or(hv_13, hg_13) wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[3][1].data[0] node _T_1607 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1607 node _T_1608 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1608 node _T_1609 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1609 node _T_1610 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1610 node _T_1611 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1611 node _T_1612 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1612 node _T_1613 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1613 node _T_1614 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1614 node _T_1615 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1615 node _T_1616 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1616 node _T_1617 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1617 node _T_1618 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1618 node _T_1619 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1619 node _T_1620 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1620 node _T_1621 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1621 node _T_1622 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1622 node _T_1623 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1623 node _T_1624 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1624 node _T_1625 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1625 node _T_1626 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1626 node _T_1627 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1627 node _T_1628 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1628 node _T_1629 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1629 node _T_1630 = eq(sectored_entries[3][1].tag_v, _T_1606) when _T_1630 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node hv_14 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_14 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1631 = eq(hg_14, UInt<1>(0h0)) node _T_1632 = and(_T_1631, io.sfence.bits.rs1) when _T_1632 : node _T_1633 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1634 = shr(_T_1633, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[3][2].data[0] node _T_1638 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1638 node _T_1639 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1639 node _T_1640 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1640 node _T_1641 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1641 node _T_1642 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1642 node _T_1643 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1643 node _T_1644 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1644 node _T_1645 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1645 node _T_1646 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1646 node _T_1647 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1647 node _T_1648 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1648 node _T_1649 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1649 node _T_1650 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1650 node _T_1651 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1651 node _T_1652 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1652 node _T_1653 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1653 node _T_1654 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1654 node _T_1655 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1655 node _T_1656 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1656 node _T_1657 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1657 node _T_1658 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1658 node _T_1659 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1659 node _T_1660 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1660 node _T_1661 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1662 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node _T_1664 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1665 = shr(_T_1664, 18) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[3][2].data[0] node _T_1667 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1667 node _T_1668 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1668 node _T_1669 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1669 node _T_1670 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1670 node _T_1671 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1671 node _T_1672 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1672 node _T_1673 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1673 node _T_1674 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1674 node _T_1675 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1675 node _T_1676 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1676 node _T_1677 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1677 node _T_1678 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1678 node _T_1679 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1679 node _T_1680 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1680 node _T_1681 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1681 node _T_1682 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1682 node _T_1683 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1683 node _T_1684 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1684 node _T_1685 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1685 node _T_1686 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1686 node _T_1687 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1687 node _T_1688 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1688 node _T_1689 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1689 node _T_1690 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1691 = and(_T_1690, _WIRE_114.fragmented_superpage) when _T_1691 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1692 = eq(hg_14, UInt<1>(0h0)) node _T_1693 = and(_T_1692, io.sfence.bits.rs2) when _T_1693 : wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[3][2].data[0] node _T_1694 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1694 node _T_1695 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1695 node _T_1696 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1696 node _T_1697 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1697 node _T_1698 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1698 node _T_1699 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1699 node _T_1700 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1700 node _T_1701 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1701 node _T_1702 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1702 node _T_1703 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1703 node _T_1704 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1704 node _T_1705 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1705 node _T_1706 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1706 node _T_1707 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1707 node _T_1708 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1708 node _T_1709 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1709 node _T_1710 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1710 node _T_1711 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1711 node _T_1712 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1712 node _T_1713 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1713 node _T_1714 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1714 node _T_1715 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1715 node _T_1716 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1716 node _T_1717 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1718 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1719 = and(_T_1717, _T_1718) when _T_1719 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1720 = or(hv_14, hg_14) wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[3][2].data[0] node _T_1721 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1721 node _T_1722 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1722 node _T_1723 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1723 node _T_1724 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1724 node _T_1725 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1725 node _T_1726 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1726 node _T_1727 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1727 node _T_1728 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1728 node _T_1729 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1729 node _T_1730 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1730 node _T_1731 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1731 node _T_1732 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1732 node _T_1733 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1733 node _T_1734 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1734 node _T_1735 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1735 node _T_1736 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1736 node _T_1737 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1737 node _T_1738 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1738 node _T_1739 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1739 node _T_1740 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1740 node _T_1741 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1741 node _T_1742 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1742 node _T_1743 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1743 node _T_1744 = eq(sectored_entries[3][2].tag_v, _T_1720) when _T_1744 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node hv_15 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_15 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_15, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 0) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[3][3].data[0] node _T_1752 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1753 node _T_1754 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1754 node _T_1755 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1755 node _T_1756 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1756 node _T_1757 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1757 node _T_1758 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1758 node _T_1759 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1759 node _T_1760 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1760 node _T_1761 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1761 node _T_1762 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1762 node _T_1763 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1763 node _T_1764 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1764 node _T_1765 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1765 node _T_1766 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1766 node _T_1767 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1767 node _T_1768 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1768 node _T_1769 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1770 node _T_1771 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1772 node _T_1773 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1773 node _T_1774 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1774 node _T_1775 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1776 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1777 = and(_T_1775, _T_1776) when _T_1777 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node _T_1778 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1779 = shr(_T_1778, 18) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[3][3].data[0] node _T_1781 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1781 node _T_1782 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1782 node _T_1783 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1783 node _T_1784 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1784 node _T_1785 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1785 node _T_1786 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1786 node _T_1787 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1787 node _T_1788 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1788 node _T_1789 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1789 node _T_1790 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1790 node _T_1791 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1791 node _T_1792 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1792 node _T_1793 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1793 node _T_1794 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1794 node _T_1795 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1795 node _T_1796 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1796 node _T_1797 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1797 node _T_1798 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1798 node _T_1799 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1799 node _T_1800 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1800 node _T_1801 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1801 node _T_1802 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1802 node _T_1803 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1803 node _T_1804 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1805 = and(_T_1804, _WIRE_122.fragmented_superpage) when _T_1805 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1806 = eq(hg_15, UInt<1>(0h0)) node _T_1807 = and(_T_1806, io.sfence.bits.rs2) when _T_1807 : wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[3][3].data[0] node _T_1808 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1808 node _T_1809 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1809 node _T_1810 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1810 node _T_1811 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1811 node _T_1812 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1812 node _T_1813 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1813 node _T_1814 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1814 node _T_1815 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1815 node _T_1816 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1816 node _T_1817 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1817 node _T_1818 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1818 node _T_1819 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1819 node _T_1820 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1820 node _T_1821 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1821 node _T_1822 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1822 node _T_1823 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1823 node _T_1824 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1824 node _T_1825 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1825 node _T_1826 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1826 node _T_1827 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1827 node _T_1828 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1828 node _T_1829 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1829 node _T_1830 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1830 node _T_1831 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1832 = eq(_WIRE_124.g, UInt<1>(0h0)) node _T_1833 = and(_T_1831, _T_1832) when _T_1833 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1834 = or(hv_15, hg_15) wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[3][3].data[0] node _T_1835 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1835 node _T_1836 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1836 node _T_1837 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1837 node _T_1838 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1838 node _T_1839 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1839 node _T_1840 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1840 node _T_1841 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1841 node _T_1842 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1842 node _T_1843 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1843 node _T_1844 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1844 node _T_1845 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1845 node _T_1846 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1846 node _T_1847 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1847 node _T_1848 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1848 node _T_1849 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1849 node _T_1850 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1850 node _T_1851 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1851 node _T_1852 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1852 node _T_1853 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1853 node _T_1854 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1854 node _T_1855 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1855 node _T_1856 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1856 node _T_1857 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1857 node _T_1858 = eq(sectored_entries[3][3].tag_v, _T_1834) when _T_1858 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node hv_16 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_16 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1859 = eq(hg_16, UInt<1>(0h0)) node _T_1860 = and(_T_1859, io.sfence.bits.rs1) when _T_1860 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_16) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_1861 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1862 = bits(_T_1861, 26, 18) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(ignore, _T_1863) node _T_1865 = and(tagMatch, _T_1864) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_1866 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1867 = bits(_T_1866, 17, 9) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) node _T_1869 = or(ignore_1, _T_1868) node _T_1870 = and(_T_1865, _T_1869) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_1871 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1872 = bits(_T_1871, 8, 0) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) node _T_1874 = or(ignore_2, _T_1873) node _T_1875 = and(_T_1870, _T_1874) when _T_1875 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_1876 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1877 = shr(_T_1876, 18) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, superpage_entries[0].data[0] node _T_1879 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1879 node _T_1880 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1880 node _T_1881 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1881 node _T_1882 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1882 node _T_1883 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1883 node _T_1884 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1884 node _T_1885 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1885 node _T_1886 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1886 node _T_1887 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1887 node _T_1888 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1888 node _T_1889 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1889 node _T_1890 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1890 node _T_1891 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1891 node _T_1892 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1892 node _T_1893 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1893 node _T_1894 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1894 node _T_1895 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1895 node _T_1896 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1896 node _T_1897 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1897 node _T_1898 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1898 node _T_1899 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1899 node _T_1900 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1900 node _T_1901 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1901 node _T_1902 = eq(superpage_entries[0].tag_v, hv_16) node _T_1903 = and(_T_1902, _WIRE_128.fragmented_superpage) when _T_1903 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1904 = eq(hg_16, UInt<1>(0h0)) node _T_1905 = and(_T_1904, io.sfence.bits.rs2) when _T_1905 : wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, superpage_entries[0].data[0] node _T_1906 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1906 node _T_1907 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1907 node _T_1908 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1908 node _T_1909 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1909 node _T_1910 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1910 node _T_1911 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1911 node _T_1912 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1912 node _T_1913 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1913 node _T_1914 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1914 node _T_1915 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1915 node _T_1916 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1916 node _T_1917 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1917 node _T_1918 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1918 node _T_1919 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1919 node _T_1920 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1920 node _T_1921 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1921 node _T_1922 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1922 node _T_1923 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1923 node _T_1924 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1924 node _T_1925 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1925 node _T_1926 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1926 node _T_1927 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1927 node _T_1928 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1928 node _T_1929 = eq(superpage_entries[0].tag_v, hv_16) node _T_1930 = eq(_WIRE_130.g, UInt<1>(0h0)) node _T_1931 = and(_T_1929, _T_1930) when _T_1931 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1932 = or(hv_16, hg_16) wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, superpage_entries[0].data[0] node _T_1933 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1933 node _T_1934 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1934 node _T_1935 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1935 node _T_1936 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1936 node _T_1937 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1937 node _T_1938 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1938 node _T_1939 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1939 node _T_1940 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1940 node _T_1941 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1941 node _T_1942 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1942 node _T_1943 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1943 node _T_1944 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1944 node _T_1945 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1945 node _T_1946 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1946 node _T_1947 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1947 node _T_1948 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1948 node _T_1949 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1949 node _T_1950 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1950 node _T_1951 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1951 node _T_1952 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1952 node _T_1953 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1953 node _T_1954 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1954 node _T_1955 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1955 node _T_1956 = eq(superpage_entries[0].tag_v, _T_1932) when _T_1956 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_17 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_17 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1957 = eq(hg_17, UInt<1>(0h0)) node _T_1958 = and(_T_1957, io.sfence.bits.rs1) when _T_1958 : node _tagMatch_T_1 = eq(special_entry.tag_v, hv_17) node tagMatch_1 = and(special_entry.valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_1959 = xor(special_entry.tag_vpn, vpn) node _T_1960 = bits(_T_1959, 26, 18) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) node _T_1962 = or(ignore_3, _T_1961) node _T_1963 = and(tagMatch_1, _T_1962) node _ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_1964 = xor(special_entry.tag_vpn, vpn) node _T_1965 = bits(_T_1964, 17, 9) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = or(ignore_4, _T_1966) node _T_1968 = and(_T_1963, _T_1967) node _ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h0)) node _T_1969 = xor(special_entry.tag_vpn, vpn) node _T_1970 = bits(_T_1969, 8, 0) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(ignore_5, _T_1971) node _T_1973 = and(_T_1968, _T_1972) when _T_1973 : connect special_entry.valid[0], UInt<1>(0h0) node _T_1974 = xor(special_entry.tag_vpn, vpn) node _T_1975 = shr(_T_1974, 18) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, special_entry.data[0] node _T_1977 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1977 node _T_1978 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1978 node _T_1979 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1979 node _T_1980 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1980 node _T_1981 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1981 node _T_1982 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1982 node _T_1983 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1983 node _T_1984 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1984 node _T_1985 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1985 node _T_1986 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1986 node _T_1987 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1987 node _T_1988 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1988 node _T_1989 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1989 node _T_1990 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1990 node _T_1991 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1991 node _T_1992 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1992 node _T_1993 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1993 node _T_1994 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1994 node _T_1995 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1995 node _T_1996 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1996 node _T_1997 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1997 node _T_1998 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1998 node _T_1999 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1999 node _T_2000 = eq(special_entry.tag_v, hv_17) node _T_2001 = and(_T_2000, _WIRE_134.fragmented_superpage) when _T_2001 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2002 = eq(hg_17, UInt<1>(0h0)) node _T_2003 = and(_T_2002, io.sfence.bits.rs2) when _T_2003 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, special_entry.data[0] node _T_2004 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_2004 node _T_2005 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_2005 node _T_2006 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_2006 node _T_2007 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_2007 node _T_2008 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_2008 node _T_2009 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_2009 node _T_2010 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_2010 node _T_2011 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_2011 node _T_2012 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_2012 node _T_2013 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_2013 node _T_2014 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_2014 node _T_2015 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_2015 node _T_2016 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_2016 node _T_2017 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_2017 node _T_2018 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_2018 node _T_2019 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_2019 node _T_2020 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_2020 node _T_2021 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_2021 node _T_2022 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_2022 node _T_2023 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_2023 node _T_2024 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_2024 node _T_2025 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_2025 node _T_2026 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_2026 node _T_2027 = eq(special_entry.tag_v, hv_17) node _T_2028 = eq(_WIRE_136.g, UInt<1>(0h0)) node _T_2029 = and(_T_2027, _T_2028) when _T_2029 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2030 = or(hv_17, hg_17) wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, special_entry.data[0] node _T_2031 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_2031 node _T_2032 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_2032 node _T_2033 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_2033 node _T_2034 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_2034 node _T_2035 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_2035 node _T_2036 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_2036 node _T_2037 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_2037 node _T_2038 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_2038 node _T_2039 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_2039 node _T_2040 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_2040 node _T_2041 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_2041 node _T_2042 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_2042 node _T_2043 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_2043 node _T_2044 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_2044 node _T_2045 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_2045 node _T_2046 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_2046 node _T_2047 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_2047 node _T_2048 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_2048 node _T_2049 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_2049 node _T_2050 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_2050 node _T_2051 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_2051 node _T_2052 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_2052 node _T_2053 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_2053 node _T_2054 = eq(special_entry.tag_v, _T_2030) when _T_2054 : connect special_entry.valid[0], UInt<1>(0h0) node _T_2055 = and(io.req.ready, io.req.valid) node _T_2056 = and(_T_2055, vsatp_mode_mismatch) when _T_2056 : wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][0].data[0] node _T_2057 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_2057 node _T_2058 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_2058 node _T_2059 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_2059 node _T_2060 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_2060 node _T_2061 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_2061 node _T_2062 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_2062 node _T_2063 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_2063 node _T_2064 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_2064 node _T_2065 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_2065 node _T_2066 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_2066 node _T_2067 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_2067 node _T_2068 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_2068 node _T_2069 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_2069 node _T_2070 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_2070 node _T_2071 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_2071 node _T_2072 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_2072 node _T_2073 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_2073 node _T_2074 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_2074 node _T_2075 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_2075 node _T_2076 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_2076 node _T_2077 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_2077 node _T_2078 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_2078 node _T_2079 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_2079 node _T_2080 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_2080 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][1].data[0] node _T_2081 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_2081 node _T_2082 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_2082 node _T_2083 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_2083 node _T_2084 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_2084 node _T_2085 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_2085 node _T_2086 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_2086 node _T_2087 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_2087 node _T_2088 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_2088 node _T_2089 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_2089 node _T_2090 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_2090 node _T_2091 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_2091 node _T_2092 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_2092 node _T_2093 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_2093 node _T_2094 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_2094 node _T_2095 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_2095 node _T_2096 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_2096 node _T_2097 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_2097 node _T_2098 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_2098 node _T_2099 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_2099 node _T_2100 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_2100 node _T_2101 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_2101 node _T_2102 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_2102 node _T_2103 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_2103 node _T_2104 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_2104 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][2].data[0] node _T_2105 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_2105 node _T_2106 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_2106 node _T_2107 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_2107 node _T_2108 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_2108 node _T_2109 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_2109 node _T_2110 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_2110 node _T_2111 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_2111 node _T_2112 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_2112 node _T_2113 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_2113 node _T_2114 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_2114 node _T_2115 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_2115 node _T_2116 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_2116 node _T_2117 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_2117 node _T_2118 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_2118 node _T_2119 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_2119 node _T_2120 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_2120 node _T_2121 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_2121 node _T_2122 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_2122 node _T_2123 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_2123 node _T_2124 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_2124 node _T_2125 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_2125 node _T_2126 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_2126 node _T_2127 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_2127 node _T_2128 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_2128 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][3].data[0] node _T_2129 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_2129 node _T_2130 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_2130 node _T_2131 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_2131 node _T_2132 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_2132 node _T_2133 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_2133 node _T_2134 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_2134 node _T_2135 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_2135 node _T_2136 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_2136 node _T_2137 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_2137 node _T_2138 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_2138 node _T_2139 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_2139 node _T_2140 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_2140 node _T_2141 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2141 node _T_2142 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2142 node _T_2143 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2143 node _T_2144 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2144 node _T_2145 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2145 node _T_2146 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2146 node _T_2147 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2147 node _T_2148 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2148 node _T_2149 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2149 node _T_2150 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2150 node _T_2151 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2151 node _T_2152 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_2152 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[1][0].data[0] node _T_2153 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2153 node _T_2154 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2154 node _T_2155 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2155 node _T_2156 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2156 node _T_2157 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2157 node _T_2158 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2158 node _T_2159 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2159 node _T_2160 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2160 node _T_2161 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2161 node _T_2162 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2162 node _T_2163 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2163 node _T_2164 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2164 node _T_2165 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2165 node _T_2166 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2166 node _T_2167 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2167 node _T_2168 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2168 node _T_2169 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2169 node _T_2170 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2170 node _T_2171 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2171 node _T_2172 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2172 node _T_2173 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2173 node _T_2174 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2174 node _T_2175 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2175 node _T_2176 = eq(sectored_entries[1][0].tag_v, UInt<1>(0h1)) when _T_2176 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[1][1].data[0] node _T_2177 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2177 node _T_2178 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2178 node _T_2179 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2179 node _T_2180 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2180 node _T_2181 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2181 node _T_2182 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2182 node _T_2183 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2183 node _T_2184 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2184 node _T_2185 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2185 node _T_2186 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2186 node _T_2187 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2187 node _T_2188 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2188 node _T_2189 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2189 node _T_2190 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2190 node _T_2191 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2191 node _T_2192 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2192 node _T_2193 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2193 node _T_2194 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2194 node _T_2195 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2195 node _T_2196 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2196 node _T_2197 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2197 node _T_2198 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2198 node _T_2199 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2199 node _T_2200 = eq(sectored_entries[1][1].tag_v, UInt<1>(0h1)) when _T_2200 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[1][2].data[0] node _T_2201 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2201 node _T_2202 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2202 node _T_2203 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2203 node _T_2204 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2204 node _T_2205 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2205 node _T_2206 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2206 node _T_2207 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2207 node _T_2208 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2208 node _T_2209 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2209 node _T_2210 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2210 node _T_2211 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2211 node _T_2212 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2212 node _T_2213 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2213 node _T_2214 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2214 node _T_2215 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2215 node _T_2216 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2216 node _T_2217 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2217 node _T_2218 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2218 node _T_2219 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2219 node _T_2220 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2220 node _T_2221 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2221 node _T_2222 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2222 node _T_2223 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2223 node _T_2224 = eq(sectored_entries[1][2].tag_v, UInt<1>(0h1)) when _T_2224 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[1][3].data[0] node _T_2225 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2225 node _T_2226 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2226 node _T_2227 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2227 node _T_2228 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2228 node _T_2229 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2229 node _T_2230 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2230 node _T_2231 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2231 node _T_2232 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2232 node _T_2233 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2233 node _T_2234 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2234 node _T_2235 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2235 node _T_2236 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2236 node _T_2237 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2237 node _T_2238 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2238 node _T_2239 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2239 node _T_2240 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2240 node _T_2241 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2241 node _T_2242 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2242 node _T_2243 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2243 node _T_2244 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2244 node _T_2245 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2245 node _T_2246 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2246 node _T_2247 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2247 node _T_2248 = eq(sectored_entries[1][3].tag_v, UInt<1>(0h1)) when _T_2248 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[2][0].data[0] node _T_2249 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2249 node _T_2250 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2250 node _T_2251 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2251 node _T_2252 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2252 node _T_2253 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2253 node _T_2254 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2254 node _T_2255 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2255 node _T_2256 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2256 node _T_2257 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2257 node _T_2258 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2258 node _T_2259 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2259 node _T_2260 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2260 node _T_2261 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2261 node _T_2262 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2262 node _T_2263 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2263 node _T_2264 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2264 node _T_2265 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2265 node _T_2266 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2266 node _T_2267 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2267 node _T_2268 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2268 node _T_2269 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2269 node _T_2270 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2270 node _T_2271 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2271 node _T_2272 = eq(sectored_entries[2][0].tag_v, UInt<1>(0h1)) when _T_2272 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[2][1].data[0] node _T_2273 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2273 node _T_2274 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2274 node _T_2275 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2275 node _T_2276 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2276 node _T_2277 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2277 node _T_2278 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2278 node _T_2279 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2279 node _T_2280 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2280 node _T_2281 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2281 node _T_2282 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2282 node _T_2283 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2283 node _T_2284 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2284 node _T_2285 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2285 node _T_2286 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2286 node _T_2287 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2287 node _T_2288 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2288 node _T_2289 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2289 node _T_2290 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2290 node _T_2291 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2291 node _T_2292 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2292 node _T_2293 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2293 node _T_2294 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2294 node _T_2295 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2295 node _T_2296 = eq(sectored_entries[2][1].tag_v, UInt<1>(0h1)) when _T_2296 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[2][2].data[0] node _T_2297 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2297 node _T_2298 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2298 node _T_2299 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2299 node _T_2300 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2300 node _T_2301 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2301 node _T_2302 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2302 node _T_2303 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2303 node _T_2304 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2304 node _T_2305 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2305 node _T_2306 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2306 node _T_2307 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2307 node _T_2308 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2308 node _T_2309 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2309 node _T_2310 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2310 node _T_2311 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2311 node _T_2312 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2312 node _T_2313 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2313 node _T_2314 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2314 node _T_2315 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2315 node _T_2316 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2316 node _T_2317 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2317 node _T_2318 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2318 node _T_2319 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2319 node _T_2320 = eq(sectored_entries[2][2].tag_v, UInt<1>(0h1)) when _T_2320 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[2][3].data[0] node _T_2321 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2321 node _T_2322 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2322 node _T_2323 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2323 node _T_2324 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2324 node _T_2325 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2325 node _T_2326 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2326 node _T_2327 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2327 node _T_2328 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2328 node _T_2329 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2329 node _T_2330 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2330 node _T_2331 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2331 node _T_2332 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2332 node _T_2333 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2333 node _T_2334 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2334 node _T_2335 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2335 node _T_2336 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2336 node _T_2337 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2337 node _T_2338 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2338 node _T_2339 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2339 node _T_2340 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2340 node _T_2341 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2341 node _T_2342 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2342 node _T_2343 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2343 node _T_2344 = eq(sectored_entries[2][3].tag_v, UInt<1>(0h1)) when _T_2344 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[3][0].data[0] node _T_2345 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2345 node _T_2346 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2346 node _T_2347 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2347 node _T_2348 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2348 node _T_2349 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2349 node _T_2350 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2350 node _T_2351 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2351 node _T_2352 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2352 node _T_2353 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2353 node _T_2354 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2354 node _T_2355 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2355 node _T_2356 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2356 node _T_2357 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2357 node _T_2358 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2358 node _T_2359 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2359 node _T_2360 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2360 node _T_2361 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2361 node _T_2362 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2362 node _T_2363 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2363 node _T_2364 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2364 node _T_2365 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2365 node _T_2366 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2366 node _T_2367 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2367 node _T_2368 = eq(sectored_entries[3][0].tag_v, UInt<1>(0h1)) when _T_2368 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[3][1].data[0] node _T_2369 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2369 node _T_2370 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2370 node _T_2371 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2371 node _T_2372 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2372 node _T_2373 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2373 node _T_2374 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2374 node _T_2375 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2375 node _T_2376 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2376 node _T_2377 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2377 node _T_2378 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2378 node _T_2379 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2379 node _T_2380 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2380 node _T_2381 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2381 node _T_2382 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2382 node _T_2383 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2383 node _T_2384 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2384 node _T_2385 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2385 node _T_2386 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2386 node _T_2387 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2387 node _T_2388 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2388 node _T_2389 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2389 node _T_2390 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2390 node _T_2391 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2391 node _T_2392 = eq(sectored_entries[3][1].tag_v, UInt<1>(0h1)) when _T_2392 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[3][2].data[0] node _T_2393 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2393 node _T_2394 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2394 node _T_2395 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2395 node _T_2396 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2396 node _T_2397 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2397 node _T_2398 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2398 node _T_2399 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2399 node _T_2400 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2400 node _T_2401 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2401 node _T_2402 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2402 node _T_2403 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2403 node _T_2404 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2404 node _T_2405 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2405 node _T_2406 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2406 node _T_2407 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2407 node _T_2408 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2408 node _T_2409 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2409 node _T_2410 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2410 node _T_2411 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2411 node _T_2412 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2412 node _T_2413 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2413 node _T_2414 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2414 node _T_2415 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2415 node _T_2416 = eq(sectored_entries[3][2].tag_v, UInt<1>(0h1)) when _T_2416 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[3][3].data[0] node _T_2417 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2417 node _T_2418 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2418 node _T_2419 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2419 node _T_2420 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2420 node _T_2421 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2421 node _T_2422 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2422 node _T_2423 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2423 node _T_2424 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2424 node _T_2425 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2425 node _T_2426 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2426 node _T_2427 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2427 node _T_2428 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2428 node _T_2429 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2429 node _T_2430 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2430 node _T_2431 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2431 node _T_2432 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2432 node _T_2433 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2433 node _T_2434 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2434 node _T_2435 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2435 node _T_2436 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2436 node _T_2437 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2437 node _T_2438 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2438 node _T_2439 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2439 node _T_2440 = eq(sectored_entries[3][3].tag_v, UInt<1>(0h1)) when _T_2440 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, superpage_entries[0].data[0] node _T_2441 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2441 node _T_2442 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2442 node _T_2443 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2443 node _T_2444 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2444 node _T_2445 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2445 node _T_2446 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2446 node _T_2447 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2447 node _T_2448 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2448 node _T_2449 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2449 node _T_2450 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2450 node _T_2451 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2451 node _T_2452 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2452 node _T_2453 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2453 node _T_2454 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2454 node _T_2455 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2455 node _T_2456 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2456 node _T_2457 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2457 node _T_2458 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2458 node _T_2459 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2459 node _T_2460 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2460 node _T_2461 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2461 node _T_2462 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2462 node _T_2463 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2463 node _T_2464 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_2464 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, special_entry.data[0] node _T_2465 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2465 node _T_2466 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2466 node _T_2467 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2467 node _T_2468 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2468 node _T_2469 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2469 node _T_2470 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2470 node _T_2471 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2471 node _T_2472 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2472 node _T_2473 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2473 node _T_2474 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2474 node _T_2475 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2475 node _T_2476 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2476 node _T_2477 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2477 node _T_2478 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2478 node _T_2479 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2479 node _T_2480 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2480 node _T_2481 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2481 node _T_2482 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2482 node _T_2483 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2483 node _T_2484 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2484 node _T_2485 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2485 node _T_2486 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2486 node _T_2487 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2487 node _T_2488 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_2488 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_2489 = asUInt(reset) node _T_2490 = or(multipleHits, _T_2489) when _T_2490 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[1][0].valid[0], UInt<1>(0h0) connect sectored_entries[1][1].valid[0], UInt<1>(0h0) connect sectored_entries[1][2].valid[0], UInt<1>(0h0) connect sectored_entries[1][3].valid[0], UInt<1>(0h0) connect sectored_entries[2][0].valid[0], UInt<1>(0h0) connect sectored_entries[2][1].valid[0], UInt<1>(0h0) connect sectored_entries[2][2].valid[0], UInt<1>(0h0) connect sectored_entries[2][3].valid[0], UInt<1>(0h0) connect sectored_entries[3][0].valid[0], UInt<1>(0h0) connect sectored_entries[3][1].valid[0], UInt<1>(0h0) connect sectored_entries[3][2].valid[0], UInt<1>(0h0) connect sectored_entries[3][3].valid[0], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_2491 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_2492 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_2493 = and(io.ptw.req.valid, _T_2492) node _T_2494 = eq(state, UInt<2>(0h3)) node _T_2495 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2496 = and(io.sfence.valid, _T_2495) node _T_2497 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2498 = and(_T_2496, _T_2497) node _T_2499 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2500 = and(io.sfence.valid, _T_2499) node _T_2501 = and(_T_2500, io.sfence.bits.rs2) node _T_2502 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2503 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2504 = and(_T_2502, _T_2503) node _T_2505 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2506 = and(_T_2505, io.sfence.bits.rs2)

module DTLB_5( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 | _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 | _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 | _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 | _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 | _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 | _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 | _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 | _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 | _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {|hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 | _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 | _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 | sector_hits_1 | sector_hits_2 | sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill | ~io_ptw_resp_bits_homogeneous_0 | io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 | ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill | _GEN_63 | ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill | _GEN_63 | ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill | _GEN_63 | ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill | _GEN_63 | ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill | _GEN_63 | ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill | _GEN_63 | ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill | _GEN_63 | ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill | _GEN_63 | ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits | reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 | special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_49 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_5 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_5 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_50 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_51 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_52 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_53 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_54 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_55 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_39 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_39 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_39( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_39 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_12 : input clock : Clock input reset : Reset output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst queue of Queue64_TLBundleA_a32d256s5k3z4u_4 connect queue.clock, clock connect queue.reset, reset inst release_ready_cycle_q of Queue64_UInt64_8 connect release_ready_cycle_q.clock, clock connect release_ready_cycle_q.reset, reset node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles) node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1) connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1 connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt connect queue.io.enq.bits.data, io.enq.bits.data connect queue.io.enq.bits.mask, io.enq.bits.mask connect queue.io.enq.bits.address, io.enq.bits.address connect queue.io.enq.bits.source, io.enq.bits.source connect queue.io.enq.bits.size, io.enq.bits.size connect queue.io.enq.bits.param, io.enq.bits.param connect queue.io.enq.bits.opcode, io.enq.bits.opcode connect io.deq.bits, queue.io.deq.bits node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid) connect queue.io.enq.valid, _queue_io_enq_valid_T node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid) connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready) connect io.enq.ready, _io_enq_ready_T node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle) node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T) node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready) connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1 node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid) node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T) connect io.deq.valid, _io_deq_valid_T_1

module LatencyInjectionQueue_12( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14] input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [31:0] io_enq_bits_address, // @[LatencyInjectionQueue.scala:10:14] input [31:0] io_enq_bits_mask, // @[LatencyInjectionQueue.scala:10:14] input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [2:0] io_deq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] output [2:0] io_deq_bits_param, // @[LatencyInjectionQueue.scala:10:14] output [3:0] io_deq_bits_size, // @[LatencyInjectionQueue.scala:10:14] output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [31:0] io_deq_bits_address, // @[LatencyInjectionQueue.scala:10:14] output [31:0] io_deq_bits_mask, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data, // @[LatencyInjectionQueue.scala:10:14] output io_deq_bits_corrupt // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt = 1'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [2:0] io_enq_bits_param = 3'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :16:26, :17:26, :18:21] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :17:26, :18:21, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue64_TLBundleA_a32d256s5k3z4u_4 queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_address (io_enq_bits_address_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_mask (io_enq_bits_mask_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode_0), .io_deq_bits_param (io_deq_bits_param_0), .io_deq_bits_size (io_deq_bits_size_0), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_address (io_deq_bits_address_0), .io_deq_bits_mask (io_deq_bits_mask_0), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt_0) ); // @[LatencyInjectionQueue.scala:18:21] Queue64_UInt64_8 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_251 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_507 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_251( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_507 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_322 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_66 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_322( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_66 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_26 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_26( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x5 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[5], out : { sync : UInt<1>[5]}} wire nodeIn : UInt<1>[5] invalidate nodeIn[0] invalidate nodeIn[1] invalidate nodeIn[2] invalidate nodeIn[3] invalidate nodeIn[4] wire nodeOut : { sync : UInt<1>[5]} invalidate nodeOut.sync[0] invalidate nodeOut.sync[1] invalidate nodeOut.sync[2] invalidate nodeOut.sync[3] invalidate nodeOut.sync[4] connect auto.out, nodeOut connect nodeIn, auto.in node lo = cat(nodeIn[1], nodeIn[0]) node hi_hi = cat(nodeIn[4], nodeIn[3]) node hi = cat(hi_hi, nodeIn[2]) node _T = cat(hi, lo) inst reg of AsyncResetRegVec_w5_i0 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, _T connect reg.io.en, UInt<1>(0h1) node _T_1 = bits(reg.io.q, 0, 0) node _T_2 = bits(reg.io.q, 1, 1) node _T_3 = bits(reg.io.q, 2, 2) node _T_4 = bits(reg.io.q, 3, 3) node _T_5 = bits(reg.io.q, 4, 4) connect nodeOut.sync[0], _T_1 connect nodeOut.sync[1], _T_2 connect nodeOut.sync[2], _T_3 connect nodeOut.sync[3], _T_4 connect nodeOut.sync[4], _T_5

module IntSyncCrossingSource_n1x5( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_2, // @[LazyModuleImp.scala:107:25] output auto_out_sync_3, // @[LazyModuleImp.scala:107:25] output auto_out_sync_4 // @[LazyModuleImp.scala:107:25] ); wire [4:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire [1:0] lo = 2'h0; // @[Crossing.scala:45:36] wire [1:0] hi_hi = 2'h0; // @[Crossing.scala:45:36] wire [2:0] hi = 3'h0; // @[Crossing.scala:45:36] wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_1 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_2 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_3 = 1'h0; // @[Crossing.scala:41:9] wire auto_in_4 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_2 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_3 = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_4 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire nodeOut_sync_2; // @[MixedNode.scala:542:17] wire nodeOut_sync_3; // @[MixedNode.scala:542:17] wire nodeOut_sync_4; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] wire auto_out_sync_2_0; // @[Crossing.scala:41:9] wire auto_out_sync_3_0; // @[Crossing.scala:41:9] wire auto_out_sync_4_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign auto_out_sync_2_0 = nodeOut_sync_2; // @[Crossing.scala:41:9] assign auto_out_sync_3_0 = nodeOut_sync_3; // @[Crossing.scala:41:9] assign auto_out_sync_4_0 = nodeOut_sync_4; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_2 = _reg_io_q[2]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_3 = _reg_io_q[3]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_4 = _reg_io_q[4]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w5_i0 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_2 = auto_out_sync_2_0; // @[Crossing.scala:41:9] assign auto_out_sync_3 = auto_out_sync_3_0; // @[Crossing.scala:41:9] assign auto_out_sync_4 = auto_out_sync_4_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a12d64s10k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a12d64s10k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [11:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [11:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [11:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_125 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_126 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module GenericDeserializer_TLBeatw88_f32_1 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}, busy : UInt<1>} reg data : UInt<32>[2], clock regreset beat : UInt<2>, clock, reset, UInt<2>(0h0) node _io_in_ready_T = neq(beat, UInt<2>(0h2)) node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = eq(beat, UInt<2>(0h2)) node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 node _io_out_bits_T = cat(data[1], data[0]) node _io_out_bits_T_1 = cat(io.in.bits.flit, _io_out_bits_T) wire _io_out_bits_WIRE : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>} wire _io_out_bits_WIRE_1 : UInt<88> connect _io_out_bits_WIRE_1, _io_out_bits_T_1 node _io_out_bits_T_2 = bits(_io_out_bits_WIRE_1, 0, 0) connect _io_out_bits_WIRE.tail, _io_out_bits_T_2 node _io_out_bits_T_3 = bits(_io_out_bits_WIRE_1, 1, 1) connect _io_out_bits_WIRE.head, _io_out_bits_T_3 node _io_out_bits_T_4 = bits(_io_out_bits_WIRE_1, 87, 2) connect _io_out_bits_WIRE.payload, _io_out_bits_T_4 connect io.out.bits, _io_out_bits_WIRE node _T = and(io.in.ready, io.in.valid) when _T : node _beat_T = eq(beat, UInt<2>(0h2)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = neq(beat, UInt<2>(0h2)) when _T_1 : node _T_2 = bits(beat, 0, 0) connect data[_T_2], io.in.bits.flit node _io_busy_T = neq(beat, UInt<1>(0h0)) connect io.busy, _io_busy_T

module GenericDeserializer_TLBeatw88_f32_1( // @[Serdes.scala:37:7] input clock, // @[Serdes.scala:37:7] input reset, // @[Serdes.scala:37:7] output io_in_ready, // @[Serdes.scala:39:14] input io_in_valid, // @[Serdes.scala:39:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:39:14] input io_out_ready, // @[Serdes.scala:39:14] output io_out_valid, // @[Serdes.scala:39:14] output [85:0] io_out_bits_payload, // @[Serdes.scala:39:14] output io_out_bits_head, // @[Serdes.scala:39:14] output io_out_bits_tail, // @[Serdes.scala:39:14] output io_busy // @[Serdes.scala:39:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:37:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:37:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:37:7] wire _io_in_ready_T_1; // @[Serdes.scala:51:31] wire _io_out_valid_T_1; // @[Serdes.scala:52:31] wire [85:0] _io_out_bits_WIRE_payload; // @[Serdes.scala:56:47] wire _io_out_bits_WIRE_head; // @[Serdes.scala:56:47] wire _io_out_bits_WIRE_tail; // @[Serdes.scala:56:47] wire _io_busy_T; // @[Serdes.scala:68:19] wire io_in_ready_0; // @[Serdes.scala:37:7] wire [85:0] io_out_bits_payload_0; // @[Serdes.scala:37:7] wire io_out_bits_head_0; // @[Serdes.scala:37:7] wire io_out_bits_tail_0; // @[Serdes.scala:37:7] wire io_out_valid_0; // @[Serdes.scala:37:7] wire io_busy_0; // @[Serdes.scala:37:7] reg [31:0] data_0; // @[Serdes.scala:48:17] reg [31:0] data_1; // @[Serdes.scala:48:17] reg [1:0] beat; // @[Serdes.scala:49:21] wire _io_in_ready_T = beat != 2'h2; // @[Serdes.scala:49:21, :51:39] assign _io_in_ready_T_1 = io_out_ready_0 | _io_in_ready_T; // @[Serdes.scala:37:7, :51:{31,39}] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:37:7, :51:31] wire _GEN = beat == 2'h2; // @[Serdes.scala:49:21, :52:39] wire _io_out_valid_T; // @[Serdes.scala:52:39] assign _io_out_valid_T = _GEN; // @[Serdes.scala:52:39] wire _beat_T; // @[Serdes.scala:60:22] assign _beat_T = _GEN; // @[Serdes.scala:52:39, :60:22] assign _io_out_valid_T_1 = io_in_valid_0 & _io_out_valid_T; // @[Serdes.scala:37:7, :52:{31,39}] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:37:7, :52:31] wire [63:0] _io_out_bits_T = {data_1, data_0}; // @[Serdes.scala:48:17, :56:31] wire [95:0] _io_out_bits_T_1 = {io_in_bits_flit_0, _io_out_bits_T}; // @[Serdes.scala:37:7, :56:{8,31}] wire [85:0] _io_out_bits_T_4; // @[Serdes.scala:56:47] assign io_out_bits_payload_0 = _io_out_bits_WIRE_payload; // @[Serdes.scala:37:7, :56:47] wire _io_out_bits_T_3; // @[Serdes.scala:56:47] assign io_out_bits_head_0 = _io_out_bits_WIRE_head; // @[Serdes.scala:37:7, :56:47] wire _io_out_bits_T_2; // @[Serdes.scala:56:47] assign io_out_bits_tail_0 = _io_out_bits_WIRE_tail; // @[Serdes.scala:37:7, :56:47] wire [87:0] _io_out_bits_WIRE_1 = _io_out_bits_T_1[87:0]; // @[Serdes.scala:56:{8,47}] assign _io_out_bits_T_2 = _io_out_bits_WIRE_1[0]; // @[Serdes.scala:56:47] assign _io_out_bits_WIRE_tail = _io_out_bits_T_2; // @[Serdes.scala:56:47] assign _io_out_bits_T_3 = _io_out_bits_WIRE_1[1]; // @[Serdes.scala:56:47] assign _io_out_bits_WIRE_head = _io_out_bits_T_3; // @[Serdes.scala:56:47] assign _io_out_bits_T_4 = _io_out_bits_WIRE_1[87:2]; // @[Serdes.scala:56:47] assign _io_out_bits_WIRE_payload = _io_out_bits_T_4; // @[Serdes.scala:56:47] wire [2:0] _beat_T_1 = {1'h0, beat} + 3'h1; // @[Serdes.scala:49:21, :60:53] wire [1:0] _beat_T_2 = _beat_T_1[1:0]; // @[Serdes.scala:60:53] wire [1:0] _beat_T_3 = _beat_T ? 2'h0 : _beat_T_2; // @[Serdes.scala:60:{16,22,53}] assign _io_busy_T = |beat; // @[Serdes.scala:49:21, :68:19] assign io_busy_0 = _io_busy_T; // @[Serdes.scala:37:7, :68:19] wire _T = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Serdes.scala:37:7] if (~_T | _GEN | beat[0]) begin // @[Decoupled.scala:51:35] end else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47] data_0 <= io_in_bits_flit_0; // @[Serdes.scala:37:7, :48:17] if (~_T | _GEN | ~(beat[0])) begin // @[Decoupled.scala:51:35] end else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47] data_1 <= io_in_bits_flit_0; // @[Serdes.scala:37:7, :48:17] if (reset) // @[Serdes.scala:37:7] beat <= 2'h0; // @[Serdes.scala:49:21] else if (_T) // @[Decoupled.scala:51:35] beat <= _beat_T_3; // @[Serdes.scala:49:21, :60:16] always @(posedge) assign io_in_ready = io_in_ready_0; // @[Serdes.scala:37:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:37:7] assign io_out_bits_payload = io_out_bits_payload_0; // @[Serdes.scala:37:7] assign io_out_bits_head = io_out_bits_head_0; // @[Serdes.scala:37:7] assign io_out_bits_tail = io_out_bits_tail_0; // @[Serdes.scala:37:7] assign io_busy = io_busy_0; // @[Serdes.scala:37:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_489 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_233 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_489( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_233 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_49 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_99 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_100 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_212 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_212( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_85 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_24 = shr(io.in.a.bits.source, 2) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_374 = shr(io.in.a.bits.source, 2) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_686 = shr(io.in.a.bits.source, 2) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_783 = shr(io.in.a.bits.source, 2) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_171 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<2>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<2>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<2>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<2>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<2>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<2>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<2>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<2>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<2>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<2>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_172 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<2>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_173 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_174 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_85( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79] wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77] wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain : output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_3 : { sync : UInt<1>[2]}, int_in_clock_xing_out_2 : { sync : UInt<1>[2]}, int_in_clock_xing_out_1 : { sync : UInt<1>[2]}, int_in_clock_xing_out_0 : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} input tick : UInt<1> output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst clint of CLINT connect clint.clock, childClock connect clint.reset, childReset inst intsource of IntSyncCrossingSource_n1x2 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x2_1 connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsource_2 of IntSyncCrossingSource_n1x2_2 connect intsource_2.clock, childClock connect intsource_2.reset, childReset inst intsource_3 of IntSyncCrossingSource_n1x2_3 connect intsource_3.clock, childClock connect intsource_3.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[2]} invalidate intInClockXingOut_1.sync[0] invalidate intInClockXingOut_1.sync[1] wire intInClockXingIn_1 : { sync : UInt<1>[2]} invalidate intInClockXingIn_1.sync[0] invalidate intInClockXingIn_1.sync[1] connect intInClockXingOut_1, intInClockXingIn_1 wire intInClockXingOut_2 : { sync : UInt<1>[2]} invalidate intInClockXingOut_2.sync[0] invalidate intInClockXingOut_2.sync[1] wire intInClockXingIn_2 : { sync : UInt<1>[2]} invalidate intInClockXingIn_2.sync[0] invalidate intInClockXingIn_2.sync[1] connect intInClockXingOut_2, intInClockXingIn_2 wire intInClockXingOut_3 : { sync : UInt<1>[2]} invalidate intInClockXingOut_3.sync[0] invalidate intInClockXingOut_3.sync[1] wire intInClockXingIn_3 : { sync : UInt<1>[2]} invalidate intInClockXingIn_3.sync[0] invalidate intInClockXingIn_3.sync[1] connect intInClockXingOut_3, intInClockXingIn_3 connect intsource.auto.in[0], clint.auto.int_out_0[0] connect intsource.auto.in[1], clint.auto.int_out_0[1] connect intsource_1.auto.in[0], clint.auto.int_out_1[0] connect intsource_1.auto.in[1], clint.auto.int_out_1[1] connect intsource_2.auto.in[0], clint.auto.int_out_2[0] connect intsource_2.auto.in[1], clint.auto.int_out_2[1] connect intsource_3.auto.in[0], clint.auto.int_out_3[0] connect intsource_3.auto.in[1], clint.auto.int_out_3[1] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect intInClockXingIn_2, intsource_2.auto.out connect intInClockXingIn_3, intsource_3.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect auto.int_in_clock_xing_out_2, intInClockXingOut_2 connect auto.int_in_clock_xing_out_3, intInClockXingOut_3 connect clint.auto.in, auto.clint_in connect clint.io.rtcTick, tick connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_114 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_115 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_3_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_2_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input tick, // @[CLINT.scala:115:20] output clock, // @[ClockDomain.scala:21:19] output reset // @[ClockDomain.scala:22:19] ); wire _clint_auto_int_out_3_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_3_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_2_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_2_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_0_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_0_1; // @[CLINT.scala:112:48] wire auto_clint_in_a_valid_0 = auto_clint_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_a_bits_opcode_0 = auto_clint_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_a_bits_param_0 = auto_clint_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_a_bits_size_0 = auto_clint_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_clint_in_a_bits_source_0 = auto_clint_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_clint_in_a_bits_address_0 = auto_clint_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_clint_in_a_bits_mask_0 = auto_clint_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_clint_in_a_bits_data_0 = auto_clint_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_clint_in_a_bits_corrupt_0 = auto_clint_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_ready_0 = auto_clint_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire intInClockXingOut_3_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_3_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_2_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_1_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_3_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_3_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_2_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_2_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_1_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_1_0 = intInClockXingOut_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_1_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_1_0 = intInClockXingOut_1_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_1_sync_1 = intInClockXingIn_1_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_2_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_2_sync_0_0 = intInClockXingOut_2_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_2_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_2_sync_1_0 = intInClockXingOut_2_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_2_sync_1 = intInClockXingIn_2_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_3_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_3_sync_0_0 = intInClockXingOut_3_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_3_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_3_sync_1_0 = intInClockXingOut_3_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_3_sync_0 = intInClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_3_sync_1 = intInClockXingIn_3_sync_1; // @[MixedNode.scala:542:17, :551:17] CLINT clint ( // @[CLINT.scala:112:48] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_out_3_0 (_clint_auto_int_out_3_0), .auto_int_out_3_1 (_clint_auto_int_out_3_1), .auto_int_out_2_0 (_clint_auto_int_out_2_0), .auto_int_out_2_1 (_clint_auto_int_out_2_1), .auto_int_out_1_0 (_clint_auto_int_out_1_0), .auto_int_out_1_1 (_clint_auto_int_out_1_1), .auto_int_out_0_0 (_clint_auto_int_out_0_0), .auto_int_out_0_1 (_clint_auto_int_out_0_1), .auto_in_a_ready (auto_clint_in_a_ready_0), .auto_in_a_valid (auto_clint_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_clint_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_clint_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_clint_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_clint_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_clint_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_clint_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_clint_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_clint_in_d_valid_0), .auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_clint_in_d_bits_size_0), .auto_in_d_bits_source (auto_clint_in_d_bits_source_0), .auto_in_d_bits_data (auto_clint_in_d_bits_data_0), .io_rtcTick (tick) ); // @[CLINT.scala:112:48] IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_0_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_0_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_sync_0), .auto_out_sync_1 (intInClockXingIn_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_1 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_1_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_1_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_1_sync_0), .auto_out_sync_1 (intInClockXingIn_1_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_2 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_2_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_2_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_2_sync_0), .auto_out_sync_1 (intInClockXingIn_2_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_3 intsource_3 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_3_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_3_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_3_sync_0), .auto_out_sync_1 (intInClockXingIn_3_sync_1) ); // @[Crossing.scala:29:31] assign auto_clint_in_a_ready = auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_valid = auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_opcode = auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_size = auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_source = auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_data = auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_3_sync_0 = auto_int_in_clock_xing_out_3_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_3_sync_1 = auto_int_in_clock_xing_out_3_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_2_sync_0 = auto_int_in_clock_xing_out_2_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_2_sync_1 = auto_int_in_clock_xing_out_2_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_1 = auto_int_in_clock_xing_out_1_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_1 = auto_int_in_clock_xing_out_0_sync_1_0; // @[ClockDomain.scala:14:9] assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9] assign reset = clockNodeIn_reset; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_94 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_95 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module SourceB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset remain : UInt<1>, clock, reset, UInt<1>(0h0) wire remain_set : UInt<1> connect remain_set, UInt<1>(0h0) wire remain_clr : UInt<1> connect remain_clr, UInt<1>(0h0) node _remain_T = or(remain, remain_set) node _remain_T_1 = not(remain_clr) node _remain_T_2 = and(_remain_T, _remain_T_1) connect remain, _remain_T_2 node busy = orr(remain) node todo = mux(busy, remain, io.req.bits.clients) node _next_T = bits(todo, 0, 0) node _next_T_1 = shl(_next_T, 1) node _next_T_2 = not(_next_T_1) node next = and(_next_T_2, todo) node _T = eq(io.req.valid, UInt<1>(0h0)) node _T_1 = neq(io.req.bits.clients, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect remain_set, io.req.bits.clients wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect io.b, b node _b_valid_T = or(busy, io.req.valid) connect b.valid, _b_valid_T node _T_7 = and(b.ready, b.valid) when _T_7 : connect remain_clr, next node _T_8 = eq(b.ready, UInt<1>(0h0)) node _T_9 = and(b.valid, _T_8) node _tag_T = eq(busy, UInt<1>(0h0)) node _tag_T_1 = and(io.req.ready, io.req.valid) reg tag_r : UInt<13>, clock when _tag_T_1 : connect tag_r, io.req.bits.tag node tag = mux(_tag_T, io.req.bits.tag, tag_r) node _set_T = eq(busy, UInt<1>(0h0)) node _set_T_1 = and(io.req.ready, io.req.valid) reg set_r : UInt<10>, clock when _set_T_1 : connect set_r, io.req.bits.set node set = mux(_set_T, io.req.bits.set, set_r) node _param_T = eq(busy, UInt<1>(0h0)) node _param_T_1 = and(io.req.ready, io.req.valid) reg param_r : UInt<3>, clock when _param_T_1 : connect param_r, io.req.bits.param node param = mux(_param_T, io.req.bits.param, param_r) connect b.bits.opcode, UInt<3>(0h6) connect b.bits.param, param connect b.bits.size, UInt<3>(0h6) node _b_bits_source_T = bits(next, 0, 0) connect b.bits.source, UInt<6>(0h21) node b_bits_address_base_y = or(tag, UInt<13>(0h0)) node _b_bits_address_base_T = shr(b_bits_address_base_y, 13) node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0)) node _b_bits_address_base_T_2 = asUInt(reset) node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0)) when _b_bits_address_base_T_3 : node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0)) when _b_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 12, 0) node b_bits_address_base_y_1 = or(set, UInt<10>(0h0)) node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10) node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0)) node _b_bits_address_base_T_8 = asUInt(reset) node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0)) when _b_bits_address_base_T_9 : node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0)) when _b_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1 assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1 node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0) node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6) node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0)) node _b_bits_address_base_T_14 = asUInt(reset) node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0)) when _b_bits_address_base_T_15 : node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0)) when _b_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2 assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2 node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0) node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11) node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17) node _b_bits_address_T = bits(b_bits_address_base, 0, 0) node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1) node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2) node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3) node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4) node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5) node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6) node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7) node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8) node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9) node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10) node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11) node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12) node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13) node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14) node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15) node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16) node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17) node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18) node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19) node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20) node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21) node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22) node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23) node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24) node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25) node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26) node _b_bits_address_T_27 = bits(b_bits_address_base, 27, 27) node _b_bits_address_T_28 = bits(b_bits_address_base, 28, 28) node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T) node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2) node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo) node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4) node b_bits_address_lo_lo_hi_hi = cat(_b_bits_address_T_7, _b_bits_address_T_6) node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo) node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo) node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_9, _b_bits_address_T_8) node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_11, _b_bits_address_T_10) node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo) node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_13, _b_bits_address_T_12) node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_15, _b_bits_address_T_14) node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo) node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo) node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo) node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_17, _b_bits_address_T_16) node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_19, _b_bits_address_T_18) node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo) node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_21, _b_bits_address_T_20) node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_23, _b_bits_address_T_22) node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo) node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo) node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_25, _b_bits_address_T_24) node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_27, _b_bits_address_T_26) node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo) node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_28, UInt<1>(0h0)) node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo) node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo) node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo) node _b_bits_address_T_29 = cat(b_bits_address_hi, b_bits_address_lo) connect b.bits.address, _b_bits_address_T_29 node _b_bits_mask_T = not(UInt<8>(0h0)) connect b.bits.mask, _b_bits_mask_T connect b.bits.data, UInt<1>(0h0) connect b.bits.corrupt, UInt<1>(0h0)

module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h21; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h21; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_mask = 8'hFF; // @[SourceB.scala:33:7] wire [7:0] b_bits_mask = 8'hFF; // @[SourceB.scala:65:17] wire [7:0] _b_bits_mask_T = 8'hFF; // @[SourceB.scala:81:23] wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7] wire [63:0] b_bits_data = 64'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]

Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_UInt2_4 : output auto : { out_3 : UInt<2>, out_2 : UInt<2>, out_1 : UInt<2>, out_0 : UInt<2>} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeOut : UInt<2> invalidate nodeOut wire x1_nodeOut : UInt<2> invalidate x1_nodeOut wire x1_nodeOut_1 : UInt<2> invalidate x1_nodeOut_1 wire x1_nodeOut_2 : UInt<2> invalidate x1_nodeOut_2 connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 node outputs_0 = or(UInt<2>(0h0), UInt<2>(0h0)) node outputs_1 = or(UInt<2>(0h0), UInt<2>(0h1)) node outputs_2 = or(UInt<2>(0h0), UInt<2>(0h2)) node outputs_3 = or(UInt<2>(0h0), UInt<2>(0h3)) connect nodeOut, outputs_0 connect x1_nodeOut, outputs_1 connect x1_nodeOut_1, outputs_2 connect x1_nodeOut_2, outputs_3

module BundleBridgeNexus_UInt2_4( // @[BundleBridgeNexus.scala:20:9] output [1:0] auto_out_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire [1:0] outputs_0 = 2'h0; // @[HasTiles.scala:78:32] wire [1:0] outputs_1 = 2'h1; // @[HasTiles.scala:78:32] wire [1:0] outputs_2 = 2'h2; // @[HasTiles.scala:78:32] wire [1:0] outputs_3 = 2'h3; // @[HasTiles.scala:78:32] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire [1:0] nodeOut; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_1; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_2; // @[MixedNode.scala:542:17] assign nodeOut = outputs_0; // @[HasTiles.scala:78:32] assign x1_nodeOut = outputs_1; // @[HasTiles.scala:78:32] assign x1_nodeOut_1 = outputs_2; // @[HasTiles.scala:78:32] assign x1_nodeOut_2 = outputs_3; // @[HasTiles.scala:78:32] assign auto_out_3 = x1_nodeOut_2; // @[MixedNode.scala:542:17] assign auto_out_2 = x1_nodeOut_1; // @[MixedNode.scala:542:17] assign auto_out_1 = x1_nodeOut; // @[MixedNode.scala:542:17] assign auto_out_0 = nodeOut; // @[MixedNode.scala:542:17] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<2>(0h3)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<2>(0h2)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 4) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<4>(0h9)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<2>(0h3)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<9>(0hc0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_17 = shr(io.in.a.bits.source, 4) node _T_18 = eq(_T_17, UInt<2>(0h2)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<9>(0hc0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_30 = shr(io.in.a.bits.source, 4) node _T_31 = eq(_T_30, UInt<1>(0h1)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<9>(0hc0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_43 = shr(io.in.a.bits.source, 4) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<9>(0hc0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_66 = shr(io.in.a.bits.source, 4) node _T_67 = eq(_T_66, UInt<2>(0h3)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_72 = shr(io.in.a.bits.source, 4) node _T_73 = eq(_T_72, UInt<2>(0h2)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_78 = shr(io.in.a.bits.source, 4) node _T_79 = eq(_T_78, UInt<1>(0h1)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_84 = shr(io.in.a.bits.source, 4) node _T_85 = eq(_T_84, UInt<1>(0h0)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = and(_T_95, _T_100) node _T_102 = or(UInt<1>(0h0), _T_101) node _T_103 = and(_T_94, _T_102) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_103, UInt<1>(0h1), "") : assert_2 node _T_107 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_108 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_109 = and(_T_107, _T_108) node _T_110 = or(UInt<1>(0h0), _T_109) node _T_111 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = and(_T_110, _T_115) node _T_117 = or(UInt<1>(0h0), _T_116) node _T_118 = and(UInt<1>(0h0), _T_117) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_118, UInt<1>(0h1), "") : assert_3 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(source_ok, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_125 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_125, UInt<1>(0h1), "") : assert_5 node _T_129 = asUInt(reset) node _T_130 = eq(_T_129, UInt<1>(0h0)) when _T_130 : node _T_131 = eq(is_aligned, UInt<1>(0h0)) when _T_131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_132 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_132, UInt<1>(0h1), "") : assert_7 node _T_136 = not(io.in.a.bits.mask) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_137, UInt<1>(0h1), "") : assert_8 node _T_141 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_141, UInt<1>(0h1), "") : assert_9 node _T_145 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_145 : node _T_146 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_147 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_149 = shr(io.in.a.bits.source, 4) node _T_150 = eq(_T_149, UInt<2>(0h3)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_8) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_155 = shr(io.in.a.bits.source, 4) node _T_156 = eq(_T_155, UInt<2>(0h2)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_9) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_161 = shr(io.in.a.bits.source, 4) node _T_162 = eq(_T_161, UInt<1>(0h1)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_10) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_166 = and(_T_164, _T_165) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_167 = shr(io.in.a.bits.source, 4) node _T_168 = eq(_T_167, UInt<1>(0h0)) node _T_169 = leq(UInt<1>(0h0), uncommonBits_11) node _T_170 = and(_T_168, _T_169) node _T_171 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_172 = and(_T_170, _T_171) node _T_173 = or(_T_154, _T_160) node _T_174 = or(_T_173, _T_166) node _T_175 = or(_T_174, _T_172) node _T_176 = and(_T_148, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_179 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<17>(0h10000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = and(_T_178, _T_183) node _T_185 = or(UInt<1>(0h0), _T_184) node _T_186 = and(_T_177, _T_185) node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_T_186, UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_186, UInt<1>(0h1), "") : assert_10 node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<17>(0h10000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = and(_T_193, _T_198) node _T_200 = or(UInt<1>(0h0), _T_199) node _T_201 = and(UInt<1>(0h0), _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_201, UInt<1>(0h1), "") : assert_11 node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(source_ok, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_208 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = asUInt(reset) node _T_210 = eq(_T_209, UInt<1>(0h0)) when _T_210 : node _T_211 = eq(_T_208, UInt<1>(0h0)) when _T_211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_208, UInt<1>(0h1), "") : assert_13 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(is_aligned, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_215 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_215, UInt<1>(0h1), "") : assert_15 node _T_219 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_219, UInt<1>(0h1), "") : assert_16 node _T_223 = not(io.in.a.bits.mask) node _T_224 = eq(_T_223, UInt<1>(0h0)) node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(_T_224, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_224, UInt<1>(0h1), "") : assert_17 node _T_228 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_228, UInt<1>(0h1), "") : assert_18 node _T_232 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_232 : node _T_233 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_234 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_236 = shr(io.in.a.bits.source, 4) node _T_237 = eq(_T_236, UInt<2>(0h3)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_242 = shr(io.in.a.bits.source, 4) node _T_243 = eq(_T_242, UInt<2>(0h2)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<4>(0h9)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_248 = shr(io.in.a.bits.source, 4) node _T_249 = eq(_T_248, UInt<1>(0h1)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<4>(0h9)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_254 = shr(io.in.a.bits.source, 4) node _T_255 = eq(_T_254, UInt<1>(0h0)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<4>(0h9)) node _T_259 = and(_T_257, _T_258) node _T_260 = or(_T_241, _T_247) node _T_261 = or(_T_260, _T_253) node _T_262 = or(_T_261, _T_259) node _T_263 = and(_T_235, _T_262) node _T_264 = or(UInt<1>(0h0), _T_263) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_264, UInt<1>(0h1), "") : assert_19 node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_270 = and(_T_268, _T_269) node _T_271 = or(UInt<1>(0h0), _T_270) node _T_272 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_278, UInt<1>(0h1), "") : assert_20 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_288 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_288, UInt<1>(0h1), "") : assert_23 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_292, UInt<1>(0h1), "") : assert_24 node _T_296 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_296, UInt<1>(0h1), "") : assert_25 node _T_300 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_300 : node _T_301 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_302 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_303 = and(_T_301, _T_302) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_304 = shr(io.in.a.bits.source, 4) node _T_305 = eq(_T_304, UInt<2>(0h3)) node _T_306 = leq(UInt<1>(0h0), uncommonBits_16) node _T_307 = and(_T_305, _T_306) node _T_308 = leq(uncommonBits_16, UInt<4>(0h9)) node _T_309 = and(_T_307, _T_308) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_310 = shr(io.in.a.bits.source, 4) node _T_311 = eq(_T_310, UInt<2>(0h2)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_17) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_17, UInt<4>(0h9)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 3, 0) node _T_316 = shr(io.in.a.bits.source, 4) node _T_317 = eq(_T_316, UInt<1>(0h1)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_18) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_18, UInt<4>(0h9)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 3, 0) node _T_322 = shr(io.in.a.bits.source, 4) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_19) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_19, UInt<4>(0h9)) node _T_327 = and(_T_325, _T_326) node _T_328 = or(_T_309, _T_315) node _T_329 = or(_T_328, _T_321) node _T_330 = or(_T_329, _T_327) node _T_331 = and(_T_303, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_334 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_335 = and(_T_333, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = and(_T_336, _T_341) node _T_343 = or(UInt<1>(0h0), _T_342) node _T_344 = and(_T_332, _T_343) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_344, UInt<1>(0h1), "") : assert_26 node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(source_ok, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(is_aligned, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_354 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_354, UInt<1>(0h1), "") : assert_29 node _T_358 = eq(io.in.a.bits.mask, mask) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_358, UInt<1>(0h1), "") : assert_30 node _T_362 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_362 : node _T_363 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_364 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 3, 0) node _T_366 = shr(io.in.a.bits.source, 4) node _T_367 = eq(_T_366, UInt<2>(0h3)) node _T_368 = leq(UInt<1>(0h0), uncommonBits_20) node _T_369 = and(_T_367, _T_368) node _T_370 = leq(uncommonBits_20, UInt<4>(0h9)) node _T_371 = and(_T_369, _T_370) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 3, 0) node _T_372 = shr(io.in.a.bits.source, 4) node _T_373 = eq(_T_372, UInt<2>(0h2)) node _T_374 = leq(UInt<1>(0h0), uncommonBits_21) node _T_375 = and(_T_373, _T_374) node _T_376 = leq(uncommonBits_21, UInt<4>(0h9)) node _T_377 = and(_T_375, _T_376) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_378 = shr(io.in.a.bits.source, 4) node _T_379 = eq(_T_378, UInt<1>(0h1)) node _T_380 = leq(UInt<1>(0h0), uncommonBits_22) node _T_381 = and(_T_379, _T_380) node _T_382 = leq(uncommonBits_22, UInt<4>(0h9)) node _T_383 = and(_T_381, _T_382) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_384 = shr(io.in.a.bits.source, 4) node _T_385 = eq(_T_384, UInt<1>(0h0)) node _T_386 = leq(UInt<1>(0h0), uncommonBits_23) node _T_387 = and(_T_385, _T_386) node _T_388 = leq(uncommonBits_23, UInt<4>(0h9)) node _T_389 = and(_T_387, _T_388) node _T_390 = or(_T_371, _T_377) node _T_391 = or(_T_390, _T_383) node _T_392 = or(_T_391, _T_389) node _T_393 = and(_T_365, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<17>(0h10000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = and(_T_398, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = and(_T_394, _T_405) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_406, UInt<1>(0h1), "") : assert_31 node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(source_ok, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(is_aligned, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_416 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_416, UInt<1>(0h1), "") : assert_34 node _T_420 = not(mask) node _T_421 = and(io.in.a.bits.mask, _T_420) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_422, UInt<1>(0h1), "") : assert_35 node _T_426 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_426 : node _T_427 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_428 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 3, 0) node _T_430 = shr(io.in.a.bits.source, 4) node _T_431 = eq(_T_430, UInt<2>(0h3)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_24) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_24, UInt<4>(0h9)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 3, 0) node _T_436 = shr(io.in.a.bits.source, 4) node _T_437 = eq(_T_436, UInt<2>(0h2)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_25) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_25, UInt<4>(0h9)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 3, 0) node _T_442 = shr(io.in.a.bits.source, 4) node _T_443 = eq(_T_442, UInt<1>(0h1)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_26) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_26, UInt<4>(0h9)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 3, 0) node _T_448 = shr(io.in.a.bits.source, 4) node _T_449 = eq(_T_448, UInt<1>(0h0)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_27) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_27, UInt<4>(0h9)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(_T_435, _T_441) node _T_455 = or(_T_454, _T_447) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_429, _T_456) node _T_458 = or(UInt<1>(0h0), _T_457) node _T_459 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<17>(0h10000))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = and(_T_459, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = and(_T_458, _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_467, UInt<1>(0h1), "") : assert_36 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(source_ok, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(is_aligned, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_477 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_477, UInt<1>(0h1), "") : assert_39 node _T_481 = eq(io.in.a.bits.mask, mask) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_481, UInt<1>(0h1), "") : assert_40 node _T_485 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_485 : node _T_486 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_487 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_489 = shr(io.in.a.bits.source, 4) node _T_490 = eq(_T_489, UInt<2>(0h3)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_28) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_28, UInt<4>(0h9)) node _T_494 = and(_T_492, _T_493) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_495 = shr(io.in.a.bits.source, 4) node _T_496 = eq(_T_495, UInt<2>(0h2)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_29) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_29, UInt<4>(0h9)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 3, 0) node _T_501 = shr(io.in.a.bits.source, 4) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_30) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_30, UInt<4>(0h9)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 3, 0) node _T_507 = shr(io.in.a.bits.source, 4) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_31) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_31, UInt<4>(0h9)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(_T_494, _T_500) node _T_514 = or(_T_513, _T_506) node _T_515 = or(_T_514, _T_512) node _T_516 = and(_T_488, _T_515) node _T_517 = or(UInt<1>(0h0), _T_516) node _T_518 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = or(UInt<1>(0h0), _T_524) node _T_526 = and(_T_517, _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_526, UInt<1>(0h1), "") : assert_41 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_536 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_536, UInt<1>(0h1), "") : assert_44 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_540, UInt<1>(0h1), "") : assert_45 node _T_544 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_544 : node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_547 = and(_T_545, _T_546) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 3, 0) node _T_548 = shr(io.in.a.bits.source, 4) node _T_549 = eq(_T_548, UInt<2>(0h3)) node _T_550 = leq(UInt<1>(0h0), uncommonBits_32) node _T_551 = and(_T_549, _T_550) node _T_552 = leq(uncommonBits_32, UInt<4>(0h9)) node _T_553 = and(_T_551, _T_552) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 3, 0) node _T_554 = shr(io.in.a.bits.source, 4) node _T_555 = eq(_T_554, UInt<2>(0h2)) node _T_556 = leq(UInt<1>(0h0), uncommonBits_33) node _T_557 = and(_T_555, _T_556) node _T_558 = leq(uncommonBits_33, UInt<4>(0h9)) node _T_559 = and(_T_557, _T_558) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_560 = shr(io.in.a.bits.source, 4) node _T_561 = eq(_T_560, UInt<1>(0h1)) node _T_562 = leq(UInt<1>(0h0), uncommonBits_34) node _T_563 = and(_T_561, _T_562) node _T_564 = leq(uncommonBits_34, UInt<4>(0h9)) node _T_565 = and(_T_563, _T_564) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_566 = shr(io.in.a.bits.source, 4) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = leq(UInt<1>(0h0), uncommonBits_35) node _T_569 = and(_T_567, _T_568) node _T_570 = leq(uncommonBits_35, UInt<4>(0h9)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(_T_553, _T_559) node _T_573 = or(_T_572, _T_565) node _T_574 = or(_T_573, _T_571) node _T_575 = and(_T_547, _T_574) node _T_576 = or(UInt<1>(0h0), _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_583) node _T_585 = and(_T_576, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_585, UInt<1>(0h1), "") : assert_46 node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(source_ok, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(is_aligned, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_595 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_595, UInt<1>(0h1), "") : assert_49 node _T_599 = eq(io.in.a.bits.mask, mask) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_599, UInt<1>(0h1), "") : assert_50 node _T_603 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_603, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_607 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_607, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 4) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<2>(0h3)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<4>(0h9)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 4) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<2>(0h2)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<4>(0h9)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 3, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 4) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<1>(0h1)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<4>(0h9)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 3, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 4) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<4>(0h9)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_611 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_611 : node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(source_ok_1, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_615 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(_T_615, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_615, UInt<1>(0h1), "") : assert_54 node _T_619 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_619, UInt<1>(0h1), "") : assert_55 node _T_623 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_623, UInt<1>(0h1), "") : assert_56 node _T_627 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_T_627, UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_627, UInt<1>(0h1), "") : assert_57 node _T_631 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_631 : node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok_1, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(sink_ok, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_638, UInt<1>(0h1), "") : assert_60 node _T_642 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_642, UInt<1>(0h1), "") : assert_61 node _T_646 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_646, UInt<1>(0h1), "") : assert_62 node _T_650 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_650, UInt<1>(0h1), "") : assert_63 node _T_654 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_655, UInt<1>(0h1), "") : assert_64 node _T_659 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_659 : node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(source_ok_1, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(sink_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_666 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_666, UInt<1>(0h1), "") : assert_67 node _T_670 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_670, UInt<1>(0h1), "") : assert_68 node _T_674 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_674, UInt<1>(0h1), "") : assert_69 node _T_678 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_679 = or(_T_678, io.in.d.bits.corrupt) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_679, UInt<1>(0h1), "") : assert_70 node _T_683 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_684, UInt<1>(0h1), "") : assert_71 node _T_688 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_688 : node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(source_ok_1, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_692 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_692, UInt<1>(0h1), "") : assert_73 node _T_696 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_696, UInt<1>(0h1), "") : assert_74 node _T_700 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_701 = or(UInt<1>(0h0), _T_700) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_701, UInt<1>(0h1), "") : assert_75 node _T_705 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_705 : node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(source_ok_1, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_709 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_709, UInt<1>(0h1), "") : assert_77 node _T_713 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_714 = or(_T_713, io.in.d.bits.corrupt) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_714, UInt<1>(0h1), "") : assert_78 node _T_718 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_719, UInt<1>(0h1), "") : assert_79 node _T_723 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(source_ok_1, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_727 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_727, UInt<1>(0h1), "") : assert_81 node _T_731 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_731, UInt<1>(0h1), "") : assert_82 node _T_735 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_736, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_740 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_740, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_744 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_744, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_748 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_748, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_752 = eq(a_first, UInt<1>(0h0)) node _T_753 = and(io.in.a.valid, _T_752) when _T_753 : node _T_754 = eq(io.in.a.bits.opcode, opcode) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_754, UInt<1>(0h1), "") : assert_87 node _T_758 = eq(io.in.a.bits.param, param) node _T_759 = asUInt(reset) node _T_760 = eq(_T_759, UInt<1>(0h0)) when _T_760 : node _T_761 = eq(_T_758, UInt<1>(0h0)) when _T_761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_758, UInt<1>(0h1), "") : assert_88 node _T_762 = eq(io.in.a.bits.size, size) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_762, UInt<1>(0h1), "") : assert_89 node _T_766 = eq(io.in.a.bits.source, source) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_766, UInt<1>(0h1), "") : assert_90 node _T_770 = eq(io.in.a.bits.address, address) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_770, UInt<1>(0h1), "") : assert_91 node _T_774 = and(io.in.a.ready, io.in.a.valid) node _T_775 = and(_T_774, a_first) when _T_775 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_776 = eq(d_first, UInt<1>(0h0)) node _T_777 = and(io.in.d.valid, _T_776) when _T_777 : node _T_778 = eq(io.in.d.bits.opcode, opcode_1) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_778, UInt<1>(0h1), "") : assert_92 node _T_782 = eq(io.in.d.bits.param, param_1) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_782, UInt<1>(0h1), "") : assert_93 node _T_786 = eq(io.in.d.bits.size, size_1) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_786, UInt<1>(0h1), "") : assert_94 node _T_790 = eq(io.in.d.bits.source, source_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_790, UInt<1>(0h1), "") : assert_95 node _T_794 = eq(io.in.d.bits.sink, sink) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_794, UInt<1>(0h1), "") : assert_96 node _T_798 = eq(io.in.d.bits.denied, denied) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_798, UInt<1>(0h1), "") : assert_97 node _T_802 = and(io.in.d.ready, io.in.d.valid) node _T_803 = and(_T_802, d_first) when _T_803 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<58>, clock, reset, UInt<58>(0h0) regreset inflight_opcodes : UInt<232>, clock, reset, UInt<232>(0h0) regreset inflight_sizes : UInt<232>, clock, reset, UInt<232>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<58> connect a_set, UInt<58>(0h0) wire a_set_wo_ready : UInt<58> connect a_set_wo_ready, UInt<58>(0h0) wire a_opcodes_set : UInt<232> connect a_opcodes_set, UInt<232>(0h0) wire a_sizes_set : UInt<232> connect a_sizes_set, UInt<232>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_804 = and(io.in.a.valid, a_first_1) node _T_805 = and(_T_804, UInt<1>(0h1)) when _T_805 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_806 = and(io.in.a.ready, io.in.a.valid) node _T_807 = and(_T_806, a_first_1) node _T_808 = and(_T_807, UInt<1>(0h1)) when _T_808 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_809 = dshr(inflight, io.in.a.bits.source) node _T_810 = bits(_T_809, 0, 0) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_811, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<58> connect d_clr, UInt<58>(0h0) wire d_clr_wo_ready : UInt<58> connect d_clr_wo_ready, UInt<58>(0h0) wire d_opcodes_clr : UInt<232> connect d_opcodes_clr, UInt<232>(0h0) wire d_sizes_clr : UInt<232> connect d_sizes_clr, UInt<232>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_815 = and(io.in.d.valid, d_first_1) node _T_816 = and(_T_815, UInt<1>(0h1)) node _T_817 = eq(d_release_ack, UInt<1>(0h0)) node _T_818 = and(_T_816, _T_817) when _T_818 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_819 = and(io.in.d.ready, io.in.d.valid) node _T_820 = and(_T_819, d_first_1) node _T_821 = and(_T_820, UInt<1>(0h1)) node _T_822 = eq(d_release_ack, UInt<1>(0h0)) node _T_823 = and(_T_821, _T_822) when _T_823 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_824 = and(io.in.d.valid, d_first_1) node _T_825 = and(_T_824, UInt<1>(0h1)) node _T_826 = eq(d_release_ack, UInt<1>(0h0)) node _T_827 = and(_T_825, _T_826) when _T_827 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_828 = dshr(inflight, io.in.d.bits.source) node _T_829 = bits(_T_828, 0, 0) node _T_830 = or(_T_829, same_cycle_resp) node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_T_830, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_830, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_834 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_835 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_836 = or(_T_834, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_836, UInt<1>(0h1), "") : assert_100 node _T_840 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_840, UInt<1>(0h1), "") : assert_101 else : node _T_844 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_845 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_846 = or(_T_844, _T_845) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_846, UInt<1>(0h1), "") : assert_102 node _T_850 = eq(io.in.d.bits.size, a_size_lookup) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_850, UInt<1>(0h1), "") : assert_103 node _T_854 = and(io.in.d.valid, d_first_1) node _T_855 = and(_T_854, a_first_1) node _T_856 = and(_T_855, io.in.a.valid) node _T_857 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(d_release_ack, UInt<1>(0h0)) node _T_860 = and(_T_858, _T_859) when _T_860 : node _T_861 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_862 = or(_T_861, io.in.a.ready) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_862, UInt<1>(0h1), "") : assert_104 node _T_866 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_867 = orr(a_set_wo_ready) node _T_868 = eq(_T_867, UInt<1>(0h0)) node _T_869 = or(_T_866, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_869, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_106 node _T_873 = orr(inflight) node _T_874 = eq(_T_873, UInt<1>(0h0)) node _T_875 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_876 = or(_T_874, _T_875) node _T_877 = lt(watchdog, plusarg_reader.out) node _T_878 = or(_T_876, _T_877) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_878, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_882 = and(io.in.a.ready, io.in.a.valid) node _T_883 = and(io.in.d.ready, io.in.d.valid) node _T_884 = or(_T_882, _T_883) when _T_884 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<58>, clock, reset, UInt<58>(0h0) regreset inflight_opcodes_1 : UInt<232>, clock, reset, UInt<232>(0h0) regreset inflight_sizes_1 : UInt<232>, clock, reset, UInt<232>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<58> connect c_set, UInt<58>(0h0) wire c_set_wo_ready : UInt<58> connect c_set_wo_ready, UInt<58>(0h0) wire c_opcodes_set : UInt<232> connect c_opcodes_set, UInt<232>(0h0) wire c_sizes_set : UInt<232> connect c_sizes_set, UInt<232>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_885 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_886 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_887 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_888 = and(_T_886, _T_887) node _T_889 = and(_T_885, _T_888) when _T_889 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_890 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_891 = and(_T_890, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_892 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_893 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_894 = and(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) when _T_895 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_896 = dshr(inflight_1, _WIRE_15.bits.source) node _T_897 = bits(_T_896, 0, 0) node _T_898 = eq(_T_897, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_898, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<58> connect d_clr_1, UInt<58>(0h0) wire d_clr_wo_ready_1 : UInt<58> connect d_clr_wo_ready_1, UInt<58>(0h0) wire d_opcodes_clr_1 : UInt<232> connect d_opcodes_clr_1, UInt<232>(0h0) wire d_sizes_clr_1 : UInt<232> connect d_sizes_clr_1, UInt<232>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_902 = and(io.in.d.valid, d_first_2) node _T_903 = and(_T_902, UInt<1>(0h1)) node _T_904 = and(_T_903, d_release_ack_1) when _T_904 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_905 = and(io.in.d.ready, io.in.d.valid) node _T_906 = and(_T_905, d_first_2) node _T_907 = and(_T_906, UInt<1>(0h1)) node _T_908 = and(_T_907, d_release_ack_1) when _T_908 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_909 = and(io.in.d.valid, d_first_2) node _T_910 = and(_T_909, UInt<1>(0h1)) node _T_911 = and(_T_910, d_release_ack_1) when _T_911 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_912 = dshr(inflight_1, io.in.d.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = or(_T_913, same_cycle_resp_1) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_914, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_918 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_918, UInt<1>(0h1), "") : assert_109 else : node _T_922 = eq(io.in.d.bits.size, c_size_lookup) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_922, UInt<1>(0h1), "") : assert_110 node _T_926 = and(io.in.d.valid, d_first_2) node _T_927 = and(_T_926, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_928 = and(_T_927, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_929 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_930 = and(_T_928, _T_929) node _T_931 = and(_T_930, d_release_ack_1) node _T_932 = eq(c_probe_ack, UInt<1>(0h0)) node _T_933 = and(_T_931, _T_932) when _T_933 : node _T_934 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_935 = or(_T_934, _WIRE_23.ready) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_935, UInt<1>(0h1), "") : assert_111 node _T_939 = orr(c_set_wo_ready) when _T_939 : node _T_940 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_940, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_107 node _T_944 = orr(inflight_1) node _T_945 = eq(_T_944, UInt<1>(0h0)) node _T_946 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_947 = or(_T_945, _T_946) node _T_948 = lt(watchdog_1, plusarg_reader_1.out) node _T_949 = or(_T_947, _T_948) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_949, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_953 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_954 = and(io.in.d.ready, io.in.d.valid) node _T_955 = or(_T_953, _T_954) when _T_955 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [57:0] inflight; // @[Monitor.scala:614:27] reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [231:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [57:0] inflight_1; // @[Monitor.scala:726:35] reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PTW : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[3], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) wire l2_refill_wire : UInt<1> inst arb of Arbiter3_Valid_PTWReq connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req connect arb.io.in[1], io.requestor[1].req connect arb.io.in[2], io.requestor[2].req node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) connect arb.io.out.ready, _arb_io_out_ready_T_2 wire _resp_valid_WIRE : UInt<1>[3] connect _resp_valid_WIRE[0], UInt<1>(0h0) connect _resp_valid_WIRE[1], UInt<1>(0h0) connect _resp_valid_WIRE[2], UInt<1>(0h0) reg resp_valid : UInt<1>[3], clock connect resp_valid, _resp_valid_WIRE node _clock_en_T = neq(state, UInt<3>(0h0)) node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[2].value, 0, 0) node clock_en = or(_clock_en_T_3, _clock_en_T_4) node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en) connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T reg invalidated : UInt<1>, clock reg count : UInt<2>, clock reg resp_ae_ptw : UInt<1>, clock reg resp_ae_final : UInt<1>, clock reg resp_pf : UInt<1>, clock reg resp_gf : UInt<1>, clock reg resp_hr : UInt<1>, clock reg resp_hw : UInt<1>, clock reg resp_hx : UInt<1>, clock reg resp_fragmented_superpage : UInt<1>, clock reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock reg r_req_dest : UInt, clock reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg aux_count : UInt<2>, clock reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg gpa_pgoff : UInt<12>, clock reg stage2 : UInt<1>, clock reg stage2_final : UInt<1>, clock node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0)) node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1) node do_both_stages = and(r_req.vstage1, r_req.stage2) node _max_count_T = lt(count, aux_count) node max_count = mux(_max_count_T, aux_count, count) node _vpn_T = and(r_req.vstage1, stage2) node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) reg mem_resp_valid : UInt<1>, clock connect mem_resp_valid, io.mem.resp.valid reg mem_resp_data : UInt, clock connect mem_resp_data, io.mem.resp.bits.data wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} wire _tmp_WIRE : UInt<64> connect _tmp_WIRE, mem_resp_data node _tmp_T = bits(_tmp_WIRE, 0, 0) connect tmp.v, _tmp_T node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) connect tmp.r, _tmp_T_1 node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) connect tmp.w, _tmp_T_2 node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) connect tmp.x, _tmp_T_3 node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) connect tmp.u, _tmp_T_4 node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) connect tmp.g, _tmp_T_5 node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) connect tmp.a, _tmp_T_6 node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) connect tmp.d, _tmp_T_7 node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) connect tmp.reserved_for_software, _tmp_T_8 node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) connect tmp.ppn, _tmp_T_9 node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) connect tmp.reserved_for_future, _tmp_T_10 wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect pte, tmp node _res_ppn_T = eq(stage2, UInt<1>(0h0)) node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) node _res_ppn_T_2 = bits(tmp.ppn, 26, 0) node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) connect pte.ppn, _res_ppn_T_4 node _T = or(tmp.r, tmp.w) node _T_1 = or(_T, tmp.x) when _T_1 : node _T_2 = leq(count, UInt<1>(0h0)) node _T_3 = bits(tmp.ppn, 17, 9) node _T_4 = neq(_T_3, UInt<1>(0h0)) node _T_5 = and(_T_2, _T_4) when _T_5 : connect pte.v, UInt<1>(0h0) node _T_6 = leq(count, UInt<1>(0h1)) node _T_7 = bits(tmp.ppn, 8, 0) node _T_8 = neq(_T_7, UInt<1>(0h0)) node _T_9 = and(_T_6, _T_8) when _T_9 : connect pte.v, UInt<1>(0h0) node _T_10 = eq(stage2, UInt<1>(0h0)) node _T_11 = and(do_both_stages, _T_10) node _T_12 = shr(tmp.ppn, 27) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = shr(tmp.ppn, 20) node _T_15 = neq(_T_14, UInt<1>(0h0)) node invalid_paddr = mux(_T_11, _T_13, _T_15) node _T_16 = eq(stage2, UInt<1>(0h0)) node _T_17 = and(do_both_stages, _T_16) node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = sub(_count_T_1, UInt<1>(0h0)) node count_1 = tail(_count_T_2, 1) node idxs_0 = shr(tmp.ppn, 29) wire _WIRE : UInt<15>[1] connect _WIRE[0], idxs_0 node _T_18 = or(count_1, UInt<0>(0h0)) node _T_19 = neq(_WIRE[0], UInt<1>(0h0)) node invalid_gpa = and(_T_17, _T_19) node _traverse_T = eq(pte.r, UInt<1>(0h0)) node _traverse_T_1 = and(pte.v, _traverse_T) node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) node _traverse_T_18 = lt(count, UInt<2>(0h2)) node traverse = and(_traverse_T_17, _traverse_T_18) node _pte_addr_vpn_idxs_T = shr(vpn, 18) node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0) node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9) node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0) node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0) node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0) node _pte_addr_mask_T = eq(count, r_hgatp_initial_count) node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T) node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff)) node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1)) node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0) node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2)) node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1) node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3)) node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3) node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask) node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9) node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx) node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3) node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0) reg pte_hit : UInt<1>, clock connect pte_hit, UInt<1>(0h0) connect io.dpath.perf.pte_miss, UInt<1>(0h0) node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 node _T_20 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) node _T_21 = and(io.dpath.perf.l2hit, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf assert(clock, _T_22, UInt<1>(0h1), "") : assert reg l2_refill : UInt<1>, clock connect l2_refill, UInt<1>(0h0) connect l2_refill_wire, l2_refill connect io.dpath.perf.l2miss, UInt<1>(0h0) connect io.dpath.perf.l2hit, UInt<1>(0h0) reg state_reg : UInt<0>, clock reg state_vec : UInt<0>[512], clock smem l2_tlb_ram : UInt<45>[1] [512] reg g : UInt<512>[1], clock wire _valid_WIRE : UInt<512>[1] connect _valid_WIRE[0], UInt<512>(0h0) regreset valid : UInt<512>[1], clock, reset, _valid_WIRE node _T_26 = bits(r_req.addr, 26, 0) node _T_27 = cat(r_req.vstage1, _T_26) node r_tag = bits(_T_27, 27, 9) node r_idx = bits(_T_27, 8, 0) node _r_valid_vec_T = dshr(valid[0], r_idx) node r_valid_vec = bits(_r_valid_vec_T, 0, 0) reg r_valid_vec_q : UInt<1>, clock reg r_l2_plru_way : UInt<0>, clock connect r_valid_vec_q, r_valid_vec connect r_l2_plru_way, UInt<1>(0h0) node _T_28 = eq(invalidated, UInt<1>(0h0)) node _T_29 = and(l2_refill, _T_28) when _T_29 : wire entry : { tag : UInt<18>, ppn : UInt<20>, d : UInt<1>, a : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} connect entry.ppn, r_pte.ppn connect entry.d, r_pte.d connect entry.a, r_pte.a connect entry.u, r_pte.u connect entry.x, r_pte.x connect entry.w, r_pte.w connect entry.r, r_pte.r connect entry.tag, r_tag node lo_lo = cat(entry.w, entry.r) node lo_hi = cat(entry.u, entry.x) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(entry.d, entry.a) node hi_hi = cat(entry.tag, entry.ppn) node hi = cat(hi_hi, hi_lo) node _T_30 = cat(hi, lo) node _T_31 = xorr(_T_30) node _T_32 = xor(_T_31, UInt<1>(0h0)) node _T_33 = cat(_T_32, _T_30) wire _WIRE_1 : UInt<45>[1] connect _WIRE_1[0], _T_33 write mport MPORT = l2_tlb_ram[r_idx], clock when UInt<1>(0h1) : connect MPORT[0], _WIRE_1[0] node mask = dshl(UInt<1>(0h1), r_idx) when UInt<1>(0h1) : node _valid_0_T = or(valid[0], mask) connect valid[0], _valid_0_T node _g_0_T = or(g[0], mask) node _g_0_T_1 = not(mask) node _g_0_T_2 = and(g[0], _g_0_T_1) node _g_0_T_3 = mux(r_pte.g, _g_0_T, _g_0_T_2) connect g[0], _g_0_T_3 when io.dpath.sfence.valid : node hg = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _valid_0_T_1 = eq(hg, UInt<1>(0h0)) node _valid_0_T_2 = and(_valid_0_T_1, io.dpath.sfence.bits.rs1) node _valid_0_T_3 = bits(io.dpath.sfence.bits.addr, 20, 12) node _valid_0_T_4 = dshl(UInt<1>(0h1), _valid_0_T_3) node _valid_0_T_5 = not(_valid_0_T_4) node _valid_0_T_6 = and(valid[0], _valid_0_T_5) node _valid_0_T_7 = eq(hg, UInt<1>(0h0)) node _valid_0_T_8 = and(_valid_0_T_7, io.dpath.sfence.bits.rs2) node _valid_0_T_9 = and(valid[0], g[0]) node _valid_0_T_10 = mux(_valid_0_T_8, _valid_0_T_9, UInt<1>(0h0)) node _valid_0_T_11 = mux(_valid_0_T_2, _valid_0_T_6, _valid_0_T_10) connect valid[0], _valid_0_T_11 node _s0_valid_T = eq(l2_refill, UInt<1>(0h0)) node _s0_valid_T_1 = and(arb.io.out.ready, arb.io.out.valid) node s0_valid = and(_s0_valid_T, _s0_valid_T_1) node _s0_suitable_T = eq(arb.io.out.bits.bits.vstage1, arb.io.out.bits.bits.stage2) node _s0_suitable_T_1 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node s0_suitable = and(_s0_suitable_T, _s0_suitable_T_1) node _s1_valid_T = and(s0_valid, s0_suitable) node _s1_valid_T_1 = and(_s1_valid_T, arb.io.out.bits.valid) reg s1_valid : UInt<1>, clock connect s1_valid, _s1_valid_T_1 reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid node _s1_rdata_T = bits(arb.io.out.bits.bits.addr, 8, 0) wire _s1_rdata_WIRE : UInt<9> invalidate _s1_rdata_WIRE when s0_valid : connect _s1_rdata_WIRE, _s1_rdata_T read mport s1_rdata = l2_tlb_ram[_s1_rdata_WIRE], clock reg r : UInt<45>, clock when s1_valid : connect r, s1_rdata[0] node uncorrected = bits(r, 43, 0) node uncorrectable = xorr(r) reg s2_valid_vec : UInt<1>, clock when s1_valid : connect s2_valid_vec, r_valid_vec node _s2_g_vec_T = dshr(g[0], r_idx) node _s2_g_vec_T_1 = bits(_s2_g_vec_T, 0, 0) wire _s2_g_vec_WIRE : UInt<1>[1] connect _s2_g_vec_WIRE[0], _s2_g_vec_T_1 reg s2_g_vec : UInt<1>[1], clock when s1_valid : connect s2_g_vec, _s2_g_vec_WIRE node _s2_error_T = bits(s2_valid_vec, 0, 0) node _s2_error_T_1 = or(UInt<1>(0h0), uncorrectable) node l2_error = and(_s2_error_T, _s2_error_T_1) node _T_34 = and(s2_valid, l2_error) when _T_34 : connect valid[0], UInt<1>(0h0) wire s2_entry_vec_0 : { tag : UInt<18>, ppn : UInt<20>, d : UInt<1>, a : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _s2_entry_vec_WIRE : UInt<44> connect _s2_entry_vec_WIRE, uncorrected node _s2_entry_vec_T = bits(_s2_entry_vec_WIRE, 0, 0) connect s2_entry_vec_0.r, _s2_entry_vec_T node _s2_entry_vec_T_1 = bits(_s2_entry_vec_WIRE, 1, 1) connect s2_entry_vec_0.w, _s2_entry_vec_T_1 node _s2_entry_vec_T_2 = bits(_s2_entry_vec_WIRE, 2, 2) connect s2_entry_vec_0.x, _s2_entry_vec_T_2 node _s2_entry_vec_T_3 = bits(_s2_entry_vec_WIRE, 3, 3) connect s2_entry_vec_0.u, _s2_entry_vec_T_3 node _s2_entry_vec_T_4 = bits(_s2_entry_vec_WIRE, 4, 4) connect s2_entry_vec_0.a, _s2_entry_vec_T_4 node _s2_entry_vec_T_5 = bits(_s2_entry_vec_WIRE, 5, 5) connect s2_entry_vec_0.d, _s2_entry_vec_T_5 node _s2_entry_vec_T_6 = bits(_s2_entry_vec_WIRE, 25, 6) connect s2_entry_vec_0.ppn, _s2_entry_vec_T_6 node _s2_entry_vec_T_7 = bits(_s2_entry_vec_WIRE, 43, 26) connect s2_entry_vec_0.tag, _s2_entry_vec_T_7 node _s2_hit_vec_T = bits(s2_valid_vec, 0, 0) node _s2_hit_vec_T_1 = eq(r_tag, s2_entry_vec_0.tag) node s2_hit_vec_0 = and(_s2_hit_vec_T, _s2_hit_vec_T_1) node l2_hit = and(s2_valid, s2_hit_vec_0) node _io_dpath_perf_l2miss_T = eq(s2_hit_vec_0, UInt<1>(0h0)) node _io_dpath_perf_l2miss_T_1 = and(s2_valid, _io_dpath_perf_l2miss_T) connect io.dpath.perf.l2miss, _io_dpath_perf_l2miss_T_1 connect io.dpath.perf.l2hit, l2_hit when l2_hit : connect state_vec[r_idx], UInt<1>(0h0) node _T_35 = eq(s2_hit_vec_0, UInt<1>(0h1)) node _T_36 = or(_T_35, l2_error) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed: L2 TLB multi-hit\n at PTW.scala:486 assert((PopCount(s2_hit_vec) === 1.U) || s2_error, \"L2 TLB multi-hit\")\n") : printf_1 assert(clock, _T_36, UInt<1>(0h1), "") : assert_1 wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect l2_pte.ppn, s2_entry_vec_0.ppn connect l2_pte.d, s2_entry_vec_0.d connect l2_pte.a, s2_entry_vec_0.a connect l2_pte.g, s2_g_vec[0] connect l2_pte.u, s2_entry_vec_0.u connect l2_pte.x, s2_entry_vec_0.x connect l2_pte.w, s2_entry_vec_0.w connect l2_pte.r, s2_entry_vec_0.r connect l2_pte.v, UInt<1>(0h1) connect l2_pte.reserved_for_future, UInt<1>(0h0) connect l2_pte.reserved_for_software, UInt<1>(0h0) node _T_40 = and(l2_hit, s2_hit_vec_0) node _invalidated_T = neq(state, UInt<3>(0h0)) node _invalidated_T_1 = and(invalidated, _invalidated_T) node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) connect invalidated, _invalidated_T_2 connect io.mem.keep_clock_enabled, UInt<1>(0h0) node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) connect io.mem.req.valid, _io_mem_req_valid_T_2 connect io.mem.req.bits.phys, UInt<1>(0h1) connect io.mem.req.bits.cmd, UInt<1>(0h0) connect io.mem.req.bits.size, UInt<2>(0h3) connect io.mem.req.bits.signed, UInt<1>(0h0) connect io.mem.req.bits.addr, pte_addr connect io.mem.req.bits.dprv, UInt<1>(0h1) node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 invalidate io.mem.req.bits.tag connect io.mem.req.bits.no_resp, UInt<1>(0h0) invalidate io.mem.req.bits.no_alloc invalidate io.mem.req.bits.no_xcpt invalidate io.mem.req.bits.data invalidate io.mem.req.bits.mask node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) node _io_mem_s1_kill_T_1 = or(l2_hit, _io_mem_s1_kill_T) node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) connect io.mem.s1_kill, _io_mem_s1_kill_T_2 invalidate io.mem.s1_data.mask invalidate io.mem.s1_data.data connect io.mem.s2_kill, UInt<1>(0h0) node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8) node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10) node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13) node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15) node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12) node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17) node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21) node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23) node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25) node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32) node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38) node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000))) node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40) node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43) node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45) node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48) node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50) node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000)) node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53) node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000))) node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55) node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000)) node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58) node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60) node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000)) node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63) node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65) node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68) node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70) node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73) node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75) node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000)) node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78) node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80) node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83) node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85) node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42) node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47) node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52) node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57) node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62) node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67) node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72) node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77) node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82) node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87) node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98) node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100) node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102) node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105) node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107) node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110) node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112) node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115) node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117) node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120) node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122) node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125) node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000))) node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127) node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109) node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114) node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119) node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124) node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129) node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135) node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000))) node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137) node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140) node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142) node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139) node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144) node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147) node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149) node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151) node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154) node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156) node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158) node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0)) node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0)) node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3) node _pmpHomogeneous_T = shl(r_pte.ppn, 12) wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T) node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4) node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6) node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2) node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3)) node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4) node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5) node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30) node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0)) node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9) node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3)) node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11) node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12) node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21) node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0)) node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16) node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3)) node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18) node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19) node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12) node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0)) node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8) node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24) node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26) node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28) node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0) node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T) node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2) node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3) node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T) node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2) node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3) node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1) node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3) node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1) node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3) node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5) node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1) node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3) node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5) node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper) node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper) node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33) node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34) node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35) node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36) node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8) node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12) node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14) node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39) node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3)) node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41) node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42) node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30) node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0)) node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46) node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3)) node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48) node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49) node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21) node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0)) node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53) node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3)) node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55) node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56) node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12) node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0)) node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45) node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61) node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63) node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65) node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0) node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5) node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7) node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8) node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5) node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7) node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8) node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6) node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8) node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7) node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9) node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11) node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7) node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9) node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11) node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1) node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1) node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70) node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71) node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72) node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73) node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16) node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20) node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22) node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76) node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3)) node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78) node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79) node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30) node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0)) node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83) node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3)) node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85) node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86) node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21) node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0)) node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90) node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3)) node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92) node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93) node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12) node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0)) node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82) node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98) node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100) node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102) node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0) node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10) node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12) node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13) node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10) node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12) node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13) node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11) node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13) node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13) node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15) node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17) node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13) node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15) node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17) node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2) node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2) node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107) node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108) node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109) node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110) node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24) node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28) node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30) node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113) node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3)) node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115) node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116) node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30) node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0)) node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120) node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3)) node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122) node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123) node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21) node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0)) node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127) node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3)) node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129) node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130) node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12) node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0)) node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119) node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135) node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137) node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139) node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0) node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15) node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17) node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18) node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15) node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17) node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18) node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16) node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18) node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19) node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21) node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23) node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19) node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21) node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23) node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3) node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3) node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144) node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145) node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146) node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147) node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32) node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36) node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38) node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150) node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3)) node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152) node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153) node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30) node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0)) node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157) node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3)) node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159) node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160) node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21) node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0)) node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164) node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3)) node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166) node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167) node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12) node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0)) node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156) node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172) node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174) node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176) node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0) node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20) node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22) node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23) node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20) node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22) node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23) node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21) node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23) node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25) node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27) node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29) node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25) node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27) node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29) node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4) node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4) node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181) node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182) node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183) node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184) node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40) node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44) node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46) node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187) node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3)) node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189) node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190) node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30) node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0)) node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194) node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3)) node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196) node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197) node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21) node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0)) node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201) node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3)) node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203) node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204) node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12) node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0)) node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193) node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209) node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211) node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213) node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0) node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25) node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27) node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28) node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25) node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27) node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28) node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26) node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28) node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31) node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33) node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35) node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31) node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33) node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35) node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5) node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5) node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218) node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219) node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220) node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221) node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48) node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52) node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54) node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224) node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3)) node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226) node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227) node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30) node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0)) node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231) node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3)) node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233) node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234) node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21) node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0)) node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238) node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3)) node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240) node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241) node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12) node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0)) node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230) node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246) node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248) node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250) node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0) node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30) node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32) node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33) node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30) node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32) node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33) node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31) node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33) node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37) node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39) node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41) node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37) node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39) node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41) node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6) node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6) node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255) node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256) node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257) node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258) node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56) node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60) node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62) node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261) node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3)) node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263) node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264) node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30) node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0)) node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268) node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3)) node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270) node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271) node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21) node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0)) node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275) node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3)) node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277) node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278) node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12) node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0)) node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267) node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283) node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285) node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287) node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0) node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35) node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37) node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38) node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35) node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37) node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38) node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36) node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38) node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43) node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45) node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47) node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43) node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45) node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47) node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7) node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7) node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292) node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293) node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294) node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295) node homogeneous = and(pmaHomogeneous, pmpHomogeneous) connect io.requestor[0].resp.valid, resp_valid[0] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[0].resp.bits.ae_final, resp_ae_final connect io.requestor[0].resp.bits.pf, resp_pf connect io.requestor[0].resp.bits.gf, resp_gf connect io.requestor[0].resp.bits.hr, resp_hr connect io.requestor[0].resp.bits.hw, resp_hw connect io.requestor[0].resp.bits.hx, resp_hx connect io.requestor[0].resp.bits.pte, r_pte connect io.requestor[0].resp.bits.level, max_count node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3) node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6) node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9) node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7) node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12) node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14 node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T connect io.requestor[0].ptbr, io.dpath.ptbr connect io.requestor[0].hgatp, io.dpath.hgatp connect io.requestor[0].vsatp, io.dpath.vsatp connect io.requestor[0].customCSRs, io.dpath.customCSRs connect io.requestor[0].status, io.dpath.status connect io.requestor[0].hstatus, io.dpath.hstatus connect io.requestor[0].gstatus, io.dpath.gstatus connect io.requestor[0].pmp, io.dpath.pmp connect io.requestor[1].resp.valid, resp_valid[1] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[1].resp.bits.ae_final, resp_ae_final connect io.requestor[1].resp.bits.pf, resp_pf connect io.requestor[1].resp.bits.gf, resp_gf connect io.requestor[1].resp.bits.hr, resp_hr connect io.requestor[1].resp.bits.hw, resp_hw connect io.requestor[1].resp.bits.hx, resp_hx connect io.requestor[1].resp.bits.pte, r_pte connect io.requestor[1].resp.bits.level, max_count node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3) node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6) node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9) node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7) node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12) node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14 node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T connect io.requestor[1].ptbr, io.dpath.ptbr connect io.requestor[1].hgatp, io.dpath.hgatp connect io.requestor[1].vsatp, io.dpath.vsatp connect io.requestor[1].customCSRs, io.dpath.customCSRs connect io.requestor[1].status, io.dpath.status connect io.requestor[1].hstatus, io.dpath.hstatus connect io.requestor[1].gstatus, io.dpath.gstatus connect io.requestor[1].pmp, io.dpath.pmp connect io.requestor[2].resp.valid, resp_valid[2] connect io.requestor[2].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[2].resp.bits.ae_final, resp_ae_final connect io.requestor[2].resp.bits.pf, resp_pf connect io.requestor[2].resp.bits.gf, resp_gf connect io.requestor[2].resp.bits.hr, resp_hr connect io.requestor[2].resp.bits.hw, resp_hw connect io.requestor[2].resp.bits.hx, resp_hx connect io.requestor[2].resp.bits.pte, r_pte connect io.requestor[2].resp.bits.level, max_count node _io_requestor_2_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[2].resp.bits.homogeneous, _io_requestor_2_resp_bits_homogeneous_T node _io_requestor_2_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[2].resp.bits.fragmented_superpage, _io_requestor_2_resp_bits_fragmented_superpage_T connect io.requestor[2].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_2_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_2_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_2_resp_bits_gpa_bits_T_2 = or(_io_requestor_2_resp_bits_gpa_bits_T, _io_requestor_2_resp_bits_gpa_bits_T_1) node _io_requestor_2_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_2_resp_bits_gpa_bits_T_4 = or(_io_requestor_2_resp_bits_gpa_bits_T_2, _io_requestor_2_resp_bits_gpa_bits_T_3) node _io_requestor_2_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_2_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_2_resp_bits_gpa_bits_T_7 = cat(_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6) node _io_requestor_2_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_2_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_2_resp_bits_gpa_bits_T_10 = cat(_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9) node _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_2_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_2_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_2_resp_bits_gpa_bits_T_11 = eq(io_requestor_2_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_2_resp_bits_gpa_bits_T_12 = mux(_io_requestor_2_resp_bits_gpa_bits_T_11, _io_requestor_2_resp_bits_gpa_bits_T_10, _io_requestor_2_resp_bits_gpa_bits_T_7) node _io_requestor_2_resp_bits_gpa_bits_T_13 = mux(_io_requestor_2_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_2_resp_bits_gpa_bits_T_12) node _io_requestor_2_resp_bits_gpa_bits_T_14 = cat(_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[2].resp.bits.gpa.bits, _io_requestor_2_resp_bits_gpa_bits_T_14 node _io_requestor_2_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[2].resp.bits.gpa_is_pte, _io_requestor_2_resp_bits_gpa_is_pte_T connect io.requestor[2].ptbr, io.dpath.ptbr connect io.requestor[2].hgatp, io.dpath.hgatp connect io.requestor[2].vsatp, io.dpath.vsatp connect io.requestor[2].customCSRs, io.dpath.customCSRs connect io.requestor[2].status, io.dpath.status connect io.requestor[2].hstatus, io.dpath.hstatus connect io.requestor[2].gstatus, io.dpath.gstatus connect io.requestor[2].pmp, io.dpath.pmp wire next_state : UInt connect next_state, state inst state_barrier of OptimizationBarrier_UInt connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state connect state, state_barrier.io.y wire do_switch : UInt<1> connect do_switch, UInt<1>(0h0) node _T_41 = eq(UInt<3>(0h0), state) when _T_41 : node _T_42 = and(arb.io.out.ready, arb.io.out.valid) when _T_42 : node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0)) node satp_initial_count = tail(_satp_initial_count_T_2, 1) node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0)) node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1) node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0)) node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1) node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) connect r_req, arb.io.out.bits.bits connect r_req_dest, arb.io.chosen node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) connect next_state, _next_state_T connect stage2, arb.io.out.bits.bits.stage2 node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) connect stage2_final, _stage2_final_T_1 node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) connect count, _count_T_3 node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) connect aux_count, _aux_count_T connect aux_pte.ppn, aux_ppn connect aux_pte.reserved_for_future, UInt<1>(0h0) connect resp_ae_ptw, UInt<1>(0h0) connect resp_ae_final, UInt<1>(0h0) connect resp_pf, UInt<1>(0h0) node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0)) node resp_gf_count = tail(_resp_gf_count_T_2, 1) node resp_gf_idxs_0 = shr(aux_ppn, 29) wire _resp_gf_WIRE : UInt<15>[1] connect _resp_gf_WIRE[0], resp_gf_idxs_0 node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0)) node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0)) node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2) connect resp_gf, _resp_gf_T_2 connect resp_hr, UInt<1>(0h1) connect resp_hw, UInt<1>(0h1) connect resp_hx, UInt<1>(0h1) connect resp_fragmented_superpage, UInt<1>(0h0) connect r_hgatp, io.dpath.hgatp node _T_43 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node _T_44 = or(_T_43, arb.io.out.bits.bits.stage2) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_2 assert(clock, _T_44, UInt<1>(0h1), "") : assert_2 else : node _T_48 = eq(UInt<3>(0h1), state) when _T_48 : node _T_49 = eq(count, r_hgatp_initial_count) node _T_50 = and(stage2, _T_49) when _T_50 : node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2)) node _gpa_pgoff_T_1 = shl(r_req.addr, 3) node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) connect gpa_pgoff, _gpa_pgoff_T_2 when UInt<1>(0h0) : node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) node _aux_count_T_2 = tail(_aux_count_T_1, 1) connect aux_count, _aux_count_T_2 connect aux_pte.ppn, UInt<1>(0h0) connect aux_pte.reserved_for_future, UInt<1>(0h0) connect pte_hit, UInt<1>(0h1) else : when UInt<1>(0h0) : node _count_T_4 = add(count, UInt<1>(0h1)) node _count_T_5 = tail(_count_T_4, 1) connect count, _count_T_5 connect pte_hit, UInt<1>(0h1) else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) connect next_state, _next_state_T_1 when resp_gf : connect next_state, UInt<3>(0h0) node _T_51 = or(r_req_dest, UInt<2>(0h0)) node _T_52 = bits(_T_51, 1, 0) connect resp_valid[_T_52], UInt<1>(0h1) else : node _T_53 = eq(UInt<3>(0h2), state) when _T_53 : node _next_state_T_2 = mux(l2_hit, UInt<3>(0h1), UInt<3>(0h4)) connect next_state, _next_state_T_2 else : node _T_54 = eq(UInt<3>(0h4), state) when _T_54 : connect next_state, UInt<3>(0h5) node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2)) connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T when io.mem.s2_xcpt.ae.ld : connect resp_ae_ptw, UInt<1>(0h1) connect next_state, UInt<3>(0h0) node _T_55 = or(r_req_dest, UInt<2>(0h0)) node _T_56 = bits(_T_55, 1, 0) connect resp_valid[_T_56], UInt<1>(0h1) else : node _T_57 = eq(UInt<3>(0h7), state) when _T_57 : connect next_state, UInt<3>(0h0) node _T_58 = or(r_req_dest, UInt<2>(0h0)) node _T_59 = bits(_T_58, 1, 0) connect resp_valid[_T_59], UInt<1>(0h1) node _T_60 = eq(homogeneous, UInt<1>(0h0)) when _T_60 : connect count, UInt<2>(0h2) connect resp_fragmented_superpage, UInt<1>(0h1) when do_both_stages : connect resp_fragmented_superpage, UInt<1>(0h1) node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000)) node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2) node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18) node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0) node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9) node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0) node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1) node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect merged_pte, aux_pte connect merged_pte.ppn, _merged_pte_T node _r_pte_T = eq(l2_error, UInt<1>(0h0)) node _r_pte_T_1 = and(l2_hit, _r_pte_T) node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) node _r_pte_T_4 = eq(state, UInt<3>(0h1)) node _r_pte_T_5 = and(_r_pte_T_4, UInt<1>(0h0)) node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0)) node r_pte_count = tail(_r_pte_count_T_2, 1) node r_pte_idxs_0 = shr(UInt<1>(0h0), 27) wire r_pte_lsbs : UInt<2> connect r_pte_lsbs, r_pte_idxs_0 wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte, l2_pte node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 node _r_pte_T_6 = eq(state, UInt<3>(0h1)) node _r_pte_T_7 = and(_r_pte_T_6, UInt<1>(0h0)) wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_1, l2_pte connect r_pte_pte_1.ppn, UInt<1>(0h0) node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1) node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0)) node r_pte_count_1 = tail(_r_pte_count_T_5, 1) node r_pte_idxs_0_1 = shr(pte.ppn, 27) wire r_pte_lsbs_1 : UInt<2> connect r_pte_lsbs_1, r_pte_idxs_0_1 wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_2, r_pte node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) node _r_pte_T_10 = and(_r_pte_T_9, stage2) node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) node _r_pte_T_12 = eq(state, UInt<3>(0h7)) node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) node _r_pte_T_15 = neq(count, UInt<2>(0h2)) node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) node _r_pte_T_17 = shr(r_pte.ppn, 18) node _r_pte_T_18 = bits(r_req.addr, 17, 0) node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) node _r_pte_T_20 = shr(r_pte.ppn, 9) node _r_pte_T_21 = bits(r_req.addr, 8, 0) node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) node _r_pte_truncIdx_T = or(count, UInt<1>(0h0)) node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0) node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1)) node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19) wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_3, r_pte connect r_pte_pte_3.ppn, _r_pte_T_24 node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid) node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1) node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0)) node r_pte_count_2 = tail(_r_pte_count_T_8, 1) node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27) wire r_pte_lsbs_2 : UInt<2> connect r_pte_lsbs_2, r_pte_idxs_0_2 wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_4, r_pte node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_5, r_pte connect r_pte_pte_5.ppn, satp.ppn node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte) node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27) node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28) node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29) node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30) node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31) node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32) inst r_pte_barrier of OptimizationBarrier_PTE connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_33.v connect r_pte_barrier.io.x.r, _r_pte_T_33.r connect r_pte_barrier.io.x.w, _r_pte_T_33.w connect r_pte_barrier.io.x.x, _r_pte_T_33.x connect r_pte_barrier.io.x.u, _r_pte_T_33.u connect r_pte_barrier.io.x.g, _r_pte_T_33.g connect r_pte_barrier.io.x.a, _r_pte_T_33.a connect r_pte_barrier.io.x.d, _r_pte_T_33.d connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future connect r_pte, r_pte_barrier.io.y node _T_61 = eq(l2_error, UInt<1>(0h0)) node _T_62 = and(l2_hit, _T_61) node _T_63 = eq(resp_gf, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) when _T_64 : node _T_65 = eq(state, UInt<3>(0h1)) node _T_66 = eq(state, UInt<3>(0h2)) node _T_67 = or(_T_65, _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 connect next_state, UInt<3>(0h0) node _T_71 = or(r_req_dest, UInt<2>(0h0)) node _T_72 = bits(_T_71, 1, 0) connect resp_valid[_T_72], UInt<1>(0h1) connect count, UInt<2>(0h2) when mem_resp_valid : node _T_73 = eq(state, UInt<3>(0h5)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_4 assert(clock, _T_73, UInt<1>(0h1), "") : assert_4 connect next_state, UInt<3>(0h1) when traverse : node _T_77 = eq(stage2, UInt<1>(0h0)) node _T_78 = and(do_both_stages, _T_77) when _T_78 : connect do_switch, UInt<1>(0h1) node _count_T_6 = add(count, UInt<1>(0h1)) node _count_T_7 = tail(_count_T_6, 1) connect count, _count_T_7 else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) node _gf_T_1 = and(stage2, _gf_T) node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) node _gf_T_3 = and(pte.x, _gf_T_2) node _gf_T_4 = or(pte.r, _gf_T_3) node _gf_T_5 = and(pte.v, _gf_T_4) node _gf_T_6 = and(_gf_T_5, pte.a) node _gf_T_7 = and(_gf_T_6, pte.r) node _gf_T_8 = and(_gf_T_7, pte.u) node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) node _gf_T_10 = and(_gf_T_1, _gf_T_9) node _gf_T_11 = eq(pte.w, UInt<1>(0h0)) node _gf_T_12 = and(pte.x, _gf_T_11) node _gf_T_13 = or(pte.r, _gf_T_12) node _gf_T_14 = and(pte.v, _gf_T_13) node _gf_T_15 = and(_gf_T_14, pte.a) node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _gf_T_17 = and(_gf_T_15, _gf_T_16) node _gf_T_18 = and(_gf_T_17, invalid_gpa) node gf = or(_gf_T_10, _gf_T_18) node ae = and(pte.v, invalid_paddr) node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) node pf = and(pte.v, _pf_T) node _success_T = eq(ae, UInt<1>(0h0)) node _success_T_1 = and(pte.v, _success_T) node _success_T_2 = eq(pf, UInt<1>(0h0)) node _success_T_3 = and(_success_T_1, _success_T_2) node _success_T_4 = eq(gf, UInt<1>(0h0)) node success = and(_success_T_3, _success_T_4) node _T_79 = eq(stage2_final, UInt<1>(0h0)) node _T_80 = and(do_both_stages, _T_79) node _T_81 = and(_T_80, success) when _T_81 : when stage2 : connect stage2, UInt<1>(0h0) connect count, aux_count else : connect stage2_final, UInt<1>(0h1) connect do_switch, UInt<1>(0h1) else : node _l2_refill_T = eq(count, UInt<2>(0h2)) node _l2_refill_T_1 = and(success, _l2_refill_T) node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2)) node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) connect l2_refill, _l2_refill_T_27 connect count, max_count node _T_82 = eq(count, UInt<2>(0h2)) node _T_83 = eq(do_both_stages, UInt<1>(0h0)) node _T_84 = eq(aux_count, UInt<2>(0h2)) node _T_85 = or(_T_83, _T_84) node _T_86 = and(_T_82, _T_85) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = and(UInt<1>(0h0), _T_87) when _T_88 : connect next_state, UInt<3>(0h7) else : connect next_state, UInt<3>(0h0) node _T_89 = or(r_req_dest, UInt<2>(0h0)) node _T_90 = bits(_T_89, 1, 0) connect resp_valid[_T_90], UInt<1>(0h1) node _resp_ae_ptw_T = lt(count, UInt<2>(0h2)) node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T) node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0)) node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2) node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4) node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0)) node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6) node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0)) node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8) node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0)) node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10) node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0)) node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12) node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14) node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15) connect resp_ae_ptw, _resp_ae_ptw_T_16 node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) connect resp_ae_final, _resp_ae_final_T_5 node _resp_pf_T = eq(stage2, UInt<1>(0h0)) node _resp_pf_T_1 = and(pf, _resp_pf_T) connect resp_pf, _resp_pf_T_1 node _resp_gf_T_3 = and(pf, stage2) node _resp_gf_T_4 = or(gf, _resp_gf_T_3) connect resp_gf, _resp_gf_T_4 node _resp_hr_T = eq(stage2, UInt<1>(0h0)) node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) connect resp_hr, _resp_hr_T_12 node _resp_hw_T = eq(stage2, UInt<1>(0h0)) node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) connect resp_hw, _resp_hw_T_13 node _resp_hx_T = eq(stage2, UInt<1>(0h0)) node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) connect resp_hx, _resp_hx_T_12 when io.mem.s2_nack : node _T_91 = eq(state, UInt<3>(0h4)) node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : node _T_94 = eq(_T_91, UInt<1>(0h0)) when _T_94 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_5 assert(clock, _T_91, UInt<1>(0h1), "") : assert_5 connect next_state, UInt<3>(0h1) when do_switch : node _aux_count_T_3 = add(count, UInt<1>(0h1)) node _aux_count_T_4 = tail(_aux_count_T_3, 1) node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) connect aux_count, _aux_count_T_5 connect count, r_hgatp_initial_count node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18) node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0) node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9) node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0) node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) node _aux_pte_T = eq(count, UInt<1>(0h1)) node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1) node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect aux_pte_pte, pte connect aux_pte_pte.ppn, _aux_pte_T_5 node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) connect aux_pte, _aux_pte_T_6 connect stage2, UInt<1>(0h1) node _leaf_T = eq(traverse, UInt<1>(0h0)) node _leaf_T_1 = and(mem_resp_valid, _leaf_T) node _leaf_T_2 = eq(count, UInt<1>(0h0)) node leaf = and(_leaf_T_1, _leaf_T_2) node _T_95 = and(leaf, pte.v) node _T_96 = eq(invalid_paddr, UInt<1>(0h0)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(invalid_gpa, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = and(leaf, pte.v) node _T_103 = and(_T_102, invalid_paddr) node _T_104 = and(leaf, pte.v) node _T_105 = and(_T_104, invalid_gpa) node _T_106 = and(leaf, pte.v) node _T_107 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = bits(mem_resp_data, 0, 0) node _T_110 = eq(_T_109, UInt<1>(0h0)) node _T_111 = and(leaf, _T_110) node _T_112 = eq(pte.v, UInt<1>(0h0)) node _T_113 = and(leaf, _T_112) node _T_114 = bits(mem_resp_data, 0, 0) node _T_115 = and(_T_113, _T_114) node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) node _leaf_T_5 = eq(count, UInt<1>(0h1)) node leaf_1 = and(_leaf_T_4, _leaf_T_5) node _T_116 = and(leaf_1, pte.v) node _T_117 = eq(invalid_paddr, UInt<1>(0h0)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(invalid_gpa, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = and(leaf_1, pte.v) node _T_124 = and(_T_123, invalid_paddr) node _T_125 = and(leaf_1, pte.v) node _T_126 = and(_T_125, invalid_gpa) node _T_127 = and(leaf_1, pte.v) node _T_128 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = bits(mem_resp_data, 0, 0) node _T_131 = eq(_T_130, UInt<1>(0h0)) node _T_132 = and(leaf_1, _T_131) node _T_133 = eq(pte.v, UInt<1>(0h0)) node _T_134 = and(leaf_1, _T_133) node _T_135 = bits(mem_resp_data, 0, 0) node _T_136 = and(_T_134, _T_135) node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) node _leaf_T_8 = eq(count, UInt<2>(0h2)) node leaf_2 = and(_leaf_T_7, _leaf_T_8) node _T_137 = and(leaf_2, pte.v) node _T_138 = eq(invalid_paddr, UInt<1>(0h0)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(invalid_gpa, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = and(leaf_2, pte.v) node _T_145 = and(_T_144, invalid_paddr) node _T_146 = and(leaf_2, pte.v) node _T_147 = and(_T_146, invalid_gpa) node _T_148 = and(leaf_2, pte.v) node _T_149 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = bits(mem_resp_data, 0, 0) node _T_152 = eq(_T_151, UInt<1>(0h0)) node _T_153 = and(leaf_2, _T_152) node _T_154 = eq(count, UInt<2>(0h2)) node _T_155 = and(mem_resp_valid, _T_154) node _T_156 = eq(pte.r, UInt<1>(0h0)) node _T_157 = and(pte.v, _T_156) node _T_158 = eq(pte.w, UInt<1>(0h0)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(pte.x, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(pte.d, UInt<1>(0h0)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(pte.a, UInt<1>(0h0)) node _T_165 = and(_T_163, _T_164) node _T_166 = eq(pte.u, UInt<1>(0h0)) node _T_167 = and(_T_165, _T_166) node _T_168 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_169 = and(_T_167, _T_168) node _T_170 = and(_T_155, _T_169) node _T_171 = eq(state, UInt<3>(0h4)) node _T_172 = and(_T_171, io.mem.s2_xcpt.ae.ld)

module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input io_requestor_0_req_bits_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_sd, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_sd, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_2_req_ready, // @[PTW.scala:220:14] output io_requestor_2_resp_valid, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_2_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_2_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_2_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_2_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_2_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_2_status_debug, // @[PTW.scala:220:14] output io_requestor_2_status_cease, // @[PTW.scala:220:14] output io_requestor_2_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_dprv, // @[PTW.scala:220:14] output io_requestor_2_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_prv, // @[PTW.scala:220:14] output io_requestor_2_status_v, // @[PTW.scala:220:14] output io_requestor_2_status_sd, // @[PTW.scala:220:14] output io_requestor_2_status_mpv, // @[PTW.scala:220:14] output io_requestor_2_status_gva, // @[PTW.scala:220:14] output io_requestor_2_status_tsr, // @[PTW.scala:220:14] output io_requestor_2_status_tw, // @[PTW.scala:220:14] output io_requestor_2_status_tvm, // @[PTW.scala:220:14] output io_requestor_2_status_mxr, // @[PTW.scala:220:14] output io_requestor_2_status_sum, // @[PTW.scala:220:14] output io_requestor_2_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_mpp, // @[PTW.scala:220:14] output io_requestor_2_status_spp, // @[PTW.scala:220:14] output io_requestor_2_status_mpie, // @[PTW.scala:220:14] output io_requestor_2_status_spie, // @[PTW.scala:220:14] output io_requestor_2_status_mie, // @[PTW.scala:220:14] output io_requestor_2_status_sie, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_7_mask, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14] input io_mem_resp_bits_dv, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_gf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_gf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_sd, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_l2miss, // @[PTW.scala:220:14] output io_dpath_perf_l2hit, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire s2_entry_vec_0_w; // @[PTW.scala:479:59] wire s2_entry_vec_0_x; // @[PTW.scala:479:59] wire s2_entry_vec_0_u; // @[PTW.scala:479:59] wire s2_entry_vec_0_a; // @[PTW.scala:479:59] wire s2_entry_vec_0_d; // @[PTW.scala:479:59] wire writeEnable; // @[PTW.scala:433:21] wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire [44:0] _l2_tlb_ram_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire [1:0] _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid_0 = io_requestor_0_req_bits_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [31:0] io_requestor_0_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_uncached = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay = 1'h0; // @[PTW.scala:219:7] wire io_mem_replay_next = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_ordered = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_acquire = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_release = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_grant = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_blocked = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_2 = 1'h0; // @[PTW.scala:242:35] wire _clock_en_T_4 = 1'h0; // @[CustomCSRs.scala:43:61] wire _io_dpath_perf_pte_hit_T_1 = 1'h0; // @[PTW.scala:394:36] wire _io_dpath_perf_pte_hit_T_3 = 1'h0; // @[PTW.scala:394:57] wire hg = 1'h0; // @[PTW.scala:458:34] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_2_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire _r_pte_T_7 = 1'h0; // @[PTW.scala:674:25] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42] wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58] wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:489:22] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45] wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61] wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46] wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62] wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46] wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62] wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27] wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27] wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44] wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40] wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44] wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [6:0] io_mem_resp_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_2_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size = 2'h3; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] r_pte_pte_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_1 = 44'h0; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_1_ppn = 44'h0; // @[PTW.scala:771:26] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire [41:0] _r_pte_pte_ppn_T = 42'h0; // @[PTW.scala:781:30] wire [41:0] _r_pte_pte_ppn_T_2 = 42'h0; // @[PTW.scala:781:30] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire io_requestor_1_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire _valid_0_T_1 = 1'h1; // @[PTW.scala:461:15] wire _valid_0_T_7 = 1'h1; // @[PTW.scala:462:15] wire _s0_suitable_T = 1'h1; // @[PTW.scala:468:52] wire l2_pte_v = 1'h1; // @[PTW.scala:489:22] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire r_pte_pte_v = 1'h1; // @[PTW.scala:780:26] wire r_pte_pte_1_v = 1'h1; // @[PTW.scala:771:26] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_2_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_2_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [26:0] io_requestor_2_req_bits_bits_addr = 27'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[PTW.scala:219:7] wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58] wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42] wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58] wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45] wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61] wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46] wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46] wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:489:22] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [511:0] _valid_WIRE_0 = 512'h0; // @[PTW.scala:422:32] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire _valid_0_T_2 = io_dpath_sfence_bits_rs1_0; // @[PTW.scala:219:7, :461:19] wire _valid_0_T_8 = io_dpath_sfence_bits_rs2_0; // @[PTW.scala:219:7, :462:19] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_2_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_l2miss_T_1; // @[PTW.scala:482:38] wire l2_hit; // @[PTW.scala:481:27] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_2_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_2_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_2_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_valid_0; // @[PTW.scala:219:7] wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] reg resp_valid_2; // @[PTW.scala:242:27] assign io_requestor_2_resp_valid_0 = resp_valid_2; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire clock_en = _clock_en_T_3; // @[PTW.scala:244:{74,99}] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_2_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_2_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_2_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_2_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_2_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_2_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_2_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [26:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_2_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg [1:0] r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire entry_d = r_pte_d; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire entry_a = r_pte_a; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire entry_u = r_pte_u; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire entry_x = r_pte_x; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire entry_w = r_pte_w; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire entry_r = r_pte_r; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [1:0] aux_count; // @[PTW.scala:278:22] wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_2_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _GEN = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _GEN; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_23; // @[package.scala:39:86] assign _pmpHomogeneous_T_23 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_60; // @[package.scala:39:86] assign _pmpHomogeneous_T_60 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_97; // @[package.scala:39:86] assign _pmpHomogeneous_T_97 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_134; // @[package.scala:39:86] assign _pmpHomogeneous_T_134 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_171; // @[package.scala:39:86] assign _pmpHomogeneous_T_171 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_245; // @[package.scala:39:86] assign _pmpHomogeneous_T_245 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_T_282; // @[package.scala:39:86] assign _pmpHomogeneous_T_282 = _GEN; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _GEN; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _GEN; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _GEN; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _GEN; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_154 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_154; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_T_25 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_62; // @[package.scala:39:86] assign _pmpHomogeneous_T_62 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_99; // @[package.scala:39:86] assign _pmpHomogeneous_T_99 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_136; // @[package.scala:39:86] assign _pmpHomogeneous_T_136 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_173; // @[package.scala:39:86] assign _pmpHomogeneous_T_173 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_210; // @[package.scala:39:86] assign _pmpHomogeneous_T_210 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_247; // @[package.scala:39:86] assign _pmpHomogeneous_T_247 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_T_284; // @[package.scala:39:86] assign _pmpHomogeneous_T_284 = _T_154; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_154; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_154; // @[package.scala:39:86] wire _l2_refill_T; // @[PTW.scala:713:39] assign _l2_refill_T = _T_154; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_154; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_154; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] wire _T_65 = state == 3'h1; // @[PTW.scala:233:22, :394:46] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_65; // @[PTW.scala:394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_65; // @[PTW.scala:394:46, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_65; // @[PTW.scala:394:46, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_65; // @[PTW.scala:394:46, :674:15] wire _io_dpath_perf_pte_hit_T_2 = ~io_dpath_perf_l2hit_0; // @[PTW.scala:219:7, :394:60] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire [8:0] r_idx; // @[package.scala:163:13] wire [8:0] _s1_rdata_WIRE; // @[PTW.scala:472:28] wire s0_valid; // @[PTW.scala:467:31] reg [511:0] g_0; // @[PTW.scala:421:16] reg [511:0] valid_0; // @[PTW.scala:422:24] wire [18:0] r_tag = {r_req_vstage1, r_req_addr[26:9]}; // @[package.scala:163:13] assign r_idx = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_2_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[package.scala:163:13] wire [511:0] _GEN_0 = {503'h0, r_idx}; // @[package.scala:163:13] wire [511:0] _r_valid_vec_T = valid_0 >> _GEN_0; // @[PTW.scala:422:24, :426:34] wire r_valid_vec = _r_valid_vec_T[0]; // @[PTW.scala:426:34] reg r_valid_vec_q; // @[PTW.scala:427:28] assign writeEnable = l2_refill & ~invalidated; // @[PTW.scala:251:24, :398:26, :433:{21,24}] wire [17:0] entry_tag; // @[PTW.scala:434:23] wire [19:0] entry_ppn; // @[PTW.scala:434:23] assign entry_ppn = r_pte_ppn[19:0]; // @[PTW.scala:275:18, :434:23, :435:17] assign entry_tag = r_tag[17:0]; // @[package.scala:163:13] wire [1:0] lo_lo = {entry_w, entry_r}; // @[PTW.scala:434:23, :446:82] wire [1:0] lo_hi = {entry_u, entry_x}; // @[PTW.scala:434:23, :446:82] wire [3:0] lo = {lo_hi, lo_lo}; // @[PTW.scala:446:82] wire [1:0] hi_lo = {entry_d, entry_a}; // @[PTW.scala:434:23, :446:82] wire [37:0] hi_hi = {entry_tag, entry_ppn}; // @[PTW.scala:434:23, :446:82] wire [39:0] hi = {hi_hi, hi_lo}; // @[PTW.scala:446:82] wire [511:0] mask = 512'h1 << _GEN_0; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T = valid_0 | mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T = g_0 | mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_1 = ~mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_2 = g_0 & _g_0_T_1; // @[PTW.scala:421:16, :452:{56,58}] wire [511:0] _g_0_T_3 = r_pte_g ? _g_0_T : _g_0_T_2; // @[PTW.scala:275:18, :452:{24,41,56}] wire [8:0] _valid_0_T_3 = io_dpath_sfence_bits_addr_0[20:12]; // @[PTW.scala:219:7, :461:96] wire [511:0] _valid_0_T_4 = 512'h1 << _valid_0_T_3; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_5 = ~_valid_0_T_4; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_6 = valid_0 & _valid_0_T_5; // @[PTW.scala:422:24, :461:{59,61}] wire [511:0] _valid_0_T_9 = valid_0 & g_0; // @[PTW.scala:421:16, :422:24, :462:59] wire [511:0] _valid_0_T_10 = _valid_0_T_8 ? _valid_0_T_9 : 512'h0; // @[PTW.scala:462:{14,19,59}] wire [511:0] _valid_0_T_11 = _valid_0_T_2 ? _valid_0_T_6 : _valid_0_T_10; // @[PTW.scala:461:{14,19,59}, :462:14] wire _s0_valid_T = ~l2_refill; // @[PTW.scala:398:26, :467:20] wire _T_42 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _s0_valid_T_1; // @[Decoupled.scala:51:35] assign _s0_valid_T_1 = _T_42; // @[Decoupled.scala:51:35] wire _r_pte_T_25; // @[Decoupled.scala:51:35] assign _r_pte_T_25 = _T_42; // @[Decoupled.scala:51:35] assign s0_valid = _s0_valid_T & _s0_valid_T_1; // @[Decoupled.scala:51:35] wire _s0_suitable_T_1 = ~_arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19, :468:87] wire s0_suitable = _s0_suitable_T_1; // @[PTW.scala:468:{84,87}] wire _s1_valid_T = s0_valid & s0_suitable; // @[PTW.scala:467:31, :468:84, :469:37] wire _s1_valid_T_1 = _s1_valid_T & _arb_io_out_bits_valid; // @[PTW.scala:236:19, :469:{37,52}] reg s1_valid; // @[PTW.scala:469:27] reg s2_valid; // @[PTW.scala:470:27] wire [8:0] _s1_rdata_T = _arb_io_out_bits_bits_addr[8:0]; // @[PTW.scala:236:19, :472:54] assign _s1_rdata_WIRE = _s1_rdata_T; // @[PTW.scala:472:{28,54}] reg [44:0] r; // @[PTW.scala:473:66] wire [43:0] uncorrected = r[43:0]; // @[ECC.scala:75:24] wire [43:0] _s2_entry_vec_WIRE = uncorrected; // @[ECC.scala:75:24] wire uncorrectable = ^r; // @[ECC.scala:78:27] wire _s2_error_T_1 = uncorrectable; // @[ECC.scala:15:27, :78:27] reg s2_valid_vec; // @[PTW.scala:474:33] wire _s2_error_T = s2_valid_vec; // @[PTW.scala:474:33, :476:75] wire _s2_hit_vec_T = s2_valid_vec; // @[PTW.scala:474:33, :480:77] wire [511:0] _s2_g_vec_T = g_0 >> _GEN_0; // @[PTW.scala:421:16, :426:34, :475:45] wire _s2_g_vec_T_1 = _s2_g_vec_T[0]; // @[PTW.scala:475:45] wire _s2_g_vec_WIRE_0 = _s2_g_vec_T_1; // @[PTW.scala:475:{37,45}] reg s2_g_vec_0; // @[PTW.scala:475:29] wire l2_pte_g = s2_g_vec_0; // @[PTW.scala:475:29, :489:22] wire l2_error = _s2_error_T & _s2_error_T_1; // @[ECC.scala:15:27] wire [17:0] _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire [19:0] _s2_entry_vec_T_6; // @[PTW.scala:479:59] wire _s2_entry_vec_T_5; // @[PTW.scala:479:59] wire _s2_entry_vec_T_4; // @[PTW.scala:479:59] wire l2_pte_d = s2_entry_vec_0_d; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_3; // @[PTW.scala:479:59] wire l2_pte_a = s2_entry_vec_0_a; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_2; // @[PTW.scala:479:59] wire l2_pte_u = s2_entry_vec_0_u; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_1; // @[PTW.scala:479:59] wire l2_pte_x = s2_entry_vec_0_x; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T; // @[PTW.scala:479:59] wire l2_pte_w = s2_entry_vec_0_w; // @[PTW.scala:479:59, :489:22] wire [17:0] s2_entry_vec_0_tag; // @[PTW.scala:479:59] wire [19:0] s2_entry_vec_0_ppn; // @[PTW.scala:479:59] wire s2_entry_vec_0_r; // @[PTW.scala:479:59] wire l2_pte_r = s2_entry_vec_0_r; // @[PTW.scala:479:59, :489:22] assign _s2_entry_vec_T = _s2_entry_vec_WIRE[0]; // @[PTW.scala:479:59] assign s2_entry_vec_0_r = _s2_entry_vec_T; // @[PTW.scala:479:59] assign _s2_entry_vec_T_1 = _s2_entry_vec_WIRE[1]; // @[PTW.scala:479:59] assign s2_entry_vec_0_w = _s2_entry_vec_T_1; // @[PTW.scala:479:59] assign _s2_entry_vec_T_2 = _s2_entry_vec_WIRE[2]; // @[PTW.scala:479:59] assign s2_entry_vec_0_x = _s2_entry_vec_T_2; // @[PTW.scala:479:59] assign _s2_entry_vec_T_3 = _s2_entry_vec_WIRE[3]; // @[PTW.scala:479:59] assign s2_entry_vec_0_u = _s2_entry_vec_T_3; // @[PTW.scala:479:59] assign _s2_entry_vec_T_4 = _s2_entry_vec_WIRE[4]; // @[PTW.scala:479:59] assign s2_entry_vec_0_a = _s2_entry_vec_T_4; // @[PTW.scala:479:59] assign _s2_entry_vec_T_5 = _s2_entry_vec_WIRE[5]; // @[PTW.scala:479:59] assign s2_entry_vec_0_d = _s2_entry_vec_T_5; // @[PTW.scala:479:59] assign _s2_entry_vec_T_6 = _s2_entry_vec_WIRE[25:6]; // @[PTW.scala:479:59] assign s2_entry_vec_0_ppn = _s2_entry_vec_T_6; // @[PTW.scala:479:59] assign _s2_entry_vec_T_7 = _s2_entry_vec_WIRE[43:26]; // @[PTW.scala:479:59] assign s2_entry_vec_0_tag = _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire _s2_hit_vec_T_1 = r_tag == {1'h0, s2_entry_vec_0_tag}; // @[package.scala:163:13] wire s2_hit_vec_0 = _s2_hit_vec_T & _s2_hit_vec_T_1; // @[PTW.scala:480:{77,83,93}] assign l2_hit = s2_valid & s2_hit_vec_0; // @[PTW.scala:470:27, :480:83, :481:27] assign io_dpath_perf_l2hit_0 = l2_hit; // @[PTW.scala:219:7, :481:27] wire _io_dpath_perf_l2miss_T = ~s2_hit_vec_0; // @[PTW.scala:480:83, :482:41] assign _io_dpath_perf_l2miss_T_1 = s2_valid & _io_dpath_perf_l2miss_T; // @[PTW.scala:470:27, :482:{38,41}] assign io_dpath_perf_l2miss_0 = _io_dpath_perf_l2miss_T_1; // @[PTW.scala:219:7, :482:38] wire r_pte_pte_d = l2_pte_d; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_d = l2_pte_d; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_a = l2_pte_a; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_a = l2_pte_a; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_g = l2_pte_g; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_g = l2_pte_g; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_u = l2_pte_u; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_u = l2_pte_u; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_x = l2_pte_x; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_x = l2_pte_x; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_w = l2_pte_w; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_w = l2_pte_w; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_r = l2_pte_r; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_r = l2_pte_r; // @[PTW.scala:489:22, :771:26] wire [43:0] l2_pte_ppn; // @[PTW.scala:489:22] assign l2_pte_ppn = {24'h0, s2_entry_vec_0_ppn}; // @[PTW.scala:479:59, :489:22, :491:16] wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = l2_hit | _io_mem_s1_kill_T; // @[PTW.scala:481:27, :531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN_1 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_37 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN_1; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_43 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_48 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_98 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_115 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_68 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_120 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_135 = _GEN_4; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_5 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_83 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_125 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_140 = _GEN_5; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_6 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76] wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_7; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_7; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_8 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_39 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76] wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_9; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_9; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_10 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_76 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_83 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76] wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_11; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_11; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_12 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_113 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_120 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_127 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76] wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_13; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_13; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_14 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_150 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_157 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_164 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76] wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_15; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_15; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_16 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_187 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_194 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_201 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76] wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_17; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_17; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_18 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_224 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_231 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_238 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76] wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_19; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_19; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_20 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_261 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_268 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_275 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76] wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_21 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_21; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_21; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_2_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _T_84 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_2_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _gpa_pgoff_T; // @[PTW.scala:615:36] assign _gpa_pgoff_T = _T_84; // @[PTW.scala:566:60, :615:36] wire _l2_refill_T_7; // @[PTW.scala:715:40] assign _l2_refill_T_7 = _T_84; // @[PTW.scala:566:60, :715:40] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_2_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_2_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_2_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_2_resp_bits_homogeneous_0 = _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_2_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_2_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_2_resp_bits_gpa_bits_T_2 = _io_requestor_2_resp_bits_gpa_bits_T | _io_requestor_2_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_2_resp_bits_gpa_bits_T_4 = _io_requestor_2_resp_bits_gpa_bits_T_2 | _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_7 = {_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_10 = {_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_2_resp_bits_gpa_bits_truncIdx = _io_requestor_2_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_2_resp_bits_gpa_bits_T_11 = io_requestor_2_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_12 = _io_requestor_2_resp_bits_gpa_bits_T_11 ? _io_requestor_2_resp_bits_gpa_bits_T_10 : _io_requestor_2_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_13 = _io_requestor_2_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_2_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_2_resp_bits_gpa_bits_T_14 = {_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_2_resp_bits_gpa_bits_0 = _io_requestor_2_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_2_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_2_resp_bits_gpa_is_pte_0 = _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _GEN_22 = ~(|state) & _T_42; // @[Decoupled.scala:51:35] wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40] wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40] wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_23 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24] wire [2:0] _count_T_4; // @[PTW.scala:624:24] assign _count_T_4 = _GEN_23; // @[PTW.scala:624:24] wire [2:0] _count_T_6; // @[PTW.scala:696:22] assign _count_T_6 = _GEN_23; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_23; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_53 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire [2:0] _next_state_T_2 = l2_hit ? 3'h1 : 3'h4; // @[PTW.scala:481:27, :636:24] wire _T_54 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39] assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _T_65 | _T_53) & _T_54 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :394:46, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T = ~l2_error; // @[PTW.scala:476:81, :670:19] wire _r_pte_T_1 = l2_hit & _r_pte_T; // @[PTW.scala:481:27, :670:{16,19}] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire _r_pte_T_3 = _r_pte_T_1 & _r_pte_T_2; // @[PTW.scala:670:{16,29,32}] wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {42'h0, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:19] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76] wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:8, :676:8] wire [43:0] _r_pte_T_31_ppn = _r_pte_T_30_ppn; // @[PTW.scala:674:8, :676:8] wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_d = _r_pte_T_30_d; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_a = _r_pte_T_30_a; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_g = _r_pte_T_30_g; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_u = _r_pte_T_30_u; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_x = _r_pte_T_30_x; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_w = _r_pte_T_30_w; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_r = _r_pte_T_30_r; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_v = _r_pte_T_30_v; // @[PTW.scala:674:8, :676:8] wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_3 ? 10'h0 : _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:{8,29}, :672:8] wire [43:0] _r_pte_T_33_ppn = _r_pte_T_3 ? l2_pte_ppn : _r_pte_T_32_ppn; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_3 ? 2'h0 : _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:{8,29}, :672:8] wire _r_pte_T_33_d = _r_pte_T_3 ? l2_pte_d : _r_pte_T_32_d; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_a = _r_pte_T_3 ? l2_pte_a : _r_pte_T_32_a; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_g = _r_pte_T_3 ? l2_pte_g : _r_pte_T_32_g; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_u = _r_pte_T_3 ? l2_pte_u : _r_pte_T_32_u; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_x = _r_pte_T_3 ? l2_pte_x : _r_pte_T_32_x; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_w = _r_pte_T_3 ? l2_pte_w : _r_pte_T_32_w; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_r = _r_pte_T_3 ? l2_pte_r : _r_pte_T_32_r; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_v = _r_pte_T_3 | _r_pte_T_32_v; // @[PTW.scala:670:{8,29}, :672:8] wire _T_64 = l2_hit & ~l2_error & ~resp_gf; // @[PTW.scala:263:20, :476:81, :481:27, :670:{19,32}, :685:{16,29}] wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_81 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :566:15, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_81 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_24 = traverse | _T_81; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]

Generate the Verilog code corresponding to this FIRRTL code module TLSlaveACDToNoC_2 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAFromNoC_2 connect a.clock, clock connect a.reset, reset inst c of TLCFromNoC_2 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_2 connect d.clock, clock connect d.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect a.io.flit, io.flits.a connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready

module TLSlaveACDToNoC_2( // @[Tilelink.scala:161:7] input clock, // @[Tilelink.scala:161:7] input reset, // @[Tilelink.scala:161:7] input io_tilelink_a_ready, // @[Tilelink.scala:168:14] output io_tilelink_a_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:168:14] output [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:168:14] output [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:168:14] output [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:168:14] input io_tilelink_c_ready, // @[Tilelink.scala:168:14] output io_tilelink_c_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:168:14] output [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:168:14] output [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:168:14] output io_tilelink_d_ready, // @[Tilelink.scala:168:14] input io_tilelink_d_valid, // @[Tilelink.scala:168:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:168:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:168:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:168:14] input [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:168:14] input [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:168:14] input [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:168:14] output io_flits_a_ready, // @[Tilelink.scala:168:14] input io_flits_a_valid, // @[Tilelink.scala:168:14] input io_flits_a_bits_head, // @[Tilelink.scala:168:14] input io_flits_a_bits_tail, // @[Tilelink.scala:168:14] input [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:168:14] output io_flits_c_ready, // @[Tilelink.scala:168:14] input io_flits_c_valid, // @[Tilelink.scala:168:14] input io_flits_c_bits_head, // @[Tilelink.scala:168:14] input io_flits_c_bits_tail, // @[Tilelink.scala:168:14] input [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:168:14] input io_flits_d_ready, // @[Tilelink.scala:168:14] output io_flits_d_valid, // @[Tilelink.scala:168:14] output io_flits_d_bits_head, // @[Tilelink.scala:168:14] output io_flits_d_bits_tail, // @[Tilelink.scala:168:14] output [144:0] io_flits_d_bits_payload, // @[Tilelink.scala:168:14] output [3:0] io_flits_d_bits_egress_id // @[Tilelink.scala:168:14] ); wire [128:0] _d_io_flit_bits_payload; // @[Tilelink.scala:179:17] TLAFromNoC a ( // @[Tilelink.scala:177:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:177:17] TLCFromNoC_1 c ( // @[Tilelink.scala:178:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[128:0]) // @[Tilelink.scala:185:14] ); // @[Tilelink.scala:178:17] TLDToNoC_2 d ( // @[Tilelink.scala:179:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:179:17] assign io_flits_d_bits_payload = {16'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:161:7, :179:17, :186:14] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ReRoCCXbar : input clock : Clock input reset : Reset output auto : { flip in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}}, out_4 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_3 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_2 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_1 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out_0 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}} wire nodeIn : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<3>, data : UInt<64>}}} invalidate nodeIn.resp.bits.data invalidate nodeIn.resp.bits.manager_id invalidate nodeIn.resp.bits.client_id invalidate nodeIn.resp.bits.opcode invalidate nodeIn.resp.valid invalidate nodeIn.resp.ready invalidate nodeIn.req.bits.data invalidate nodeIn.req.bits.manager_id invalidate nodeIn.req.bits.client_id invalidate nodeIn.req.bits.opcode invalidate nodeIn.req.valid invalidate nodeIn.req.ready wire nodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate nodeOut.resp.bits.data invalidate nodeOut.resp.bits.manager_id invalidate nodeOut.resp.bits.client_id invalidate nodeOut.resp.bits.opcode invalidate nodeOut.resp.valid invalidate nodeOut.resp.ready invalidate nodeOut.req.bits.data invalidate nodeOut.req.bits.manager_id invalidate nodeOut.req.bits.client_id invalidate nodeOut.req.bits.opcode invalidate nodeOut.req.valid invalidate nodeOut.req.ready wire x1_nodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut.resp.bits.data invalidate x1_nodeOut.resp.bits.manager_id invalidate x1_nodeOut.resp.bits.client_id invalidate x1_nodeOut.resp.bits.opcode invalidate x1_nodeOut.resp.valid invalidate x1_nodeOut.resp.ready invalidate x1_nodeOut.req.bits.data invalidate x1_nodeOut.req.bits.manager_id invalidate x1_nodeOut.req.bits.client_id invalidate x1_nodeOut.req.bits.opcode invalidate x1_nodeOut.req.valid invalidate x1_nodeOut.req.ready wire x1_nodeOut_1 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut_1.resp.bits.data invalidate x1_nodeOut_1.resp.bits.manager_id invalidate x1_nodeOut_1.resp.bits.client_id invalidate x1_nodeOut_1.resp.bits.opcode invalidate x1_nodeOut_1.resp.valid invalidate x1_nodeOut_1.resp.ready invalidate x1_nodeOut_1.req.bits.data invalidate x1_nodeOut_1.req.bits.manager_id invalidate x1_nodeOut_1.req.bits.client_id invalidate x1_nodeOut_1.req.bits.opcode invalidate x1_nodeOut_1.req.valid invalidate x1_nodeOut_1.req.ready wire x1_nodeOut_2 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut_2.resp.bits.data invalidate x1_nodeOut_2.resp.bits.manager_id invalidate x1_nodeOut_2.resp.bits.client_id invalidate x1_nodeOut_2.resp.bits.opcode invalidate x1_nodeOut_2.resp.valid invalidate x1_nodeOut_2.resp.ready invalidate x1_nodeOut_2.req.bits.data invalidate x1_nodeOut_2.req.bits.manager_id invalidate x1_nodeOut_2.req.bits.client_id invalidate x1_nodeOut_2.req.bits.opcode invalidate x1_nodeOut_2.req.valid invalidate x1_nodeOut_2.req.ready wire x1_nodeOut_3 : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} invalidate x1_nodeOut_3.resp.bits.data invalidate x1_nodeOut_3.resp.bits.manager_id invalidate x1_nodeOut_3.resp.bits.client_id invalidate x1_nodeOut_3.resp.bits.opcode invalidate x1_nodeOut_3.resp.valid invalidate x1_nodeOut_3.resp.ready invalidate x1_nodeOut_3.req.bits.data invalidate x1_nodeOut_3.req.bits.manager_id invalidate x1_nodeOut_3.req.bits.client_id invalidate x1_nodeOut_3.req.bits.opcode invalidate x1_nodeOut_3.req.valid invalidate x1_nodeOut_3.req.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 connect auto.out_4, x1_nodeOut_3 connect nodeIn, auto.in connect nodeIn.req.ready, UInt<1>(0h0) inst out_arb of ReRoCCMsgArbiter_6 connect out_arb.clock, clock connect out_arb.reset, reset node sel = eq(UInt<1>(0h0), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T = and(nodeIn.req.valid, sel) connect out_arb.io.in[0].valid, _out_arb_io_in_0_valid_T connect out_arb.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T when sel : connect nodeIn.req.ready, out_arb.io.in[0].ready connect nodeOut.req.bits, out_arb.io.out.bits connect nodeOut.req.valid, out_arb.io.out.valid connect out_arb.io.out.ready, nodeOut.req.ready inst out_arb_1 of ReRoCCMsgArbiter_7 connect out_arb_1.clock, clock connect out_arb_1.reset, reset node sel_1 = eq(UInt<1>(0h1), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_1 = and(nodeIn.req.valid, sel_1) connect out_arb_1.io.in[0].valid, _out_arb_io_in_0_valid_T_1 connect out_arb_1.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_1.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_1.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_1.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_1.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_1 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_1.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_1 when sel_1 : connect nodeIn.req.ready, out_arb_1.io.in[0].ready connect x1_nodeOut.req.bits, out_arb_1.io.out.bits connect x1_nodeOut.req.valid, out_arb_1.io.out.valid connect out_arb_1.io.out.ready, x1_nodeOut.req.ready inst out_arb_2 of ReRoCCMsgArbiter_8 connect out_arb_2.clock, clock connect out_arb_2.reset, reset node sel_2 = eq(UInt<2>(0h2), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_2 = and(nodeIn.req.valid, sel_2) connect out_arb_2.io.in[0].valid, _out_arb_io_in_0_valid_T_2 connect out_arb_2.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_2.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_2.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_2.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_2.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_2 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_2.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_2 when sel_2 : connect nodeIn.req.ready, out_arb_2.io.in[0].ready connect x1_nodeOut_1.req.bits, out_arb_2.io.out.bits connect x1_nodeOut_1.req.valid, out_arb_2.io.out.valid connect out_arb_2.io.out.ready, x1_nodeOut_1.req.ready inst out_arb_3 of ReRoCCMsgArbiter_9 connect out_arb_3.clock, clock connect out_arb_3.reset, reset node sel_3 = eq(UInt<2>(0h3), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_3 = and(nodeIn.req.valid, sel_3) connect out_arb_3.io.in[0].valid, _out_arb_io_in_0_valid_T_3 connect out_arb_3.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_3.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_3.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_3.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_3.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_3 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_3.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_3 when sel_3 : connect nodeIn.req.ready, out_arb_3.io.in[0].ready connect x1_nodeOut_2.req.bits, out_arb_3.io.out.bits connect x1_nodeOut_2.req.valid, out_arb_3.io.out.valid connect out_arb_3.io.out.ready, x1_nodeOut_2.req.ready inst out_arb_4 of ReRoCCMsgArbiter_10 connect out_arb_4.clock, clock connect out_arb_4.reset, reset node sel_4 = eq(UInt<3>(0h4), nodeIn.req.bits.manager_id) node _out_arb_io_in_0_valid_T_4 = and(nodeIn.req.valid, sel_4) connect out_arb_4.io.in[0].valid, _out_arb_io_in_0_valid_T_4 connect out_arb_4.io.in[0].bits.data, nodeIn.req.bits.data connect out_arb_4.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id connect out_arb_4.io.in[0].bits.client_id, nodeIn.req.bits.client_id connect out_arb_4.io.in[0].bits.opcode, nodeIn.req.bits.opcode connect out_arb_4.io.in[0].bits.manager_id, nodeIn.req.bits.manager_id node _out_arb_io_in_0_bits_client_id_T_4 = add(UInt<1>(0h0), nodeIn.req.bits.client_id) connect out_arb_4.io.in[0].bits.client_id, _out_arb_io_in_0_bits_client_id_T_4 when sel_4 : connect nodeIn.req.ready, out_arb_4.io.in[0].ready connect x1_nodeOut_3.req.bits, out_arb_4.io.out.bits connect x1_nodeOut_3.req.valid, out_arb_4.io.out.valid connect out_arb_4.io.out.ready, x1_nodeOut_3.req.ready connect nodeOut.resp.ready, UInt<1>(0h0) connect x1_nodeOut.resp.ready, UInt<1>(0h0) connect x1_nodeOut_1.resp.ready, UInt<1>(0h0) connect x1_nodeOut_2.resp.ready, UInt<1>(0h0) connect x1_nodeOut_3.resp.ready, UInt<1>(0h0) inst in_arb of ReRoCCMsgArbiter_11 connect in_arb.clock, clock connect in_arb.reset, reset node _sel_T = leq(UInt<1>(0h0), nodeOut.resp.bits.client_id) node _sel_T_1 = gt(UInt<5>(0h10), nodeOut.resp.bits.client_id) node sel_5 = and(_sel_T, _sel_T_1) node _in_arb_io_in_0_valid_T = and(nodeOut.resp.valid, sel_5) connect in_arb.io.in[0].valid, _in_arb_io_in_0_valid_T connect in_arb.io.in[0].bits.data, nodeOut.resp.bits.data connect in_arb.io.in[0].bits.manager_id, nodeOut.resp.bits.manager_id connect in_arb.io.in[0].bits.client_id, nodeOut.resp.bits.client_id connect in_arb.io.in[0].bits.opcode, nodeOut.resp.bits.opcode node _in_arb_io_in_0_bits_client_id_T = sub(nodeOut.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_0_bits_client_id_T_1 = tail(_in_arb_io_in_0_bits_client_id_T, 1) connect in_arb.io.in[0].bits.client_id, _in_arb_io_in_0_bits_client_id_T_1 connect in_arb.io.in[0].bits.manager_id, nodeOut.resp.bits.manager_id when sel_5 : connect nodeOut.resp.ready, in_arb.io.in[0].ready node _sel_T_2 = leq(UInt<1>(0h0), x1_nodeOut.resp.bits.client_id) node _sel_T_3 = gt(UInt<5>(0h10), x1_nodeOut.resp.bits.client_id) node sel_6 = and(_sel_T_2, _sel_T_3) node _in_arb_io_in_1_valid_T = and(x1_nodeOut.resp.valid, sel_6) connect in_arb.io.in[1].valid, _in_arb_io_in_1_valid_T connect in_arb.io.in[1].bits.data, x1_nodeOut.resp.bits.data connect in_arb.io.in[1].bits.manager_id, x1_nodeOut.resp.bits.manager_id connect in_arb.io.in[1].bits.client_id, x1_nodeOut.resp.bits.client_id connect in_arb.io.in[1].bits.opcode, x1_nodeOut.resp.bits.opcode node _in_arb_io_in_1_bits_client_id_T = sub(x1_nodeOut.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_1_bits_client_id_T_1 = tail(_in_arb_io_in_1_bits_client_id_T, 1) connect in_arb.io.in[1].bits.client_id, _in_arb_io_in_1_bits_client_id_T_1 connect in_arb.io.in[1].bits.manager_id, x1_nodeOut.resp.bits.manager_id when sel_6 : connect x1_nodeOut.resp.ready, in_arb.io.in[1].ready node _sel_T_4 = leq(UInt<1>(0h0), x1_nodeOut_1.resp.bits.client_id) node _sel_T_5 = gt(UInt<5>(0h10), x1_nodeOut_1.resp.bits.client_id) node sel_7 = and(_sel_T_4, _sel_T_5) node _in_arb_io_in_2_valid_T = and(x1_nodeOut_1.resp.valid, sel_7) connect in_arb.io.in[2].valid, _in_arb_io_in_2_valid_T connect in_arb.io.in[2].bits.data, x1_nodeOut_1.resp.bits.data connect in_arb.io.in[2].bits.manager_id, x1_nodeOut_1.resp.bits.manager_id connect in_arb.io.in[2].bits.client_id, x1_nodeOut_1.resp.bits.client_id connect in_arb.io.in[2].bits.opcode, x1_nodeOut_1.resp.bits.opcode node _in_arb_io_in_2_bits_client_id_T = sub(x1_nodeOut_1.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_2_bits_client_id_T_1 = tail(_in_arb_io_in_2_bits_client_id_T, 1) connect in_arb.io.in[2].bits.client_id, _in_arb_io_in_2_bits_client_id_T_1 connect in_arb.io.in[2].bits.manager_id, x1_nodeOut_1.resp.bits.manager_id when sel_7 : connect x1_nodeOut_1.resp.ready, in_arb.io.in[2].ready node _sel_T_6 = leq(UInt<1>(0h0), x1_nodeOut_2.resp.bits.client_id) node _sel_T_7 = gt(UInt<5>(0h10), x1_nodeOut_2.resp.bits.client_id) node sel_8 = and(_sel_T_6, _sel_T_7) node _in_arb_io_in_3_valid_T = and(x1_nodeOut_2.resp.valid, sel_8) connect in_arb.io.in[3].valid, _in_arb_io_in_3_valid_T connect in_arb.io.in[3].bits.data, x1_nodeOut_2.resp.bits.data connect in_arb.io.in[3].bits.manager_id, x1_nodeOut_2.resp.bits.manager_id connect in_arb.io.in[3].bits.client_id, x1_nodeOut_2.resp.bits.client_id connect in_arb.io.in[3].bits.opcode, x1_nodeOut_2.resp.bits.opcode node _in_arb_io_in_3_bits_client_id_T = sub(x1_nodeOut_2.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_3_bits_client_id_T_1 = tail(_in_arb_io_in_3_bits_client_id_T, 1) connect in_arb.io.in[3].bits.client_id, _in_arb_io_in_3_bits_client_id_T_1 connect in_arb.io.in[3].bits.manager_id, x1_nodeOut_2.resp.bits.manager_id when sel_8 : connect x1_nodeOut_2.resp.ready, in_arb.io.in[3].ready node _sel_T_8 = leq(UInt<1>(0h0), x1_nodeOut_3.resp.bits.client_id) node _sel_T_9 = gt(UInt<5>(0h10), x1_nodeOut_3.resp.bits.client_id) node sel_9 = and(_sel_T_8, _sel_T_9) node _in_arb_io_in_4_valid_T = and(x1_nodeOut_3.resp.valid, sel_9) connect in_arb.io.in[4].valid, _in_arb_io_in_4_valid_T connect in_arb.io.in[4].bits.data, x1_nodeOut_3.resp.bits.data connect in_arb.io.in[4].bits.manager_id, x1_nodeOut_3.resp.bits.manager_id connect in_arb.io.in[4].bits.client_id, x1_nodeOut_3.resp.bits.client_id connect in_arb.io.in[4].bits.opcode, x1_nodeOut_3.resp.bits.opcode node _in_arb_io_in_4_bits_client_id_T = sub(x1_nodeOut_3.resp.bits.client_id, UInt<1>(0h0)) node _in_arb_io_in_4_bits_client_id_T_1 = tail(_in_arb_io_in_4_bits_client_id_T, 1) connect in_arb.io.in[4].bits.client_id, _in_arb_io_in_4_bits_client_id_T_1 connect in_arb.io.in[4].bits.manager_id, x1_nodeOut_3.resp.bits.manager_id when sel_9 : connect x1_nodeOut_3.resp.ready, in_arb.io.in[4].ready connect nodeIn.resp.bits, in_arb.io.out.bits connect nodeIn.resp.valid, in_arb.io.out.valid connect in_arb.io.out.ready, nodeIn.resp.ready

module ReRoCCXbar( // @[Xbar.scala:34:25] input clock, // @[Xbar.scala:34:25] input reset, // @[Xbar.scala:34:25] output auto_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_4_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_4_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_4_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_4_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_4_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_4_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_4_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_4_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_4_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_4_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_4_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_4_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_3_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_3_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_3_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_3_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_3_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_3_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_3_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_3_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_3_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_3_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_2_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_2_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_2_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_2_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_2_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_2_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_2_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_2_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_2_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_2_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_1_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_1_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_resp_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_req_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_req_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_req_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_req_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_out_0_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_req_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_resp_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_resp_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_out_0_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_resp_bits_data // @[LazyModuleImp.scala:107:25] ); wire _out_arb_4_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_4_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_3_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_3_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_2_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_2_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_1_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_1_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire _out_arb_io_in_0_ready; // @[Xbar.scala:47:27] wire [2:0] _out_arb_io_out_bits_manager_id; // @[Xbar.scala:47:27] wire auto_in_req_valid_0 = auto_in_req_valid; // @[Xbar.scala:34:25] wire [2:0] auto_in_req_bits_opcode_0 = auto_in_req_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_in_req_bits_client_id_0 = auto_in_req_bits_client_id; // @[Xbar.scala:34:25] wire [2:0] auto_in_req_bits_manager_id_0 = auto_in_req_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_in_req_bits_data_0 = auto_in_req_bits_data; // @[Xbar.scala:34:25] wire auto_in_resp_ready_0 = auto_in_resp_ready; // @[Xbar.scala:34:25] wire auto_out_4_req_ready_0 = auto_out_4_req_ready; // @[Xbar.scala:34:25] wire auto_out_4_resp_valid_0 = auto_out_4_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_4_resp_bits_opcode_0 = auto_out_4_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_4_resp_bits_client_id_0 = auto_out_4_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_4_resp_bits_manager_id_0 = auto_out_4_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_4_resp_bits_data_0 = auto_out_4_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_3_req_ready_0 = auto_out_3_req_ready; // @[Xbar.scala:34:25] wire auto_out_3_resp_valid_0 = auto_out_3_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_3_resp_bits_opcode_0 = auto_out_3_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_3_resp_bits_client_id_0 = auto_out_3_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_3_resp_bits_manager_id_0 = auto_out_3_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_3_resp_bits_data_0 = auto_out_3_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_2_req_ready_0 = auto_out_2_req_ready; // @[Xbar.scala:34:25] wire auto_out_2_resp_valid_0 = auto_out_2_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_2_resp_bits_opcode_0 = auto_out_2_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_2_resp_bits_client_id_0 = auto_out_2_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_2_resp_bits_manager_id_0 = auto_out_2_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_2_resp_bits_data_0 = auto_out_2_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_1_req_ready_0 = auto_out_1_req_ready; // @[Xbar.scala:34:25] wire auto_out_1_resp_valid_0 = auto_out_1_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_1_resp_bits_opcode_0 = auto_out_1_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_1_resp_bits_client_id_0 = auto_out_1_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_1_resp_bits_manager_id_0 = auto_out_1_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_1_resp_bits_data_0 = auto_out_1_resp_bits_data; // @[Xbar.scala:34:25] wire auto_out_0_req_ready_0 = auto_out_0_req_ready; // @[Xbar.scala:34:25] wire auto_out_0_resp_valid_0 = auto_out_0_resp_valid; // @[Xbar.scala:34:25] wire [2:0] auto_out_0_resp_bits_opcode_0 = auto_out_0_resp_bits_opcode; // @[Xbar.scala:34:25] wire [3:0] auto_out_0_resp_bits_client_id_0 = auto_out_0_resp_bits_client_id; // @[Xbar.scala:34:25] wire auto_out_0_resp_bits_manager_id_0 = auto_out_0_resp_bits_manager_id; // @[Xbar.scala:34:25] wire [63:0] auto_out_0_resp_bits_data_0 = auto_out_0_resp_bits_data; // @[Xbar.scala:34:25] wire nodeIn_req_ready; // @[MixedNode.scala:551:17] wire _sel_T = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_1 = 1'h1; // @[Xbar.scala:26:77] wire sel_5 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_2 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_3 = 1'h1; // @[Xbar.scala:26:77] wire sel_6 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_4 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_5 = 1'h1; // @[Xbar.scala:26:77] wire sel_7 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_6 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_7 = 1'h1; // @[Xbar.scala:26:77] wire sel_8 = 1'h1; // @[Xbar.scala:26:46] wire _sel_T_8 = 1'h1; // @[Xbar.scala:26:31] wire _sel_T_9 = 1'h1; // @[Xbar.scala:26:77] wire sel_9 = 1'h1; // @[Xbar.scala:26:46] wire nodeIn_req_valid = auto_in_req_valid_0; // @[Xbar.scala:34:25] wire [2:0] nodeIn_req_bits_opcode = auto_in_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] nodeIn_req_bits_client_id = auto_in_req_bits_client_id_0; // @[Xbar.scala:34:25] wire [2:0] nodeIn_req_bits_manager_id = auto_in_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] nodeIn_req_bits_data = auto_in_req_bits_data_0; // @[Xbar.scala:34:25] wire nodeIn_resp_ready = auto_in_resp_ready_0; // @[Xbar.scala:34:25] wire nodeIn_resp_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_resp_bits_data; // @[MixedNode.scala:551:17] wire x1_nodeOut_3_req_ready = auto_out_4_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_3_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_3_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_3_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_3_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_resp_valid = auto_out_4_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_3_resp_bits_opcode = auto_out_4_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_3_resp_bits_client_id = auto_out_4_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_3_resp_bits_manager_id = auto_out_4_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_3_resp_bits_data = auto_out_4_resp_bits_data_0; // @[Xbar.scala:34:25] wire x1_nodeOut_2_req_ready = auto_out_3_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_2_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_2_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_2_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_2_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_resp_valid = auto_out_3_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_2_resp_bits_opcode = auto_out_3_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_2_resp_bits_client_id = auto_out_3_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_2_resp_bits_manager_id = auto_out_3_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_2_resp_bits_data = auto_out_3_resp_bits_data_0; // @[Xbar.scala:34:25] wire x1_nodeOut_1_req_ready = auto_out_2_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_1_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_1_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_1_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_1_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_resp_valid = auto_out_2_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_1_resp_bits_opcode = auto_out_2_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_1_resp_bits_client_id = auto_out_2_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_1_resp_bits_manager_id = auto_out_2_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_1_resp_bits_data = auto_out_2_resp_bits_data_0; // @[Xbar.scala:34:25] wire x1_nodeOut_req_ready = auto_out_1_req_ready_0; // @[Xbar.scala:34:25] wire x1_nodeOut_req_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_req_bits_client_id; // @[MixedNode.scala:542:17] wire x1_nodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_req_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_resp_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_resp_valid = auto_out_1_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] x1_nodeOut_resp_bits_opcode = auto_out_1_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] x1_nodeOut_resp_bits_client_id = auto_out_1_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire x1_nodeOut_resp_bits_manager_id = auto_out_1_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] x1_nodeOut_resp_bits_data = auto_out_1_resp_bits_data_0; // @[Xbar.scala:34:25] wire nodeOut_req_ready = auto_out_0_req_ready_0; // @[Xbar.scala:34:25] wire nodeOut_req_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_req_bits_client_id; // @[MixedNode.scala:542:17] wire nodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_req_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_resp_ready; // @[MixedNode.scala:542:17] wire nodeOut_resp_valid = auto_out_0_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] nodeOut_resp_bits_opcode = auto_out_0_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] nodeOut_resp_bits_client_id = auto_out_0_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire nodeOut_resp_bits_manager_id = auto_out_0_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] nodeOut_resp_bits_data = auto_out_0_resp_bits_data_0; // @[Xbar.scala:34:25] wire auto_in_req_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_in_resp_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_in_resp_bits_client_id_0; // @[Xbar.scala:34:25] wire [2:0] auto_in_resp_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_in_resp_bits_data_0; // @[Xbar.scala:34:25] wire auto_in_resp_valid_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_4_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_4_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_4_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_4_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_4_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_4_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_3_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_3_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_3_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_3_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_3_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_3_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_2_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_2_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_2_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_2_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_2_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_2_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_1_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_1_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_1_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_1_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_1_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_1_resp_ready_0; // @[Xbar.scala:34:25] wire [2:0] auto_out_0_req_bits_opcode_0; // @[Xbar.scala:34:25] wire [3:0] auto_out_0_req_bits_client_id_0; // @[Xbar.scala:34:25] wire auto_out_0_req_bits_manager_id_0; // @[Xbar.scala:34:25] wire [63:0] auto_out_0_req_bits_data_0; // @[Xbar.scala:34:25] wire auto_out_0_req_valid_0; // @[Xbar.scala:34:25] wire auto_out_0_resp_ready_0; // @[Xbar.scala:34:25] assign auto_in_req_ready_0 = nodeIn_req_ready; // @[Xbar.scala:34:25] assign auto_in_resp_valid_0 = nodeIn_resp_valid; // @[Xbar.scala:34:25] assign auto_in_resp_bits_opcode_0 = nodeIn_resp_bits_opcode; // @[Xbar.scala:34:25] assign auto_in_resp_bits_client_id_0 = nodeIn_resp_bits_client_id; // @[Xbar.scala:34:25] assign auto_in_resp_bits_manager_id_0 = nodeIn_resp_bits_manager_id; // @[Xbar.scala:34:25] assign auto_in_resp_bits_data_0 = nodeIn_resp_bits_data; // @[Xbar.scala:34:25] assign auto_out_0_req_valid_0 = nodeOut_req_valid; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_opcode_0 = nodeOut_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_client_id_0 = nodeOut_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_manager_id_0 = nodeOut_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_data_0 = nodeOut_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_0_resp_ready_0 = nodeOut_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_0_valid_T = nodeOut_resp_valid; // @[Xbar.scala:69:42] assign auto_out_1_req_valid_0 = x1_nodeOut_req_valid; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_opcode_0 = x1_nodeOut_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_client_id_0 = x1_nodeOut_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_manager_id_0 = x1_nodeOut_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_data_0 = x1_nodeOut_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_1_resp_ready_0 = x1_nodeOut_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_1_valid_T = x1_nodeOut_resp_valid; // @[Xbar.scala:69:42] assign auto_out_2_req_valid_0 = x1_nodeOut_1_req_valid; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_opcode_0 = x1_nodeOut_1_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_client_id_0 = x1_nodeOut_1_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_manager_id_0 = x1_nodeOut_1_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_data_0 = x1_nodeOut_1_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_2_resp_ready_0 = x1_nodeOut_1_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_2_valid_T = x1_nodeOut_1_resp_valid; // @[Xbar.scala:69:42] assign auto_out_3_req_valid_0 = x1_nodeOut_2_req_valid; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_opcode_0 = x1_nodeOut_2_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_client_id_0 = x1_nodeOut_2_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_manager_id_0 = x1_nodeOut_2_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_data_0 = x1_nodeOut_2_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_3_resp_ready_0 = x1_nodeOut_2_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_3_valid_T = x1_nodeOut_2_resp_valid; // @[Xbar.scala:69:42] assign auto_out_4_req_valid_0 = x1_nodeOut_3_req_valid; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_opcode_0 = x1_nodeOut_3_req_bits_opcode; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_client_id_0 = x1_nodeOut_3_req_bits_client_id; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_manager_id_0 = x1_nodeOut_3_req_bits_manager_id; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_data_0 = x1_nodeOut_3_req_bits_data; // @[Xbar.scala:34:25] assign auto_out_4_resp_ready_0 = x1_nodeOut_3_resp_ready; // @[Xbar.scala:34:25] wire _in_arb_io_in_4_valid_T = x1_nodeOut_3_resp_valid; // @[Xbar.scala:69:42] wire sel = nodeIn_req_bits_manager_id == 3'h0; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T = nodeIn_req_valid & sel; // @[Xbar.scala:49:67, :50:40] wire [4:0] _GEN = {1'h0, nodeIn_req_bits_client_id}; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_1; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_1 = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_2; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_2 = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_3; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_3 = _GEN; // @[Xbar.scala:28:87] wire [4:0] _out_arb_io_in_0_bits_client_id_T_4; // @[Xbar.scala:28:87] assign _out_arb_io_in_0_bits_client_id_T_4 = _GEN; // @[Xbar.scala:28:87] assign nodeOut_req_bits_manager_id = _out_arb_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_1 = nodeIn_req_bits_manager_id == 3'h1; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_1 = nodeIn_req_valid & sel_1; // @[Xbar.scala:49:67, :50:40] assign x1_nodeOut_req_bits_manager_id = _out_arb_1_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_2 = nodeIn_req_bits_manager_id == 3'h2; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_2 = nodeIn_req_valid & sel_2; // @[Xbar.scala:49:67, :50:40] assign x1_nodeOut_1_req_bits_manager_id = _out_arb_2_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_3 = nodeIn_req_bits_manager_id == 3'h3; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_3 = nodeIn_req_valid & sel_3; // @[Xbar.scala:49:67, :50:40] assign x1_nodeOut_2_req_bits_manager_id = _out_arb_3_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire sel_4 = nodeIn_req_bits_manager_id == 3'h4; // @[Xbar.scala:49:67] wire _out_arb_io_in_0_valid_T_4 = nodeIn_req_valid & sel_4; // @[Xbar.scala:49:67, :50:40] assign nodeIn_req_ready = sel_4 ? _out_arb_4_io_in_0_ready : sel_3 ? _out_arb_3_io_in_0_ready : sel_2 ? _out_arb_2_io_in_0_ready : sel_1 ? _out_arb_1_io_in_0_ready : sel & _out_arb_io_in_0_ready; // @[Xbar.scala:42:31, :47:27, :49:67, :54:20, :55:31] assign x1_nodeOut_3_req_bits_manager_id = _out_arb_4_io_out_bits_manager_id[0]; // @[Xbar.scala:47:27, :58:13] wire [4:0] _in_arb_io_in_0_bits_client_id_T = {1'h0, nodeOut_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_0_bits_client_id_T_1 = _in_arb_io_in_0_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_1_bits_client_id_T = {1'h0, x1_nodeOut_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_1_bits_client_id_T_1 = _in_arb_io_in_1_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_2_bits_client_id_T = {1'h0, x1_nodeOut_1_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_2_bits_client_id_T_1 = _in_arb_io_in_2_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_3_bits_client_id_T = {1'h0, x1_nodeOut_2_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_3_bits_client_id_T_1 = _in_arb_io_in_3_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] wire [4:0] _in_arb_io_in_4_bits_client_id_T = {1'h0, x1_nodeOut_3_resp_bits_client_id}; // @[Xbar.scala:29:74] wire [3:0] _in_arb_io_in_4_bits_client_id_T_1 = _in_arb_io_in_4_bits_client_id_T[3:0]; // @[Xbar.scala:29:74] ReRoCCMsgArbiter_6 out_arb ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (nodeOut_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (nodeOut_req_valid), .io_out_bits_opcode (nodeOut_req_bits_opcode), .io_out_bits_client_id (nodeOut_req_bits_client_id), .io_out_bits_manager_id (_out_arb_io_out_bits_manager_id), .io_out_bits_data (nodeOut_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_7 out_arb_1 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_1_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_1), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_1[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_req_valid), .io_out_bits_opcode (x1_nodeOut_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_req_bits_client_id), .io_out_bits_manager_id (_out_arb_1_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_8 out_arb_2 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_2_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_2), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_2[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_1_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_1_req_valid), .io_out_bits_opcode (x1_nodeOut_1_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_1_req_bits_client_id), .io_out_bits_manager_id (_out_arb_2_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_1_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_9 out_arb_3 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_3_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_3), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_3[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_2_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_2_req_valid), .io_out_bits_opcode (x1_nodeOut_2_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_2_req_bits_client_id), .io_out_bits_manager_id (_out_arb_3_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_2_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_10 out_arb_4 ( // @[Xbar.scala:47:27] .clock (clock), .reset (reset), .io_in_0_ready (_out_arb_4_io_in_0_ready), .io_in_0_valid (_out_arb_io_in_0_valid_T_4), // @[Xbar.scala:50:40] .io_in_0_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17] .io_in_0_bits_client_id (_out_arb_io_in_0_bits_client_id_T_4[3:0]), // @[Xbar.scala:28:87, :53:26] .io_in_0_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17] .io_in_0_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17] .io_out_ready (x1_nodeOut_3_req_ready), // @[MixedNode.scala:542:17] .io_out_valid (x1_nodeOut_3_req_valid), .io_out_bits_opcode (x1_nodeOut_3_req_bits_opcode), .io_out_bits_client_id (x1_nodeOut_3_req_bits_client_id), .io_out_bits_manager_id (_out_arb_4_io_out_bits_manager_id), .io_out_bits_data (x1_nodeOut_3_req_bits_data) ); // @[Xbar.scala:47:27] ReRoCCMsgArbiter_11 in_arb ( // @[Xbar.scala:64:26] .clock (clock), .reset (reset), .io_in_0_ready (nodeOut_resp_ready), .io_in_0_valid (_in_arb_io_in_0_valid_T), // @[Xbar.scala:69:42] .io_in_0_bits_opcode (nodeOut_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_0_bits_client_id (_in_arb_io_in_0_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_0_bits_manager_id ({2'h0, nodeOut_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_0_bits_data (nodeOut_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_1_ready (x1_nodeOut_resp_ready), .io_in_1_valid (_in_arb_io_in_1_valid_T), // @[Xbar.scala:69:42] .io_in_1_bits_opcode (x1_nodeOut_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_1_bits_client_id (_in_arb_io_in_1_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_1_bits_manager_id ({2'h0, x1_nodeOut_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_1_bits_data (x1_nodeOut_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_2_ready (x1_nodeOut_1_resp_ready), .io_in_2_valid (_in_arb_io_in_2_valid_T), // @[Xbar.scala:69:42] .io_in_2_bits_opcode (x1_nodeOut_1_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_2_bits_client_id (_in_arb_io_in_2_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_2_bits_manager_id ({2'h0, x1_nodeOut_1_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_2_bits_data (x1_nodeOut_1_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_3_ready (x1_nodeOut_2_resp_ready), .io_in_3_valid (_in_arb_io_in_3_valid_T), // @[Xbar.scala:69:42] .io_in_3_bits_opcode (x1_nodeOut_2_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_3_bits_client_id (_in_arb_io_in_3_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_3_bits_manager_id ({2'h0, x1_nodeOut_2_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_3_bits_data (x1_nodeOut_2_resp_bits_data), // @[MixedNode.scala:542:17] .io_in_4_ready (x1_nodeOut_3_resp_ready), .io_in_4_valid (_in_arb_io_in_4_valid_T), // @[Xbar.scala:69:42] .io_in_4_bits_opcode (x1_nodeOut_3_resp_bits_opcode), // @[MixedNode.scala:542:17] .io_in_4_bits_client_id (_in_arb_io_in_4_bits_client_id_T_1), // @[Xbar.scala:29:74] .io_in_4_bits_manager_id ({2'h0, x1_nodeOut_3_resp_bits_manager_id}), // @[Xbar.scala:49:67, :70:16] .io_in_4_bits_data (x1_nodeOut_3_resp_bits_data), // @[MixedNode.scala:542:17] .io_out_ready (nodeIn_resp_ready), // @[MixedNode.scala:551:17] .io_out_valid (nodeIn_resp_valid), .io_out_bits_opcode (nodeIn_resp_bits_opcode), .io_out_bits_client_id (nodeIn_resp_bits_client_id), .io_out_bits_manager_id (nodeIn_resp_bits_manager_id), .io_out_bits_data (nodeIn_resp_bits_data) ); // @[Xbar.scala:64:26] assign auto_in_req_ready = auto_in_req_ready_0; // @[Xbar.scala:34:25] assign auto_in_resp_valid = auto_in_resp_valid_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_opcode = auto_in_resp_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_client_id = auto_in_resp_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_manager_id = auto_in_resp_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_in_resp_bits_data = auto_in_resp_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_4_req_valid = auto_out_4_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_opcode = auto_out_4_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_client_id = auto_out_4_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_manager_id = auto_out_4_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_4_req_bits_data = auto_out_4_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_4_resp_ready = auto_out_4_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_3_req_valid = auto_out_3_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_opcode = auto_out_3_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_client_id = auto_out_3_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_manager_id = auto_out_3_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_3_req_bits_data = auto_out_3_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_3_resp_ready = auto_out_3_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_2_req_valid = auto_out_2_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_opcode = auto_out_2_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_client_id = auto_out_2_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_manager_id = auto_out_2_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_2_req_bits_data = auto_out_2_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_2_resp_ready = auto_out_2_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_1_req_valid = auto_out_1_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_opcode = auto_out_1_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_client_id = auto_out_1_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_manager_id = auto_out_1_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_1_req_bits_data = auto_out_1_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_1_resp_ready = auto_out_1_resp_ready_0; // @[Xbar.scala:34:25] assign auto_out_0_req_valid = auto_out_0_req_valid_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_opcode = auto_out_0_req_bits_opcode_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_client_id = auto_out_0_req_bits_client_id_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_manager_id = auto_out_0_req_bits_manager_id_0; // @[Xbar.scala:34:25] assign auto_out_0_req_bits_data = auto_out_0_req_bits_data_0; // @[Xbar.scala:34:25] assign auto_out_0_resp_ready = auto_out_0_resp_ready_0; // @[Xbar.scala:34:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module FullyPortedRF_2 : input clock : Clock input reset : Reset output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<6>}[6], rrd_read_resps : UInt<64>[6], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<64>}}[5]} node _T = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr) node _T_4 = or(_T_2, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _T_8 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_9 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_10 = or(_T_8, _T_9) node _T_11 = neq(io.write_ports[0].bits.addr, io.write_ports[2].bits.addr) node _T_12 = or(_T_10, _T_11) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_1 assert(clock, _T_12, UInt<1>(0h1), "") : assert_1 node _T_16 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_17 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_18 = or(_T_16, _T_17) node _T_19 = neq(io.write_ports[0].bits.addr, io.write_ports[3].bits.addr) node _T_20 = or(_T_18, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 node _T_24 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_25 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_26 = or(_T_24, _T_25) node _T_27 = neq(io.write_ports[0].bits.addr, io.write_ports[4].bits.addr) node _T_28 = or(_T_26, _T_27) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_3 assert(clock, _T_28, UInt<1>(0h1), "") : assert_3 node _T_32 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_33 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_34 = or(_T_32, _T_33) node _T_35 = neq(io.write_ports[1].bits.addr, io.write_ports[2].bits.addr) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_4 assert(clock, _T_36, UInt<1>(0h1), "") : assert_4 node _T_40 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_41 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = neq(io.write_ports[1].bits.addr, io.write_ports[3].bits.addr) node _T_44 = or(_T_42, _T_43) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_5 assert(clock, _T_44, UInt<1>(0h1), "") : assert_5 node _T_48 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_49 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_50 = or(_T_48, _T_49) node _T_51 = neq(io.write_ports[1].bits.addr, io.write_ports[4].bits.addr) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_6 assert(clock, _T_52, UInt<1>(0h1), "") : assert_6 node _T_56 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_57 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_58 = or(_T_56, _T_57) node _T_59 = neq(io.write_ports[2].bits.addr, io.write_ports[3].bits.addr) node _T_60 = or(_T_58, _T_59) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_7 assert(clock, _T_60, UInt<1>(0h1), "") : assert_7 node _T_64 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_65 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_66 = or(_T_64, _T_65) node _T_67 = neq(io.write_ports[2].bits.addr, io.write_ports[4].bits.addr) node _T_68 = or(_T_66, _T_67) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_8 assert(clock, _T_68, UInt<1>(0h1), "") : assert_8 node _T_72 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_73 = eq(io.write_ports[4].valid, UInt<1>(0h0)) node _T_74 = or(_T_72, _T_73) node _T_75 = neq(io.write_ports[3].bits.addr, io.write_ports[4].bits.addr) node _T_76 = or(_T_74, _T_75) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_9 assert(clock, _T_76, UInt<1>(0h1), "") : assert_9 connect io.arb_read_reqs[0].ready, UInt<1>(0h1) connect io.arb_read_reqs[1].ready, UInt<1>(0h1) connect io.arb_read_reqs[2].ready, UInt<1>(0h1) connect io.arb_read_reqs[3].ready, UInt<1>(0h1) connect io.arb_read_reqs[4].ready, UInt<1>(0h1) connect io.arb_read_reqs[5].ready, UInt<1>(0h1) cmem regfile : UInt<64> [50] reg io_rrd_read_resps_0_REG : UInt, clock connect io_rrd_read_resps_0_REG, io.arb_read_reqs[0].bits node _io_rrd_read_resps_0_T = or(io_rrd_read_resps_0_REG, UInt<6>(0h0)) node _io_rrd_read_resps_0_T_1 = bits(_io_rrd_read_resps_0_T, 5, 0) infer mport io_rrd_read_resps_0_MPORT = regfile[_io_rrd_read_resps_0_T_1], clock connect io.rrd_read_resps[0], io_rrd_read_resps_0_MPORT reg io_rrd_read_resps_1_REG : UInt, clock connect io_rrd_read_resps_1_REG, io.arb_read_reqs[1].bits node _io_rrd_read_resps_1_T = or(io_rrd_read_resps_1_REG, UInt<6>(0h0)) node _io_rrd_read_resps_1_T_1 = bits(_io_rrd_read_resps_1_T, 5, 0) infer mport io_rrd_read_resps_1_MPORT = regfile[_io_rrd_read_resps_1_T_1], clock connect io.rrd_read_resps[1], io_rrd_read_resps_1_MPORT reg io_rrd_read_resps_2_REG : UInt, clock connect io_rrd_read_resps_2_REG, io.arb_read_reqs[2].bits node _io_rrd_read_resps_2_T = or(io_rrd_read_resps_2_REG, UInt<6>(0h0)) node _io_rrd_read_resps_2_T_1 = bits(_io_rrd_read_resps_2_T, 5, 0) infer mport io_rrd_read_resps_2_MPORT = regfile[_io_rrd_read_resps_2_T_1], clock connect io.rrd_read_resps[2], io_rrd_read_resps_2_MPORT reg io_rrd_read_resps_3_REG : UInt, clock connect io_rrd_read_resps_3_REG, io.arb_read_reqs[3].bits node _io_rrd_read_resps_3_T = or(io_rrd_read_resps_3_REG, UInt<6>(0h0)) node _io_rrd_read_resps_3_T_1 = bits(_io_rrd_read_resps_3_T, 5, 0) infer mport io_rrd_read_resps_3_MPORT = regfile[_io_rrd_read_resps_3_T_1], clock connect io.rrd_read_resps[3], io_rrd_read_resps_3_MPORT reg io_rrd_read_resps_4_REG : UInt, clock connect io_rrd_read_resps_4_REG, io.arb_read_reqs[4].bits node _io_rrd_read_resps_4_T = or(io_rrd_read_resps_4_REG, UInt<6>(0h0)) node _io_rrd_read_resps_4_T_1 = bits(_io_rrd_read_resps_4_T, 5, 0) infer mport io_rrd_read_resps_4_MPORT = regfile[_io_rrd_read_resps_4_T_1], clock connect io.rrd_read_resps[4], io_rrd_read_resps_4_MPORT reg io_rrd_read_resps_5_REG : UInt, clock connect io_rrd_read_resps_5_REG, io.arb_read_reqs[5].bits node _io_rrd_read_resps_5_T = or(io_rrd_read_resps_5_REG, UInt<6>(0h0)) node _io_rrd_read_resps_5_T_1 = bits(_io_rrd_read_resps_5_T, 5, 0) infer mport io_rrd_read_resps_5_MPORT = regfile[_io_rrd_read_resps_5_T_1], clock connect io.rrd_read_resps[5], io_rrd_read_resps_5_MPORT when io.write_ports[0].valid : node _T_80 = bits(io.write_ports[0].bits.addr, 5, 0) infer mport MPORT = regfile[_T_80], clock connect MPORT, io.write_ports[0].bits.data when io.write_ports[1].valid : node _T_81 = bits(io.write_ports[1].bits.addr, 5, 0) infer mport MPORT_1 = regfile[_T_81], clock connect MPORT_1, io.write_ports[1].bits.data when io.write_ports[2].valid : node _T_82 = bits(io.write_ports[2].bits.addr, 5, 0) infer mport MPORT_2 = regfile[_T_82], clock connect MPORT_2, io.write_ports[2].bits.data when io.write_ports[3].valid : node _T_83 = bits(io.write_ports[3].bits.addr, 5, 0) infer mport MPORT_3 = regfile[_T_83], clock connect MPORT_3, io.write_ports[3].bits.data when io.write_ports[4].valid : node _T_84 = bits(io.write_ports[4].bits.addr, 5, 0) infer mport MPORT_4 = regfile[_T_84], clock connect MPORT_4, io.write_ports[4].bits.data

module FullyPortedRF_2( // @[regfile.scala:186:7] input clock, // @[regfile.scala:186:7] input reset, // @[regfile.scala:186:7] input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_3_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_3_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_4_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_4_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_5_valid, // @[regfile.scala:31:14] input [5:0] io_arb_read_reqs_5_bits, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_0, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_1, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_2, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_3, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_4, // @[regfile.scala:31:14] output [63:0] io_rrd_read_resps_5, // @[regfile.scala:31:14] input io_write_ports_0_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14] input io_write_ports_1_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_1_bits_data, // @[regfile.scala:31:14] input io_write_ports_2_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_2_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_2_bits_data, // @[regfile.scala:31:14] input io_write_ports_3_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_3_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_3_bits_data, // @[regfile.scala:31:14] input io_write_ports_4_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_4_bits_addr, // @[regfile.scala:31:14] input [63:0] io_write_ports_4_bits_data // @[regfile.scala:31:14] ); wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_3_valid_0 = io_arb_read_reqs_3_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_3_bits_0 = io_arb_read_reqs_3_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_4_valid_0 = io_arb_read_reqs_4_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_4_bits_0 = io_arb_read_reqs_4_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_5_valid_0 = io_arb_read_reqs_5_valid; // @[regfile.scala:186:7] wire [5:0] io_arb_read_reqs_5_bits_0 = io_arb_read_reqs_5_bits; // @[regfile.scala:186:7] wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:186:7] wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:186:7] wire io_write_ports_2_valid_0 = io_write_ports_2_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_2_bits_addr_0 = io_write_ports_2_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_2_bits_data_0 = io_write_ports_2_bits_data; // @[regfile.scala:186:7] wire io_write_ports_3_valid_0 = io_write_ports_3_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_3_bits_addr_0 = io_write_ports_3_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_3_bits_data_0 = io_write_ports_3_bits_data; // @[regfile.scala:186:7] wire io_write_ports_4_valid_0 = io_write_ports_4_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_4_bits_addr_0 = io_write_ports_4_bits_addr; // @[regfile.scala:186:7] wire [63:0] io_write_ports_4_bits_data_0 = io_write_ports_4_bits_data; // @[regfile.scala:186:7] wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_3_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_4_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_5_ready = 1'h1; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_0_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_1_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_2_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_3_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_4_0; // @[regfile.scala:186:7] wire [63:0] io_rrd_read_resps_5_0; // @[regfile.scala:186:7]

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_37 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_51 = and(io.pred_wakeup_port.valid, _T_50) when _T_51 : connect ppred, UInt<1>(0h1) node _T_52 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_59 = and(io.spec_ld_wakeup[0].valid, _T_58) node _T_60 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) when _T_61 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_62 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_62, UInt<1>(0h1), "") : assert_4 node _T_66 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_67 = and(io.spec_ld_wakeup[0].valid, _T_66) node _T_68 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_69 = and(_T_67, _T_68) when _T_69 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_70 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_74 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_75 = neq(_T_74, UInt<1>(0h0)) when _T_75 : connect next_state, UInt<2>(0h0) node _T_76 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_76 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_77 = eq(state, UInt<2>(0h1)) when _T_77 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_78 = eq(state, UInt<2>(0h2)) when _T_78 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_79 = eq(state, UInt<2>(0h2)) when _T_79 : node _T_80 = and(p1, p2) node _T_81 = and(_T_80, ppred) when _T_81 : skip else : node _T_82 = and(p1, ppred) when _T_82 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_83 = and(p2, ppred) when _T_83 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_37( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module TagMan : input clock : Clock input reset : Reset output io : { available : UInt<1>, tagOut : UInt<3>, flip take : UInt<1>, flip put : UInt<1>, flip tagIn : UInt<3>} regreset inUse_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_5 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_6 : UInt<1>, clock, reset, UInt<1>(0h0) regreset inUse_7 : UInt<1>, clock, reset, UInt<1>(0h0) regreset nextTag : UInt<3>, clock, reset, UInt<3>(0h0) connect io.tagOut, nextTag node _io_available_T = eq(UInt<1>(0h1), nextTag) node _io_available_T_1 = mux(_io_available_T, inUse_1, inUse_0) node _io_available_T_2 = eq(UInt<2>(0h2), nextTag) node _io_available_T_3 = mux(_io_available_T_2, inUse_2, _io_available_T_1) node _io_available_T_4 = eq(UInt<2>(0h3), nextTag) node _io_available_T_5 = mux(_io_available_T_4, inUse_3, _io_available_T_3) node _io_available_T_6 = eq(UInt<3>(0h4), nextTag) node _io_available_T_7 = mux(_io_available_T_6, inUse_4, _io_available_T_5) node _io_available_T_8 = eq(UInt<3>(0h5), nextTag) node _io_available_T_9 = mux(_io_available_T_8, inUse_5, _io_available_T_7) node _io_available_T_10 = eq(UInt<3>(0h6), nextTag) node _io_available_T_11 = mux(_io_available_T_10, inUse_6, _io_available_T_9) node _io_available_T_12 = eq(UInt<3>(0h7), nextTag) node _io_available_T_13 = mux(_io_available_T_12, inUse_7, _io_available_T_11) node _io_available_T_14 = not(_io_available_T_13) connect io.available, _io_available_T_14 when io.take : node _T = eq(UInt<1>(0h0), nextTag) when _T : connect inUse_0, UInt<1>(0h1) node _T_1 = eq(UInt<1>(0h1), nextTag) when _T_1 : connect inUse_1, UInt<1>(0h1) node _T_2 = eq(UInt<2>(0h2), nextTag) when _T_2 : connect inUse_2, UInt<1>(0h1) node _T_3 = eq(UInt<2>(0h3), nextTag) when _T_3 : connect inUse_3, UInt<1>(0h1) node _T_4 = eq(UInt<3>(0h4), nextTag) when _T_4 : connect inUse_4, UInt<1>(0h1) node _T_5 = eq(UInt<3>(0h5), nextTag) when _T_5 : connect inUse_5, UInt<1>(0h1) node _T_6 = eq(UInt<3>(0h6), nextTag) when _T_6 : connect inUse_6, UInt<1>(0h1) node _T_7 = eq(UInt<3>(0h7), nextTag) when _T_7 : connect inUse_7, UInt<1>(0h1) node _nextTag_T = add(nextTag, UInt<1>(0h1)) node _nextTag_T_1 = tail(_nextTag_T, 1) connect nextTag, _nextTag_T_1 when io.put : node _T_8 = eq(UInt<1>(0h0), io.tagIn) when _T_8 : connect inUse_0, UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h1), io.tagIn) when _T_9 : connect inUse_1, UInt<1>(0h0) node _T_10 = eq(UInt<2>(0h2), io.tagIn) when _T_10 : connect inUse_2, UInt<1>(0h0) node _T_11 = eq(UInt<2>(0h3), io.tagIn) when _T_11 : connect inUse_3, UInt<1>(0h0) node _T_12 = eq(UInt<3>(0h4), io.tagIn) when _T_12 : connect inUse_4, UInt<1>(0h0) node _T_13 = eq(UInt<3>(0h5), io.tagIn) when _T_13 : connect inUse_5, UInt<1>(0h0) node _T_14 = eq(UInt<3>(0h6), io.tagIn) when _T_14 : connect inUse_6, UInt<1>(0h0) node _T_15 = eq(UInt<3>(0h7), io.tagIn) when _T_15 : connect inUse_7, UInt<1>(0h0)

module TagMan( // @[TraceGen.scala:162:7] input clock, // @[TraceGen.scala:162:7] input reset, // @[TraceGen.scala:162:7] output io_available, // @[TraceGen.scala:163:14] output [2:0] io_tagOut, // @[TraceGen.scala:163:14] input io_take, // @[TraceGen.scala:163:14] input io_put, // @[TraceGen.scala:163:14] input [2:0] io_tagIn // @[TraceGen.scala:163:14] ); wire io_take_0 = io_take; // @[TraceGen.scala:162:7] wire io_put_0 = io_put; // @[TraceGen.scala:162:7] wire [2:0] io_tagIn_0 = io_tagIn; // @[TraceGen.scala:162:7] wire _io_available_T_14; // @[TraceGen.scala:190:19] wire io_available_0; // @[TraceGen.scala:162:7] wire [2:0] io_tagOut_0; // @[TraceGen.scala:162:7] reg inUse_0; // @[TraceGen.scala:180:41] reg inUse_1; // @[TraceGen.scala:180:41] reg inUse_2; // @[TraceGen.scala:180:41] reg inUse_3; // @[TraceGen.scala:180:41] reg inUse_4; // @[TraceGen.scala:180:41] reg inUse_5; // @[TraceGen.scala:180:41] reg inUse_6; // @[TraceGen.scala:180:41] reg inUse_7; // @[TraceGen.scala:180:41] reg [2:0] nextTag; // @[TraceGen.scala:186:24] assign io_tagOut_0 = nextTag; // @[TraceGen.scala:162:7, :186:24] wire _io_available_T = nextTag == 3'h1; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_1 = _io_available_T ? inUse_1 : inUse_0; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_2 = nextTag == 3'h2; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_3 = _io_available_T_2 ? inUse_2 : _io_available_T_1; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_4 = nextTag == 3'h3; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_5 = _io_available_T_4 ? inUse_3 : _io_available_T_3; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_6 = nextTag == 3'h4; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_7 = _io_available_T_6 ? inUse_4 : _io_available_T_5; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_8 = nextTag == 3'h5; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_9 = _io_available_T_8 ? inUse_5 : _io_available_T_7; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_10 = nextTag == 3'h6; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_11 = _io_available_T_10 ? inUse_6 : _io_available_T_9; // @[TraceGen.scala:180:41, :190:46] wire _io_available_T_12 = &nextTag; // @[TraceGen.scala:186:24, :190:46] wire _io_available_T_13 = _io_available_T_12 ? inUse_7 : _io_available_T_11; // @[TraceGen.scala:180:41, :190:46] assign _io_available_T_14 = ~_io_available_T_13; // @[TraceGen.scala:190:{19,46}] assign io_available_0 = _io_available_T_14; // @[TraceGen.scala:162:7, :190:19] wire [3:0] _nextTag_T = {1'h0, nextTag} + 4'h1; // @[TraceGen.scala:186:24, :197:24] wire [2:0] _nextTag_T_1 = _nextTag_T[2:0]; // @[TraceGen.scala:197:24] always @(posedge clock) begin // @[TraceGen.scala:162:7] if (reset) begin // @[TraceGen.scala:162:7] inUse_0 <= 1'h0; // @[TraceGen.scala:180:41] inUse_1 <= 1'h0; // @[TraceGen.scala:180:41] inUse_2 <= 1'h0; // @[TraceGen.scala:180:41] inUse_3 <= 1'h0; // @[TraceGen.scala:180:41] inUse_4 <= 1'h0; // @[TraceGen.scala:180:41] inUse_5 <= 1'h0; // @[TraceGen.scala:180:41] inUse_6 <= 1'h0; // @[TraceGen.scala:180:41] inUse_7 <= 1'h0; // @[TraceGen.scala:180:41] nextTag <= 3'h0; // @[TraceGen.scala:186:24] end else begin // @[TraceGen.scala:162:7] inUse_0 <= ~(io_put_0 & io_tagIn_0 == 3'h0) & (io_take_0 & nextTag == 3'h0 | inUse_0); // @[TraceGen.scala:162:7, :180:41, :186:24, :193:18, :195:{15,28,32}, :201:17, :203:{15,29,33}] inUse_1 <= ~(io_put_0 & io_tagIn_0 == 3'h1) & (io_take_0 & _io_available_T | inUse_1); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_2 <= ~(io_put_0 & io_tagIn_0 == 3'h2) & (io_take_0 & _io_available_T_2 | inUse_2); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_3 <= ~(io_put_0 & io_tagIn_0 == 3'h3) & (io_take_0 & _io_available_T_4 | inUse_3); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_4 <= ~(io_put_0 & io_tagIn_0 == 3'h4) & (io_take_0 & _io_available_T_6 | inUse_4); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_5 <= ~(io_put_0 & io_tagIn_0 == 3'h5) & (io_take_0 & _io_available_T_8 | inUse_5); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_6 <= ~(io_put_0 & io_tagIn_0 == 3'h6) & (io_take_0 & _io_available_T_10 | inUse_6); // @[TraceGen.scala:162:7, :180:41, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] inUse_7 <= ~(io_put_0 & (&io_tagIn_0)) & (io_take_0 & (&nextTag) | inUse_7); // @[TraceGen.scala:162:7, :180:41, :186:24, :190:46, :193:18, :195:{28,32}, :201:17, :203:{15,29,33}] if (io_take_0) // @[TraceGen.scala:162:7] nextTag <= _nextTag_T_1; // @[TraceGen.scala:186:24, :197:24] end always @(posedge) assign io_available = io_available_0; // @[TraceGen.scala:162:7] assign io_tagOut = io_tagOut_0; // @[TraceGen.scala:162:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_124 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_134 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_124( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_134 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_3 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_3( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_17 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<20> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_12, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_14_1, decoded_andMatrixOutputs_andMatrixInput_15) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_12_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_8_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_14_2) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_13_3, decoded_andMatrixOutputs_andMatrixInput_14_3) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_11_3, decoded_andMatrixOutputs_andMatrixInput_12_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_14_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_15_2, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_5, decoded_andMatrixOutputs_andMatrixInput_14_5) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_2) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_14_6, decoded_andMatrixOutputs_andMatrixInput_15_3) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_lo_lo_lo_3) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_12_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_14_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_14_8, decoded_andMatrixOutputs_andMatrixInput_15_4) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_12_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_4) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_12_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_14_9) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_15_5, decoded_andMatrixOutputs_andMatrixInput_16_2) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_13_10, decoded_andMatrixOutputs_andMatrixInput_14_10) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_lo_lo_lo_5) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_11_10, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_12_11, decoded_andMatrixOutputs_andMatrixInput_13_11) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_14_11) node decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_10_11, decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_lo_hi_lo_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_11) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_11, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_15_6, decoded_andMatrixOutputs_andMatrixInput_16_3) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_13_12, decoded_andMatrixOutputs_andMatrixInput_14_12) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_lo_lo_lo_6) node decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_11_12, decoded_andMatrixOutputs_andMatrixInput_12_12) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_lo_hi_lo_12) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_hi_lo_lo_12) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoded_plaInput, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_14_13, decoded_andMatrixOutputs_andMatrixInput_15_7) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_12_13, decoded_andMatrixOutputs_andMatrixInput_13_13) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_lo_lo_lo_7) node decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_10_13, decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_8_13, decoded_andMatrixOutputs_andMatrixInput_9_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_lo_hi_lo_13) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_hi_lo_lo_13) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_12_14, decoded_andMatrixOutputs_andMatrixInput_13_14) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_14_14) node decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_10_14, decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_8_14, decoded_andMatrixOutputs_andMatrixInput_9_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_lo_hi_lo_14) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_hi_lo_lo_14) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_14_15, decoded_andMatrixOutputs_andMatrixInput_15_8) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_12_15, decoded_andMatrixOutputs_andMatrixInput_13_15) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_lo_lo_lo_8) node decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_10_15, decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_8_15, decoded_andMatrixOutputs_andMatrixInput_9_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_lo_hi_lo_15) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_4_15, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_hi_lo_lo_15) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_12_16, decoded_andMatrixOutputs_andMatrixInput_13_16) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_14_16) node decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_8_16, decoded_andMatrixOutputs_andMatrixInput_9_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_16) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_hi_lo_lo_16) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_16, decoded_andMatrixOutputs_andMatrixInput_3_16) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_15_9, decoded_andMatrixOutputs_andMatrixInput_16_4) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_13_17, decoded_andMatrixOutputs_andMatrixInput_14_17) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_lo_lo_lo_9) node decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_11_17, decoded_andMatrixOutputs_andMatrixInput_12_17) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_lo_hi_lo_17) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_7_17, decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_hi_lo_lo_17) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_12_18, decoded_andMatrixOutputs_andMatrixInput_13_18) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_14_18) node decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_10_18, decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_8_18, decoded_andMatrixOutputs_andMatrixInput_9_18) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_lo_hi_lo_18) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_hi_lo_lo_18) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_15_10, decoded_andMatrixOutputs_andMatrixInput_16_5) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_13_19, decoded_andMatrixOutputs_andMatrixInput_14_19) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_lo_lo_lo_10) node decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_11_19, decoded_andMatrixOutputs_andMatrixInput_12_19) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_lo_hi_lo_19) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_19, decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_5_19, decoded_andMatrixOutputs_andMatrixInput_6_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_hi_lo_lo_19) node decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_19) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_14_20, decoded_andMatrixOutputs_andMatrixInput_15_11) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_12_20, decoded_andMatrixOutputs_andMatrixInput_13_20) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_lo_lo_lo_11) node decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_10_20, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_8_20, decoded_andMatrixOutputs_andMatrixInput_9_20) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_lo_hi_lo_20) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_4_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_hi_lo_lo_20) node decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_20) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_hi_hi_lo_20) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_8 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_6 = cat(decoded_orMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_20_2) node decoded_orMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_15_2, decoded_andMatrixOutputs_10_2) node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_7_2) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_6) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_7, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_7, decoded_orMatrixOutputs_hi_lo) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_7) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_8 = cat(decoded_orMatrixOutputs_lo_hi_8, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_8, decoded_orMatrixOutputs_hi_lo_1) node _decoded_orMatrixOutputs_T_16 = cat(decoded_orMatrixOutputs_hi_8, decoded_orMatrixOutputs_lo_8) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_9 = cat(decoded_orMatrixOutputs_lo_hi_9, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_9, decoded_orMatrixOutputs_hi_lo_2) node _decoded_orMatrixOutputs_T_18 = cat(decoded_orMatrixOutputs_hi_9, decoded_orMatrixOutputs_lo_9) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_10 = cat(decoded_orMatrixOutputs_lo_hi_10, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_10, decoded_orMatrixOutputs_hi_lo_3) node _decoded_orMatrixOutputs_T_20 = cat(decoded_orMatrixOutputs_hi_10, decoded_orMatrixOutputs_lo_10) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_11 = cat(decoded_orMatrixOutputs_lo_hi_11, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_11, decoded_orMatrixOutputs_hi_lo_4) node _decoded_orMatrixOutputs_T_22 = cat(decoded_orMatrixOutputs_hi_11, decoded_orMatrixOutputs_lo_11) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_12 = cat(decoded_orMatrixOutputs_lo_hi_12, decoded_orMatrixOutputs_lo_lo_5) node decoded_orMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_12, decoded_orMatrixOutputs_hi_lo_5) node _decoded_orMatrixOutputs_T_24 = cat(decoded_orMatrixOutputs_hi_12, decoded_orMatrixOutputs_lo_12) node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_lo_13 = cat(decoded_orMatrixOutputs_lo_hi_13, decoded_orMatrixOutputs_lo_lo_6) node decoded_orMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_16_2) node decoded_orMatrixOutputs_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_13, decoded_orMatrixOutputs_hi_lo_6) node _decoded_orMatrixOutputs_T_26 = cat(decoded_orMatrixOutputs_hi_13, decoded_orMatrixOutputs_lo_13) node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_lo_7 = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_decoded_orMatrixOutputs_T_15, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_lo_hi_14 = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo_14 = cat(decoded_orMatrixOutputs_lo_hi_14, decoded_orMatrixOutputs_lo_lo_7) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_25) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_7 = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_hi_7, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_14, decoded_orMatrixOutputs_hi_lo_7) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_14, decoded_orMatrixOutputs_lo_14) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo) node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_20, _decoded_invMatrixOutputs_T_19) node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, _decoded_invMatrixOutputs_T_21) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 15, 0) node _decoded_T_1 = shl(UInt<8>(0hff), 8) node _decoded_T_2 = xor(UInt<16>(0hffff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 8) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 7, 0) node _decoded_T_6 = shl(_decoded_T_5, 8) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 11, 0) node _decoded_T_11 = shl(_decoded_T_10, 4) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 4) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 11, 0) node _decoded_T_16 = shl(_decoded_T_15, 4) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 13, 0) node _decoded_T_21 = shl(_decoded_T_20, 2) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 2) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 13, 0) node _decoded_T_26 = shl(_decoded_T_25, 2) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(_decoded_T_22, 14, 0) node _decoded_T_31 = shl(_decoded_T_30, 1) node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31) node _decoded_T_33 = shr(_decoded_T_29, 1) node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32) node _decoded_T_35 = bits(_decoded_T_29, 14, 0) node _decoded_T_36 = shl(_decoded_T_35, 1) node _decoded_T_37 = not(_decoded_T_32) node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38) node _decoded_T_40 = bits(decoded_plaOutput, 23, 16) node _decoded_T_41 = shl(UInt<4>(0hf), 4) node _decoded_T_42 = xor(UInt<8>(0hff), _decoded_T_41) node _decoded_T_43 = shr(_decoded_T_40, 4) node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42) node _decoded_T_45 = bits(_decoded_T_40, 3, 0) node _decoded_T_46 = shl(_decoded_T_45, 4) node _decoded_T_47 = not(_decoded_T_42) node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47) node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48) node _decoded_T_50 = bits(_decoded_T_42, 5, 0) node _decoded_T_51 = shl(_decoded_T_50, 2) node _decoded_T_52 = xor(_decoded_T_42, _decoded_T_51) node _decoded_T_53 = shr(_decoded_T_49, 2) node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52) node _decoded_T_55 = bits(_decoded_T_49, 5, 0) node _decoded_T_56 = shl(_decoded_T_55, 2) node _decoded_T_57 = not(_decoded_T_52) node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57) node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58) node _decoded_T_60 = bits(_decoded_T_52, 6, 0) node _decoded_T_61 = shl(_decoded_T_60, 1) node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61) node _decoded_T_63 = shr(_decoded_T_59, 1) node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62) node _decoded_T_65 = bits(_decoded_T_59, 6, 0) node _decoded_T_66 = shl(_decoded_T_65, 1) node _decoded_T_67 = not(_decoded_T_62) node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67) node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68) node decoded = cat(_decoded_T_39, _decoded_T_69) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_1_3_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T node _io_resp_0_vc_sel_1_4_T = bits(decoded, 12, 12) connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T node _io_resp_0_vc_sel_1_5_T = bits(decoded, 13, 13) connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T node _io_resp_0_vc_sel_1_6_T = bits(decoded, 14, 14) connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T node _io_resp_0_vc_sel_1_7_T = bits(decoded, 15, 15) connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 16, 16) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 17, 17) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 18, 18) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_2_3_T = bits(decoded, 19, 19) connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T node _io_resp_0_vc_sel_2_4_T = bits(decoded, 20, 20) connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T node _io_resp_0_vc_sel_2_5_T = bits(decoded, 21, 21) connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T node _io_resp_0_vc_sel_2_6_T = bits(decoded, 22, 22) connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T node _io_resp_0_vc_sel_2_7_T = bits(decoded, 23, 23) connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<20> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_21) node _decoded_orMatrixOutputs_T_28 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_29 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_30 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_31 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_8 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_15 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_15 = cat(decoded_orMatrixOutputs_lo_hi_15, decoded_orMatrixOutputs_lo_lo_8) node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_29, _decoded_orMatrixOutputs_T_28) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_8 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_31) node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, _decoded_orMatrixOutputs_T_30) node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_hi_8, decoded_orMatrixOutputs_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_15, decoded_orMatrixOutputs_hi_lo_8) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_15, decoded_orMatrixOutputs_lo_15) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_1, 11, 11) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_1, 12, 12) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_1, 13, 13) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_1, 14, 14) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_1, 15, 15) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 16, 16) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 17, 17) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 18, 18) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 19, 19) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 20, 20) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 21, 21) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 22, 22) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, _decoded_invMatrixOutputs_T_42) node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_70 = bits(decoded_plaOutput_1, 15, 0) node _decoded_T_71 = shl(UInt<8>(0hff), 8) node _decoded_T_72 = xor(UInt<16>(0hffff), _decoded_T_71) node _decoded_T_73 = shr(_decoded_T_70, 8) node _decoded_T_74 = and(_decoded_T_73, _decoded_T_72) node _decoded_T_75 = bits(_decoded_T_70, 7, 0) node _decoded_T_76 = shl(_decoded_T_75, 8) node _decoded_T_77 = not(_decoded_T_72) node _decoded_T_78 = and(_decoded_T_76, _decoded_T_77) node _decoded_T_79 = or(_decoded_T_74, _decoded_T_78) node _decoded_T_80 = bits(_decoded_T_72, 11, 0) node _decoded_T_81 = shl(_decoded_T_80, 4) node _decoded_T_82 = xor(_decoded_T_72, _decoded_T_81) node _decoded_T_83 = shr(_decoded_T_79, 4) node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82) node _decoded_T_85 = bits(_decoded_T_79, 11, 0) node _decoded_T_86 = shl(_decoded_T_85, 4) node _decoded_T_87 = not(_decoded_T_82) node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87) node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88) node _decoded_T_90 = bits(_decoded_T_82, 13, 0) node _decoded_T_91 = shl(_decoded_T_90, 2) node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91) node _decoded_T_93 = shr(_decoded_T_89, 2) node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92) node _decoded_T_95 = bits(_decoded_T_89, 13, 0) node _decoded_T_96 = shl(_decoded_T_95, 2) node _decoded_T_97 = not(_decoded_T_92) node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97) node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98) node _decoded_T_100 = bits(_decoded_T_92, 14, 0) node _decoded_T_101 = shl(_decoded_T_100, 1) node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101) node _decoded_T_103 = shr(_decoded_T_99, 1) node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102) node _decoded_T_105 = bits(_decoded_T_99, 14, 0) node _decoded_T_106 = shl(_decoded_T_105, 1) node _decoded_T_107 = not(_decoded_T_102) node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107) node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108) node _decoded_T_110 = bits(decoded_plaOutput_1, 23, 16) node _decoded_T_111 = shl(UInt<4>(0hf), 4) node _decoded_T_112 = xor(UInt<8>(0hff), _decoded_T_111) node _decoded_T_113 = shr(_decoded_T_110, 4) node _decoded_T_114 = and(_decoded_T_113, _decoded_T_112) node _decoded_T_115 = bits(_decoded_T_110, 3, 0) node _decoded_T_116 = shl(_decoded_T_115, 4) node _decoded_T_117 = not(_decoded_T_112) node _decoded_T_118 = and(_decoded_T_116, _decoded_T_117) node _decoded_T_119 = or(_decoded_T_114, _decoded_T_118) node _decoded_T_120 = bits(_decoded_T_112, 5, 0) node _decoded_T_121 = shl(_decoded_T_120, 2) node _decoded_T_122 = xor(_decoded_T_112, _decoded_T_121) node _decoded_T_123 = shr(_decoded_T_119, 2) node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122) node _decoded_T_125 = bits(_decoded_T_119, 5, 0) node _decoded_T_126 = shl(_decoded_T_125, 2) node _decoded_T_127 = not(_decoded_T_122) node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127) node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128) node _decoded_T_130 = bits(_decoded_T_122, 6, 0) node _decoded_T_131 = shl(_decoded_T_130, 1) node _decoded_T_132 = xor(_decoded_T_122, _decoded_T_131) node _decoded_T_133 = shr(_decoded_T_129, 1) node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132) node _decoded_T_135 = bits(_decoded_T_129, 6, 0) node _decoded_T_136 = shl(_decoded_T_135, 1) node _decoded_T_137 = not(_decoded_T_132) node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137) node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138) node decoded_1 = cat(_decoded_T_109, _decoded_T_139) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 12, 12) connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 13, 13) connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 14, 14) connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 15, 15) connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 16, 16) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 17, 17) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 18, 18) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 19, 19) connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 20, 20) connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 21, 21) connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 22, 22) connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 23, 23) connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<20> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_22) node _decoded_orMatrixOutputs_T_32 = orr(decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_33 = orr(decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_34 = orr(decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_35 = orr(decoded_andMatrixOutputs_0_2_2) node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_9 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_16 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_orMatrixOutputs_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_16 = cat(decoded_orMatrixOutputs_lo_hi_16, decoded_orMatrixOutputs_lo_lo_9) node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_33, _decoded_orMatrixOutputs_T_32) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_9 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_35) node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, _decoded_orMatrixOutputs_T_34) node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_16 = cat(decoded_orMatrixOutputs_hi_hi_hi_9, decoded_orMatrixOutputs_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_16 = cat(decoded_orMatrixOutputs_hi_hi_16, decoded_orMatrixOutputs_hi_lo_9) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_16, decoded_orMatrixOutputs_lo_16) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_2, 11, 11) node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_2, 12, 12) node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_2, 13, 13) node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_2, 14, 14) node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_2, 15, 15) node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_2, 16, 16) node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_2, 17, 17) node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_2, 18, 18) node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_2, 19, 19) node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_2, 20, 20) node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_2, 21, 21) node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_2, 22, 22) node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_2, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_50, _decoded_invMatrixOutputs_T_49) node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, _decoded_invMatrixOutputs_T_51) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55) node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, _decoded_invMatrixOutputs_T_57) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_62, _decoded_invMatrixOutputs_T_61) node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, _decoded_invMatrixOutputs_T_60) node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_65, _decoded_invMatrixOutputs_T_64) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, _decoded_invMatrixOutputs_T_63) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_68, _decoded_invMatrixOutputs_T_67) node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, _decoded_invMatrixOutputs_T_66) node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_71, _decoded_invMatrixOutputs_T_70) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, _decoded_invMatrixOutputs_T_69) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_140 = bits(decoded_plaOutput_2, 15, 0) node _decoded_T_141 = shl(UInt<8>(0hff), 8) node _decoded_T_142 = xor(UInt<16>(0hffff), _decoded_T_141) node _decoded_T_143 = shr(_decoded_T_140, 8) node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142) node _decoded_T_145 = bits(_decoded_T_140, 7, 0) node _decoded_T_146 = shl(_decoded_T_145, 8) node _decoded_T_147 = not(_decoded_T_142) node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147) node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148) node _decoded_T_150 = bits(_decoded_T_142, 11, 0) node _decoded_T_151 = shl(_decoded_T_150, 4) node _decoded_T_152 = xor(_decoded_T_142, _decoded_T_151) node _decoded_T_153 = shr(_decoded_T_149, 4) node _decoded_T_154 = and(_decoded_T_153, _decoded_T_152) node _decoded_T_155 = bits(_decoded_T_149, 11, 0) node _decoded_T_156 = shl(_decoded_T_155, 4) node _decoded_T_157 = not(_decoded_T_152) node _decoded_T_158 = and(_decoded_T_156, _decoded_T_157) node _decoded_T_159 = or(_decoded_T_154, _decoded_T_158) node _decoded_T_160 = bits(_decoded_T_152, 13, 0) node _decoded_T_161 = shl(_decoded_T_160, 2) node _decoded_T_162 = xor(_decoded_T_152, _decoded_T_161) node _decoded_T_163 = shr(_decoded_T_159, 2) node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162) node _decoded_T_165 = bits(_decoded_T_159, 13, 0) node _decoded_T_166 = shl(_decoded_T_165, 2) node _decoded_T_167 = not(_decoded_T_162) node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_162, 14, 0) node _decoded_T_171 = shl(_decoded_T_170, 1) node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171) node _decoded_T_173 = shr(_decoded_T_169, 1) node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172) node _decoded_T_175 = bits(_decoded_T_169, 14, 0) node _decoded_T_176 = shl(_decoded_T_175, 1) node _decoded_T_177 = not(_decoded_T_172) node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177) node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178) node _decoded_T_180 = bits(decoded_plaOutput_2, 23, 16) node _decoded_T_181 = shl(UInt<4>(0hf), 4) node _decoded_T_182 = xor(UInt<8>(0hff), _decoded_T_181) node _decoded_T_183 = shr(_decoded_T_180, 4) node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182) node _decoded_T_185 = bits(_decoded_T_180, 3, 0) node _decoded_T_186 = shl(_decoded_T_185, 4) node _decoded_T_187 = not(_decoded_T_182) node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187) node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188) node _decoded_T_190 = bits(_decoded_T_182, 5, 0) node _decoded_T_191 = shl(_decoded_T_190, 2) node _decoded_T_192 = xor(_decoded_T_182, _decoded_T_191) node _decoded_T_193 = shr(_decoded_T_189, 2) node _decoded_T_194 = and(_decoded_T_193, _decoded_T_192) node _decoded_T_195 = bits(_decoded_T_189, 5, 0) node _decoded_T_196 = shl(_decoded_T_195, 2) node _decoded_T_197 = not(_decoded_T_192) node _decoded_T_198 = and(_decoded_T_196, _decoded_T_197) node _decoded_T_199 = or(_decoded_T_194, _decoded_T_198) node _decoded_T_200 = bits(_decoded_T_192, 6, 0) node _decoded_T_201 = shl(_decoded_T_200, 1) node _decoded_T_202 = xor(_decoded_T_192, _decoded_T_201) node _decoded_T_203 = shr(_decoded_T_199, 1) node _decoded_T_204 = and(_decoded_T_203, _decoded_T_202) node _decoded_T_205 = bits(_decoded_T_199, 6, 0) node _decoded_T_206 = shl(_decoded_T_205, 1) node _decoded_T_207 = not(_decoded_T_202) node _decoded_T_208 = and(_decoded_T_206, _decoded_T_207) node _decoded_T_209 = or(_decoded_T_204, _decoded_T_208) node decoded_2 = cat(_decoded_T_179, _decoded_T_209) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 12, 12) connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 13, 13) connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 14, 14) connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 15, 15) connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 16, 16) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 17, 17) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 18, 18) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 19, 19) connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 20, 20) connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 21, 21) connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 22, 22) connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 23, 23) connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T extmodule plusarg_reader_35 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20

module RouteComputer_17( // @[RouteComputer.scala:29:7] input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14] ); wire [15:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id[1]}; // @[pla.scala:78:21] wire [14:0] _decoded_andMatrixOutputs_T = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_1 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_2 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_4 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_6 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_7 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_8 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_9 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_11 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_13 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_14 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_15 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_16 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_18 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_20 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_1 = ~io_req_1_bits_flow_egress_node_id; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_21 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_2 = ~io_req_2_bits_flow_egress_node_id; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_22 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_2_vc_sel_0_4 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_0_5 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_0_6 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_2_vc_sel_0_7 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_4 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_5 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_6 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_0_7 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_2_1 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[4], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_2 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_3 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_5 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_7 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_18}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_1 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_2 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_3 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_4 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_5 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_6 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_7 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_20}; // @[pla.scala:98:{53,70}, :114:{19,36}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w32_16 : input clock : Clock input reset : Reset output io : { flip d : UInt<32>, q : UInt<32>, flip en : UInt<1>} reg cdc_reg : UInt<32>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg

module ClockCrossingReg_w32_16( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_32 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_288 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_32( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_288 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_SerialRAM : input clock : Clock input reset : Reset output auto : { flip manager_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire managerNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate managerNodeIn.d.bits.corrupt invalidate managerNodeIn.d.bits.data invalidate managerNodeIn.d.bits.denied invalidate managerNodeIn.d.bits.sink invalidate managerNodeIn.d.bits.source invalidate managerNodeIn.d.bits.size invalidate managerNodeIn.d.bits.param invalidate managerNodeIn.d.bits.opcode invalidate managerNodeIn.d.valid invalidate managerNodeIn.d.ready invalidate managerNodeIn.a.bits.corrupt invalidate managerNodeIn.a.bits.data invalidate managerNodeIn.a.bits.mask invalidate managerNodeIn.a.bits.address invalidate managerNodeIn.a.bits.source invalidate managerNodeIn.a.bits.size invalidate managerNodeIn.a.bits.param invalidate managerNodeIn.a.bits.opcode invalidate managerNodeIn.a.valid invalidate managerNodeIn.a.ready inst monitor of TLMonitor_74 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, managerNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, managerNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, managerNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, managerNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, managerNodeIn.d.bits.source connect monitor.io.in.d.bits.size, managerNodeIn.d.bits.size connect monitor.io.in.d.bits.param, managerNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, managerNodeIn.d.bits.opcode connect monitor.io.in.d.valid, managerNodeIn.d.valid connect monitor.io.in.d.ready, managerNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, managerNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, managerNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, managerNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, managerNodeIn.a.bits.address connect monitor.io.in.a.bits.source, managerNodeIn.a.bits.source connect monitor.io.in.a.bits.size, managerNodeIn.a.bits.size connect monitor.io.in.a.bits.param, managerNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, managerNodeIn.a.bits.opcode connect monitor.io.in.a.valid, managerNodeIn.a.valid connect monitor.io.in.a.ready, managerNodeIn.a.ready connect managerNodeIn, auto.manager_in wire client_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect client_tl.e.bits.sink, UInt<8>(0h0) connect client_tl.e.valid, UInt<1>(0h0) connect client_tl.e.ready, UInt<1>(0h0) connect client_tl.d.bits.corrupt, UInt<1>(0h0) connect client_tl.d.bits.data, UInt<64>(0h0) connect client_tl.d.bits.denied, UInt<1>(0h0) connect client_tl.d.bits.sink, UInt<8>(0h0) connect client_tl.d.bits.source, UInt<8>(0h0) connect client_tl.d.bits.size, UInt<8>(0h0) connect client_tl.d.bits.param, UInt<2>(0h0) connect client_tl.d.bits.opcode, UInt<3>(0h0) connect client_tl.d.valid, UInt<1>(0h0) connect client_tl.d.ready, UInt<1>(0h0) connect client_tl.c.bits.corrupt, UInt<1>(0h0) connect client_tl.c.bits.data, UInt<64>(0h0) connect client_tl.c.bits.address, UInt<64>(0h0) connect client_tl.c.bits.source, UInt<8>(0h0) connect client_tl.c.bits.size, UInt<8>(0h0) connect client_tl.c.bits.param, UInt<3>(0h0) connect client_tl.c.bits.opcode, UInt<3>(0h0) connect client_tl.c.valid, UInt<1>(0h0) connect client_tl.c.ready, UInt<1>(0h0) connect client_tl.b.bits.corrupt, UInt<1>(0h0) connect client_tl.b.bits.data, UInt<64>(0h0) connect client_tl.b.bits.mask, UInt<8>(0h0) connect client_tl.b.bits.address, UInt<64>(0h0) connect client_tl.b.bits.source, UInt<8>(0h0) connect client_tl.b.bits.size, UInt<8>(0h0) connect client_tl.b.bits.param, UInt<2>(0h0) connect client_tl.b.bits.opcode, UInt<3>(0h0) connect client_tl.b.valid, UInt<1>(0h0) connect client_tl.b.ready, UInt<1>(0h0) connect client_tl.a.bits.corrupt, UInt<1>(0h0) connect client_tl.a.bits.data, UInt<64>(0h0) connect client_tl.a.bits.mask, UInt<8>(0h0) connect client_tl.a.bits.address, UInt<64>(0h0) connect client_tl.a.bits.source, UInt<8>(0h0) connect client_tl.a.bits.size, UInt<8>(0h0) connect client_tl.a.bits.param, UInt<3>(0h0) connect client_tl.a.bits.opcode, UInt<3>(0h0) connect client_tl.a.valid, UInt<1>(0h0) connect client_tl.a.ready, UInt<1>(0h0) wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _out_channels_WIRE.bits.sink, UInt<4>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect out_channels_0_1.bits, _out_channels_WIRE.bits connect out_channels_0_1.valid, _out_channels_WIRE.valid connect out_channels_0_1.ready, _out_channels_WIRE.ready inst out_channels_0_2 of TLEToBeat_SerialRAM_a64d64s8k8z8c connect out_channels_0_2.clock, clock connect out_channels_0_2.reset, reset wire _out_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _out_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _out_channels_WIRE_1.bits.source, UInt<1>(0h0) connect _out_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _out_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _out_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE_1.valid, UInt<1>(0h0) connect _out_channels_WIRE_1.ready, UInt<1>(0h0) wire out_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_2_1.bits, _out_channels_WIRE_1.bits connect out_channels_2_1.valid, _out_channels_WIRE_1.valid connect out_channels_2_1.ready, _out_channels_WIRE_1.ready inst out_channels_2_2 of TLCToBeat_SerialRAM_a64d64s8k8z8c connect out_channels_2_2.clock, clock connect out_channels_2_2.reset, reset inst out_channels_4_2 of TLAToBeat_SerialRAM_a64d64s8k8z8c connect out_channels_4_2.clock, clock connect out_channels_4_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_0_2.io.protocol, out_channels_0_1 inst ser_0 of GenericSerializer_TLBeatw10_f32 connect ser_0.clock, clock connect ser_0.reset, reset connect ser_0.io.in, out_channels_0_2.io.beat connect io.ser[0].out.bits, ser_0.io.out.bits connect io.ser[0].out.valid, ser_0.io.out.valid connect ser_0.io.out.ready, io.ser[0].out.ready connect out_channels_2_2.io.protocol, out_channels_2_1 inst ser_2 of GenericSerializer_TLBeatw88_f32 connect ser_2.clock, clock connect ser_2.reset, reset connect ser_2.io.in, out_channels_2_2.io.beat connect io.ser[2].out.bits, ser_2.io.out.bits connect io.ser[2].out.valid, ser_2.io.out.valid connect ser_2.io.out.ready, io.ser[2].out.ready connect out_channels_4_2.io.protocol, managerNodeIn.a inst ser_4 of GenericSerializer_TLBeatw88_f32_1 connect ser_4.clock, clock connect ser_4.reset, reset connect ser_4.io.in, out_channels_4_2.io.beat connect io.ser[4].out.bits, ser_4.io.out.bits connect io.ser[4].out.valid, ser_4.io.out.valid connect ser_4.io.out.ready, io.ser[4].out.ready node _io_debug_ser_busy_T = or(ser_0.io.busy, ser_2.io.busy) node _io_debug_ser_busy_T_1 = or(_io_debug_ser_busy_T, ser_4.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T_1 inst in_channels_0_2 of TLEFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset inst in_channels_2_2 of TLCFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE.bits.data, UInt<64>(0h0) connect _in_channels_WIRE.bits.mask, UInt<8>(0h0) connect _in_channels_WIRE.bits.address, UInt<32>(0h0) connect _in_channels_WIRE.bits.source, UInt<1>(0h0) connect _in_channels_WIRE.bits.size, UInt<4>(0h0) connect _in_channels_WIRE.bits.param, UInt<2>(0h0) connect _in_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_3_1.bits, _in_channels_WIRE.bits connect in_channels_3_1.valid, _in_channels_WIRE.valid connect in_channels_3_1.ready, _in_channels_WIRE.ready inst in_channels_3_2 of TLBFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_SerialRAM_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect client_tl.e.bits.sink, in_channels_0_2.io.protocol.bits.sink connect client_tl.e.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, client_tl.e.ready inst des_0 of GenericDeserializer_TLBeatw10_f32_1 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect managerNodeIn.d.bits, in_channels_1_2.io.protocol.bits connect managerNodeIn.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, managerNodeIn.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32_1 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect client_tl.c.bits.corrupt, in_channels_2_2.io.protocol.bits.corrupt connect client_tl.c.bits.data, in_channels_2_2.io.protocol.bits.data connect client_tl.c.bits.address, in_channels_2_2.io.protocol.bits.address connect client_tl.c.bits.source, in_channels_2_2.io.protocol.bits.source connect client_tl.c.bits.size, in_channels_2_2.io.protocol.bits.size connect client_tl.c.bits.param, in_channels_2_2.io.protocol.bits.param connect client_tl.c.bits.opcode, in_channels_2_2.io.protocol.bits.opcode connect client_tl.c.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, client_tl.c.ready inst des_2 of GenericDeserializer_TLBeatw88_f32_2 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect in_channels_3_1.bits, in_channels_3_2.io.protocol.bits connect in_channels_3_1.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, in_channels_3_1.ready inst des_3 of GenericDeserializer_TLBeatw87_f32_1 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect client_tl.a.bits.corrupt, in_channels_4_2.io.protocol.bits.corrupt connect client_tl.a.bits.data, in_channels_4_2.io.protocol.bits.data connect client_tl.a.bits.mask, in_channels_4_2.io.protocol.bits.mask connect client_tl.a.bits.address, in_channels_4_2.io.protocol.bits.address connect client_tl.a.bits.source, in_channels_4_2.io.protocol.bits.source connect client_tl.a.bits.size, in_channels_4_2.io.protocol.bits.size connect client_tl.a.bits.param, in_channels_4_2.io.protocol.bits.param connect client_tl.a.bits.opcode, in_channels_4_2.io.protocol.bits.opcode connect client_tl.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, client_tl.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_3 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3

module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_0_out_ready, // @[TLSerdes.scala:40:16] output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_2_out_ready, // @[TLSerdes.scala:40:16] output io_ser_2_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_4_out_ready, // @[TLSerdes.scala:40:16] output io_ser_4_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28] wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_4_io_busy; // @[TLSerdes.scala:69:23] wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50] wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50] wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50] wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50] wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9] wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9] wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74] wire [3:0] out_channels_0_1_bits_sink = 4'h0; // @[Bundles.scala:267:61] wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17] wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61] wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire _io_debug_ser_busy_T_1; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy; // @[TLSerdes.scala:39:9] wire io_debug_des_busy; // @[TLSerdes.scala:39:9] assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_a_valid; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_c_valid; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71] wire client_tl_e_valid; // @[TLSerdes.scala:45:71] wire _io_debug_ser_busy_T; // @[package.scala:81:59] assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9] wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61] wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61] wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61] wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61] wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61] wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61] wire in_channels_3_1_valid; // @[Bundles.scala:264:61] assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLMonitor_74 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_0_2_io_beat_bits_head) ); // @[TLSerdes.scala:59:50] TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_2_2_io_beat_bits_head) ); // @[TLSerdes.scala:61:50] TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_a_ready), .io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21] .io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_4_2_io_beat_valid), .io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_4_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail) ); // @[TLSerdes.scala:63:50] GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_0_io_in_ready), .io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50] .io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_bits_flit (io_ser_0_out_bits_flit_0) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_2_io_in_ready), .io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50] .io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_2_out_valid_0), .io_out_bits_flit (io_ser_2_out_bits_flit_0), .io_busy (_io_debug_ser_busy_T) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_4_io_in_ready), .io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50] .io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50] .io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50] .io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50] .io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_4_out_valid_0), .io_out_bits_flit (io_ser_4_out_bits_flit_0), .io_busy (_ser_4_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_e_valid), .io_protocol_bits_sink (client_tl_e_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_protocol_valid (managerNodeIn_d_valid), .io_protocol_bits_opcode (managerNodeIn_d_bits_opcode), .io_protocol_bits_param (managerNodeIn_d_bits_param), .io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source), .io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink), .io_protocol_bits_denied (managerNodeIn_d_bits_denied), .io_protocol_bits_data (managerNodeIn_d_bits_data), .io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_c_valid), .io_protocol_bits_opcode (client_tl_c_bits_opcode), .io_protocol_bits_param (client_tl_c_bits_param), .io_protocol_bits_size (client_tl_c_bits_size), .io_protocol_bits_source (client_tl_c_bits_source), .io_protocol_bits_address (client_tl_c_bits_address), .io_protocol_bits_data (client_tl_c_bits_data), .io_protocol_bits_corrupt (client_tl_c_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_3_1_valid), .io_protocol_bits_opcode (in_channels_3_1_bits_opcode), .io_protocol_bits_param (in_channels_3_1_bits_param), .io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address), .io_protocol_bits_mask (in_channels_3_1_bits_mask), .io_protocol_bits_data (in_channels_3_1_bits_data), .io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_a_valid), .io_protocol_bits_opcode (client_tl_a_bits_opcode), .io_protocol_bits_param (client_tl_a_bits_param), .io_protocol_bits_size (client_tl_a_bits_size), .io_protocol_bits_source (client_tl_a_bits_source), .io_protocol_bits_address (client_tl_a_bits_address), .io_protocol_bits_mask (client_tl_a_bits_mask), .io_protocol_bits_data (client_tl_a_bits_data), .io_protocol_bits_corrupt (client_tl_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_14 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_14( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_34 node _source_ok_T_35 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[2]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[3]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[4]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[5]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[6]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[7]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_42, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_102 = eq(_T_101, UInt<1>(0h0)) node _T_103 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_104 = cvt(_T_103) node _T_105 = and(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = asSInt(_T_105) node _T_107 = eq(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = or(_T_102, _T_107) node _T_109 = and(_T_11, _T_24) node _T_110 = and(_T_109, _T_37) node _T_111 = and(_T_110, _T_50) node _T_112 = and(_T_111, _T_63) node _T_113 = and(_T_112, _T_76) node _T_114 = and(_T_113, _T_84) node _T_115 = and(_T_114, _T_92) node _T_116 = and(_T_115, _T_100) node _T_117 = and(_T_116, _T_108) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_117, UInt<1>(0h1), "") : assert_1 node _T_121 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_121 : node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<1>(0h0)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_5) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_132 = shr(io.in.a.bits.source, 2) node _T_133 = eq(_T_132, UInt<1>(0h1)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_6) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_137 = and(_T_135, _T_136) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_138 = shr(io.in.a.bits.source, 2) node _T_139 = eq(_T_138, UInt<2>(0h2)) node _T_140 = leq(UInt<1>(0h0), uncommonBits_7) node _T_141 = and(_T_139, _T_140) node _T_142 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_143 = and(_T_141, _T_142) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_144 = shr(io.in.a.bits.source, 2) node _T_145 = eq(_T_144, UInt<2>(0h3)) node _T_146 = leq(UInt<1>(0h0), uncommonBits_8) node _T_147 = and(_T_145, _T_146) node _T_148 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_149 = and(_T_147, _T_148) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_150 = shr(io.in.a.bits.source, 3) node _T_151 = eq(_T_150, UInt<3>(0h4)) node _T_152 = leq(UInt<1>(0h0), uncommonBits_9) node _T_153 = and(_T_151, _T_152) node _T_154 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_157 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_158 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_159 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_160 = or(_T_125, _T_131) node _T_161 = or(_T_160, _T_137) node _T_162 = or(_T_161, _T_143) node _T_163 = or(_T_162, _T_149) node _T_164 = or(_T_163, _T_155) node _T_165 = or(_T_164, _T_156) node _T_166 = or(_T_165, _T_157) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_159) node _T_169 = and(_T_124, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_172 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<27>(0h4000000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = and(_T_171, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = and(_T_170, _T_178) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_179, UInt<1>(0h1), "") : assert_2 node _T_183 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_184 = shr(io.in.a.bits.source, 2) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_10) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_189 = and(_T_187, _T_188) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_190 = shr(io.in.a.bits.source, 2) node _T_191 = eq(_T_190, UInt<1>(0h1)) node _T_192 = leq(UInt<1>(0h0), uncommonBits_11) node _T_193 = and(_T_191, _T_192) node _T_194 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_195 = and(_T_193, _T_194) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<2>(0h2)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_12) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<2>(0h3)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_13) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_208 = shr(io.in.a.bits.source, 3) node _T_209 = eq(_T_208, UInt<3>(0h4)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_14) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_215 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_217 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_183 connect _WIRE[1], _T_189 connect _WIRE[2], _T_195 connect _WIRE[3], _T_201 connect _WIRE[4], _T_207 connect _WIRE[5], _T_213 connect _WIRE[6], _T_214 connect _WIRE[7], _T_215 connect _WIRE[8], _T_216 connect _WIRE[9], _T_217 node _T_218 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_219 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_220 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_221 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_222 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_223 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_224 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_225 = mux(_WIRE[6], _T_218, UInt<1>(0h0)) node _T_226 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_227 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_228 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_229 = or(_T_219, _T_220) node _T_230 = or(_T_229, _T_221) node _T_231 = or(_T_230, _T_222) node _T_232 = or(_T_231, _T_223) node _T_233 = or(_T_232, _T_224) node _T_234 = or(_T_233, _T_225) node _T_235 = or(_T_234, _T_226) node _T_236 = or(_T_235, _T_227) node _T_237 = or(_T_236, _T_228) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_237 node _T_238 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_239 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_240 = and(_T_238, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<27>(0h4000000))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = and(_T_241, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = and(_WIRE_1, _T_248) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_249, UInt<1>(0h1), "") : assert_3 node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(source_ok, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_256 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_T_256, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_256, UInt<1>(0h1), "") : assert_5 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_263 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_263, UInt<1>(0h1), "") : assert_7 node _T_267 = not(io.in.a.bits.mask) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_268, UInt<1>(0h1), "") : assert_8 node _T_272 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_272, UInt<1>(0h1), "") : assert_9 node _T_276 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_276 : node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_281 = shr(io.in.a.bits.source, 2) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_15) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_287 = shr(io.in.a.bits.source, 2) node _T_288 = eq(_T_287, UInt<1>(0h1)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_16) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_293 = shr(io.in.a.bits.source, 2) node _T_294 = eq(_T_293, UInt<2>(0h2)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_17) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_298 = and(_T_296, _T_297) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_299 = shr(io.in.a.bits.source, 2) node _T_300 = eq(_T_299, UInt<2>(0h3)) node _T_301 = leq(UInt<1>(0h0), uncommonBits_18) node _T_302 = and(_T_300, _T_301) node _T_303 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_304 = and(_T_302, _T_303) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_305 = shr(io.in.a.bits.source, 3) node _T_306 = eq(_T_305, UInt<3>(0h4)) node _T_307 = leq(UInt<1>(0h0), uncommonBits_19) node _T_308 = and(_T_306, _T_307) node _T_309 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_314 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_315 = or(_T_280, _T_286) node _T_316 = or(_T_315, _T_292) node _T_317 = or(_T_316, _T_298) node _T_318 = or(_T_317, _T_304) node _T_319 = or(_T_318, _T_310) node _T_320 = or(_T_319, _T_311) node _T_321 = or(_T_320, _T_312) node _T_322 = or(_T_321, _T_313) node _T_323 = or(_T_322, _T_314) node _T_324 = and(_T_279, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_327 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<27>(0h4000000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = and(_T_326, _T_331) node _T_333 = or(UInt<1>(0h0), _T_332) node _T_334 = and(_T_325, _T_333) node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_T_334, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_334, UInt<1>(0h1), "") : assert_10 node _T_338 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<1>(0h0)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_20) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<1>(0h1)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_21) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_351 = shr(io.in.a.bits.source, 2) node _T_352 = eq(_T_351, UInt<2>(0h2)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_22) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_356 = and(_T_354, _T_355) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_357 = shr(io.in.a.bits.source, 2) node _T_358 = eq(_T_357, UInt<2>(0h3)) node _T_359 = leq(UInt<1>(0h0), uncommonBits_23) node _T_360 = and(_T_358, _T_359) node _T_361 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_362 = and(_T_360, _T_361) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_363 = shr(io.in.a.bits.source, 3) node _T_364 = eq(_T_363, UInt<3>(0h4)) node _T_365 = leq(UInt<1>(0h0), uncommonBits_24) node _T_366 = and(_T_364, _T_365) node _T_367 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_370 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_371 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_372 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_338 connect _WIRE_2[1], _T_344 connect _WIRE_2[2], _T_350 connect _WIRE_2[3], _T_356 connect _WIRE_2[4], _T_362 connect _WIRE_2[5], _T_368 connect _WIRE_2[6], _T_369 connect _WIRE_2[7], _T_370 connect _WIRE_2[8], _T_371 connect _WIRE_2[9], _T_372 node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_374 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_375 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE_2[6], _T_373, UInt<1>(0h0)) node _T_381 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_384 = or(_T_374, _T_375) node _T_385 = or(_T_384, _T_376) node _T_386 = or(_T_385, _T_377) node _T_387 = or(_T_386, _T_378) node _T_388 = or(_T_387, _T_379) node _T_389 = or(_T_388, _T_380) node _T_390 = or(_T_389, _T_381) node _T_391 = or(_T_390, _T_382) node _T_392 = or(_T_391, _T_383) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_392 node _T_393 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_394 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = and(_T_396, _T_401) node _T_403 = or(UInt<1>(0h0), _T_402) node _T_404 = and(_WIRE_3, _T_403) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_404, UInt<1>(0h1), "") : assert_11 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(source_ok, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_411 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_411, UInt<1>(0h1), "") : assert_13 node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(is_aligned, UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_418 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_418, UInt<1>(0h1), "") : assert_15 node _T_422 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_422, UInt<1>(0h1), "") : assert_16 node _T_426 = not(io.in.a.bits.mask) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_427, UInt<1>(0h1), "") : assert_17 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_431, UInt<1>(0h1), "") : assert_18 node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_25) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<1>(0h1)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_26) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_452 = shr(io.in.a.bits.source, 2) node _T_453 = eq(_T_452, UInt<2>(0h2)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_27) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<2>(0h3)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_28) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_464 = shr(io.in.a.bits.source, 3) node _T_465 = eq(_T_464, UInt<3>(0h4)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_29) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_473 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_474 = or(_T_439, _T_445) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_457) node _T_477 = or(_T_476, _T_463) node _T_478 = or(_T_477, _T_469) node _T_479 = or(_T_478, _T_470) node _T_480 = or(_T_479, _T_471) node _T_481 = or(_T_480, _T_472) node _T_482 = or(_T_481, _T_473) node _T_483 = and(_T_438, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_484, UInt<1>(0h1), "") : assert_19 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<27>(0h4000000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_498, UInt<1>(0h1), "") : assert_20 node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(source_ok, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(is_aligned, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_508 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_508, UInt<1>(0h1), "") : assert_23 node _T_512 = eq(io.in.a.bits.mask, mask) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_512, UInt<1>(0h1), "") : assert_24 node _T_516 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_516, UInt<1>(0h1), "") : assert_25 node _T_520 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_520 : node _T_521 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_522 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_523 = and(_T_521, _T_522) node _T_524 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<1>(0h0)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_30) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_531 = shr(io.in.a.bits.source, 2) node _T_532 = eq(_T_531, UInt<1>(0h1)) node _T_533 = leq(UInt<1>(0h0), uncommonBits_31) node _T_534 = and(_T_532, _T_533) node _T_535 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_537 = shr(io.in.a.bits.source, 2) node _T_538 = eq(_T_537, UInt<2>(0h2)) node _T_539 = leq(UInt<1>(0h0), uncommonBits_32) node _T_540 = and(_T_538, _T_539) node _T_541 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_542 = and(_T_540, _T_541) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_543 = shr(io.in.a.bits.source, 2) node _T_544 = eq(_T_543, UInt<2>(0h3)) node _T_545 = leq(UInt<1>(0h0), uncommonBits_33) node _T_546 = and(_T_544, _T_545) node _T_547 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_548 = and(_T_546, _T_547) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_549 = shr(io.in.a.bits.source, 3) node _T_550 = eq(_T_549, UInt<3>(0h4)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_34) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_559 = or(_T_524, _T_530) node _T_560 = or(_T_559, _T_536) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_548) node _T_563 = or(_T_562, _T_554) node _T_564 = or(_T_563, _T_555) node _T_565 = or(_T_564, _T_556) node _T_566 = or(_T_565, _T_557) node _T_567 = or(_T_566, _T_558) node _T_568 = and(_T_523, _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<27>(0h4000000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = and(_T_573, _T_578) node _T_580 = or(UInt<1>(0h0), _T_579) node _T_581 = and(_T_569, _T_580) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_581, UInt<1>(0h1), "") : assert_26 node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(source_ok, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(is_aligned, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_591 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_591, UInt<1>(0h1), "") : assert_29 node _T_595 = eq(io.in.a.bits.mask, mask) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_595, UInt<1>(0h1), "") : assert_30 node _T_599 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_599 : node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_602 = and(_T_600, _T_601) node _T_603 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<1>(0h0)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_35) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_610 = shr(io.in.a.bits.source, 2) node _T_611 = eq(_T_610, UInt<1>(0h1)) node _T_612 = leq(UInt<1>(0h0), uncommonBits_36) node _T_613 = and(_T_611, _T_612) node _T_614 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_615 = and(_T_613, _T_614) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_616 = shr(io.in.a.bits.source, 2) node _T_617 = eq(_T_616, UInt<2>(0h2)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_37) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_622 = shr(io.in.a.bits.source, 2) node _T_623 = eq(_T_622, UInt<2>(0h3)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_38) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_628 = shr(io.in.a.bits.source, 3) node _T_629 = eq(_T_628, UInt<3>(0h4)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_39) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_633 = and(_T_631, _T_632) node _T_634 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_635 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_636 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_637 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_638 = or(_T_603, _T_609) node _T_639 = or(_T_638, _T_615) node _T_640 = or(_T_639, _T_621) node _T_641 = or(_T_640, _T_627) node _T_642 = or(_T_641, _T_633) node _T_643 = or(_T_642, _T_634) node _T_644 = or(_T_643, _T_635) node _T_645 = or(_T_644, _T_636) node _T_646 = or(_T_645, _T_637) node _T_647 = and(_T_602, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = and(_T_648, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_660, UInt<1>(0h1), "") : assert_31 node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(source_ok, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(is_aligned, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_670 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_670, UInt<1>(0h1), "") : assert_34 node _T_674 = not(mask) node _T_675 = and(io.in.a.bits.mask, _T_674) node _T_676 = eq(_T_675, UInt<1>(0h0)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_676, UInt<1>(0h1), "") : assert_35 node _T_680 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_680 : node _T_681 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_682 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h0)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_40) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<1>(0h1)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_41) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h2)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_42) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<2>(0h3)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_43) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_709 = shr(io.in.a.bits.source, 3) node _T_710 = eq(_T_709, UInt<3>(0h4)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_44) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_718 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_719 = or(_T_684, _T_690) node _T_720 = or(_T_719, _T_696) node _T_721 = or(_T_720, _T_702) node _T_722 = or(_T_721, _T_708) node _T_723 = or(_T_722, _T_714) node _T_724 = or(_T_723, _T_715) node _T_725 = or(_T_724, _T_716) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_718) node _T_728 = and(_T_683, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<27>(0h4000000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = and(_T_730, _T_735) node _T_737 = or(UInt<1>(0h0), _T_736) node _T_738 = and(_T_729, _T_737) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_738, UInt<1>(0h1), "") : assert_36 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(source_ok, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(is_aligned, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_748 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_748, UInt<1>(0h1), "") : assert_39 node _T_752 = eq(io.in.a.bits.mask, mask) node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(_T_752, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_752, UInt<1>(0h1), "") : assert_40 node _T_756 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_756 : node _T_757 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_758 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_759 = and(_T_757, _T_758) node _T_760 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_761 = shr(io.in.a.bits.source, 2) node _T_762 = eq(_T_761, UInt<1>(0h0)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_45) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_767 = shr(io.in.a.bits.source, 2) node _T_768 = eq(_T_767, UInt<1>(0h1)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_46) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_773 = shr(io.in.a.bits.source, 2) node _T_774 = eq(_T_773, UInt<2>(0h2)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_47) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_779 = shr(io.in.a.bits.source, 2) node _T_780 = eq(_T_779, UInt<2>(0h3)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_48) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_785 = shr(io.in.a.bits.source, 3) node _T_786 = eq(_T_785, UInt<3>(0h4)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_49) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_790 = and(_T_788, _T_789) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_792 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_793 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_794 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_795 = or(_T_760, _T_766) node _T_796 = or(_T_795, _T_772) node _T_797 = or(_T_796, _T_778) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_790) node _T_800 = or(_T_799, _T_791) node _T_801 = or(_T_800, _T_792) node _T_802 = or(_T_801, _T_793) node _T_803 = or(_T_802, _T_794) node _T_804 = and(_T_759, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_807 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_808 = cvt(_T_807) node _T_809 = and(_T_808, asSInt(UInt<27>(0h4000000))) node _T_810 = asSInt(_T_809) node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0))) node _T_812 = and(_T_806, _T_811) node _T_813 = or(UInt<1>(0h0), _T_812) node _T_814 = and(_T_805, _T_813) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_814, UInt<1>(0h1), "") : assert_41 node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(source_ok, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(is_aligned, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_824 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_824, UInt<1>(0h1), "") : assert_44 node _T_828 = eq(io.in.a.bits.mask, mask) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_828, UInt<1>(0h1), "") : assert_45 node _T_832 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_832 : node _T_833 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_834 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_835 = and(_T_833, _T_834) node _T_836 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_837 = shr(io.in.a.bits.source, 2) node _T_838 = eq(_T_837, UInt<1>(0h0)) node _T_839 = leq(UInt<1>(0h0), uncommonBits_50) node _T_840 = and(_T_838, _T_839) node _T_841 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_842 = and(_T_840, _T_841) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_843 = shr(io.in.a.bits.source, 2) node _T_844 = eq(_T_843, UInt<1>(0h1)) node _T_845 = leq(UInt<1>(0h0), uncommonBits_51) node _T_846 = and(_T_844, _T_845) node _T_847 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_848 = and(_T_846, _T_847) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_849 = shr(io.in.a.bits.source, 2) node _T_850 = eq(_T_849, UInt<2>(0h2)) node _T_851 = leq(UInt<1>(0h0), uncommonBits_52) node _T_852 = and(_T_850, _T_851) node _T_853 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_854 = and(_T_852, _T_853) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_855 = shr(io.in.a.bits.source, 2) node _T_856 = eq(_T_855, UInt<2>(0h3)) node _T_857 = leq(UInt<1>(0h0), uncommonBits_53) node _T_858 = and(_T_856, _T_857) node _T_859 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_860 = and(_T_858, _T_859) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_861 = shr(io.in.a.bits.source, 3) node _T_862 = eq(_T_861, UInt<3>(0h4)) node _T_863 = leq(UInt<1>(0h0), uncommonBits_54) node _T_864 = and(_T_862, _T_863) node _T_865 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_866 = and(_T_864, _T_865) node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_871 = or(_T_836, _T_842) node _T_872 = or(_T_871, _T_848) node _T_873 = or(_T_872, _T_854) node _T_874 = or(_T_873, _T_860) node _T_875 = or(_T_874, _T_866) node _T_876 = or(_T_875, _T_867) node _T_877 = or(_T_876, _T_868) node _T_878 = or(_T_877, _T_869) node _T_879 = or(_T_878, _T_870) node _T_880 = and(_T_835, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_883 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<27>(0h4000000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = and(_T_882, _T_887) node _T_889 = or(UInt<1>(0h0), _T_888) node _T_890 = and(_T_881, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_890, UInt<1>(0h1), "") : assert_46 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_900 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_900, UInt<1>(0h1), "") : assert_49 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_904, UInt<1>(0h1), "") : assert_50 node _T_908 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_908, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_912 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_912, UInt<1>(0h1), "") : assert_52 node _source_ok_T_43 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_50 = shr(io.in.d.bits.source, 2) node _source_ok_T_51 = eq(_source_ok_T_50, UInt<1>(0h1)) node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_T_54 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<2>(0h2)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<2>(0h3)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 3) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<3>(0h4)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_77 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_43 connect _source_ok_WIRE_1[1], _source_ok_T_49 connect _source_ok_WIRE_1[2], _source_ok_T_55 connect _source_ok_WIRE_1[3], _source_ok_T_61 connect _source_ok_WIRE_1[4], _source_ok_T_67 connect _source_ok_WIRE_1[5], _source_ok_T_73 connect _source_ok_WIRE_1[6], _source_ok_T_74 connect _source_ok_WIRE_1[7], _source_ok_T_75 connect _source_ok_WIRE_1[8], _source_ok_T_76 connect _source_ok_WIRE_1[9], _source_ok_T_77 node _source_ok_T_78 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[2]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[3]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[4]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[5]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[6]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[7]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_85, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_916 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_916 : node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(source_ok_1, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_920 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_920, UInt<1>(0h1), "") : assert_54 node _T_924 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_924, UInt<1>(0h1), "") : assert_55 node _T_928 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_928, UInt<1>(0h1), "") : assert_56 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_932, UInt<1>(0h1), "") : assert_57 node _T_936 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_936 : node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(source_ok_1, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(sink_ok, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_943 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_943, UInt<1>(0h1), "") : assert_60 node _T_947 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_947, UInt<1>(0h1), "") : assert_61 node _T_951 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_951, UInt<1>(0h1), "") : assert_62 node _T_955 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_955, UInt<1>(0h1), "") : assert_63 node _T_959 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_960 = or(UInt<1>(0h0), _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_960, UInt<1>(0h1), "") : assert_64 node _T_964 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_964 : node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(source_ok_1, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(sink_ok, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_971 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_971, UInt<1>(0h1), "") : assert_67 node _T_975 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_975, UInt<1>(0h1), "") : assert_68 node _T_979 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(_T_979, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_979, UInt<1>(0h1), "") : assert_69 node _T_983 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_984 = or(_T_983, io.in.d.bits.corrupt) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_984, UInt<1>(0h1), "") : assert_70 node _T_988 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_989 = or(UInt<1>(0h0), _T_988) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_989, UInt<1>(0h1), "") : assert_71 node _T_993 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_993 : node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(source_ok_1, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_997 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_997, UInt<1>(0h1), "") : assert_73 node _T_1001 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_74 node _T_1005 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_75 node _T_1010 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1010 : node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok_1, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1014 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_77 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_78 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h0), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_79 node _T_1028 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok_1, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_81 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_82 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h0), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1045 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1049 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1053 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1057 = eq(a_first, UInt<1>(0h0)) node _T_1058 = and(io.in.a.valid, _T_1057) when _T_1058 : node _T_1059 = eq(io.in.a.bits.opcode, opcode) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_87 node _T_1063 = eq(io.in.a.bits.param, param) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_88 node _T_1067 = eq(io.in.a.bits.size, size) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_89 node _T_1071 = eq(io.in.a.bits.source, source) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_90 node _T_1075 = eq(io.in.a.bits.address, address) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_91 node _T_1079 = and(io.in.a.ready, io.in.a.valid) node _T_1080 = and(_T_1079, a_first) when _T_1080 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1081 = eq(d_first, UInt<1>(0h0)) node _T_1082 = and(io.in.d.valid, _T_1081) when _T_1082 : node _T_1083 = eq(io.in.d.bits.opcode, opcode_1) node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(_T_1083, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1083, UInt<1>(0h1), "") : assert_92 node _T_1087 = eq(io.in.d.bits.param, param_1) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_93 node _T_1091 = eq(io.in.d.bits.size, size_1) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_94 node _T_1095 = eq(io.in.d.bits.source, source_1) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_95 node _T_1099 = eq(io.in.d.bits.sink, sink) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_96 node _T_1103 = eq(io.in.d.bits.denied, denied) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_97 node _T_1107 = and(io.in.d.ready, io.in.d.valid) node _T_1108 = and(_T_1107, d_first) when _T_1108 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1109 = and(io.in.a.valid, a_first_1) node _T_1110 = and(_T_1109, UInt<1>(0h1)) when _T_1110 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1111 = and(io.in.a.ready, io.in.a.valid) node _T_1112 = and(_T_1111, a_first_1) node _T_1113 = and(_T_1112, UInt<1>(0h1)) when _T_1113 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1114 = dshr(inflight, io.in.a.bits.source) node _T_1115 = bits(_T_1114, 0, 0) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1120 = and(io.in.d.valid, d_first_1) node _T_1121 = and(_T_1120, UInt<1>(0h1)) node _T_1122 = eq(d_release_ack, UInt<1>(0h0)) node _T_1123 = and(_T_1121, _T_1122) when _T_1123 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_1) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = eq(d_release_ack, UInt<1>(0h0)) node _T_1128 = and(_T_1126, _T_1127) when _T_1128 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1133 = dshr(inflight, io.in.d.bits.source) node _T_1134 = bits(_T_1133, 0, 0) node _T_1135 = or(_T_1134, same_cycle_resp) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1139 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1140 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1141 = or(_T_1139, _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_100 node _T_1145 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_101 else : node _T_1149 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1150 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1151 = or(_T_1149, _T_1150) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_102 node _T_1155 = eq(io.in.d.bits.size, a_size_lookup) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_103 node _T_1159 = and(io.in.d.valid, d_first_1) node _T_1160 = and(_T_1159, a_first_1) node _T_1161 = and(_T_1160, io.in.a.valid) node _T_1162 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(d_release_ack, UInt<1>(0h0)) node _T_1165 = and(_T_1163, _T_1164) when _T_1165 : node _T_1166 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1167 = or(_T_1166, io.in.a.ready) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_104 node _T_1171 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1172 = orr(a_set_wo_ready) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = or(_T_1171, _T_1173) node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(_T_1174, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1174, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_54 node _T_1178 = orr(inflight) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1181 = or(_T_1179, _T_1180) node _T_1182 = lt(watchdog, plusarg_reader.out) node _T_1183 = or(_T_1181, _T_1182) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1187 = and(io.in.a.ready, io.in.a.valid) node _T_1188 = and(io.in.d.ready, io.in.d.valid) node _T_1189 = or(_T_1187, _T_1188) when _T_1189 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1190 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1191 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1192 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = and(_T_1190, _T_1193) when _T_1194 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1195 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1196 = and(_T_1195, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1197 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1198 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = and(_T_1196, _T_1199) when _T_1200 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1201 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1202 = bits(_T_1201, 0, 0) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1207 = and(io.in.d.valid, d_first_2) node _T_1208 = and(_T_1207, UInt<1>(0h1)) node _T_1209 = and(_T_1208, d_release_ack_1) when _T_1209 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = and(_T_1210, d_first_2) node _T_1212 = and(_T_1211, UInt<1>(0h1)) node _T_1213 = and(_T_1212, d_release_ack_1) when _T_1213 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1214 = and(io.in.d.valid, d_first_2) node _T_1215 = and(_T_1214, UInt<1>(0h1)) node _T_1216 = and(_T_1215, d_release_ack_1) when _T_1216 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1217 = dshr(inflight_1, io.in.d.bits.source) node _T_1218 = bits(_T_1217, 0, 0) node _T_1219 = or(_T_1218, same_cycle_resp_1) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1223 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_109 else : node _T_1227 = eq(io.in.d.bits.size, c_size_lookup) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_110 node _T_1231 = and(io.in.d.valid, d_first_2) node _T_1232 = and(_T_1231, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1233 = and(_T_1232, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1234 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1235 = and(_T_1233, _T_1234) node _T_1236 = and(_T_1235, d_release_ack_1) node _T_1237 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1238 = and(_T_1236, _T_1237) when _T_1238 : node _T_1239 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1240 = or(_T_1239, _WIRE_27.ready) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_111 node _T_1244 = orr(c_set_wo_ready) when _T_1244 : node _T_1245 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_55 node _T_1249 = orr(inflight_1) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) node _T_1251 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1252 = or(_T_1250, _T_1251) node _T_1253 = lt(watchdog_1, plusarg_reader_1.out) node _T_1254 = or(_T_1252, _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1258 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1259 = and(io.in.d.ready, io.in.d.valid) node _T_1260 = or(_T_1258, _T_1259) when _T_1260 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_42 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_43 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_44 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_50 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_56 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_62 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_45 = _source_ok_T_44 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = _source_ok_T_50 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_69 = _source_ok_T_68 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire _source_ok_T_77 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire _source_ok_T_78 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_85 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1187 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1187; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1187; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1260 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1260; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1260; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1260; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1113 = _T_1187 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1113 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1113 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1113 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1113 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1113 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1159 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1159 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1128 = _T_1260 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1128 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1128 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1128 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1231 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1231 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1213 = _T_1260 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1213 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1213 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1213 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_184 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_184( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate : input clock : Clock input reset : Reset output io : { flip chainIn : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, chainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, capture : { flip bits : { addr : UInt<7>, data : UInt<32>, resp : UInt<2>}, capture : UInt<1>}, update : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}} connect io.chainOut.shift, io.chainIn.shift connect io.chainOut.capture, io.chainIn.capture connect io.chainOut.update, io.chainIn.update reg regs_0 : UInt<1>, clock reg regs_1 : UInt<1>, clock reg regs_2 : UInt<1>, clock reg regs_3 : UInt<1>, clock reg regs_4 : UInt<1>, clock reg regs_5 : UInt<1>, clock reg regs_6 : UInt<1>, clock reg regs_7 : UInt<1>, clock reg regs_8 : UInt<1>, clock reg regs_9 : UInt<1>, clock reg regs_10 : UInt<1>, clock reg regs_11 : UInt<1>, clock reg regs_12 : UInt<1>, clock reg regs_13 : UInt<1>, clock reg regs_14 : UInt<1>, clock reg regs_15 : UInt<1>, clock reg regs_16 : UInt<1>, clock reg regs_17 : UInt<1>, clock reg regs_18 : UInt<1>, clock reg regs_19 : UInt<1>, clock reg regs_20 : UInt<1>, clock reg regs_21 : UInt<1>, clock reg regs_22 : UInt<1>, clock reg regs_23 : UInt<1>, clock reg regs_24 : UInt<1>, clock reg regs_25 : UInt<1>, clock reg regs_26 : UInt<1>, clock reg regs_27 : UInt<1>, clock reg regs_28 : UInt<1>, clock reg regs_29 : UInt<1>, clock reg regs_30 : UInt<1>, clock reg regs_31 : UInt<1>, clock reg regs_32 : UInt<1>, clock reg regs_33 : UInt<1>, clock reg regs_34 : UInt<1>, clock reg regs_35 : UInt<1>, clock reg regs_36 : UInt<1>, clock reg regs_37 : UInt<1>, clock reg regs_38 : UInt<1>, clock reg regs_39 : UInt<1>, clock reg regs_40 : UInt<1>, clock connect io.chainOut.data, regs_0 node updateBits_lo_lo_lo_lo = cat(regs_1, regs_0) node updateBits_lo_lo_lo_hi_hi = cat(regs_4, regs_3) node updateBits_lo_lo_lo_hi = cat(updateBits_lo_lo_lo_hi_hi, regs_2) node updateBits_lo_lo_lo = cat(updateBits_lo_lo_lo_hi, updateBits_lo_lo_lo_lo) node updateBits_lo_lo_hi_lo = cat(regs_6, regs_5) node updateBits_lo_lo_hi_hi_hi = cat(regs_9, regs_8) node updateBits_lo_lo_hi_hi = cat(updateBits_lo_lo_hi_hi_hi, regs_7) node updateBits_lo_lo_hi = cat(updateBits_lo_lo_hi_hi, updateBits_lo_lo_hi_lo) node updateBits_lo_lo = cat(updateBits_lo_lo_hi, updateBits_lo_lo_lo) node updateBits_lo_hi_lo_lo = cat(regs_11, regs_10) node updateBits_lo_hi_lo_hi_hi = cat(regs_14, regs_13) node updateBits_lo_hi_lo_hi = cat(updateBits_lo_hi_lo_hi_hi, regs_12) node updateBits_lo_hi_lo = cat(updateBits_lo_hi_lo_hi, updateBits_lo_hi_lo_lo) node updateBits_lo_hi_hi_lo = cat(regs_16, regs_15) node updateBits_lo_hi_hi_hi_hi = cat(regs_19, regs_18) node updateBits_lo_hi_hi_hi = cat(updateBits_lo_hi_hi_hi_hi, regs_17) node updateBits_lo_hi_hi = cat(updateBits_lo_hi_hi_hi, updateBits_lo_hi_hi_lo) node updateBits_lo_hi = cat(updateBits_lo_hi_hi, updateBits_lo_hi_lo) node updateBits_lo = cat(updateBits_lo_hi, updateBits_lo_lo) node updateBits_hi_lo_lo_lo = cat(regs_21, regs_20) node updateBits_hi_lo_lo_hi_hi = cat(regs_24, regs_23) node updateBits_hi_lo_lo_hi = cat(updateBits_hi_lo_lo_hi_hi, regs_22) node updateBits_hi_lo_lo = cat(updateBits_hi_lo_lo_hi, updateBits_hi_lo_lo_lo) node updateBits_hi_lo_hi_lo = cat(regs_26, regs_25) node updateBits_hi_lo_hi_hi_hi = cat(regs_29, regs_28) node updateBits_hi_lo_hi_hi = cat(updateBits_hi_lo_hi_hi_hi, regs_27) node updateBits_hi_lo_hi = cat(updateBits_hi_lo_hi_hi, updateBits_hi_lo_hi_lo) node updateBits_hi_lo = cat(updateBits_hi_lo_hi, updateBits_hi_lo_lo) node updateBits_hi_hi_lo_lo = cat(regs_31, regs_30) node updateBits_hi_hi_lo_hi_hi = cat(regs_34, regs_33) node updateBits_hi_hi_lo_hi = cat(updateBits_hi_hi_lo_hi_hi, regs_32) node updateBits_hi_hi_lo = cat(updateBits_hi_hi_lo_hi, updateBits_hi_hi_lo_lo) node updateBits_hi_hi_hi_lo_hi = cat(regs_37, regs_36) node updateBits_hi_hi_hi_lo = cat(updateBits_hi_hi_hi_lo_hi, regs_35) node updateBits_hi_hi_hi_hi_hi = cat(regs_40, regs_39) node updateBits_hi_hi_hi_hi = cat(updateBits_hi_hi_hi_hi_hi, regs_38) node updateBits_hi_hi_hi = cat(updateBits_hi_hi_hi_hi, updateBits_hi_hi_hi_lo) node updateBits_hi_hi = cat(updateBits_hi_hi_hi, updateBits_hi_hi_lo) node updateBits_hi = cat(updateBits_hi_hi, updateBits_hi_lo) node _updateBits_T = cat(updateBits_hi, updateBits_lo) node updateBits = bits(_updateBits_T, 40, 0) wire _io_update_bits_WIRE : { addr : UInt<7>, data : UInt<32>, op : UInt<2>} wire _io_update_bits_WIRE_1 : UInt<41> connect _io_update_bits_WIRE_1, updateBits node _io_update_bits_T = bits(_io_update_bits_WIRE_1, 1, 0) connect _io_update_bits_WIRE.op, _io_update_bits_T node _io_update_bits_T_1 = bits(_io_update_bits_WIRE_1, 33, 2) connect _io_update_bits_WIRE.data, _io_update_bits_T_1 node _io_update_bits_T_2 = bits(_io_update_bits_WIRE_1, 40, 34) connect _io_update_bits_WIRE.addr, _io_update_bits_T_2 connect io.update.bits, _io_update_bits_WIRE node captureBits_hi = cat(io.capture.bits.addr, io.capture.bits.data) node captureBits = cat(captureBits_hi, io.capture.bits.resp) when io.chainIn.capture : node _regs_0_T = bits(captureBits, 0, 0) connect regs_0, _regs_0_T node _regs_1_T = bits(captureBits, 1, 1) connect regs_1, _regs_1_T node _regs_2_T = bits(captureBits, 2, 2) connect regs_2, _regs_2_T node _regs_3_T = bits(captureBits, 3, 3) connect regs_3, _regs_3_T node _regs_4_T = bits(captureBits, 4, 4) connect regs_4, _regs_4_T node _regs_5_T = bits(captureBits, 5, 5) connect regs_5, _regs_5_T node _regs_6_T = bits(captureBits, 6, 6) connect regs_6, _regs_6_T node _regs_7_T = bits(captureBits, 7, 7) connect regs_7, _regs_7_T node _regs_8_T = bits(captureBits, 8, 8) connect regs_8, _regs_8_T node _regs_9_T = bits(captureBits, 9, 9) connect regs_9, _regs_9_T node _regs_10_T = bits(captureBits, 10, 10) connect regs_10, _regs_10_T node _regs_11_T = bits(captureBits, 11, 11) connect regs_11, _regs_11_T node _regs_12_T = bits(captureBits, 12, 12) connect regs_12, _regs_12_T node _regs_13_T = bits(captureBits, 13, 13) connect regs_13, _regs_13_T node _regs_14_T = bits(captureBits, 14, 14) connect regs_14, _regs_14_T node _regs_15_T = bits(captureBits, 15, 15) connect regs_15, _regs_15_T node _regs_16_T = bits(captureBits, 16, 16) connect regs_16, _regs_16_T node _regs_17_T = bits(captureBits, 17, 17) connect regs_17, _regs_17_T node _regs_18_T = bits(captureBits, 18, 18) connect regs_18, _regs_18_T node _regs_19_T = bits(captureBits, 19, 19) connect regs_19, _regs_19_T node _regs_20_T = bits(captureBits, 20, 20) connect regs_20, _regs_20_T node _regs_21_T = bits(captureBits, 21, 21) connect regs_21, _regs_21_T node _regs_22_T = bits(captureBits, 22, 22) connect regs_22, _regs_22_T node _regs_23_T = bits(captureBits, 23, 23) connect regs_23, _regs_23_T node _regs_24_T = bits(captureBits, 24, 24) connect regs_24, _regs_24_T node _regs_25_T = bits(captureBits, 25, 25) connect regs_25, _regs_25_T node _regs_26_T = bits(captureBits, 26, 26) connect regs_26, _regs_26_T node _regs_27_T = bits(captureBits, 27, 27) connect regs_27, _regs_27_T node _regs_28_T = bits(captureBits, 28, 28) connect regs_28, _regs_28_T node _regs_29_T = bits(captureBits, 29, 29) connect regs_29, _regs_29_T node _regs_30_T = bits(captureBits, 30, 30) connect regs_30, _regs_30_T node _regs_31_T = bits(captureBits, 31, 31) connect regs_31, _regs_31_T node _regs_32_T = bits(captureBits, 32, 32) connect regs_32, _regs_32_T node _regs_33_T = bits(captureBits, 33, 33) connect regs_33, _regs_33_T node _regs_34_T = bits(captureBits, 34, 34) connect regs_34, _regs_34_T node _regs_35_T = bits(captureBits, 35, 35) connect regs_35, _regs_35_T node _regs_36_T = bits(captureBits, 36, 36) connect regs_36, _regs_36_T node _regs_37_T = bits(captureBits, 37, 37) connect regs_37, _regs_37_T node _regs_38_T = bits(captureBits, 38, 38) connect regs_38, _regs_38_T node _regs_39_T = bits(captureBits, 39, 39) connect regs_39, _regs_39_T node _regs_40_T = bits(captureBits, 40, 40) connect regs_40, _regs_40_T connect io.capture.capture, UInt<1>(0h1) connect io.update.valid, UInt<1>(0h0) else : when io.chainIn.update : connect io.capture.capture, UInt<1>(0h0) connect io.update.valid, UInt<1>(0h1) else : when io.chainIn.shift : connect regs_40, io.chainIn.data connect regs_0, regs_1 connect regs_1, regs_2 connect regs_2, regs_3 connect regs_3, regs_4 connect regs_4, regs_5 connect regs_5, regs_6 connect regs_6, regs_7 connect regs_7, regs_8 connect regs_8, regs_9 connect regs_9, regs_10 connect regs_10, regs_11 connect regs_11, regs_12 connect regs_12, regs_13 connect regs_13, regs_14 connect regs_14, regs_15 connect regs_15, regs_16 connect regs_16, regs_17 connect regs_17, regs_18 connect regs_18, regs_19 connect regs_19, regs_20 connect regs_20, regs_21 connect regs_21, regs_22 connect regs_22, regs_23 connect regs_23, regs_24 connect regs_24, regs_25 connect regs_25, regs_26 connect regs_26, regs_27 connect regs_27, regs_28 connect regs_28, regs_29 connect regs_29, regs_30 connect regs_30, regs_31 connect regs_31, regs_32 connect regs_32, regs_33 connect regs_33, regs_34 connect regs_34, regs_35 connect regs_35, regs_36 connect regs_36, regs_37 connect regs_37, regs_38 connect regs_38, regs_39 connect regs_39, regs_40 connect io.capture.capture, UInt<1>(0h0) connect io.update.valid, UInt<1>(0h0) else : connect io.capture.capture, UInt<1>(0h0) connect io.update.valid, UInt<1>(0h0) node _T = and(io.chainIn.capture, io.chainIn.update) node _T_1 = eq(_T, UInt<1>(0h0)) node _T_2 = and(io.chainIn.capture, io.chainIn.shift) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = and(_T_1, _T_3) node _T_5 = and(io.chainIn.update, io.chainIn.shift) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = and(_T_4, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at JtagShifter.scala:185 assert(!(io.chainIn.capture && io.chainIn.update)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert

module CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate( // @[JtagShifter.scala:137:7] input clock, // @[JtagShifter.scala:137:7] input reset, // @[JtagShifter.scala:137:7] input io_chainIn_shift, // @[JtagShifter.scala:143:14] input io_chainIn_data, // @[JtagShifter.scala:143:14] input io_chainIn_capture, // @[JtagShifter.scala:143:14] input io_chainIn_update, // @[JtagShifter.scala:143:14] output io_chainOut_data, // @[JtagShifter.scala:143:14] input [6:0] io_capture_bits_addr, // @[JtagShifter.scala:143:14] input [31:0] io_capture_bits_data, // @[JtagShifter.scala:143:14] input [1:0] io_capture_bits_resp, // @[JtagShifter.scala:143:14] output io_capture_capture, // @[JtagShifter.scala:143:14] output io_update_valid, // @[JtagShifter.scala:143:14] output [6:0] io_update_bits_addr, // @[JtagShifter.scala:143:14] output [31:0] io_update_bits_data, // @[JtagShifter.scala:143:14] output [1:0] io_update_bits_op // @[JtagShifter.scala:143:14] ); reg regs_0; // @[JtagShifter.scala:156:39] reg regs_1; // @[JtagShifter.scala:156:39] reg regs_2; // @[JtagShifter.scala:156:39] reg regs_3; // @[JtagShifter.scala:156:39] reg regs_4; // @[JtagShifter.scala:156:39] reg regs_5; // @[JtagShifter.scala:156:39] reg regs_6; // @[JtagShifter.scala:156:39] reg regs_7; // @[JtagShifter.scala:156:39] reg regs_8; // @[JtagShifter.scala:156:39] reg regs_9; // @[JtagShifter.scala:156:39] reg regs_10; // @[JtagShifter.scala:156:39] reg regs_11; // @[JtagShifter.scala:156:39] reg regs_12; // @[JtagShifter.scala:156:39] reg regs_13; // @[JtagShifter.scala:156:39] reg regs_14; // @[JtagShifter.scala:156:39] reg regs_15; // @[JtagShifter.scala:156:39] reg regs_16; // @[JtagShifter.scala:156:39] reg regs_17; // @[JtagShifter.scala:156:39] reg regs_18; // @[JtagShifter.scala:156:39] reg regs_19; // @[JtagShifter.scala:156:39] reg regs_20; // @[JtagShifter.scala:156:39] reg regs_21; // @[JtagShifter.scala:156:39] reg regs_22; // @[JtagShifter.scala:156:39] reg regs_23; // @[JtagShifter.scala:156:39] reg regs_24; // @[JtagShifter.scala:156:39] reg regs_25; // @[JtagShifter.scala:156:39] reg regs_26; // @[JtagShifter.scala:156:39] reg regs_27; // @[JtagShifter.scala:156:39] reg regs_28; // @[JtagShifter.scala:156:39] reg regs_29; // @[JtagShifter.scala:156:39] reg regs_30; // @[JtagShifter.scala:156:39] reg regs_31; // @[JtagShifter.scala:156:39] reg regs_32; // @[JtagShifter.scala:156:39] reg regs_33; // @[JtagShifter.scala:156:39] reg regs_34; // @[JtagShifter.scala:156:39] reg regs_35; // @[JtagShifter.scala:156:39] reg regs_36; // @[JtagShifter.scala:156:39] reg regs_37; // @[JtagShifter.scala:156:39] reg regs_38; // @[JtagShifter.scala:156:39] reg regs_39; // @[JtagShifter.scala:156:39] reg regs_40; // @[JtagShifter.scala:156:39]

Generate the Verilog code corresponding to this FIRRTL code module PE_488 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_232 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_488( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_232 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<17>(0h10000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_50 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_51 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_189 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_199 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_189( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_199 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_9 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x

module PMPChecker_s3_9( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_156 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_177 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_156( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_177 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_52 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_5 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_109 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_52 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_5 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleD_a32d64s1k3z4u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleD_a32d64s1k3z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_sink, // @[Repeater.scala:13:14] input io_enq_bits_denied, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_sink, // @[Repeater.scala:13:14] output io_deq_bits_denied, // @[Repeater.scala:13:14] output [63:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [1:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [2:0] saved_sink; // @[Repeater.scala:21:18] reg saved_denied; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_sink <= io_enq_bits_sink; // @[Repeater.scala:21:18] saved_denied <= io_enq_bits_denied; // @[Repeater.scala:21:18] saved_data <= io_enq_bits_data; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module PE_25 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_25( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PlusArgTimeout_2 : input clock : Clock input reset : Reset output io : { flip count : UInt<32>} inst plusarg_reader of plusarg_reader_104 node _T = gt(plusarg_reader.out, UInt<1>(0h0)) when _T : node _T_1 = lt(io.count, plusarg_reader.out) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert

module PlusArgTimeout_2( // @[PlusArg.scala:58:7] input clock, // @[PlusArg.scala:58:7] input reset, // @[PlusArg.scala:58:7] input [31:0] io_count // @[PlusArg.scala:59:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19] wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_36 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<17>(0h10000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = or(_T_156, _T_161) node _T_163 = and(_T_151, _T_162) node _T_164 = or(UInt<1>(0h0), _T_163) node _T_165 = and(_T_149, _T_164) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_165, UInt<1>(0h1), "") : assert_2 node _T_169 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_170 = shr(io.in.a.bits.source, 2) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = leq(UInt<1>(0h0), uncommonBits_8) node _T_173 = and(_T_171, _T_172) node _T_174 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_176 = shr(io.in.a.bits.source, 2) node _T_177 = eq(_T_176, UInt<1>(0h1)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_9) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_181 = and(_T_179, _T_180) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_182 = shr(io.in.a.bits.source, 2) node _T_183 = eq(_T_182, UInt<2>(0h2)) node _T_184 = leq(UInt<1>(0h0), uncommonBits_10) node _T_185 = and(_T_183, _T_184) node _T_186 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_187 = and(_T_185, _T_186) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_188 = shr(io.in.a.bits.source, 2) node _T_189 = eq(_T_188, UInt<2>(0h3)) node _T_190 = leq(UInt<1>(0h0), uncommonBits_11) node _T_191 = and(_T_189, _T_190) node _T_192 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_193 = and(_T_191, _T_192) node _T_194 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_195 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_196 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_197 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_169 connect _WIRE[1], _T_175 connect _WIRE[2], _T_181 connect _WIRE[3], _T_187 connect _WIRE[4], _T_193 connect _WIRE[5], _T_194 connect _WIRE[6], _T_195 connect _WIRE[7], _T_196 connect _WIRE[8], _T_197 node _T_198 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_199 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_200 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_202 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[5], _T_198, UInt<1>(0h0)) node _T_206 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[7], _T_199, UInt<1>(0h0)) node _T_208 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = or(_T_200, _T_201) node _T_210 = or(_T_209, _T_202) node _T_211 = or(_T_210, _T_203) node _T_212 = or(_T_211, _T_204) node _T_213 = or(_T_212, _T_205) node _T_214 = or(_T_213, _T_206) node _T_215 = or(_T_214, _T_207) node _T_216 = or(_T_215, _T_208) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h10000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h10000000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_12) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_13) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_14) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_15) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_294 = or(_T_265, _T_271) node _T_295 = or(_T_294, _T_277) node _T_296 = or(_T_295, _T_283) node _T_297 = or(_T_296, _T_289) node _T_298 = or(_T_297, _T_290) node _T_299 = or(_T_298, _T_291) node _T_300 = or(_T_299, _T_292) node _T_301 = or(_T_300, _T_293) node _T_302 = and(_T_264, _T_301) node _T_303 = or(UInt<1>(0h0), _T_302) node _T_304 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<29>(0h10000000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = or(_T_310, _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = and(_T_303, _T_318) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_319, UInt<1>(0h1), "") : assert_10 node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_16) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_17) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_18) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_19) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_349 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_323 connect _WIRE_2[1], _T_329 connect _WIRE_2[2], _T_335 connect _WIRE_2[3], _T_341 connect _WIRE_2[4], _T_347 connect _WIRE_2[5], _T_348 connect _WIRE_2[6], _T_349 connect _WIRE_2[7], _T_350 connect _WIRE_2[8], _T_351 node _T_352 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_353 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_354 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[5], _T_352, UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[7], _T_353, UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = or(_T_354, _T_355) node _T_364 = or(_T_363, _T_356) node _T_365 = or(_T_364, _T_357) node _T_366 = or(_T_365, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_370 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<17>(0h10000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<29>(0h10000000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = or(_T_379, _T_384) node _T_386 = and(_T_374, _T_385) node _T_387 = or(UInt<1>(0h0), _T_386) node _T_388 = and(_WIRE_3, _T_387) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_388, UInt<1>(0h1), "") : assert_11 node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(source_ok, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_395 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_395, UInt<1>(0h1), "") : assert_13 node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(is_aligned, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_402 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_402, UInt<1>(0h1), "") : assert_15 node _T_406 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_406, UInt<1>(0h1), "") : assert_16 node _T_410 = not(io.in.a.bits.mask) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_411, UInt<1>(0h1), "") : assert_17 node _T_415 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_415, UInt<1>(0h1), "") : assert_18 node _T_419 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_419 : node _T_420 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_421 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_422 = and(_T_420, _T_421) node _T_423 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_424 = shr(io.in.a.bits.source, 2) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_20) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_430 = shr(io.in.a.bits.source, 2) node _T_431 = eq(_T_430, UInt<1>(0h1)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_21) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<2>(0h2)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_22) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_442 = shr(io.in.a.bits.source, 2) node _T_443 = eq(_T_442, UInt<2>(0h3)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_23) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_452 = or(_T_423, _T_429) node _T_453 = or(_T_452, _T_435) node _T_454 = or(_T_453, _T_441) node _T_455 = or(_T_454, _T_447) node _T_456 = or(_T_455, _T_448) node _T_457 = or(_T_456, _T_449) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = and(_T_422, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_461, UInt<1>(0h1), "") : assert_19 node _T_465 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_466 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_467 = and(_T_465, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<29>(0h10000000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = or(_T_473, _T_478) node _T_480 = and(_T_468, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_481, UInt<1>(0h1), "") : assert_20 node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(source_ok, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(is_aligned, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_491 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_491, UInt<1>(0h1), "") : assert_23 node _T_495 = eq(io.in.a.bits.mask, mask) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_495, UInt<1>(0h1), "") : assert_24 node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_499, UInt<1>(0h1), "") : assert_25 node _T_503 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_503 : node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_508 = shr(io.in.a.bits.source, 2) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = leq(UInt<1>(0h0), uncommonBits_24) node _T_511 = and(_T_509, _T_510) node _T_512 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_513 = and(_T_511, _T_512) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_514 = shr(io.in.a.bits.source, 2) node _T_515 = eq(_T_514, UInt<1>(0h1)) node _T_516 = leq(UInt<1>(0h0), uncommonBits_25) node _T_517 = and(_T_515, _T_516) node _T_518 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_519 = and(_T_517, _T_518) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_520 = shr(io.in.a.bits.source, 2) node _T_521 = eq(_T_520, UInt<2>(0h2)) node _T_522 = leq(UInt<1>(0h0), uncommonBits_26) node _T_523 = and(_T_521, _T_522) node _T_524 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_525 = and(_T_523, _T_524) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<2>(0h3)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_27) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_536 = or(_T_507, _T_513) node _T_537 = or(_T_536, _T_519) node _T_538 = or(_T_537, _T_525) node _T_539 = or(_T_538, _T_531) node _T_540 = or(_T_539, _T_532) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = and(_T_506, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_547 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_548 = and(_T_546, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_551 = cvt(_T_550) node _T_552 = and(_T_551, asSInt(UInt<17>(0h10000))) node _T_553 = asSInt(_T_552) node _T_554 = eq(_T_553, asSInt(UInt<1>(0h0))) node _T_555 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<29>(0h10000000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = or(_T_554, _T_559) node _T_561 = and(_T_549, _T_560) node _T_562 = or(UInt<1>(0h0), _T_561) node _T_563 = and(_T_545, _T_562) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_563, UInt<1>(0h1), "") : assert_26 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(source_ok, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(is_aligned, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_573 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_573, UInt<1>(0h1), "") : assert_29 node _T_577 = eq(io.in.a.bits.mask, mask) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_577, UInt<1>(0h1), "") : assert_30 node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_581 : node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_584 = and(_T_582, _T_583) node _T_585 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h0)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_28) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<1>(0h1)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_29) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h2)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_30) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<2>(0h3)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_31) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_613 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_614 = or(_T_585, _T_591) node _T_615 = or(_T_614, _T_597) node _T_616 = or(_T_615, _T_603) node _T_617 = or(_T_616, _T_609) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_584, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<17>(0h10000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<29>(0h10000000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = or(_T_632, _T_637) node _T_639 = and(_T_627, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_623, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_641, UInt<1>(0h1), "") : assert_31 node _T_645 = asUInt(reset) node _T_646 = eq(_T_645, UInt<1>(0h0)) when _T_646 : node _T_647 = eq(source_ok, UInt<1>(0h0)) when _T_647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(is_aligned, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_651 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_651, UInt<1>(0h1), "") : assert_34 node _T_655 = not(mask) node _T_656 = and(io.in.a.bits.mask, _T_655) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(_T_657, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_657, UInt<1>(0h1), "") : assert_35 node _T_661 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_661 : node _T_662 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_663 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h0)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_32) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<1>(0h1)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_33) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h2)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_34) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<2>(0h3)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_35) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = or(_T_665, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = or(_T_700, _T_693) node _T_702 = and(_T_664, _T_701) node _T_703 = or(UInt<1>(0h0), _T_702) node _T_704 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_705 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<17>(0h10000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<29>(0h10000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = or(_T_712, _T_717) node _T_719 = and(_T_707, _T_718) node _T_720 = or(UInt<1>(0h0), _T_719) node _T_721 = and(_T_703, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_721, UInt<1>(0h1), "") : assert_36 node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(source_ok, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(is_aligned, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_731 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_731, UInt<1>(0h1), "") : assert_39 node _T_735 = eq(io.in.a.bits.mask, mask) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_735, UInt<1>(0h1), "") : assert_40 node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_739 : node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<1>(0h0)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_36) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_750 = shr(io.in.a.bits.source, 2) node _T_751 = eq(_T_750, UInt<1>(0h1)) node _T_752 = leq(UInt<1>(0h0), uncommonBits_37) node _T_753 = and(_T_751, _T_752) node _T_754 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_755 = and(_T_753, _T_754) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_756 = shr(io.in.a.bits.source, 2) node _T_757 = eq(_T_756, UInt<2>(0h2)) node _T_758 = leq(UInt<1>(0h0), uncommonBits_38) node _T_759 = and(_T_757, _T_758) node _T_760 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_762 = shr(io.in.a.bits.source, 2) node _T_763 = eq(_T_762, UInt<2>(0h3)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_39) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_772 = or(_T_743, _T_749) node _T_773 = or(_T_772, _T_755) node _T_774 = or(_T_773, _T_761) node _T_775 = or(_T_774, _T_767) node _T_776 = or(_T_775, _T_768) node _T_777 = or(_T_776, _T_769) node _T_778 = or(_T_777, _T_770) node _T_779 = or(_T_778, _T_771) node _T_780 = and(_T_742, _T_779) node _T_781 = or(UInt<1>(0h0), _T_780) node _T_782 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_783 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_784 = and(_T_782, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_792 = cvt(_T_791) node _T_793 = and(_T_792, asSInt(UInt<29>(0h10000000))) node _T_794 = asSInt(_T_793) node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0))) node _T_796 = or(_T_790, _T_795) node _T_797 = and(_T_785, _T_796) node _T_798 = or(UInt<1>(0h0), _T_797) node _T_799 = and(_T_781, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_799, UInt<1>(0h1), "") : assert_41 node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(source_ok, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(is_aligned, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_809 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_809, UInt<1>(0h1), "") : assert_44 node _T_813 = eq(io.in.a.bits.mask, mask) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_813, UInt<1>(0h1), "") : assert_45 node _T_817 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_817 : node _T_818 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_819 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_820 = and(_T_818, _T_819) node _T_821 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_822 = shr(io.in.a.bits.source, 2) node _T_823 = eq(_T_822, UInt<1>(0h0)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_40) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_828 = shr(io.in.a.bits.source, 2) node _T_829 = eq(_T_828, UInt<1>(0h1)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_41) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_833 = and(_T_831, _T_832) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_834 = shr(io.in.a.bits.source, 2) node _T_835 = eq(_T_834, UInt<2>(0h2)) node _T_836 = leq(UInt<1>(0h0), uncommonBits_42) node _T_837 = and(_T_835, _T_836) node _T_838 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_839 = and(_T_837, _T_838) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_840 = shr(io.in.a.bits.source, 2) node _T_841 = eq(_T_840, UInt<2>(0h3)) node _T_842 = leq(UInt<1>(0h0), uncommonBits_43) node _T_843 = and(_T_841, _T_842) node _T_844 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_845 = and(_T_843, _T_844) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_850 = or(_T_821, _T_827) node _T_851 = or(_T_850, _T_833) node _T_852 = or(_T_851, _T_839) node _T_853 = or(_T_852, _T_845) node _T_854 = or(_T_853, _T_846) node _T_855 = or(_T_854, _T_847) node _T_856 = or(_T_855, _T_848) node _T_857 = or(_T_856, _T_849) node _T_858 = and(_T_820, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_861 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_862 = and(_T_860, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<17>(0h10000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<29>(0h10000000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = or(_T_868, _T_873) node _T_875 = and(_T_863, _T_874) node _T_876 = or(UInt<1>(0h0), _T_875) node _T_877 = and(_T_859, _T_876) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_877, UInt<1>(0h1), "") : assert_46 node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(source_ok, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(is_aligned, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_887 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_887, UInt<1>(0h1), "") : assert_49 node _T_891 = eq(io.in.a.bits.mask, mask) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_891, UInt<1>(0h1), "") : assert_50 node _T_895 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_895, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_899 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_899, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_903 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_903 : node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(source_ok_1, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_907 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_907, UInt<1>(0h1), "") : assert_54 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_911, UInt<1>(0h1), "") : assert_55 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_915, UInt<1>(0h1), "") : assert_56 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_919, UInt<1>(0h1), "") : assert_57 node _T_923 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_923 : node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(source_ok_1, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(sink_ok, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_930, UInt<1>(0h1), "") : assert_60 node _T_934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_934, UInt<1>(0h1), "") : assert_61 node _T_938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_938, UInt<1>(0h1), "") : assert_62 node _T_942 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_942, UInt<1>(0h1), "") : assert_63 node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_947 = or(UInt<1>(0h1), _T_946) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_947, UInt<1>(0h1), "") : assert_64 node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(source_ok_1, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(sink_ok, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_958 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_958, UInt<1>(0h1), "") : assert_67 node _T_962 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_962, UInt<1>(0h1), "") : assert_68 node _T_966 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_966, UInt<1>(0h1), "") : assert_69 node _T_970 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_971 = or(_T_970, io.in.d.bits.corrupt) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_971, UInt<1>(0h1), "") : assert_70 node _T_975 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_976 = or(UInt<1>(0h1), _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_976, UInt<1>(0h1), "") : assert_71 node _T_980 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_980 : node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(source_ok_1, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_984 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_984, UInt<1>(0h1), "") : assert_73 node _T_988 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_988, UInt<1>(0h1), "") : assert_74 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(UInt<1>(0h1), _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_993, UInt<1>(0h1), "") : assert_75 node _T_997 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_997 : node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(source_ok_1, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_77 node _T_1005 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1006 = or(_T_1005, io.in.d.bits.corrupt) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_78 node _T_1010 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1011 = or(UInt<1>(0h1), _T_1010) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_79 node _T_1015 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1015 : node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(source_ok_1, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_81 node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_82 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(UInt<1>(0h1), _T_1027) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1032 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_84 node _T_1036 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) node _T_1038 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<1>(0h0))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1044 = shr(io.in.b.bits.source, 2) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) node _T_1046 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) node _T_1051 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = or(_T_1050, _T_1055) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1057 = shr(io.in.b.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<1>(0h1)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) node _T_1064 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1065 = cvt(_T_1064) node _T_1066 = and(_T_1065, asSInt(UInt<1>(0h0))) node _T_1067 = asSInt(_T_1066) node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0))) node _T_1069 = or(_T_1063, _T_1068) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1070 = shr(io.in.b.bits.source, 2) node _T_1071 = eq(_T_1070, UInt<2>(0h2)) node _T_1072 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1073 = and(_T_1071, _T_1072) node _T_1074 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) node _T_1077 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<1>(0h0))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1083 = shr(io.in.b.bits.source, 2) node _T_1084 = eq(_T_1083, UInt<2>(0h3)) node _T_1085 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) node _T_1090 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1091 = cvt(_T_1090) node _T_1092 = and(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = asSInt(_T_1092) node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0))) node _T_1095 = or(_T_1089, _T_1094) node _T_1096 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1099 = cvt(_T_1098) node _T_1100 = and(_T_1099, asSInt(UInt<1>(0h0))) node _T_1101 = asSInt(_T_1100) node _T_1102 = eq(_T_1101, asSInt(UInt<1>(0h0))) node _T_1103 = or(_T_1097, _T_1102) node _T_1104 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) node _T_1106 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<1>(0h0))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = or(_T_1105, _T_1110) node _T_1112 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) node _T_1114 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = or(_T_1113, _T_1118) node _T_1120 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) node _T_1122 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = or(_T_1121, _T_1126) node _T_1128 = and(_T_1043, _T_1056) node _T_1129 = and(_T_1128, _T_1069) node _T_1130 = and(_T_1129, _T_1082) node _T_1131 = and(_T_1130, _T_1095) node _T_1132 = and(_T_1131, _T_1103) node _T_1133 = and(_T_1132, _T_1111) node _T_1134 = and(_T_1133, _T_1119) node _T_1135 = and(_T_1134, _T_1127) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[9] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 node _legal_source_T_29 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_30 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_31 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_32 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_33 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[5], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[6], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[7], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[8], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_38 = or(_legal_source_T_29, _legal_source_T_30) node _legal_source_T_39 = or(_legal_source_T_38, _legal_source_T_31) node _legal_source_T_40 = or(_legal_source_T_39, _legal_source_T_32) node _legal_source_T_41 = or(_legal_source_T_40, _legal_source_T_33) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_34) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_35) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_36) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_37) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_45 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1139 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1139 : node _T_1140 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1141 = shr(io.in.b.bits.source, 2) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) node _T_1143 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1146 = and(_T_1144, _T_1145) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1147 = shr(io.in.b.bits.source, 2) node _T_1148 = eq(_T_1147, UInt<1>(0h1)) node _T_1149 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1152 = and(_T_1150, _T_1151) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1153 = shr(io.in.b.bits.source, 2) node _T_1154 = eq(_T_1153, UInt<2>(0h2)) node _T_1155 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1158 = and(_T_1156, _T_1157) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<2>(0h3)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _T_1165 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1166 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1167 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1168 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[9] connect _WIRE_4[0], _T_1140 connect _WIRE_4[1], _T_1146 connect _WIRE_4[2], _T_1152 connect _WIRE_4[3], _T_1158 connect _WIRE_4[4], _T_1164 connect _WIRE_4[5], _T_1165 connect _WIRE_4[6], _T_1166 connect _WIRE_4[7], _T_1167 connect _WIRE_4[8], _T_1168 node _T_1169 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1170 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1171 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1172 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1173 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1174 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1175 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1176 = mux(_WIRE_4[5], _T_1169, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[7], _T_1170, UInt<1>(0h0)) node _T_1179 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1180 = or(_T_1171, _T_1172) node _T_1181 = or(_T_1180, _T_1173) node _T_1182 = or(_T_1181, _T_1174) node _T_1183 = or(_T_1182, _T_1175) node _T_1184 = or(_T_1183, _T_1176) node _T_1185 = or(_T_1184, _T_1177) node _T_1186 = or(_T_1185, _T_1178) node _T_1187 = or(_T_1186, _T_1179) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1187 node _T_1188 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1189 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = or(UInt<1>(0h0), _T_1190) node _T_1192 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1193 = cvt(_T_1192) node _T_1194 = and(_T_1193, asSInt(UInt<17>(0h10000))) node _T_1195 = asSInt(_T_1194) node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0))) node _T_1197 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1198 = cvt(_T_1197) node _T_1199 = and(_T_1198, asSInt(UInt<29>(0h10000000))) node _T_1200 = asSInt(_T_1199) node _T_1201 = eq(_T_1200, asSInt(UInt<1>(0h0))) node _T_1202 = or(_T_1196, _T_1201) node _T_1203 = and(_T_1191, _T_1202) node _T_1204 = or(UInt<1>(0h0), _T_1203) node _T_1205 = and(_WIRE_5, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_86 node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(address_ok, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(legal_source, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1218 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_90 node _T_1222 = eq(io.in.b.bits.mask, mask_1) node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(_T_1222, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1222, UInt<1>(0h1), "") : assert_91 node _T_1226 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_92 node _T_1230 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1230 : node _T_1231 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1232 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1233) node _T_1235 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<17>(0h10000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<29>(0h10000000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = or(_T_1239, _T_1244) node _T_1246 = and(_T_1234, _T_1245) node _T_1247 = or(UInt<1>(0h0), _T_1246) node _T_1248 = and(UInt<1>(0h0), _T_1247) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_93 node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(address_ok, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(legal_source, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1261 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_97 node _T_1265 = eq(io.in.b.bits.mask, mask_1) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_98 node _T_1269 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_99 node _T_1273 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1273 : node _T_1274 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1275 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = or(UInt<1>(0h0), _T_1276) node _T_1278 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1284 = cvt(_T_1283) node _T_1285 = and(_T_1284, asSInt(UInt<29>(0h10000000))) node _T_1286 = asSInt(_T_1285) node _T_1287 = eq(_T_1286, asSInt(UInt<1>(0h0))) node _T_1288 = or(_T_1282, _T_1287) node _T_1289 = and(_T_1277, _T_1288) node _T_1290 = or(UInt<1>(0h0), _T_1289) node _T_1291 = and(UInt<1>(0h0), _T_1290) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_100 node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(address_ok, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(legal_source, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1304 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_104 node _T_1308 = eq(io.in.b.bits.mask, mask_1) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_105 node _T_1312 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1312 : node _T_1313 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1314 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1315 = and(_T_1313, _T_1314) node _T_1316 = or(UInt<1>(0h0), _T_1315) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<29>(0h10000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = or(_T_1321, _T_1326) node _T_1328 = and(_T_1316, _T_1327) node _T_1329 = or(UInt<1>(0h0), _T_1328) node _T_1330 = and(UInt<1>(0h0), _T_1329) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_106 node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(address_ok, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(legal_source, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1343 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_110 node _T_1347 = not(mask_1) node _T_1348 = and(io.in.b.bits.mask, _T_1347) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_111 node _T_1353 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1353 : node _T_1354 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1355 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1356 = and(_T_1354, _T_1355) node _T_1357 = or(UInt<1>(0h0), _T_1356) node _T_1358 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1359 = cvt(_T_1358) node _T_1360 = and(_T_1359, asSInt(UInt<17>(0h10000))) node _T_1361 = asSInt(_T_1360) node _T_1362 = eq(_T_1361, asSInt(UInt<1>(0h0))) node _T_1363 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1364 = cvt(_T_1363) node _T_1365 = and(_T_1364, asSInt(UInt<29>(0h10000000))) node _T_1366 = asSInt(_T_1365) node _T_1367 = eq(_T_1366, asSInt(UInt<1>(0h0))) node _T_1368 = or(_T_1362, _T_1367) node _T_1369 = and(_T_1357, _T_1368) node _T_1370 = or(UInt<1>(0h0), _T_1369) node _T_1371 = and(UInt<1>(0h0), _T_1370) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_112 node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(address_ok, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(legal_source, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1384 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_116 node _T_1388 = eq(io.in.b.bits.mask, mask_1) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_117 node _T_1392 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1392 : node _T_1393 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1394 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = or(UInt<1>(0h0), _T_1395) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<29>(0h10000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = or(_T_1401, _T_1406) node _T_1408 = and(_T_1396, _T_1407) node _T_1409 = or(UInt<1>(0h0), _T_1408) node _T_1410 = and(UInt<1>(0h0), _T_1409) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_118 node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(address_ok, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(legal_source, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1423 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_122 node _T_1427 = eq(io.in.b.bits.mask, mask_1) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_123 node _T_1431 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1431 : node _T_1432 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1433 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<17>(0h10000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<29>(0h10000000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = or(_T_1440, _T_1445) node _T_1447 = and(_T_1435, _T_1446) node _T_1448 = or(UInt<1>(0h0), _T_1447) node _T_1449 = and(UInt<1>(0h0), _T_1448) node _T_1450 = asUInt(reset) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) when _T_1451 : node _T_1452 = eq(_T_1449, UInt<1>(0h0)) when _T_1452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1449, UInt<1>(0h1), "") : assert_124 node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(address_ok, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(legal_source, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1462 = eq(io.in.b.bits.mask, mask_1) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_128 node _T_1466 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1470 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_130 node _source_ok_T_72 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_73 = shr(io.in.c.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<1>(0h0)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h1)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<2>(0h2)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h3)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_98 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_99 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_100 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[9] connect _source_ok_WIRE_2[0], _source_ok_T_72 connect _source_ok_WIRE_2[1], _source_ok_T_78 connect _source_ok_WIRE_2[2], _source_ok_T_84 connect _source_ok_WIRE_2[3], _source_ok_T_90 connect _source_ok_WIRE_2[4], _source_ok_T_96 connect _source_ok_WIRE_2[5], _source_ok_T_97 connect _source_ok_WIRE_2[6], _source_ok_T_98 connect _source_ok_WIRE_2[7], _source_ok_T_99 connect _source_ok_WIRE_2[8], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_2[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_2[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_2[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_2[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_2[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_2[7]) node source_ok_2 = or(_source_ok_T_107, _source_ok_WIRE_2[8]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1474 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) node _T_1476 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = or(_T_1475, _T_1480) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1482 = shr(io.in.c.bits.source, 2) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) node _T_1484 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1485 = and(_T_1483, _T_1484) node _T_1486 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) node _T_1489 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = or(_T_1488, _T_1493) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1495 = shr(io.in.c.bits.source, 2) node _T_1496 = eq(_T_1495, UInt<1>(0h1)) node _T_1497 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1500 = and(_T_1498, _T_1499) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) node _T_1502 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1503 = cvt(_T_1502) node _T_1504 = and(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = asSInt(_T_1504) node _T_1506 = eq(_T_1505, asSInt(UInt<1>(0h0))) node _T_1507 = or(_T_1501, _T_1506) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1508 = shr(io.in.c.bits.source, 2) node _T_1509 = eq(_T_1508, UInt<2>(0h2)) node _T_1510 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1511 = and(_T_1509, _T_1510) node _T_1512 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1513 = and(_T_1511, _T_1512) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) node _T_1515 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1516 = cvt(_T_1515) node _T_1517 = and(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = asSInt(_T_1517) node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0))) node _T_1520 = or(_T_1514, _T_1519) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1521 = shr(io.in.c.bits.source, 2) node _T_1522 = eq(_T_1521, UInt<2>(0h3)) node _T_1523 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1524 = and(_T_1522, _T_1523) node _T_1525 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1526 = and(_T_1524, _T_1525) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) node _T_1528 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<1>(0h0))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = or(_T_1527, _T_1532) node _T_1534 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) node _T_1536 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = or(_T_1535, _T_1540) node _T_1542 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) node _T_1544 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<1>(0h0))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = or(_T_1543, _T_1548) node _T_1550 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) node _T_1552 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1553 = cvt(_T_1552) node _T_1554 = and(_T_1553, asSInt(UInt<1>(0h0))) node _T_1555 = asSInt(_T_1554) node _T_1556 = eq(_T_1555, asSInt(UInt<1>(0h0))) node _T_1557 = or(_T_1551, _T_1556) node _T_1558 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = and(_T_1481, _T_1494) node _T_1567 = and(_T_1566, _T_1507) node _T_1568 = and(_T_1567, _T_1520) node _T_1569 = and(_T_1568, _T_1533) node _T_1570 = and(_T_1569, _T_1541) node _T_1571 = and(_T_1570, _T_1549) node _T_1572 = and(_T_1571, _T_1557) node _T_1573 = and(_T_1572, _T_1565) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_131 node _T_1577 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1577 : node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(address_ok_1, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(source_ok_2, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1584 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_134 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1591 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_136 node _T_1595 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_137 node _T_1599 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1599 : node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(address_ok_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(source_ok_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1606 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_140 node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1613 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(_T_1613, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1613, UInt<1>(0h1), "") : assert_142 node _T_1617 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1617 : node _T_1618 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1619 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1620 = and(_T_1618, _T_1619) node _T_1621 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1622 = shr(io.in.c.bits.source, 2) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) node _T_1624 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1627 = and(_T_1625, _T_1626) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1628 = shr(io.in.c.bits.source, 2) node _T_1629 = eq(_T_1628, UInt<1>(0h1)) node _T_1630 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1631 = and(_T_1629, _T_1630) node _T_1632 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1633 = and(_T_1631, _T_1632) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1634 = shr(io.in.c.bits.source, 2) node _T_1635 = eq(_T_1634, UInt<2>(0h2)) node _T_1636 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1637 = and(_T_1635, _T_1636) node _T_1638 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1639 = and(_T_1637, _T_1638) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1640 = shr(io.in.c.bits.source, 2) node _T_1641 = eq(_T_1640, UInt<2>(0h3)) node _T_1642 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1643 = and(_T_1641, _T_1642) node _T_1644 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1645 = and(_T_1643, _T_1644) node _T_1646 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1647 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1648 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1649 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1650 = or(_T_1621, _T_1627) node _T_1651 = or(_T_1650, _T_1633) node _T_1652 = or(_T_1651, _T_1639) node _T_1653 = or(_T_1652, _T_1645) node _T_1654 = or(_T_1653, _T_1646) node _T_1655 = or(_T_1654, _T_1647) node _T_1656 = or(_T_1655, _T_1648) node _T_1657 = or(_T_1656, _T_1649) node _T_1658 = and(_T_1620, _T_1657) node _T_1659 = or(UInt<1>(0h0), _T_1658) node _T_1660 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1661 = or(UInt<1>(0h0), _T_1660) node _T_1662 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1663 = cvt(_T_1662) node _T_1664 = and(_T_1663, asSInt(UInt<17>(0h10000))) node _T_1665 = asSInt(_T_1664) node _T_1666 = eq(_T_1665, asSInt(UInt<1>(0h0))) node _T_1667 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<29>(0h10000000))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = or(_T_1666, _T_1671) node _T_1673 = and(_T_1661, _T_1672) node _T_1674 = or(UInt<1>(0h0), _T_1673) node _T_1675 = and(_T_1659, _T_1674) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_143 node _T_1679 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1680 = shr(io.in.c.bits.source, 2) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) node _T_1682 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1685 = and(_T_1683, _T_1684) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1686 = shr(io.in.c.bits.source, 2) node _T_1687 = eq(_T_1686, UInt<1>(0h1)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1691 = and(_T_1689, _T_1690) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1692 = shr(io.in.c.bits.source, 2) node _T_1693 = eq(_T_1692, UInt<2>(0h2)) node _T_1694 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1697 = and(_T_1695, _T_1696) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<2>(0h3)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1705 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1706 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1707 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[9] connect _WIRE_6[0], _T_1679 connect _WIRE_6[1], _T_1685 connect _WIRE_6[2], _T_1691 connect _WIRE_6[3], _T_1697 connect _WIRE_6[4], _T_1703 connect _WIRE_6[5], _T_1704 connect _WIRE_6[6], _T_1705 connect _WIRE_6[7], _T_1706 connect _WIRE_6[8], _T_1707 node _T_1708 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1709 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1710 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1711 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1712 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1713 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1714 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1715 = mux(_WIRE_6[5], _T_1708, UInt<1>(0h0)) node _T_1716 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1717 = mux(_WIRE_6[7], _T_1709, UInt<1>(0h0)) node _T_1718 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1719 = or(_T_1710, _T_1711) node _T_1720 = or(_T_1719, _T_1712) node _T_1721 = or(_T_1720, _T_1713) node _T_1722 = or(_T_1721, _T_1714) node _T_1723 = or(_T_1722, _T_1715) node _T_1724 = or(_T_1723, _T_1716) node _T_1725 = or(_T_1724, _T_1717) node _T_1726 = or(_T_1725, _T_1718) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1726 node _T_1727 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1728 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1729 = and(_T_1727, _T_1728) node _T_1730 = or(UInt<1>(0h0), _T_1729) node _T_1731 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1732 = cvt(_T_1731) node _T_1733 = and(_T_1732, asSInt(UInt<17>(0h10000))) node _T_1734 = asSInt(_T_1733) node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0))) node _T_1736 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1737 = cvt(_T_1736) node _T_1738 = and(_T_1737, asSInt(UInt<29>(0h10000000))) node _T_1739 = asSInt(_T_1738) node _T_1740 = eq(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = or(_T_1735, _T_1740) node _T_1742 = and(_T_1730, _T_1741) node _T_1743 = or(UInt<1>(0h0), _T_1742) node _T_1744 = and(_WIRE_7, _T_1743) node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(_T_1744, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1744, UInt<1>(0h1), "") : assert_144 node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(source_ok_2, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1751 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1752 = asUInt(reset) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) when _T_1753 : node _T_1754 = eq(_T_1751, UInt<1>(0h0)) when _T_1754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1751, UInt<1>(0h1), "") : assert_146 node _T_1755 = asUInt(reset) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) when _T_1756 : node _T_1757 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1758 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1759 = asUInt(reset) node _T_1760 = eq(_T_1759, UInt<1>(0h0)) when _T_1760 : node _T_1761 = eq(_T_1758, UInt<1>(0h0)) when _T_1761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1758, UInt<1>(0h1), "") : assert_148 node _T_1762 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_149 node _T_1766 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1766 : node _T_1767 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1768 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1769 = and(_T_1767, _T_1768) node _T_1770 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_1771 = shr(io.in.c.bits.source, 2) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) node _T_1773 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1774 = and(_T_1772, _T_1773) node _T_1775 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_1776 = and(_T_1774, _T_1775) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1777 = shr(io.in.c.bits.source, 2) node _T_1778 = eq(_T_1777, UInt<1>(0h1)) node _T_1779 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1782 = and(_T_1780, _T_1781) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1783 = shr(io.in.c.bits.source, 2) node _T_1784 = eq(_T_1783, UInt<2>(0h2)) node _T_1785 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1788 = and(_T_1786, _T_1787) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1789 = shr(io.in.c.bits.source, 2) node _T_1790 = eq(_T_1789, UInt<2>(0h3)) node _T_1791 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1792 = and(_T_1790, _T_1791) node _T_1793 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1794 = and(_T_1792, _T_1793) node _T_1795 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1796 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1797 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1798 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1799 = or(_T_1770, _T_1776) node _T_1800 = or(_T_1799, _T_1782) node _T_1801 = or(_T_1800, _T_1788) node _T_1802 = or(_T_1801, _T_1794) node _T_1803 = or(_T_1802, _T_1795) node _T_1804 = or(_T_1803, _T_1796) node _T_1805 = or(_T_1804, _T_1797) node _T_1806 = or(_T_1805, _T_1798) node _T_1807 = and(_T_1769, _T_1806) node _T_1808 = or(UInt<1>(0h0), _T_1807) node _T_1809 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1810 = or(UInt<1>(0h0), _T_1809) node _T_1811 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1812 = cvt(_T_1811) node _T_1813 = and(_T_1812, asSInt(UInt<17>(0h10000))) node _T_1814 = asSInt(_T_1813) node _T_1815 = eq(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1817 = cvt(_T_1816) node _T_1818 = and(_T_1817, asSInt(UInt<29>(0h10000000))) node _T_1819 = asSInt(_T_1818) node _T_1820 = eq(_T_1819, asSInt(UInt<1>(0h0))) node _T_1821 = or(_T_1815, _T_1820) node _T_1822 = and(_T_1810, _T_1821) node _T_1823 = or(UInt<1>(0h0), _T_1822) node _T_1824 = and(_T_1808, _T_1823) node _T_1825 = asUInt(reset) node _T_1826 = eq(_T_1825, UInt<1>(0h0)) when _T_1826 : node _T_1827 = eq(_T_1824, UInt<1>(0h0)) when _T_1827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1824, UInt<1>(0h1), "") : assert_150 node _T_1828 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1829 = shr(io.in.c.bits.source, 2) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) node _T_1831 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1832 = and(_T_1830, _T_1831) node _T_1833 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1834 = and(_T_1832, _T_1833) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_1835 = shr(io.in.c.bits.source, 2) node _T_1836 = eq(_T_1835, UInt<1>(0h1)) node _T_1837 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1838 = and(_T_1836, _T_1837) node _T_1839 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_1840 = and(_T_1838, _T_1839) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1841 = shr(io.in.c.bits.source, 2) node _T_1842 = eq(_T_1841, UInt<2>(0h2)) node _T_1843 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1844 = and(_T_1842, _T_1843) node _T_1845 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1846 = and(_T_1844, _T_1845) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1847 = shr(io.in.c.bits.source, 2) node _T_1848 = eq(_T_1847, UInt<2>(0h3)) node _T_1849 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1850 = and(_T_1848, _T_1849) node _T_1851 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1852 = and(_T_1850, _T_1851) node _T_1853 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1854 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1855 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1856 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[9] connect _WIRE_8[0], _T_1828 connect _WIRE_8[1], _T_1834 connect _WIRE_8[2], _T_1840 connect _WIRE_8[3], _T_1846 connect _WIRE_8[4], _T_1852 connect _WIRE_8[5], _T_1853 connect _WIRE_8[6], _T_1854 connect _WIRE_8[7], _T_1855 connect _WIRE_8[8], _T_1856 node _T_1857 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1858 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1859 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1860 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1861 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1862 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1863 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1864 = mux(_WIRE_8[5], _T_1857, UInt<1>(0h0)) node _T_1865 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1866 = mux(_WIRE_8[7], _T_1858, UInt<1>(0h0)) node _T_1867 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1868 = or(_T_1859, _T_1860) node _T_1869 = or(_T_1868, _T_1861) node _T_1870 = or(_T_1869, _T_1862) node _T_1871 = or(_T_1870, _T_1863) node _T_1872 = or(_T_1871, _T_1864) node _T_1873 = or(_T_1872, _T_1865) node _T_1874 = or(_T_1873, _T_1866) node _T_1875 = or(_T_1874, _T_1867) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1875 node _T_1876 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1877 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = or(UInt<1>(0h0), _T_1878) node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1881 = cvt(_T_1880) node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000))) node _T_1883 = asSInt(_T_1882) node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = and(_T_1879, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1891) node _T_1893 = and(_WIRE_9, _T_1892) node _T_1894 = asUInt(reset) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) when _T_1895 : node _T_1896 = eq(_T_1893, UInt<1>(0h0)) when _T_1896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1893, UInt<1>(0h1), "") : assert_151 node _T_1897 = asUInt(reset) node _T_1898 = eq(_T_1897, UInt<1>(0h0)) when _T_1898 : node _T_1899 = eq(source_ok_2, UInt<1>(0h0)) when _T_1899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1900 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1901 = asUInt(reset) node _T_1902 = eq(_T_1901, UInt<1>(0h0)) when _T_1902 : node _T_1903 = eq(_T_1900, UInt<1>(0h0)) when _T_1903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1900, UInt<1>(0h1), "") : assert_153 node _T_1904 = asUInt(reset) node _T_1905 = eq(_T_1904, UInt<1>(0h0)) when _T_1905 : node _T_1906 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1907 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1908 = asUInt(reset) node _T_1909 = eq(_T_1908, UInt<1>(0h0)) when _T_1909 : node _T_1910 = eq(_T_1907, UInt<1>(0h0)) when _T_1910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1907, UInt<1>(0h1), "") : assert_155 node _T_1911 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1911 : node _T_1912 = asUInt(reset) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) when _T_1913 : node _T_1914 = eq(address_ok_1, UInt<1>(0h0)) when _T_1914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(source_ok_2, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1918 = asUInt(reset) node _T_1919 = eq(_T_1918, UInt<1>(0h0)) when _T_1919 : node _T_1920 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1921 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1922 = asUInt(reset) node _T_1923 = eq(_T_1922, UInt<1>(0h0)) when _T_1923 : node _T_1924 = eq(_T_1921, UInt<1>(0h0)) when _T_1924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1921, UInt<1>(0h1), "") : assert_159 node _T_1925 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1926 = asUInt(reset) node _T_1927 = eq(_T_1926, UInt<1>(0h0)) when _T_1927 : node _T_1928 = eq(_T_1925, UInt<1>(0h0)) when _T_1928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1925, UInt<1>(0h1), "") : assert_160 node _T_1929 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1929 : node _T_1930 = asUInt(reset) node _T_1931 = eq(_T_1930, UInt<1>(0h0)) when _T_1931 : node _T_1932 = eq(address_ok_1, UInt<1>(0h0)) when _T_1932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1933 = asUInt(reset) node _T_1934 = eq(_T_1933, UInt<1>(0h0)) when _T_1934 : node _T_1935 = eq(source_ok_2, UInt<1>(0h0)) when _T_1935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1936 = asUInt(reset) node _T_1937 = eq(_T_1936, UInt<1>(0h0)) when _T_1937 : node _T_1938 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1939 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_164 node _T_1943 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1943 : node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(address_ok_1, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1947 = asUInt(reset) node _T_1948 = eq(_T_1947, UInt<1>(0h0)) when _T_1948 : node _T_1949 = eq(source_ok_2, UInt<1>(0h0)) when _T_1949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1950 = asUInt(reset) node _T_1951 = eq(_T_1950, UInt<1>(0h0)) when _T_1951 : node _T_1952 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1953 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(_T_1953, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1953, UInt<1>(0h1), "") : assert_168 node _T_1957 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1964 = eq(a_first, UInt<1>(0h0)) node _T_1965 = and(io.in.a.valid, _T_1964) when _T_1965 : node _T_1966 = eq(io.in.a.bits.opcode, opcode) node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(_T_1966, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1966, UInt<1>(0h1), "") : assert_171 node _T_1970 = eq(io.in.a.bits.param, param) node _T_1971 = asUInt(reset) node _T_1972 = eq(_T_1971, UInt<1>(0h0)) when _T_1972 : node _T_1973 = eq(_T_1970, UInt<1>(0h0)) when _T_1973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1970, UInt<1>(0h1), "") : assert_172 node _T_1974 = eq(io.in.a.bits.size, size) node _T_1975 = asUInt(reset) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : node _T_1977 = eq(_T_1974, UInt<1>(0h0)) when _T_1977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1974, UInt<1>(0h1), "") : assert_173 node _T_1978 = eq(io.in.a.bits.source, source) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_174 node _T_1982 = eq(io.in.a.bits.address, address) node _T_1983 = asUInt(reset) node _T_1984 = eq(_T_1983, UInt<1>(0h0)) when _T_1984 : node _T_1985 = eq(_T_1982, UInt<1>(0h0)) when _T_1985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1982, UInt<1>(0h1), "") : assert_175 node _T_1986 = and(io.in.a.ready, io.in.a.valid) node _T_1987 = and(_T_1986, a_first) when _T_1987 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1988 = eq(d_first, UInt<1>(0h0)) node _T_1989 = and(io.in.d.valid, _T_1988) when _T_1989 : node _T_1990 = eq(io.in.d.bits.opcode, opcode_1) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_176 node _T_1994 = eq(io.in.d.bits.param, param_1) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_177 node _T_1998 = eq(io.in.d.bits.size, size_1) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_178 node _T_2002 = eq(io.in.d.bits.source, source_1) node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(_T_2002, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2002, UInt<1>(0h1), "") : assert_179 node _T_2006 = eq(io.in.d.bits.sink, sink) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_180 node _T_2010 = eq(io.in.d.bits.denied, denied) node _T_2011 = asUInt(reset) node _T_2012 = eq(_T_2011, UInt<1>(0h0)) when _T_2012 : node _T_2013 = eq(_T_2010, UInt<1>(0h0)) when _T_2013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2010, UInt<1>(0h1), "") : assert_181 node _T_2014 = and(io.in.d.ready, io.in.d.valid) node _T_2015 = and(_T_2014, d_first) when _T_2015 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2016 = eq(b_first, UInt<1>(0h0)) node _T_2017 = and(io.in.b.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.b.bits.opcode, opcode_2) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_182 node _T_2022 = eq(io.in.b.bits.param, param_2) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_183 node _T_2026 = eq(io.in.b.bits.size, size_2) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_184 node _T_2030 = eq(io.in.b.bits.source, source_2) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_185 node _T_2034 = eq(io.in.b.bits.address, address_1) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_186 node _T_2038 = and(io.in.b.ready, io.in.b.valid) node _T_2039 = and(_T_2038, b_first) when _T_2039 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2040 = eq(c_first, UInt<1>(0h0)) node _T_2041 = and(io.in.c.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.c.bits.opcode, opcode_3) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_187 node _T_2046 = eq(io.in.c.bits.param, param_3) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_188 node _T_2050 = eq(io.in.c.bits.size, size_3) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_189 node _T_2054 = eq(io.in.c.bits.source, source_3) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_190 node _T_2058 = eq(io.in.c.bits.address, address_2) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_191 node _T_2062 = and(io.in.c.ready, io.in.c.valid) node _T_2063 = and(_T_2062, c_first) when _T_2063 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<39>, clock, reset, UInt<39>(0h0) regreset inflight_opcodes : UInt<156>, clock, reset, UInt<156>(0h0) regreset inflight_sizes : UInt<156>, clock, reset, UInt<156>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<39> connect a_set, UInt<39>(0h0) wire a_set_wo_ready : UInt<39> connect a_set_wo_ready, UInt<39>(0h0) wire a_opcodes_set : UInt<156> connect a_opcodes_set, UInt<156>(0h0) wire a_sizes_set : UInt<156> connect a_sizes_set, UInt<156>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2064 = and(io.in.a.valid, a_first_1) node _T_2065 = and(_T_2064, UInt<1>(0h1)) when _T_2065 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2066 = and(io.in.a.ready, io.in.a.valid) node _T_2067 = and(_T_2066, a_first_1) node _T_2068 = and(_T_2067, UInt<1>(0h1)) when _T_2068 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2069 = dshr(inflight, io.in.a.bits.source) node _T_2070 = bits(_T_2069, 0, 0) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<39> connect d_clr, UInt<39>(0h0) wire d_clr_wo_ready : UInt<39> connect d_clr_wo_ready, UInt<39>(0h0) wire d_opcodes_clr : UInt<156> connect d_opcodes_clr, UInt<156>(0h0) wire d_sizes_clr : UInt<156> connect d_sizes_clr, UInt<156>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2075 = and(io.in.d.valid, d_first_1) node _T_2076 = and(_T_2075, UInt<1>(0h1)) node _T_2077 = eq(d_release_ack, UInt<1>(0h0)) node _T_2078 = and(_T_2076, _T_2077) when _T_2078 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2079 = and(io.in.d.ready, io.in.d.valid) node _T_2080 = and(_T_2079, d_first_1) node _T_2081 = and(_T_2080, UInt<1>(0h1)) node _T_2082 = eq(d_release_ack, UInt<1>(0h0)) node _T_2083 = and(_T_2081, _T_2082) when _T_2083 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2084 = and(io.in.d.valid, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2088 = dshr(inflight, io.in.d.bits.source) node _T_2089 = bits(_T_2088, 0, 0) node _T_2090 = or(_T_2089, same_cycle_resp) node _T_2091 = asUInt(reset) node _T_2092 = eq(_T_2091, UInt<1>(0h0)) when _T_2092 : node _T_2093 = eq(_T_2090, UInt<1>(0h0)) when _T_2093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2090, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2094 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2095 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2096 = or(_T_2094, _T_2095) node _T_2097 = asUInt(reset) node _T_2098 = eq(_T_2097, UInt<1>(0h0)) when _T_2098 : node _T_2099 = eq(_T_2096, UInt<1>(0h0)) when _T_2099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2096, UInt<1>(0h1), "") : assert_194 node _T_2100 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_195 else : node _T_2104 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2105 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2106 = or(_T_2104, _T_2105) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_196 node _T_2110 = eq(io.in.d.bits.size, a_size_lookup) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_197 node _T_2114 = and(io.in.d.valid, d_first_1) node _T_2115 = and(_T_2114, a_first_1) node _T_2116 = and(_T_2115, io.in.a.valid) node _T_2117 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2118 = and(_T_2116, _T_2117) node _T_2119 = eq(d_release_ack, UInt<1>(0h0)) node _T_2120 = and(_T_2118, _T_2119) when _T_2120 : node _T_2121 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2122 = or(_T_2121, io.in.a.ready) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_198 node _T_2126 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2127 = orr(a_set_wo_ready) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) node _T_2129 = or(_T_2126, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_72 node _T_2133 = orr(inflight) node _T_2134 = eq(_T_2133, UInt<1>(0h0)) node _T_2135 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2136 = or(_T_2134, _T_2135) node _T_2137 = lt(watchdog, plusarg_reader.out) node _T_2138 = or(_T_2136, _T_2137) node _T_2139 = asUInt(reset) node _T_2140 = eq(_T_2139, UInt<1>(0h0)) when _T_2140 : node _T_2141 = eq(_T_2138, UInt<1>(0h0)) when _T_2141 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2138, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2142 = and(io.in.a.ready, io.in.a.valid) node _T_2143 = and(io.in.d.ready, io.in.d.valid) node _T_2144 = or(_T_2142, _T_2143) when _T_2144 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<39>, clock, reset, UInt<39>(0h0) regreset inflight_opcodes_1 : UInt<156>, clock, reset, UInt<156>(0h0) regreset inflight_sizes_1 : UInt<156>, clock, reset, UInt<156>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<39> connect c_set, UInt<39>(0h0) wire c_set_wo_ready : UInt<39> connect c_set_wo_ready, UInt<39>(0h0) wire c_opcodes_set : UInt<156> connect c_opcodes_set, UInt<156>(0h0) wire c_sizes_set : UInt<156> connect c_sizes_set, UInt<156>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2145 = and(io.in.c.valid, c_first_1) node _T_2146 = bits(io.in.c.bits.opcode, 2, 2) node _T_2147 = bits(io.in.c.bits.opcode, 1, 1) node _T_2148 = and(_T_2146, _T_2147) node _T_2149 = and(_T_2145, _T_2148) when _T_2149 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2150 = and(io.in.c.ready, io.in.c.valid) node _T_2151 = and(_T_2150, c_first_1) node _T_2152 = bits(io.in.c.bits.opcode, 2, 2) node _T_2153 = bits(io.in.c.bits.opcode, 1, 1) node _T_2154 = and(_T_2152, _T_2153) node _T_2155 = and(_T_2151, _T_2154) when _T_2155 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2156 = dshr(inflight_1, io.in.c.bits.source) node _T_2157 = bits(_T_2156, 0, 0) node _T_2158 = eq(_T_2157, UInt<1>(0h0)) node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(_T_2158, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2158, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<39> connect d_clr_1, UInt<39>(0h0) wire d_clr_wo_ready_1 : UInt<39> connect d_clr_wo_ready_1, UInt<39>(0h0) wire d_opcodes_clr_1 : UInt<156> connect d_opcodes_clr_1, UInt<156>(0h0) wire d_sizes_clr_1 : UInt<156> connect d_sizes_clr_1, UInt<156>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2162 = and(io.in.d.valid, d_first_2) node _T_2163 = and(_T_2162, UInt<1>(0h1)) node _T_2164 = and(_T_2163, d_release_ack_1) when _T_2164 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2165 = and(io.in.d.ready, io.in.d.valid) node _T_2166 = and(_T_2165, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2169 = and(io.in.d.valid, d_first_2) node _T_2170 = and(_T_2169, UInt<1>(0h1)) node _T_2171 = and(_T_2170, d_release_ack_1) when _T_2171 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2172 = dshr(inflight_1, io.in.d.bits.source) node _T_2173 = bits(_T_2172, 0, 0) node _T_2174 = or(_T_2173, same_cycle_resp_1) node _T_2175 = asUInt(reset) node _T_2176 = eq(_T_2175, UInt<1>(0h0)) when _T_2176 : node _T_2177 = eq(_T_2174, UInt<1>(0h0)) when _T_2177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2174, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2178 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2179 = asUInt(reset) node _T_2180 = eq(_T_2179, UInt<1>(0h0)) when _T_2180 : node _T_2181 = eq(_T_2178, UInt<1>(0h0)) when _T_2181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2178, UInt<1>(0h1), "") : assert_203 else : node _T_2182 = eq(io.in.d.bits.size, c_size_lookup) node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(_T_2182, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2182, UInt<1>(0h1), "") : assert_204 node _T_2186 = and(io.in.d.valid, d_first_2) node _T_2187 = and(_T_2186, c_first_1) node _T_2188 = and(_T_2187, io.in.c.valid) node _T_2189 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2190 = and(_T_2188, _T_2189) node _T_2191 = and(_T_2190, d_release_ack_1) node _T_2192 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2193 = and(_T_2191, _T_2192) when _T_2193 : node _T_2194 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2195 = or(_T_2194, io.in.c.ready) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_205 node _T_2199 = orr(c_set_wo_ready) when _T_2199 : node _T_2200 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_73 node _T_2204 = orr(inflight_1) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) node _T_2206 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2207 = or(_T_2205, _T_2206) node _T_2208 = lt(watchdog_1, plusarg_reader_1.out) node _T_2209 = or(_T_2207, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2213 = and(io.in.c.ready, io.in.c.valid) node _T_2214 = and(io.in.d.ready, io.in.d.valid) node _T_2215 = or(_T_2213, _T_2214) when _T_2215 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2216 = and(io.in.d.ready, io.in.d.valid) node _T_2217 = and(_T_2216, d_first_3) node _T_2218 = bits(io.in.d.bits.opcode, 2, 2) node _T_2219 = bits(io.in.d.bits.opcode, 1, 1) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) node _T_2221 = and(_T_2218, _T_2220) node _T_2222 = and(_T_2217, _T_2221) when _T_2222 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2223 = dshr(inflight_2, io.in.d.bits.sink) node _T_2224 = bits(_T_2223, 0, 0) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2229 = and(io.in.e.ready, io.in.e.valid) node _T_2230 = and(_T_2229, UInt<1>(0h1)) node _T_2231 = and(_T_2230, UInt<1>(0h1)) when _T_2231 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2232 = or(d_set, inflight_2) node _T_2233 = dshr(_T_2232, io.in.e.bits.sink) node _T_2234 = bits(_T_2233, 0, 0) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [5:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_30 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_2 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_3 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_37 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_43 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_49 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_55 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire _legal_source_T = io_in_b_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _legal_source_T_1 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_7 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_13 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_19 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_25 = io_in_b_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _legal_source_T_26 = io_in_b_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _legal_source_T_27 = io_in_b_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _legal_source_T_28 = io_in_b_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_2 = _legal_source_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_4 = _legal_source_T_2; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_6 = _legal_source_T_4; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_8 = _legal_source_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_10 = _legal_source_T_8; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_12 = _legal_source_T_10; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_2 = _legal_source_T_12; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_2 = _legal_source_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_14 = _legal_source_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_16 = _legal_source_T_14; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_18 = _legal_source_T_16; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_3 = _legal_source_T_18; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_3 = _legal_source_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_20 = _legal_source_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_22 = _legal_source_T_20; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_24 = _legal_source_T_22; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_4 = _legal_source_T_24; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = _legal_source_T_25; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = _legal_source_T_26; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = _legal_source_T_27; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = _legal_source_T_28; // @[Parameters.scala:1138:31] wire [4:0] _legal_source_T_29 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_38 = _legal_source_T_29; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_31 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_32 = {_legal_source_WIRE_3, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_33 = _legal_source_WIRE_4 ? 4'hC : 4'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_34 = _legal_source_WIRE_5 ? 6'h24 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_35 = _legal_source_WIRE_6 ? 6'h26 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_36 = {_legal_source_WIRE_7, 5'h0}; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_37 = _legal_source_WIRE_8 ? 6'h22 : 6'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_39 = {_legal_source_T_38[4:3], _legal_source_T_38[2:0] | _legal_source_T_31}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_40 = {_legal_source_T_39[4], _legal_source_T_39[3:0] | _legal_source_T_32}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = {_legal_source_T_40[4], _legal_source_T_40[3:0] | _legal_source_T_33}; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_42 = {1'h0, _legal_source_T_41} | _legal_source_T_34; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_43 = _legal_source_T_42 | _legal_source_T_35; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_44 = _legal_source_T_43 | _legal_source_T_36; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = _legal_source_T_44 | _legal_source_T_37; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1_0 = _legal_source_T_45; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_73 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_74 = _source_ok_T_73 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_c_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_5 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_c_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_c_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_c_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_8 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_107 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_2142 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2142; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2142; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2216 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2216; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2216; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2216; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2216; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2213 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2213; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2213; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [38:0] inflight; // @[Monitor.scala:614:27] reg [155:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [155:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [38:0] a_set; // @[Monitor.scala:626:34] wire [38:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [155:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [155:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [155:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [155:0] _a_opcode_lookup_T_6 = {152'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [155:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[155:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [155:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [155:0] _a_size_lookup_T_6 = {152'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [155:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[155:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2068 = _T_2142 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2068 ? _a_set_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2068 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2068 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2068 ? _a_opcodes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2068 ? _a_sizes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [38:0] d_clr; // @[Monitor.scala:664:34] wire [38:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [155:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [155:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2114 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2114 & ~d_release_ack ? _d_clr_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2083 = _T_2216 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2083 ? _d_clr_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2083 ? _d_opcodes_clr_T_5[155:0] : 156'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2083 ? _d_sizes_clr_T_5[155:0] : 156'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [38:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [38:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [38:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [155:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [155:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [155:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [155:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [155:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [155:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [38:0] inflight_1; // @[Monitor.scala:726:35] reg [155:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [155:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [38:0] c_set; // @[Monitor.scala:738:34] wire [38:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [155:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [155:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [155:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [155:0] _c_opcode_lookup_T_6 = {152'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [155:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[155:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [155:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [155:0] _c_size_lookup_T_6 = {152'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [155:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[155:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2155 = _T_2213 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2155 ? _c_set_T[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2155 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2155 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2155 ? _c_opcodes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2155 ? _c_sizes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [38:0] d_clr_1; // @[Monitor.scala:774:34] wire [38:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [155:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [155:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2186 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2186 & d_release_ack_1 ? _d_clr_wo_ready_T_1[38:0] : 39'h0; // @[OneHot.scala:58:35] wire _T_2168 = _T_2216 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2168 ? _d_clr_T_1[38:0] : 39'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2168 ? _d_opcodes_clr_T_11[155:0] : 156'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2168 ? _d_sizes_clr_T_11[155:0] : 156'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [38:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [38:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [38:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [155:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [155:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [155:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [155:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [155:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [155:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_2222 = _T_2216 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2222 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_4 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_4( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AXI4IdIndexer : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<4>}}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.tl_state.source invalidate nodeOut.r.bits.echo.tl_state.size invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.tl_state.source invalidate nodeOut.ar.bits.echo.tl_state.size invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.tl_state.source invalidate nodeOut.b.bits.echo.tl_state.size invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.tl_state.source invalidate nodeOut.aw.bits.echo.tl_state.size invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.ar.bits.echo.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect nodeOut.ar.bits.echo.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id connect nodeOut.ar.valid, nodeIn.ar.valid connect nodeIn.ar.ready, nodeOut.ar.ready connect nodeOut.aw.bits.echo.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect nodeOut.aw.bits.echo.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id connect nodeOut.aw.valid, nodeIn.aw.valid connect nodeIn.aw.ready, nodeOut.aw.ready connect nodeOut.w.bits.last, nodeIn.w.bits.last connect nodeOut.w.bits.strb, nodeIn.w.bits.strb connect nodeOut.w.bits.data, nodeIn.w.bits.data connect nodeOut.w.valid, nodeIn.w.valid connect nodeIn.w.ready, nodeOut.w.ready connect nodeIn.b.bits.echo.tl_state.source, nodeOut.b.bits.echo.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, nodeOut.b.bits.echo.tl_state.size connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.tl_state.source, nodeOut.r.bits.echo.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, nodeOut.r.bits.echo.tl_state.size connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready extmodule plusarg_reader_22 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_23 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module AXI4IdIndexer( // @[IdIndexer.scala:63:9] input clock, // @[IdIndexer.scala:63:9] input reset, // @[IdIndexer.scala:63:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[IdIndexer.scala:63:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[IdIndexer.scala:63:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[IdIndexer.scala:63:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[IdIndexer.scala:63:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[IdIndexer.scala:63:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[IdIndexer.scala:63:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[IdIndexer.scala:63:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] wire auto_in_w_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_b_valid_0; // @[IdIndexer.scala:63:9] wire auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_out_w_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_b_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_r_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[IdIndexer.scala:63:9] assign nodeOut_aw_valid = nodeIn_aw_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_size = nodeIn_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_source = nodeIn_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[IdIndexer.scala:63:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[IdIndexer.scala:63:9] assign nodeOut_ar_valid = nodeIn_ar_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_size = nodeIn_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_source = nodeIn_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[IdIndexer.scala:63:9] assign nodeIn_aw_ready = nodeOut_aw_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[IdIndexer.scala:63:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_size = nodeOut_b_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_source = nodeOut_b_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_ar_ready = nodeOut_ar_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[IdIndexer.scala:63:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_size = nodeOut_r_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_source = nodeOut_r_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] assign auto_in_aw_ready = auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_w_ready = auto_in_w_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id = auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp = auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size = auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source = auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready = auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_r_valid = auto_in_r_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id = auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data = auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp = auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size = auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source = auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last = auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_valid = auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id = auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr = auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len = auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size = auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst = auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock = auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache = auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot = auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos = auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size = auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source = auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_w_valid = auto_out_w_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data = auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb = auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last = auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_valid = auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id = auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr = auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len = auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size = auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst = auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock = auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache = auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot = auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos = auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size = auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source = auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_r_ready = auto_out_r_ready_0; // @[IdIndexer.scala:63:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<9>(0h100))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<9>(0h100))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<9>(0h100))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<9>(0h100))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<9>(0h100))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<9>(0h100))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<9>(0h100))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<9>(0h100))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<9>(0h100))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<9>(0h100))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_115 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_116 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = |flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TageTable_2 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<8>(0hff)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history = bits(io.f1_req_ghist, 7, 0) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 7, 0) node tag_history = bits(io.f1_req_ghist, 7, 0) node _tag_T = shr(_T_1, 8) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 7, 0) smem tage_u_8 : UInt<1>[8] [256] smem tage_table_8 : UInt<12>[4] [256] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] wire s2_req_rus : UInt<1>[8] node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 connect io.f2_resp[0].valid, s2_req_rhits[0] node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0]) connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr connect io.f2_resp[1].valid, s2_req_rhits[1] node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2]) connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr connect io.f2_resp[2].valid, s2_req_rhits[2] node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4]) connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr connect io.f2_resp[3].valid, s2_req_rhits[3] node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6]) connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _clear_u_hi_T = bits(clear_u_ctr, 19, 19) node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1)) node _clear_u_lo_T = bits(clear_u_ctr, 19, 19) node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0)) node clear_u_idx = shr(clear_u_ctr, 11) wire _clear_u_mask_WIRE : UInt<1>[8] connect _clear_u_mask_WIRE[0], clear_u_lo connect _clear_u_mask_WIRE[1], clear_u_hi connect _clear_u_mask_WIRE[2], clear_u_lo connect _clear_u_mask_WIRE[3], clear_u_hi connect _clear_u_mask_WIRE[4], clear_u_lo connect _clear_u_mask_WIRE[5], clear_u_hi connect _clear_u_mask_WIRE[6], clear_u_lo connect _clear_u_mask_WIRE[7], clear_u_hi node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0]) node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2]) node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo) node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4]) node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6]) node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo) node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo) node _T_2 = shr(io.update_pc, 4) node idx_history_1 = bits(io.update_hist, 7, 0) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 7, 0) node tag_history_1 = bits(io.update_hist, 7, 0) node _tag_T_2 = shr(_T_2, 8) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 7, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] node _wen_T = or(io.update_mask[0], io.update_mask[1]) node _wen_T_1 = or(_wen_T, io.update_mask[2]) node _wen_T_2 = or(_wen_T_1, io.update_mask[3]) node _wen_T_3 = or(doing_reset, _wen_T_2) wire wen : UInt<1> connect wen, _wen_T_3 wire _rdata_WIRE : UInt<8> invalidate _rdata_WIRE when io.f1_req_valid : connect _rdata_WIRE, s1_hashed_idx read mport rdata = tage_table_8[_rdata_WIRE], clock reg REG : UInt<1>, clock connect REG, wen node _T_3 = and(REG, UInt<1>(0h0)) when _T_3 : wire _WIRE : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] connect _WIRE[0].ctr, UInt<3>(0h0) connect _WIRE[0].tag, UInt<8>(0h0) connect _WIRE[0].valid, UInt<1>(0h0) connect _WIRE[1].ctr, UInt<3>(0h0) connect _WIRE[1].tag, UInt<8>(0h0) connect _WIRE[1].valid, UInt<1>(0h0) connect _WIRE[2].ctr, UInt<3>(0h0) connect _WIRE[2].tag, UInt<8>(0h0) connect _WIRE[2].valid, UInt<1>(0h0) connect _WIRE[3].ctr, UInt<3>(0h0) connect _WIRE[3].tag, UInt<8>(0h0) connect _WIRE[3].valid, UInt<1>(0h0) connect s2_req_rtage, _WIRE else : wire _WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_2 : UInt<12> connect _WIRE_2, rdata[0] node _T_4 = bits(_WIRE_2, 2, 0) connect _WIRE_1.ctr, _T_4 node _T_5 = bits(_WIRE_2, 10, 3) connect _WIRE_1.tag, _T_5 node _T_6 = bits(_WIRE_2, 11, 11) connect _WIRE_1.valid, _T_6 wire _WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_4 : UInt<12> connect _WIRE_4, rdata[1] node _T_7 = bits(_WIRE_4, 2, 0) connect _WIRE_3.ctr, _T_7 node _T_8 = bits(_WIRE_4, 10, 3) connect _WIRE_3.tag, _T_8 node _T_9 = bits(_WIRE_4, 11, 11) connect _WIRE_3.valid, _T_9 wire _WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_6 : UInt<12> connect _WIRE_6, rdata[2] node _T_10 = bits(_WIRE_6, 2, 0) connect _WIRE_5.ctr, _T_10 node _T_11 = bits(_WIRE_6, 10, 3) connect _WIRE_5.tag, _T_11 node _T_12 = bits(_WIRE_6, 11, 11) connect _WIRE_5.valid, _T_12 wire _WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _WIRE_8 : UInt<12> connect _WIRE_8, rdata[3] node _T_13 = bits(_WIRE_8, 2, 0) connect _WIRE_7.ctr, _T_13 node _T_14 = bits(_WIRE_8, 10, 3) connect _WIRE_7.tag, _T_14 node _T_15 = bits(_WIRE_8, 11, 11) connect _WIRE_7.valid, _T_15 wire _WIRE_9 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] connect _WIRE_9[0].ctr, _WIRE_1.ctr connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].valid, _WIRE_1.valid connect _WIRE_9[1].ctr, _WIRE_3.ctr connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].valid, _WIRE_3.valid connect _WIRE_9[2].ctr, _WIRE_5.ctr connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].valid, _WIRE_5.valid connect _WIRE_9[3].ctr, _WIRE_7.ctr connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].valid, _WIRE_7.valid connect s2_req_rtage, _WIRE_9 when wen : node widx = mux(doing_reset, reset_idx, update_idx) wire _wdata_WIRE : UInt<12>[4] connect _wdata_WIRE[0], UInt<12>(0h0) connect _wdata_WIRE[1], UInt<12>(0h0) connect _wdata_WIRE[2], UInt<12>(0h0) connect _wdata_WIRE[3], UInt<12>(0h0) node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _wdata_T = cat(wdata_hi, update_wdata[0].ctr) node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr) node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr) node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr) wire _wdata_WIRE_1 : UInt<12>[4] connect _wdata_WIRE_1[0], _wdata_T connect _wdata_WIRE_1[1], _wdata_T_1 connect _wdata_WIRE_1[2], _wdata_T_2 connect _wdata_WIRE_1[3], _wdata_T_3 node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1) node _wmask_T = not(UInt<4>(0h0)) node wmask_lo = cat(io.update_mask[1], io.update_mask[0]) node wmask_hi = cat(io.update_mask[3], io.update_mask[2]) node _wmask_T_1 = cat(wmask_hi, wmask_lo) node wmask = mux(doing_reset, _wmask_T, _wmask_T_1) node _T_16 = bits(wmask, 0, 0) node _T_17 = bits(wmask, 1, 1) node _T_18 = bits(wmask, 2, 2) node _T_19 = bits(wmask, 3, 3) write mport MPORT = tage_table_8[widx], clock when _T_16 : connect MPORT[0], wdata[0] when _T_17 : connect MPORT[1], wdata[1] when _T_18 : connect MPORT[2], wdata[2] when _T_19 : connect MPORT[3], wdata[3] wire update_u_mask : UInt<1>[8] connect update_u_mask[0], io.update_u_mask[0] connect update_u_mask[1], io.update_u_mask[0] connect update_u_mask[2], io.update_u_mask[1] connect update_u_mask[3], io.update_u_mask[1] connect update_u_mask[4], io.update_u_mask[2] connect update_u_mask[5], io.update_u_mask[2] connect update_u_mask[6], io.update_u_mask[3] connect update_u_mask[7], io.update_u_mask[3] node _update_u_wen_T = or(doing_reset, doing_clear_u) node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1]) node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2]) node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3]) node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4]) node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5]) node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6]) node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7]) node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7) wire update_u_wen : UInt<1> connect update_u_wen, _update_u_wen_T_8 wire _u_rdata_WIRE : UInt<8> invalidate _u_rdata_WIRE when io.f1_req_valid : connect _u_rdata_WIRE, s1_hashed_idx read mport u_rdata = tage_u_8[_u_rdata_WIRE], clock connect s2_req_rus, u_rdata when update_u_wen : node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx) node widx_1 = mux(doing_reset, reset_idx, _widx_T) node _wdata_T_4 = or(doing_reset, doing_clear_u) wire _wdata_WIRE_2 : UInt<1>[8] connect _wdata_WIRE_2[0], UInt<1>(0h0) connect _wdata_WIRE_2[1], UInt<1>(0h0) connect _wdata_WIRE_2[2], UInt<1>(0h0) connect _wdata_WIRE_2[3], UInt<1>(0h0) connect _wdata_WIRE_2[4], UInt<1>(0h0) connect _wdata_WIRE_2[5], UInt<1>(0h0) connect _wdata_WIRE_2[6], UInt<1>(0h0) connect _wdata_WIRE_2[7], UInt<1>(0h0) node wdata_lo = cat(io.update_u[1], io.update_u[0]) node wdata_hi_4 = cat(io.update_u[3], io.update_u[2]) node _wdata_T_5 = cat(wdata_hi_4, wdata_lo) node _wdata_T_6 = bits(_wdata_T_5, 0, 0) node _wdata_T_7 = bits(_wdata_T_5, 1, 1) node _wdata_T_8 = bits(_wdata_T_5, 2, 2) node _wdata_T_9 = bits(_wdata_T_5, 3, 3) node _wdata_T_10 = bits(_wdata_T_5, 4, 4) node _wdata_T_11 = bits(_wdata_T_5, 5, 5) node _wdata_T_12 = bits(_wdata_T_5, 6, 6) node _wdata_T_13 = bits(_wdata_T_5, 7, 7) wire _wdata_WIRE_3 : UInt<1>[8] connect _wdata_WIRE_3[0], _wdata_T_6 connect _wdata_WIRE_3[1], _wdata_T_7 connect _wdata_WIRE_3[2], _wdata_T_8 connect _wdata_WIRE_3[3], _wdata_T_9 connect _wdata_WIRE_3[4], _wdata_T_10 connect _wdata_WIRE_3[5], _wdata_T_11 connect _wdata_WIRE_3[6], _wdata_T_12 connect _wdata_WIRE_3[7], _wdata_T_13 node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3) node _wmask_T_2 = not(UInt<8>(0h0)) node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0]) node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2]) node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo) node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4]) node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6]) node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo) node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1) node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3) node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4) node _T_20 = bits(wmask_1, 0, 0) node _T_21 = bits(wmask_1, 1, 1) node _T_22 = bits(wmask_1, 2, 2) node _T_23 = bits(wmask_1, 3, 3) node _T_24 = bits(wmask_1, 4, 4) node _T_25 = bits(wmask_1, 5, 5) node _T_26 = bits(wmask_1, 6, 6) node _T_27 = bits(wmask_1, 7, 7) node _T_28 = bits(widx_1, 7, 0) write mport MPORT_1 = tage_u_8[_T_28], clock when _T_20 : connect MPORT_1[0], wdata_1[0] when _T_21 : connect MPORT_1[1], wdata_1[1] when _T_22 : connect MPORT_1[2], wdata_1[2] when _T_23 : connect MPORT_1[3], wdata_1[3] when _T_24 : connect MPORT_1[4], wdata_1[4] when _T_25 : connect MPORT_1[5], wdata_1[5] when _T_26 : connect MPORT_1[6], wdata_1[6] when _T_27 : connect MPORT_1[7], wdata_1[7] reg wrbypass_tags : UInt<8>[2], clock reg wrbypass_idxs : UInt<8>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _T_29 = or(io.update_mask[0], io.update_mask[1]) node _T_30 = or(_T_29, io.update_mask[2]) node _T_31 = or(_T_30, io.update_mask[3]) when _T_31 : node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_32 : wire _WIRE_10 : UInt<3>[4] connect _WIRE_10[0], update_wdata[0].ctr connect _WIRE_10[1], update_wdata[1].ctr connect _WIRE_10[2], update_wdata[2].ctr connect _WIRE_10[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_10 else : wire _WIRE_11 : UInt<3>[4] connect _WIRE_11[0], update_wdata[0].ctr connect _WIRE_11[1], update_wdata[1].ctr connect _WIRE_11[2], update_wdata[2].ctr connect _WIRE_11[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_11 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2

module TageTable_2( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [47:0] _tage_table_8_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_8_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [11:0] _wdata_WIRE_0 = 12'h0; // @[tage.scala:130:41] wire [11:0] _wdata_WIRE_1 = 12'h0; // @[tage.scala:130:41] wire [11:0] _wdata_WIRE_2 = 12'h0; // @[tage.scala:130:41] wire [11:0] _wdata_WIRE_3 = 12'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [7:0] reset_idx; // @[tage.scala:73:26] wire [8:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [8:0] _reset_idx_T = _GEN + {8'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26] wire [7:0] idx_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:149:35] wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}] wire [7:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [7:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_8_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_8_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_8_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_8_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_8_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_8_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_8_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_8_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [11:0] wdata_0; // @[tage.scala:130:20] wire [11:0] wdata_1; // @[tage.scala:130:20] wire [11:0] wdata_2; // @[tage.scala:130:20] wire [11:0] wdata_3; // @[tage.scala:130:20] reg [7:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [7:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [19:0] clear_u_ctr; // @[tage.scala:109:28] wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85] wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [7:0] idx_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}] wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}] wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_8_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_8_R0_data[10:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_8_R0_data[11]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_8_R0_data[14:12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_8_R0_data[22:15]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_8_R0_data[23]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_8_R0_data[26:24]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_8_R0_data[34:27]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_8_R0_data[35]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_8_R0_data[38:36]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_8_R0_data[46:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_8_R0_data[47]; // @[tage.scala:90:27, :98:26, :126:49] wire [7:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [8:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [8:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [8:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [8:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [11:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 12'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 12'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 12'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 12'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [8:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [8:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [7:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [7:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [7:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [7:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 8'h0; // @[tage.scala:73:26] clear_u_ctr <= 20'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_8 tage_u_8 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_8_R0_data), .W0_addr (widx_1[7:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_8 tage_table_8 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_8_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheControl : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip flush_match : UInt<1>, flush_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip flush_resp : UInt<1>} wire ctrlnodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlnodeIn.d.bits.corrupt invalidate ctrlnodeIn.d.bits.data invalidate ctrlnodeIn.d.bits.denied invalidate ctrlnodeIn.d.bits.sink invalidate ctrlnodeIn.d.bits.source invalidate ctrlnodeIn.d.bits.size invalidate ctrlnodeIn.d.bits.param invalidate ctrlnodeIn.d.bits.opcode invalidate ctrlnodeIn.d.valid invalidate ctrlnodeIn.d.ready invalidate ctrlnodeIn.a.bits.corrupt invalidate ctrlnodeIn.a.bits.data invalidate ctrlnodeIn.a.bits.mask invalidate ctrlnodeIn.a.bits.address invalidate ctrlnodeIn.a.bits.source invalidate ctrlnodeIn.a.bits.size invalidate ctrlnodeIn.a.bits.param invalidate ctrlnodeIn.a.bits.opcode invalidate ctrlnodeIn.a.valid invalidate ctrlnodeIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlnodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlnodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlnodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlnodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlnodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlnodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlnodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlnodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlnodeIn.d.valid connect monitor.io.in.d.ready, ctrlnodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlnodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlnodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlnodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlnodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlnodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlnodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlnodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlnodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlnodeIn.a.valid connect monitor.io.in.a.ready, ctrlnodeIn.a.ready connect ctrlnodeIn, auto.ctrl_in regreset flushInValid : UInt<1>, clock, reset, UInt<1>(0h0) reg flushInAddress : UInt<64>, clock regreset flushOutValid : UInt<1>, clock, reset, UInt<1>(0h0) wire flushOutReady : UInt<1> connect flushOutReady, UInt<1>(0h0) when flushOutReady : connect flushOutValid, UInt<1>(0h0) when io.flush_resp : connect flushOutValid, UInt<1>(0h1) when io.flush_req.ready : connect flushInValid, UInt<1>(0h0) connect io.flush_req.valid, flushInValid connect io.flush_req.bits, flushInAddress node _T = eq(io.flush_match, UInt<1>(0h0)) node _T_1 = and(_T, flushInValid) when _T_1 : connect flushInValid, UInt<1>(0h0) connect flushOutValid, UInt<1>(0h1) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(ctrlnodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlnodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlnodeIn.a.bits.data connect in.bits.mask, ctrlnodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlnodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlnodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h48)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[6] wire out_wivalid : UInt<1>[6] wire out_roready : UInt<1>[6] wire out_woready : UInt<1>[6] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = eq(out_rimask, UInt<1>(0h0)) node _out_T_10 = eq(out_wimask, UInt<1>(0h0)) node _out_T_11 = eq(out_romask, UInt<1>(0h0)) node _out_T_12 = eq(out_womask, UInt<1>(0h0)) node _out_T_13 = or(UInt<1>(0h1), UInt<8>(0h0)) node _out_T_14 = bits(_out_T_13, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_15 = bits(out_back_front_q.io.deq.bits.data, 15, 8) node _out_T_16 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_17 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_18 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_20 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_14, UInt<8>(0h0)) node out_prepend = cat(UInt<4>(0h8), _out_prepend_T) node _out_T_22 = or(out_prepend, UInt<16>(0h0)) node _out_T_23 = bits(_out_T_22, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_24 = bits(out_back_front_q.io.deq.bits.data, 23, 16) node _out_T_25 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_26 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_27 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_28 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_29 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_23, UInt<16>(0h0)) node out_prepend_1 = cat(UInt<4>(0ha), _out_prepend_T_1) node _out_T_31 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_32 = bits(_out_T_31, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_33 = bits(out_back_front_q.io.deq.bits.data, 31, 24) node _out_T_34 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_35 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_36 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_37 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_38 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_32, UInt<24>(0h0)) node out_prepend_2 = cat(UInt<3>(0h6), _out_prepend_T_2) node _out_T_40 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_41 = bits(_out_T_40, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 63, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 63, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 63, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 63, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_42 = bits(out_front.bits.data, 63, 0) when out_f_woready_4 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_4 : connect flushInValid, UInt<1>(0h1) node _out_T_43 = eq(flushInValid, UInt<1>(0h0)) node _out_T_44 = and(out_f_wivalid_4, _out_T_43) when _out_T_44 : connect flushInAddress, _out_T_42 node out_f_wiready = eq(flushInValid, UInt<1>(0h0)) node _out_T_45 = and(out_f_wivalid_4, out_f_wiready) node _out_T_46 = and(flushOutValid, out_f_woready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = or(out_f_wiready, _out_T_48) node _out_T_50 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_51 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_52 = or(flushOutValid, _out_T_51) node _out_T_53 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_54 = bits(_out_T_53, 63, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_55 = bits(out_front.bits.data, 31, 0) when out_f_woready_5 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_5 : connect flushInValid, UInt<1>(0h1) node _out_T_56 = eq(flushInValid, UInt<1>(0h0)) node _out_T_57 = and(out_f_wivalid_5, _out_T_56) when _out_T_57 : node _out_flushInAddress_T = shl(_out_T_55, 4) connect flushInAddress, _out_flushInAddress_T node out_f_wiready_1 = eq(flushInValid, UInt<1>(0h0)) node _out_T_58 = and(out_f_wivalid_5, out_f_wiready_1) node _out_T_59 = and(flushOutValid, out_f_woready_5) node _out_T_60 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_61 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_62 = or(out_f_wiready_1, _out_T_61) node _out_T_63 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_64 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_65 = or(flushOutValid, _out_T_64) node _out_T_66 = or(UInt<1>(0h0), UInt<32>(0h0)) node _out_T_67 = bits(_out_T_66, 31, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_6, _out_iindex_T_3) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_6, _out_oindex_T_3) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) connect out_rifireMux_out_1, UInt<1>(0h1) node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_4) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) connect out_wifireMux_out_1, UInt<1>(0h1) node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) node out_wifireMux_all = and(_out_wifireMux_T_12, _out_T_49) connect out_wifireMux_out_2, _out_T_49 connect out_wivalid[4], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_4) node out_wifireMux_all_1 = and(_out_wifireMux_T_16, _out_T_62) connect out_wifireMux_out_3, _out_T_62 connect out_wivalid[5], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) connect out_rofireMux_out_1, UInt<1>(0h1) node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[4], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_5) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) connect out_wofireMux_out_1, UInt<1>(0h1) node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) node out_wofireMux_all = and(_out_wofireMux_T_12, _out_T_52) connect out_wofireMux_out_2, _out_T_52 connect out_woready[4], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_5) node out_wofireMux_all_1 = and(_out_wofireMux_T_16, _out_T_65) connect out_wofireMux_out_3, _out_T_65 connect out_woready[5], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], UInt<1>(0h1) connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], _out_T_5 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_41 connect _out_out_bits_data_WIRE_1[1], UInt<1>(0h0) connect _out_out_bits_data_WIRE_1[2], _out_T_54 connect _out_out_bits_data_WIRE_1[3], _out_T_67 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlnodeIn.a.valid connect ctrlnodeIn.a.ready, in.ready connect ctrlnodeIn.d.valid, out.valid connect out.ready, ctrlnodeIn.d.ready wire ctrlnodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlnodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlnodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlnodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlnodeIn_d_bits_d.data connect ctrlnodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlnodeIn.d.bits.corrupt, ctrlnodeIn_d_bits_d.corrupt connect ctrlnodeIn.d.bits.data, ctrlnodeIn_d_bits_d.data connect ctrlnodeIn.d.bits.denied, ctrlnodeIn_d_bits_d.denied connect ctrlnodeIn.d.bits.sink, ctrlnodeIn_d_bits_d.sink connect ctrlnodeIn.d.bits.source, ctrlnodeIn_d_bits_d.source connect ctrlnodeIn.d.bits.size, ctrlnodeIn_d_bits_d.size connect ctrlnodeIn.d.bits.param, ctrlnodeIn_d_bits_d.param connect ctrlnodeIn.d.bits.opcode, ctrlnodeIn_d_bits_d.opcode connect ctrlnodeIn.d.bits.data, out.bits.data node _ctrlnodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlnodeIn.d.bits.opcode, _ctrlnodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_78 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_79 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [11:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [11:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [11:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [11:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i32_14 : input clock : Clock input reset : Reset output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 8, 8) node posExp = bits(rawIn.sExp, 7, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 22, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 22) node _alignedSig_T_1 = bits(shiftedSig, 21, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f)) node _roundCarryBut2_T = bits(unroundedInt, 29, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<6>(0h20)) node _common_overflow_T_1 = bits(unroundedInt, 30, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 30, 30) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1

module RecFNToIN_e8_s24_i32_14( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [32:0] io_in, // @[RecFNToIN.scala:49:16] output [31:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53] wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53] wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53] wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53] wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53] wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35] wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28] wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49] wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27] wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31] wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13] wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27] wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41] wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7] wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7] wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [31:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [54:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [32:0] _alignedSig_T = shiftedSig[54:22]; // @[RecFNToIN.scala:83:49, :89:20] wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}] wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31] wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire [31:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11] wire magGeOne_atOverflowEdge = posExp == 8'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[7:5]); // @[RecFNToIN.scala:62:28, :116:21] wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 8'h1E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24] wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27] wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_23 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_23( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_21 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_21( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_201( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_3 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x

module PMPChecker_s3_3( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TSIToTileLink : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, state : UInt} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut reg cmd : UInt<32>, clock reg addr : UInt<64>, clock reg len : UInt<64>, clock reg body : UInt<32>[2], clock reg bodyValid : UInt<2>, clock reg idx : UInt<1>, clock regreset state : UInt<4>, clock, reset, UInt<4>(0h0) connect io.state, state node _io_tsi_in_ready_T = eq(state, UInt<4>(0h0)) node _io_tsi_in_ready_T_1 = eq(state, UInt<4>(0h1)) node _io_tsi_in_ready_T_2 = eq(state, UInt<4>(0h2)) node _io_tsi_in_ready_T_3 = eq(state, UInt<4>(0h6)) node _io_tsi_in_ready_T_4 = or(_io_tsi_in_ready_T, _io_tsi_in_ready_T_1) node _io_tsi_in_ready_T_5 = or(_io_tsi_in_ready_T_4, _io_tsi_in_ready_T_2) node _io_tsi_in_ready_T_6 = or(_io_tsi_in_ready_T_5, _io_tsi_in_ready_T_3) connect io.tsi.in.ready, _io_tsi_in_ready_T_6 node _io_tsi_out_valid_T = eq(state, UInt<4>(0h5)) connect io.tsi.out.valid, _io_tsi_out_valid_T connect io.tsi.out.bits, body[idx] node beatAddr = bits(addr, 31, 3) node _nextAddr_T = add(beatAddr, UInt<1>(0h1)) node _nextAddr_T_1 = tail(_nextAddr_T, 1) node nextAddr = cat(_nextAddr_T_1, UInt<3>(0h0)) node _wmask_T = bits(bodyValid, 0, 0) node _wmask_T_1 = bits(bodyValid, 1, 1) node _wmask_T_2 = mux(_wmask_T, UInt<4>(0hf), UInt<4>(0h0)) node _wmask_T_3 = mux(_wmask_T_1, UInt<4>(0hf), UInt<4>(0h0)) node wmask = cat(_wmask_T_3, _wmask_T_2) node _addr_size_T = sub(nextAddr, addr) node addr_size = tail(_addr_size_T, 1) node _len_size_T = add(len, UInt<1>(0h1)) node _len_size_T_1 = tail(_len_size_T, 1) node len_size = cat(_len_size_T_1, UInt<2>(0h0)) node _raw_size_T = lt(len_size, addr_size) node raw_size = mux(_raw_size_T, len_size, addr_size) node _rsize_T = eq(UInt<1>(0h1), raw_size) node _rsize_T_1 = mux(_rsize_T, UInt<1>(0h0), UInt<2>(0h3)) node _rsize_T_2 = eq(UInt<2>(0h2), raw_size) node _rsize_T_3 = mux(_rsize_T_2, UInt<1>(0h1), _rsize_T_1) node _rsize_T_4 = eq(UInt<3>(0h4), raw_size) node rsize = mux(_rsize_T_4, UInt<2>(0h2), _rsize_T_3) node _pow2size_T = bits(raw_size, 0, 0) node _pow2size_T_1 = bits(raw_size, 1, 1) node _pow2size_T_2 = bits(raw_size, 2, 2) node _pow2size_T_3 = bits(raw_size, 3, 3) node _pow2size_T_4 = bits(raw_size, 4, 4) node _pow2size_T_5 = bits(raw_size, 5, 5) node _pow2size_T_6 = bits(raw_size, 6, 6) node _pow2size_T_7 = bits(raw_size, 7, 7) node _pow2size_T_8 = bits(raw_size, 8, 8) node _pow2size_T_9 = bits(raw_size, 9, 9) node _pow2size_T_10 = bits(raw_size, 10, 10) node _pow2size_T_11 = bits(raw_size, 11, 11) node _pow2size_T_12 = bits(raw_size, 12, 12) node _pow2size_T_13 = bits(raw_size, 13, 13) node _pow2size_T_14 = bits(raw_size, 14, 14) node _pow2size_T_15 = bits(raw_size, 15, 15) node _pow2size_T_16 = bits(raw_size, 16, 16) node _pow2size_T_17 = bits(raw_size, 17, 17) node _pow2size_T_18 = bits(raw_size, 18, 18) node _pow2size_T_19 = bits(raw_size, 19, 19) node _pow2size_T_20 = bits(raw_size, 20, 20) node _pow2size_T_21 = bits(raw_size, 21, 21) node _pow2size_T_22 = bits(raw_size, 22, 22) node _pow2size_T_23 = bits(raw_size, 23, 23) node _pow2size_T_24 = bits(raw_size, 24, 24) node _pow2size_T_25 = bits(raw_size, 25, 25) node _pow2size_T_26 = bits(raw_size, 26, 26) node _pow2size_T_27 = bits(raw_size, 27, 27) node _pow2size_T_28 = bits(raw_size, 28, 28) node _pow2size_T_29 = bits(raw_size, 29, 29) node _pow2size_T_30 = bits(raw_size, 30, 30) node _pow2size_T_31 = bits(raw_size, 31, 31) node _pow2size_T_32 = bits(raw_size, 32, 32) node _pow2size_T_33 = bits(raw_size, 33, 33) node _pow2size_T_34 = bits(raw_size, 34, 34) node _pow2size_T_35 = bits(raw_size, 35, 35) node _pow2size_T_36 = bits(raw_size, 36, 36) node _pow2size_T_37 = bits(raw_size, 37, 37) node _pow2size_T_38 = bits(raw_size, 38, 38) node _pow2size_T_39 = bits(raw_size, 39, 39) node _pow2size_T_40 = bits(raw_size, 40, 40) node _pow2size_T_41 = bits(raw_size, 41, 41) node _pow2size_T_42 = bits(raw_size, 42, 42) node _pow2size_T_43 = bits(raw_size, 43, 43) node _pow2size_T_44 = bits(raw_size, 44, 44) node _pow2size_T_45 = bits(raw_size, 45, 45) node _pow2size_T_46 = bits(raw_size, 46, 46) node _pow2size_T_47 = bits(raw_size, 47, 47) node _pow2size_T_48 = bits(raw_size, 48, 48) node _pow2size_T_49 = bits(raw_size, 49, 49) node _pow2size_T_50 = bits(raw_size, 50, 50) node _pow2size_T_51 = bits(raw_size, 51, 51) node _pow2size_T_52 = bits(raw_size, 52, 52) node _pow2size_T_53 = bits(raw_size, 53, 53) node _pow2size_T_54 = bits(raw_size, 54, 54) node _pow2size_T_55 = bits(raw_size, 55, 55) node _pow2size_T_56 = bits(raw_size, 56, 56) node _pow2size_T_57 = bits(raw_size, 57, 57) node _pow2size_T_58 = bits(raw_size, 58, 58) node _pow2size_T_59 = bits(raw_size, 59, 59) node _pow2size_T_60 = bits(raw_size, 60, 60) node _pow2size_T_61 = bits(raw_size, 61, 61) node _pow2size_T_62 = bits(raw_size, 62, 62) node _pow2size_T_63 = bits(raw_size, 63, 63) node _pow2size_T_64 = bits(raw_size, 64, 64) node _pow2size_T_65 = bits(raw_size, 65, 65) node _pow2size_T_66 = add(_pow2size_T, _pow2size_T_1) node _pow2size_T_67 = bits(_pow2size_T_66, 1, 0) node _pow2size_T_68 = add(_pow2size_T_2, _pow2size_T_3) node _pow2size_T_69 = bits(_pow2size_T_68, 1, 0) node _pow2size_T_70 = add(_pow2size_T_67, _pow2size_T_69) node _pow2size_T_71 = bits(_pow2size_T_70, 2, 0) node _pow2size_T_72 = add(_pow2size_T_4, _pow2size_T_5) node _pow2size_T_73 = bits(_pow2size_T_72, 1, 0) node _pow2size_T_74 = add(_pow2size_T_6, _pow2size_T_7) node _pow2size_T_75 = bits(_pow2size_T_74, 1, 0) node _pow2size_T_76 = add(_pow2size_T_73, _pow2size_T_75) node _pow2size_T_77 = bits(_pow2size_T_76, 2, 0) node _pow2size_T_78 = add(_pow2size_T_71, _pow2size_T_77) node _pow2size_T_79 = bits(_pow2size_T_78, 3, 0) node _pow2size_T_80 = add(_pow2size_T_8, _pow2size_T_9) node _pow2size_T_81 = bits(_pow2size_T_80, 1, 0) node _pow2size_T_82 = add(_pow2size_T_10, _pow2size_T_11) node _pow2size_T_83 = bits(_pow2size_T_82, 1, 0) node _pow2size_T_84 = add(_pow2size_T_81, _pow2size_T_83) node _pow2size_T_85 = bits(_pow2size_T_84, 2, 0) node _pow2size_T_86 = add(_pow2size_T_12, _pow2size_T_13) node _pow2size_T_87 = bits(_pow2size_T_86, 1, 0) node _pow2size_T_88 = add(_pow2size_T_14, _pow2size_T_15) node _pow2size_T_89 = bits(_pow2size_T_88, 1, 0) node _pow2size_T_90 = add(_pow2size_T_87, _pow2size_T_89) node _pow2size_T_91 = bits(_pow2size_T_90, 2, 0) node _pow2size_T_92 = add(_pow2size_T_85, _pow2size_T_91) node _pow2size_T_93 = bits(_pow2size_T_92, 3, 0) node _pow2size_T_94 = add(_pow2size_T_79, _pow2size_T_93) node _pow2size_T_95 = bits(_pow2size_T_94, 4, 0) node _pow2size_T_96 = add(_pow2size_T_16, _pow2size_T_17) node _pow2size_T_97 = bits(_pow2size_T_96, 1, 0) node _pow2size_T_98 = add(_pow2size_T_18, _pow2size_T_19) node _pow2size_T_99 = bits(_pow2size_T_98, 1, 0) node _pow2size_T_100 = add(_pow2size_T_97, _pow2size_T_99) node _pow2size_T_101 = bits(_pow2size_T_100, 2, 0) node _pow2size_T_102 = add(_pow2size_T_20, _pow2size_T_21) node _pow2size_T_103 = bits(_pow2size_T_102, 1, 0) node _pow2size_T_104 = add(_pow2size_T_22, _pow2size_T_23) node _pow2size_T_105 = bits(_pow2size_T_104, 1, 0) node _pow2size_T_106 = add(_pow2size_T_103, _pow2size_T_105) node _pow2size_T_107 = bits(_pow2size_T_106, 2, 0) node _pow2size_T_108 = add(_pow2size_T_101, _pow2size_T_107) node _pow2size_T_109 = bits(_pow2size_T_108, 3, 0) node _pow2size_T_110 = add(_pow2size_T_24, _pow2size_T_25) node _pow2size_T_111 = bits(_pow2size_T_110, 1, 0) node _pow2size_T_112 = add(_pow2size_T_26, _pow2size_T_27) node _pow2size_T_113 = bits(_pow2size_T_112, 1, 0) node _pow2size_T_114 = add(_pow2size_T_111, _pow2size_T_113) node _pow2size_T_115 = bits(_pow2size_T_114, 2, 0) node _pow2size_T_116 = add(_pow2size_T_28, _pow2size_T_29) node _pow2size_T_117 = bits(_pow2size_T_116, 1, 0) node _pow2size_T_118 = add(_pow2size_T_31, _pow2size_T_32) node _pow2size_T_119 = bits(_pow2size_T_118, 1, 0) node _pow2size_T_120 = add(_pow2size_T_30, _pow2size_T_119) node _pow2size_T_121 = bits(_pow2size_T_120, 1, 0) node _pow2size_T_122 = add(_pow2size_T_117, _pow2size_T_121) node _pow2size_T_123 = bits(_pow2size_T_122, 2, 0) node _pow2size_T_124 = add(_pow2size_T_115, _pow2size_T_123) node _pow2size_T_125 = bits(_pow2size_T_124, 3, 0) node _pow2size_T_126 = add(_pow2size_T_109, _pow2size_T_125) node _pow2size_T_127 = bits(_pow2size_T_126, 4, 0) node _pow2size_T_128 = add(_pow2size_T_95, _pow2size_T_127) node _pow2size_T_129 = bits(_pow2size_T_128, 5, 0) node _pow2size_T_130 = add(_pow2size_T_33, _pow2size_T_34) node _pow2size_T_131 = bits(_pow2size_T_130, 1, 0) node _pow2size_T_132 = add(_pow2size_T_35, _pow2size_T_36) node _pow2size_T_133 = bits(_pow2size_T_132, 1, 0) node _pow2size_T_134 = add(_pow2size_T_131, _pow2size_T_133) node _pow2size_T_135 = bits(_pow2size_T_134, 2, 0) node _pow2size_T_136 = add(_pow2size_T_37, _pow2size_T_38) node _pow2size_T_137 = bits(_pow2size_T_136, 1, 0) node _pow2size_T_138 = add(_pow2size_T_39, _pow2size_T_40) node _pow2size_T_139 = bits(_pow2size_T_138, 1, 0) node _pow2size_T_140 = add(_pow2size_T_137, _pow2size_T_139) node _pow2size_T_141 = bits(_pow2size_T_140, 2, 0) node _pow2size_T_142 = add(_pow2size_T_135, _pow2size_T_141) node _pow2size_T_143 = bits(_pow2size_T_142, 3, 0) node _pow2size_T_144 = add(_pow2size_T_41, _pow2size_T_42) node _pow2size_T_145 = bits(_pow2size_T_144, 1, 0) node _pow2size_T_146 = add(_pow2size_T_43, _pow2size_T_44) node _pow2size_T_147 = bits(_pow2size_T_146, 1, 0) node _pow2size_T_148 = add(_pow2size_T_145, _pow2size_T_147) node _pow2size_T_149 = bits(_pow2size_T_148, 2, 0) node _pow2size_T_150 = add(_pow2size_T_45, _pow2size_T_46) node _pow2size_T_151 = bits(_pow2size_T_150, 1, 0) node _pow2size_T_152 = add(_pow2size_T_47, _pow2size_T_48) node _pow2size_T_153 = bits(_pow2size_T_152, 1, 0) node _pow2size_T_154 = add(_pow2size_T_151, _pow2size_T_153) node _pow2size_T_155 = bits(_pow2size_T_154, 2, 0) node _pow2size_T_156 = add(_pow2size_T_149, _pow2size_T_155) node _pow2size_T_157 = bits(_pow2size_T_156, 3, 0) node _pow2size_T_158 = add(_pow2size_T_143, _pow2size_T_157) node _pow2size_T_159 = bits(_pow2size_T_158, 4, 0) node _pow2size_T_160 = add(_pow2size_T_49, _pow2size_T_50) node _pow2size_T_161 = bits(_pow2size_T_160, 1, 0) node _pow2size_T_162 = add(_pow2size_T_51, _pow2size_T_52) node _pow2size_T_163 = bits(_pow2size_T_162, 1, 0) node _pow2size_T_164 = add(_pow2size_T_161, _pow2size_T_163) node _pow2size_T_165 = bits(_pow2size_T_164, 2, 0) node _pow2size_T_166 = add(_pow2size_T_53, _pow2size_T_54) node _pow2size_T_167 = bits(_pow2size_T_166, 1, 0) node _pow2size_T_168 = add(_pow2size_T_55, _pow2size_T_56) node _pow2size_T_169 = bits(_pow2size_T_168, 1, 0) node _pow2size_T_170 = add(_pow2size_T_167, _pow2size_T_169) node _pow2size_T_171 = bits(_pow2size_T_170, 2, 0) node _pow2size_T_172 = add(_pow2size_T_165, _pow2size_T_171) node _pow2size_T_173 = bits(_pow2size_T_172, 3, 0) node _pow2size_T_174 = add(_pow2size_T_57, _pow2size_T_58) node _pow2size_T_175 = bits(_pow2size_T_174, 1, 0) node _pow2size_T_176 = add(_pow2size_T_59, _pow2size_T_60) node _pow2size_T_177 = bits(_pow2size_T_176, 1, 0) node _pow2size_T_178 = add(_pow2size_T_175, _pow2size_T_177) node _pow2size_T_179 = bits(_pow2size_T_178, 2, 0) node _pow2size_T_180 = add(_pow2size_T_61, _pow2size_T_62) node _pow2size_T_181 = bits(_pow2size_T_180, 1, 0) node _pow2size_T_182 = add(_pow2size_T_64, _pow2size_T_65) node _pow2size_T_183 = bits(_pow2size_T_182, 1, 0) node _pow2size_T_184 = add(_pow2size_T_63, _pow2size_T_183) node _pow2size_T_185 = bits(_pow2size_T_184, 1, 0) node _pow2size_T_186 = add(_pow2size_T_181, _pow2size_T_185) node _pow2size_T_187 = bits(_pow2size_T_186, 2, 0) node _pow2size_T_188 = add(_pow2size_T_179, _pow2size_T_187) node _pow2size_T_189 = bits(_pow2size_T_188, 3, 0) node _pow2size_T_190 = add(_pow2size_T_173, _pow2size_T_189) node _pow2size_T_191 = bits(_pow2size_T_190, 4, 0) node _pow2size_T_192 = add(_pow2size_T_159, _pow2size_T_191) node _pow2size_T_193 = bits(_pow2size_T_192, 5, 0) node _pow2size_T_194 = add(_pow2size_T_129, _pow2size_T_193) node _pow2size_T_195 = bits(_pow2size_T_194, 6, 0) node pow2size = eq(_pow2size_T_195, UInt<1>(0h1)) node _byteAddr_T = bits(addr, 2, 0) node byteAddr = mux(pow2size, _byteAddr_T, UInt<1>(0h0)) node _put_acquire_T = dshl(beatAddr, UInt<2>(0h3)) node _put_acquire_T_1 = cat(body[1], body[0]) node _put_acquire_legal_T = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_1 = leq(UInt<2>(0h3), UInt<4>(0hc)) node _put_acquire_legal_T_2 = and(_put_acquire_legal_T, _put_acquire_legal_T_1) node _put_acquire_legal_T_3 = or(UInt<1>(0h0), _put_acquire_legal_T_2) node _put_acquire_legal_T_4 = xor(_put_acquire_T, UInt<14>(0h3000)) node _put_acquire_legal_T_5 = cvt(_put_acquire_legal_T_4) node _put_acquire_legal_T_6 = and(_put_acquire_legal_T_5, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_7 = asSInt(_put_acquire_legal_T_6) node _put_acquire_legal_T_8 = eq(_put_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_9 = and(_put_acquire_legal_T_3, _put_acquire_legal_T_8) node _put_acquire_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_11 = leq(UInt<2>(0h3), UInt<3>(0h6)) node _put_acquire_legal_T_12 = and(_put_acquire_legal_T_10, _put_acquire_legal_T_11) node _put_acquire_legal_T_13 = or(UInt<1>(0h0), _put_acquire_legal_T_12) node _put_acquire_legal_T_14 = xor(_put_acquire_T, UInt<1>(0h0)) node _put_acquire_legal_T_15 = cvt(_put_acquire_legal_T_14) node _put_acquire_legal_T_16 = and(_put_acquire_legal_T_15, asSInt(UInt<33>(0h9a312000))) node _put_acquire_legal_T_17 = asSInt(_put_acquire_legal_T_16) node _put_acquire_legal_T_18 = eq(_put_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_19 = xor(_put_acquire_T, UInt<21>(0h100000)) node _put_acquire_legal_T_20 = cvt(_put_acquire_legal_T_19) node _put_acquire_legal_T_21 = and(_put_acquire_legal_T_20, asSInt(UInt<33>(0h9a303000))) node _put_acquire_legal_T_22 = asSInt(_put_acquire_legal_T_21) node _put_acquire_legal_T_23 = eq(_put_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_24 = xor(_put_acquire_T, UInt<22>(0h200000)) node _put_acquire_legal_T_25 = cvt(_put_acquire_legal_T_24) node _put_acquire_legal_T_26 = and(_put_acquire_legal_T_25, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_27 = asSInt(_put_acquire_legal_T_26) node _put_acquire_legal_T_28 = eq(_put_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_29 = xor(_put_acquire_T, UInt<22>(0h300000)) node _put_acquire_legal_T_30 = cvt(_put_acquire_legal_T_29) node _put_acquire_legal_T_31 = and(_put_acquire_legal_T_30, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_32 = asSInt(_put_acquire_legal_T_31) node _put_acquire_legal_T_33 = eq(_put_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_34 = xor(_put_acquire_T, UInt<26>(0h2000000)) node _put_acquire_legal_T_35 = cvt(_put_acquire_legal_T_34) node _put_acquire_legal_T_36 = and(_put_acquire_legal_T_35, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_37 = asSInt(_put_acquire_legal_T_36) node _put_acquire_legal_T_38 = eq(_put_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_39 = xor(_put_acquire_T, UInt<26>(0h2010000)) node _put_acquire_legal_T_40 = cvt(_put_acquire_legal_T_39) node _put_acquire_legal_T_41 = and(_put_acquire_legal_T_40, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_42 = asSInt(_put_acquire_legal_T_41) node _put_acquire_legal_T_43 = eq(_put_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_44 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_45 = cvt(_put_acquire_legal_T_44) node _put_acquire_legal_T_46 = and(_put_acquire_legal_T_45, asSInt(UInt<33>(0h98000000))) node _put_acquire_legal_T_47 = asSInt(_put_acquire_legal_T_46) node _put_acquire_legal_T_48 = eq(_put_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_49 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_50 = cvt(_put_acquire_legal_T_49) node _put_acquire_legal_T_51 = and(_put_acquire_legal_T_50, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_52 = asSInt(_put_acquire_legal_T_51) node _put_acquire_legal_T_53 = eq(_put_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_54 = xor(_put_acquire_T, UInt<29>(0h10000000)) node _put_acquire_legal_T_55 = cvt(_put_acquire_legal_T_54) node _put_acquire_legal_T_56 = and(_put_acquire_legal_T_55, asSInt(UInt<33>(0h9a313000))) node _put_acquire_legal_T_57 = asSInt(_put_acquire_legal_T_56) node _put_acquire_legal_T_58 = eq(_put_acquire_legal_T_57, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_59 = xor(_put_acquire_T, UInt<32>(0h80000000)) node _put_acquire_legal_T_60 = cvt(_put_acquire_legal_T_59) node _put_acquire_legal_T_61 = and(_put_acquire_legal_T_60, asSInt(UInt<33>(0h90000000))) node _put_acquire_legal_T_62 = asSInt(_put_acquire_legal_T_61) node _put_acquire_legal_T_63 = eq(_put_acquire_legal_T_62, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_64 = or(_put_acquire_legal_T_18, _put_acquire_legal_T_23) node _put_acquire_legal_T_65 = or(_put_acquire_legal_T_64, _put_acquire_legal_T_28) node _put_acquire_legal_T_66 = or(_put_acquire_legal_T_65, _put_acquire_legal_T_33) node _put_acquire_legal_T_67 = or(_put_acquire_legal_T_66, _put_acquire_legal_T_38) node _put_acquire_legal_T_68 = or(_put_acquire_legal_T_67, _put_acquire_legal_T_43) node _put_acquire_legal_T_69 = or(_put_acquire_legal_T_68, _put_acquire_legal_T_48) node _put_acquire_legal_T_70 = or(_put_acquire_legal_T_69, _put_acquire_legal_T_53) node _put_acquire_legal_T_71 = or(_put_acquire_legal_T_70, _put_acquire_legal_T_58) node _put_acquire_legal_T_72 = or(_put_acquire_legal_T_71, _put_acquire_legal_T_63) node _put_acquire_legal_T_73 = and(_put_acquire_legal_T_13, _put_acquire_legal_T_72) node _put_acquire_legal_T_74 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_acquire_legal_T_75 = xor(_put_acquire_T, UInt<17>(0h10000)) node _put_acquire_legal_T_76 = cvt(_put_acquire_legal_T_75) node _put_acquire_legal_T_77 = and(_put_acquire_legal_T_76, asSInt(UInt<33>(0h9a310000))) node _put_acquire_legal_T_78 = asSInt(_put_acquire_legal_T_77) node _put_acquire_legal_T_79 = eq(_put_acquire_legal_T_78, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_80 = and(_put_acquire_legal_T_74, _put_acquire_legal_T_79) node _put_acquire_legal_T_81 = or(UInt<1>(0h0), _put_acquire_legal_T_9) node _put_acquire_legal_T_82 = or(_put_acquire_legal_T_81, _put_acquire_legal_T_73) node put_acquire_legal = or(_put_acquire_legal_T_82, _put_acquire_legal_T_80) wire put_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect put_acquire.opcode, UInt<1>(0h1) connect put_acquire.param, UInt<1>(0h0) connect put_acquire.size, UInt<2>(0h3) connect put_acquire.source, UInt<1>(0h0) connect put_acquire.address, _put_acquire_T connect put_acquire.mask, wmask connect put_acquire.data, _put_acquire_T_1 connect put_acquire.corrupt, UInt<1>(0h0) node _get_acquire_T = cat(beatAddr, byteAddr) node _get_acquire_legal_T = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_1 = leq(rsize, UInt<4>(0hc)) node _get_acquire_legal_T_2 = and(_get_acquire_legal_T, _get_acquire_legal_T_1) node _get_acquire_legal_T_3 = or(UInt<1>(0h0), _get_acquire_legal_T_2) node _get_acquire_legal_T_4 = xor(_get_acquire_T, UInt<14>(0h3000)) node _get_acquire_legal_T_5 = cvt(_get_acquire_legal_T_4) node _get_acquire_legal_T_6 = and(_get_acquire_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _get_acquire_legal_T_7 = asSInt(_get_acquire_legal_T_6) node _get_acquire_legal_T_8 = eq(_get_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_9 = and(_get_acquire_legal_T_3, _get_acquire_legal_T_8) node _get_acquire_legal_T_10 = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_11 = leq(rsize, UInt<3>(0h6)) node _get_acquire_legal_T_12 = and(_get_acquire_legal_T_10, _get_acquire_legal_T_11) node _get_acquire_legal_T_13 = or(UInt<1>(0h0), _get_acquire_legal_T_12) node _get_acquire_legal_T_14 = xor(_get_acquire_T, UInt<1>(0h0)) node _get_acquire_legal_T_15 = cvt(_get_acquire_legal_T_14) node _get_acquire_legal_T_16 = and(_get_acquire_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _get_acquire_legal_T_17 = asSInt(_get_acquire_legal_T_16) node _get_acquire_legal_T_18 = eq(_get_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_19 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_20 = cvt(_get_acquire_legal_T_19) node _get_acquire_legal_T_21 = and(_get_acquire_legal_T_20, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_22 = asSInt(_get_acquire_legal_T_21) node _get_acquire_legal_T_23 = eq(_get_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_24 = xor(_get_acquire_T, UInt<21>(0h100000)) node _get_acquire_legal_T_25 = cvt(_get_acquire_legal_T_24) node _get_acquire_legal_T_26 = and(_get_acquire_legal_T_25, asSInt(UInt<33>(0h9a103000))) node _get_acquire_legal_T_27 = asSInt(_get_acquire_legal_T_26) node _get_acquire_legal_T_28 = eq(_get_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_29 = xor(_get_acquire_T, UInt<21>(0h100000)) node _get_acquire_legal_T_30 = cvt(_get_acquire_legal_T_29) node _get_acquire_legal_T_31 = and(_get_acquire_legal_T_30, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_32 = asSInt(_get_acquire_legal_T_31) node _get_acquire_legal_T_33 = eq(_get_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_34 = xor(_get_acquire_T, UInt<26>(0h2000000)) node _get_acquire_legal_T_35 = cvt(_get_acquire_legal_T_34) node _get_acquire_legal_T_36 = and(_get_acquire_legal_T_35, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_37 = asSInt(_get_acquire_legal_T_36) node _get_acquire_legal_T_38 = eq(_get_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_39 = xor(_get_acquire_T, UInt<26>(0h2010000)) node _get_acquire_legal_T_40 = cvt(_get_acquire_legal_T_39) node _get_acquire_legal_T_41 = and(_get_acquire_legal_T_40, asSInt(UInt<33>(0h9a113000))) node _get_acquire_legal_T_42 = asSInt(_get_acquire_legal_T_41) node _get_acquire_legal_T_43 = eq(_get_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_44 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_45 = cvt(_get_acquire_legal_T_44) node _get_acquire_legal_T_46 = and(_get_acquire_legal_T_45, asSInt(UInt<33>(0h98000000))) node _get_acquire_legal_T_47 = asSInt(_get_acquire_legal_T_46) node _get_acquire_legal_T_48 = eq(_get_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_49 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_50 = cvt(_get_acquire_legal_T_49) node _get_acquire_legal_T_51 = and(_get_acquire_legal_T_50, asSInt(UInt<33>(0h9a110000))) node _get_acquire_legal_T_52 = asSInt(_get_acquire_legal_T_51) node _get_acquire_legal_T_53 = eq(_get_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_54 = xor(_get_acquire_T, UInt<29>(0h10000000)) node _get_acquire_legal_T_55 = cvt(_get_acquire_legal_T_54) node _get_acquire_legal_T_56 = and(_get_acquire_legal_T_55, asSInt(UInt<33>(0h9a113000))) node _get_acquire_legal_T_57 = asSInt(_get_acquire_legal_T_56) node _get_acquire_legal_T_58 = eq(_get_acquire_legal_T_57, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_59 = xor(_get_acquire_T, UInt<32>(0h80000000)) node _get_acquire_legal_T_60 = cvt(_get_acquire_legal_T_59) node _get_acquire_legal_T_61 = and(_get_acquire_legal_T_60, asSInt(UInt<33>(0h90000000))) node _get_acquire_legal_T_62 = asSInt(_get_acquire_legal_T_61) node _get_acquire_legal_T_63 = eq(_get_acquire_legal_T_62, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_64 = or(_get_acquire_legal_T_18, _get_acquire_legal_T_23) node _get_acquire_legal_T_65 = or(_get_acquire_legal_T_64, _get_acquire_legal_T_28) node _get_acquire_legal_T_66 = or(_get_acquire_legal_T_65, _get_acquire_legal_T_33) node _get_acquire_legal_T_67 = or(_get_acquire_legal_T_66, _get_acquire_legal_T_38) node _get_acquire_legal_T_68 = or(_get_acquire_legal_T_67, _get_acquire_legal_T_43) node _get_acquire_legal_T_69 = or(_get_acquire_legal_T_68, _get_acquire_legal_T_48) node _get_acquire_legal_T_70 = or(_get_acquire_legal_T_69, _get_acquire_legal_T_53) node _get_acquire_legal_T_71 = or(_get_acquire_legal_T_70, _get_acquire_legal_T_58) node _get_acquire_legal_T_72 = or(_get_acquire_legal_T_71, _get_acquire_legal_T_63) node _get_acquire_legal_T_73 = and(_get_acquire_legal_T_13, _get_acquire_legal_T_72) node _get_acquire_legal_T_74 = or(UInt<1>(0h0), _get_acquire_legal_T_9) node get_acquire_legal = or(_get_acquire_legal_T_74, _get_acquire_legal_T_73) wire get_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect get_acquire.opcode, UInt<3>(0h4) connect get_acquire.param, UInt<1>(0h0) connect get_acquire.size, rsize connect get_acquire.source, UInt<1>(0h0) connect get_acquire.address, _get_acquire_T node _get_acquire_a_mask_sizeOH_T = or(rsize, UInt<3>(0h0)) node get_acquire_a_mask_sizeOH_shiftAmount = bits(_get_acquire_a_mask_sizeOH_T, 1, 0) node _get_acquire_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_acquire_a_mask_sizeOH_shiftAmount) node _get_acquire_a_mask_sizeOH_T_2 = bits(_get_acquire_a_mask_sizeOH_T_1, 2, 0) node get_acquire_a_mask_sizeOH = or(_get_acquire_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_acquire_a_mask_sub_sub_sub_0_1 = geq(rsize, UInt<2>(0h3)) node get_acquire_a_mask_sub_sub_size = bits(get_acquire_a_mask_sizeOH, 2, 2) node get_acquire_a_mask_sub_sub_bit = bits(_get_acquire_T, 2, 2) node get_acquire_a_mask_sub_sub_nbit = eq(get_acquire_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_nbit) node _get_acquire_a_mask_sub_sub_acc_T = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_0_2) node get_acquire_a_mask_sub_sub_0_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T) node get_acquire_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_bit) node _get_acquire_a_mask_sub_sub_acc_T_1 = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_1_2) node get_acquire_a_mask_sub_sub_1_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T_1) node get_acquire_a_mask_sub_size = bits(get_acquire_a_mask_sizeOH, 1, 1) node get_acquire_a_mask_sub_bit = bits(_get_acquire_T, 1, 1) node get_acquire_a_mask_sub_nbit = eq(get_acquire_a_mask_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_0_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_0_2) node get_acquire_a_mask_sub_0_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T) node get_acquire_a_mask_sub_1_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_1 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_1_2) node get_acquire_a_mask_sub_1_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T_1) node get_acquire_a_mask_sub_2_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T_2 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_2_2) node get_acquire_a_mask_sub_2_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_2) node get_acquire_a_mask_sub_3_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_3 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_3_2) node get_acquire_a_mask_sub_3_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_3) node get_acquire_a_mask_size = bits(get_acquire_a_mask_sizeOH, 0, 0) node get_acquire_a_mask_bit = bits(_get_acquire_T, 0, 0) node get_acquire_a_mask_nbit = eq(get_acquire_a_mask_bit, UInt<1>(0h0)) node get_acquire_a_mask_eq = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T = and(get_acquire_a_mask_size, get_acquire_a_mask_eq) node get_acquire_a_mask_acc = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T) node get_acquire_a_mask_eq_1 = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_1 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_1) node get_acquire_a_mask_acc_1 = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T_1) node get_acquire_a_mask_eq_2 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_2 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_2) node get_acquire_a_mask_acc_2 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_2) node get_acquire_a_mask_eq_3 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_3 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_3) node get_acquire_a_mask_acc_3 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_3) node get_acquire_a_mask_eq_4 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_4 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_4) node get_acquire_a_mask_acc_4 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_4) node get_acquire_a_mask_eq_5 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_5 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_5) node get_acquire_a_mask_acc_5 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_5) node get_acquire_a_mask_eq_6 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_6 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_6) node get_acquire_a_mask_acc_6 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_6) node get_acquire_a_mask_eq_7 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_7 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_7) node get_acquire_a_mask_acc_7 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_7) node get_acquire_a_mask_lo_lo = cat(get_acquire_a_mask_acc_1, get_acquire_a_mask_acc) node get_acquire_a_mask_lo_hi = cat(get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2) node get_acquire_a_mask_lo = cat(get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo) node get_acquire_a_mask_hi_lo = cat(get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4) node get_acquire_a_mask_hi_hi = cat(get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6) node get_acquire_a_mask_hi = cat(get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo) node _get_acquire_a_mask_T = cat(get_acquire_a_mask_hi, get_acquire_a_mask_lo) connect get_acquire.mask, _get_acquire_a_mask_T invalidate get_acquire.data connect get_acquire.corrupt, UInt<1>(0h0) node _nodeOut_a_valid_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_valid_T_1 = eq(state, UInt<4>(0h3)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_bits_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_bits_T_1 = mux(_nodeOut_a_bits_T, put_acquire, get_acquire) connect nodeOut.a.bits, _nodeOut_a_bits_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) node _nodeOut_d_ready_T = eq(state, UInt<4>(0h8)) node _nodeOut_d_ready_T_1 = eq(state, UInt<4>(0h4)) node _nodeOut_d_ready_T_2 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_T_1) connect nodeOut.d.ready, _nodeOut_d_ready_T_2 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T = eq(state, UInt<4>(0h0)) node _T_1 = and(_T, io.tsi.in.valid) when _T_1 : connect cmd, io.tsi.in.bits connect idx, UInt<1>(0h0) connect addr, UInt<1>(0h0) connect len, UInt<1>(0h0) connect state, UInt<4>(0h1) node _T_2 = eq(state, UInt<4>(0h1)) node _T_3 = and(_T_2, io.tsi.in.valid) when _T_3 : node _addr_T = bits(idx, 0, 0) node _addr_T_1 = cat(_addr_T, UInt<5>(0h0)) node _addr_T_2 = dshl(io.tsi.in.bits, _addr_T_1) node _addr_T_3 = or(addr, _addr_T_2) connect addr, _addr_T_3 node _idx_T = add(idx, UInt<1>(0h1)) node _idx_T_1 = tail(_idx_T, 1) connect idx, _idx_T_1 node _T_4 = eq(idx, UInt<1>(0h1)) when _T_4 : connect idx, UInt<1>(0h0) connect state, UInt<4>(0h2) node _T_5 = eq(state, UInt<4>(0h2)) node _T_6 = and(_T_5, io.tsi.in.valid) when _T_6 : node _len_T = bits(idx, 0, 0) node _len_T_1 = cat(_len_T, UInt<5>(0h0)) node _len_T_2 = dshl(io.tsi.in.bits, _len_T_1) node _len_T_3 = or(len, _len_T_2) connect len, _len_T_3 node _idx_T_2 = add(idx, UInt<1>(0h1)) node _idx_T_3 = tail(_idx_T_2, 1) connect idx, _idx_T_3 node _T_7 = eq(idx, UInt<1>(0h1)) when _T_7 : node _idx_T_4 = bits(addr, 2, 2) connect idx, _idx_T_4 node _T_8 = eq(cmd, UInt<1>(0h1)) when _T_8 : connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) else : node _T_9 = eq(cmd, UInt<1>(0h0)) when _T_9 : connect state, UInt<4>(0h3) else : node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Bad TSI command\n at TSIToTileLink.scala:137 assert(false.B, \"Bad TSI command\")\n") : printf assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert node _T_13 = eq(state, UInt<4>(0h3)) node _T_14 = and(_T_13, nodeOut.a.ready) when _T_14 : connect state, UInt<4>(0h4) node _T_15 = eq(state, UInt<4>(0h4)) node _T_16 = and(_T_15, nodeOut.d.valid) when _T_16 : wire _WIRE_6 : UInt<32>[2] wire _WIRE_7 : UInt<64> connect _WIRE_7, nodeOut.d.bits.data node _T_17 = bits(_WIRE_7, 31, 0) connect _WIRE_6[0], _T_17 node _T_18 = bits(_WIRE_7, 63, 32) connect _WIRE_6[1], _T_18 connect body, _WIRE_6 node _idx_T_5 = bits(addr, 2, 2) connect idx, _idx_T_5 connect addr, nextAddr connect state, UInt<4>(0h5) node _T_19 = eq(state, UInt<4>(0h5)) node _T_20 = and(_T_19, io.tsi.out.ready) when _T_20 : node _idx_T_6 = add(idx, UInt<1>(0h1)) node _idx_T_7 = tail(_idx_T_6, 1) connect idx, _idx_T_7 node _len_T_4 = sub(len, UInt<1>(0h1)) node _len_T_5 = tail(_len_T_4, 1) connect len, _len_T_5 node _T_21 = eq(len, UInt<1>(0h0)) when _T_21 : connect state, UInt<4>(0h0) else : node _T_22 = eq(idx, UInt<1>(0h1)) when _T_22 : connect state, UInt<4>(0h3) node _T_23 = eq(state, UInt<4>(0h6)) node _T_24 = and(_T_23, io.tsi.in.valid) when _T_24 : connect body[idx], io.tsi.in.bits node _bodyValid_T = dshl(UInt<1>(0h1), idx) node _bodyValid_T_1 = or(bodyValid, _bodyValid_T) connect bodyValid, _bodyValid_T_1 node _T_25 = eq(idx, UInt<1>(0h1)) node _T_26 = eq(len, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) when _T_27 : connect state, UInt<4>(0h7) else : node _idx_T_8 = add(idx, UInt<1>(0h1)) node _idx_T_9 = tail(_idx_T_8, 1) connect idx, _idx_T_9 node _len_T_6 = sub(len, UInt<1>(0h1)) node _len_T_7 = tail(_len_T_6, 1) connect len, _len_T_7 node _T_28 = eq(state, UInt<4>(0h7)) node _T_29 = and(_T_28, nodeOut.a.ready) when _T_29 : connect state, UInt<4>(0h8) node _T_30 = eq(state, UInt<4>(0h8)) node _T_31 = and(_T_30, nodeOut.d.valid) when _T_31 : node _T_32 = eq(len, UInt<1>(0h0)) when _T_32 : connect state, UInt<4>(0h0) else : connect addr, nextAddr node _len_T_8 = sub(len, UInt<1>(0h1)) node _len_T_9 = tail(_len_T_8, 1) connect len, _len_T_9 connect idx, UInt<1>(0h0) connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) extmodule plusarg_reader_129 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_74 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_80 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T | _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 | _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 | _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_81 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'h9A312000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'h9A303000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:22], _put_acquire_T[21:0] ^ 22'h200000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:22], _put_acquire_T[21:0] ^ 22'h300000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_34 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_39 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [31:0] _put_acquire_legal_T_44; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_44 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _put_acquire_legal_T_49; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_49 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_54 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_55 = {1'h0, _put_acquire_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_56 = _put_acquire_legal_T_55 & 33'h9A313000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_57 = _put_acquire_legal_T_56; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_59 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_60 = {1'h0, _put_acquire_legal_T_59}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_61 = _put_acquire_legal_T_60 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_62 = _put_acquire_legal_T_61; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_63 = _put_acquire_legal_T_62 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_64 = _put_acquire_legal_T_18 | _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_65 = _put_acquire_legal_T_64 | _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_66 = _put_acquire_legal_T_65 | _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 | _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_68 = _put_acquire_legal_T_67 | _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_69 = _put_acquire_legal_T_68 | _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_70 = _put_acquire_legal_T_69 | _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_71 = _put_acquire_legal_T_70 | _put_acquire_legal_T_58; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_72 = _put_acquire_legal_T_71 | _put_acquire_legal_T_63; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_73 = _put_acquire_legal_T_72; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_75 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_76 = {1'h0, _put_acquire_legal_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_77 = _put_acquire_legal_T_76 & 33'h9A310000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_78 = _put_acquire_legal_T_77; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_79 = _put_acquire_legal_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_82 = _put_acquire_legal_T_81 | _put_acquire_legal_T_73; // @[Parameters.scala:684:54, :686:26] wire put_acquire_legal = _put_acquire_legal_T_82; // @[Parameters.scala:686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_74 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_19 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {_get_acquire_T[31:21], _get_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_29; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_29 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_34 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_39 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_44; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_49; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_49 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_54 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_55 = {1'h0, _get_acquire_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_56 = _get_acquire_legal_T_55 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_57 = _get_acquire_legal_T_56; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_59 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_60 = {1'h0, _get_acquire_legal_T_59}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_61 = _get_acquire_legal_T_60 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_62 = _get_acquire_legal_T_61; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_63 = _get_acquire_legal_T_62 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_64 = _get_acquire_legal_T_18 | _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_65 = _get_acquire_legal_T_64 | _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_66 = _get_acquire_legal_T_65 | _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_67 = _get_acquire_legal_T_66 | _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_68 = _get_acquire_legal_T_67 | _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_69 = _get_acquire_legal_T_68 | _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_70 = _get_acquire_legal_T_69 | _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_71 = _get_acquire_legal_T_70 | _get_acquire_legal_T_58; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_72 = _get_acquire_legal_T_71 | _get_acquire_legal_T_63; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_73 = _get_acquire_legal_T_72; // @[Parameters.scala:684:54, :685:42] wire get_acquire_legal = _get_acquire_legal_T_74 | _get_acquire_legal_T_73; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 | _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 | _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 | _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 | _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 | _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 | _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 | _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 | _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 | _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 | _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 | _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 | _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 | _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 | _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T | _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_4 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_4 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} | _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_5 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_6 = _GEN_5 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_6; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_6; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_6; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_6; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_4 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} | _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_7 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]

Generate the Verilog code corresponding to this FIRRTL code module PE_400 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_144 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_400( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_144 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_98 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_98( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_2 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d128s7k6z4c_2 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<5>(0h13)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<5>(0h12)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<5>(0h11)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<5>(0h10)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_5 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_5 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_5, 1, 0) node _io_flit_bits_egress_id_requestOH_T_25 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_26 = eq(_io_flit_bits_egress_id_requestOH_T_25, UInt<4>(0hf)) node _io_flit_bits_egress_id_requestOH_T_27 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_5) node _io_flit_bits_egress_id_requestOH_T_28 = and(_io_flit_bits_egress_id_requestOH_T_26, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_5, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_5 = and(_io_flit_bits_egress_id_requestOH_T_28, _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_6 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_6 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_6, 1, 0) node _io_flit_bits_egress_id_requestOH_T_30 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_31 = eq(_io_flit_bits_egress_id_requestOH_T_30, UInt<4>(0he)) node _io_flit_bits_egress_id_requestOH_T_32 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_6) node _io_flit_bits_egress_id_requestOH_T_33 = and(_io_flit_bits_egress_id_requestOH_T_31, _io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_6, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_6 = and(_io_flit_bits_egress_id_requestOH_T_33, _io_flit_bits_egress_id_requestOH_T_34) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_7 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_7 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_7, 1, 0) node _io_flit_bits_egress_id_requestOH_T_35 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_36 = eq(_io_flit_bits_egress_id_requestOH_T_35, UInt<4>(0hd)) node _io_flit_bits_egress_id_requestOH_T_37 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_7) node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_36, _io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_7, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_7 = and(_io_flit_bits_egress_id_requestOH_T_38, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_8 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_8 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_8, 1, 0) node _io_flit_bits_egress_id_requestOH_T_40 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_41 = eq(_io_flit_bits_egress_id_requestOH_T_40, UInt<4>(0hc)) node _io_flit_bits_egress_id_requestOH_T_42 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_8) node _io_flit_bits_egress_id_requestOH_T_43 = and(_io_flit_bits_egress_id_requestOH_T_41, _io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_8, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_8 = and(_io_flit_bits_egress_id_requestOH_T_43, _io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_9 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_9 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_9, 1, 0) node _io_flit_bits_egress_id_requestOH_T_45 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_47 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_9) node _io_flit_bits_egress_id_requestOH_T_48 = and(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_47) node _io_flit_bits_egress_id_requestOH_T_49 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_9, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_9 = and(_io_flit_bits_egress_id_requestOH_T_48, _io_flit_bits_egress_id_requestOH_T_49) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_10 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_10 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_10, 1, 0) node _io_flit_bits_egress_id_requestOH_T_50 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_52 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_10) node _io_flit_bits_egress_id_requestOH_T_53 = and(_io_flit_bits_egress_id_requestOH_T_51, _io_flit_bits_egress_id_requestOH_T_52) node _io_flit_bits_egress_id_requestOH_T_54 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_10, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_10 = and(_io_flit_bits_egress_id_requestOH_T_53, _io_flit_bits_egress_id_requestOH_T_54) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_11 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_11 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_11, 1, 0) node _io_flit_bits_egress_id_requestOH_T_55 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_56 = eq(_io_flit_bits_egress_id_requestOH_T_55, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_57 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_11) node _io_flit_bits_egress_id_requestOH_T_58 = and(_io_flit_bits_egress_id_requestOH_T_56, _io_flit_bits_egress_id_requestOH_T_57) node _io_flit_bits_egress_id_requestOH_T_59 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_11, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_11 = and(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_59) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_12 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_12 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_12, 1, 0) node _io_flit_bits_egress_id_requestOH_T_60 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_61 = eq(_io_flit_bits_egress_id_requestOH_T_60, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_62 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_12) node _io_flit_bits_egress_id_requestOH_T_63 = and(_io_flit_bits_egress_id_requestOH_T_61, _io_flit_bits_egress_id_requestOH_T_62) node _io_flit_bits_egress_id_requestOH_T_64 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_12, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_12 = and(_io_flit_bits_egress_id_requestOH_T_63, _io_flit_bits_egress_id_requestOH_T_64) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h0), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<2>(0h2), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<3>(0h4), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<3>(0h6), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_8 = mux(io_flit_bits_egress_id_requestOH_8, UInt<4>(0h8), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_9 = mux(io_flit_bits_egress_id_requestOH_9, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_10 = mux(io_flit_bits_egress_id_requestOH_10, UInt<4>(0ha), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_11 = mux(io_flit_bits_egress_id_requestOH_11, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_12 = mux(io_flit_bits_egress_id_requestOH_12, UInt<4>(0hc), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_15 = or(_io_flit_bits_egress_id_T_14, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_16 = or(_io_flit_bits_egress_id_T_15, _io_flit_bits_egress_id_T_4) node _io_flit_bits_egress_id_T_17 = or(_io_flit_bits_egress_id_T_16, _io_flit_bits_egress_id_T_5) node _io_flit_bits_egress_id_T_18 = or(_io_flit_bits_egress_id_T_17, _io_flit_bits_egress_id_T_6) node _io_flit_bits_egress_id_T_19 = or(_io_flit_bits_egress_id_T_18, _io_flit_bits_egress_id_T_7) node _io_flit_bits_egress_id_T_20 = or(_io_flit_bits_egress_id_T_19, _io_flit_bits_egress_id_T_8) node _io_flit_bits_egress_id_T_21 = or(_io_flit_bits_egress_id_T_20, _io_flit_bits_egress_id_T_9) node _io_flit_bits_egress_id_T_22 = or(_io_flit_bits_egress_id_T_21, _io_flit_bits_egress_id_T_10) node _io_flit_bits_egress_id_T_23 = or(_io_flit_bits_egress_id_T_22, _io_flit_bits_egress_id_T_11) node _io_flit_bits_egress_id_T_24 = or(_io_flit_bits_egress_id_T_23, _io_flit_bits_egress_id_T_12) wire _io_flit_bits_egress_id_WIRE : UInt<4> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_24 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<6>(0h20)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T

module TLDToNoC_2( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [1:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire [1:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:4]) : 2'h0; // @[package.scala:243:{46,71,76}] reg [1:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 2'h1 | tail_beats1 == 2'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 2'h0; // @[Edges.scala:229:27] tail_counter <= 2'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:4]) : 2'h0) : head_counter - 2'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 2'h0 ? tail_beats1 : tail_counter - 2'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a26d64s7k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a26d64s7k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [25:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [25:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [25:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_116 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_130 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_116( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_130 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_17 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_177 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_178 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_17( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_177 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_178 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_90 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_91 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_1 : output auto : { icenic_intsink_out : UInt<1>[2], icenic_dma_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, icenic_dma_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip icenic_mmio_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} output nic : { flip in : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, out : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, flip macAddr : UInt<48>, flip rlimit : { inc : UInt<8>, period : UInt<8>, size : UInt<8>}, flip pauser : { threshold : UInt<16>, quanta : UInt<16>, refresh : UInt<16>}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst icenic of IceNIC connect icenic.clock, childClock connect icenic.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect icenic.auto.mmio_in, auto.icenic_mmio_in connect icenic.auto.dma_out_0.d, auto.icenic_dma_out_0.d connect auto.icenic_dma_out_0.a.bits, icenic.auto.dma_out_0.a.bits connect auto.icenic_dma_out_0.a.valid, icenic.auto.dma_out_0.a.valid connect icenic.auto.dma_out_0.a.ready, auto.icenic_dma_out_0.a.ready connect icenic.auto.dma_out_1.d, auto.icenic_dma_out_1.d connect auto.icenic_dma_out_1.a.bits, icenic.auto.dma_out_1.a.bits connect auto.icenic_dma_out_1.a.valid, icenic.auto.dma_out_1.a.valid connect icenic.auto.dma_out_1.a.ready, auto.icenic_dma_out_1.a.ready connect auto.icenic_intsink_out, icenic.auto.intsink_out wire nic_vonly : { flip in : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, out : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, flip macAddr : UInt<48>, flip rlimit : { inc : UInt<8>, period : UInt<8>, size : UInt<8>}, flip pauser : { threshold : UInt<16>, quanta : UInt<16>, refresh : UInt<16>}} connect nic_vonly.out.valid, icenic.io.ext.out.valid connect nic_vonly.out.bits, icenic.io.ext.out.bits connect icenic.io.ext.out.ready, UInt<1>(0h1) connect icenic.io.ext.in.valid, nic_vonly.in.valid connect icenic.io.ext.in.bits.last, nic_vonly.in.bits.last connect icenic.io.ext.in.bits.keep, nic_vonly.in.bits.keep connect icenic.io.ext.in.bits.data, nic_vonly.in.bits.data node _nic_T = eq(nic_vonly.in.valid, UInt<1>(0h0)) node _nic_T_1 = or(_nic_T, icenic.io.ext.in.ready) node _nic_T_2 = asUInt(childReset) node _nic_T_3 = eq(_nic_T_2, UInt<1>(0h0)) when _nic_T_3 : node _nic_T_4 = eq(_nic_T_1, UInt<1>(0h0)) when _nic_T_4 : printf(childClock, UInt<1>(0h1), "Assertion failed: NIC input not ready for valid\n at NIC.scala:525 assert(!vonly.in.valid || nicio.in.ready, \"NIC input not ready for valid\")\n") : nic_printf assert(childClock, _nic_T_1, UInt<1>(0h1), "") : nic_assert connect icenic.io.ext.macAddr, nic_vonly.macAddr connect icenic.io.ext.rlimit.size, nic_vonly.rlimit.size connect icenic.io.ext.rlimit.period, nic_vonly.rlimit.period connect icenic.io.ext.rlimit.inc, nic_vonly.rlimit.inc connect icenic.io.ext.pauser.refresh, nic_vonly.pauser.refresh connect icenic.io.ext.pauser.quanta, nic_vonly.pauser.quanta connect icenic.io.ext.pauser.threshold, nic_vonly.pauser.threshold connect nic, nic_vonly connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_126 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_127 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module ClockSinkDomain_1( // @[ClockDomain.scala:14:9] output auto_icenic_intsink_out_0, // @[LazyModuleImp.scala:107:25] output auto_icenic_intsink_out_1, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icenic_dma_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_dma_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_icenic_dma_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_dma_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icenic_dma_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_icenic_dma_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_icenic_dma_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_icenic_dma_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icenic_dma_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icenic_dma_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icenic_dma_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_icenic_dma_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_dma_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icenic_dma_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_icenic_dma_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icenic_dma_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_dma_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icenic_dma_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icenic_dma_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icenic_dma_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_icenic_mmio_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_icenic_mmio_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_mmio_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icenic_mmio_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icenic_mmio_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_icenic_mmio_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_icenic_mmio_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_icenic_mmio_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icenic_mmio_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icenic_mmio_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_icenic_mmio_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_icenic_mmio_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icenic_mmio_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_icenic_mmio_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_icenic_mmio_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_icenic_mmio_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input nic_in_valid, // @[NIC.scala:568:24] input [63:0] nic_in_bits_data, // @[NIC.scala:568:24] input [7:0] nic_in_bits_keep, // @[NIC.scala:568:24] input nic_in_bits_last, // @[NIC.scala:568:24] output nic_out_valid, // @[NIC.scala:568:24] output [63:0] nic_out_bits_data, // @[NIC.scala:568:24] output [7:0] nic_out_bits_keep, // @[NIC.scala:568:24] output nic_out_bits_last, // @[NIC.scala:568:24] input [47:0] nic_macAddr, // @[NIC.scala:568:24] input [7:0] nic_rlimit_inc, // @[NIC.scala:568:24] input [7:0] nic_rlimit_period, // @[NIC.scala:568:24] input [7:0] nic_rlimit_size, // @[NIC.scala:568:24] input [15:0] nic_pauser_threshold, // @[NIC.scala:568:24] input [15:0] nic_pauser_quanta, // @[NIC.scala:568:24] input [15:0] nic_pauser_refresh, // @[NIC.scala:568:24] output clock // @[ClockDomain.scala:21:19] ); wire auto_icenic_dma_out_1_a_ready_0 = auto_icenic_dma_out_1_a_ready; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_valid_0 = auto_icenic_dma_out_1_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_d_bits_opcode_0 = auto_icenic_dma_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_dma_out_1_d_bits_param_0 = auto_icenic_dma_out_1_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_1_d_bits_size_0 = auto_icenic_dma_out_1_d_bits_size; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_d_bits_source_0 = auto_icenic_dma_out_1_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_1_d_bits_sink_0 = auto_icenic_dma_out_1_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_bits_denied_0 = auto_icenic_dma_out_1_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_1_d_bits_data_0 = auto_icenic_dma_out_1_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_bits_corrupt_0 = auto_icenic_dma_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_a_ready_0 = auto_icenic_dma_out_0_a_ready; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_valid_0 = auto_icenic_dma_out_0_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_d_bits_opcode_0 = auto_icenic_dma_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_dma_out_0_d_bits_param_0 = auto_icenic_dma_out_0_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_0_d_bits_size_0 = auto_icenic_dma_out_0_d_bits_size; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_d_bits_source_0 = auto_icenic_dma_out_0_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_0_d_bits_sink_0 = auto_icenic_dma_out_0_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_bits_denied_0 = auto_icenic_dma_out_0_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_0_d_bits_data_0 = auto_icenic_dma_out_0_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_bits_corrupt_0 = auto_icenic_dma_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_a_valid_0 = auto_icenic_mmio_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_mmio_in_a_bits_opcode_0 = auto_icenic_mmio_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_mmio_in_a_bits_param_0 = auto_icenic_mmio_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_mmio_in_a_bits_size_0 = auto_icenic_mmio_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_icenic_mmio_in_a_bits_source_0 = auto_icenic_mmio_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_icenic_mmio_in_a_bits_address_0 = auto_icenic_mmio_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_icenic_mmio_in_a_bits_mask_0 = auto_icenic_mmio_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_mmio_in_a_bits_data_0 = auto_icenic_mmio_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_a_bits_corrupt_0 = auto_icenic_mmio_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_ready_0 = auto_icenic_mmio_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire nic_in_valid_0 = nic_in_valid; // @[ClockDomain.scala:14:9] wire [63:0] nic_in_bits_data_0 = nic_in_bits_data; // @[ClockDomain.scala:14:9] wire [7:0] nic_in_bits_keep_0 = nic_in_bits_keep; // @[ClockDomain.scala:14:9] wire nic_in_bits_last_0 = nic_in_bits_last; // @[ClockDomain.scala:14:9] wire [47:0] nic_macAddr_0 = nic_macAddr; // @[ClockDomain.scala:14:9] wire [7:0] nic_rlimit_inc_0 = nic_rlimit_inc; // @[ClockDomain.scala:14:9] wire [7:0] nic_rlimit_period_0 = nic_rlimit_period; // @[ClockDomain.scala:14:9] wire [7:0] nic_rlimit_size_0 = nic_rlimit_size; // @[ClockDomain.scala:14:9] wire [15:0] nic_pauser_threshold_0 = nic_pauser_threshold; // @[ClockDomain.scala:14:9] wire [15:0] nic_pauser_quanta_0 = nic_pauser_quanta; // @[ClockDomain.scala:14:9] wire [15:0] nic_pauser_refresh_0 = nic_pauser_refresh; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_a_bits_param = 3'h0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_a_bits_param = 3'h0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_a_bits_opcode = 3'h4; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_0_a_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_d_ready = 1'h1; // @[ClockDomain.scala:14:9] wire _nic_T_1 = 1'h1; // @[NIC.scala:525:28] wire [1:0] auto_icenic_mmio_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire _nic_T_4 = 1'h0; // @[NIC.scala:525:11] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire nic_vonly_in_valid = nic_in_valid_0; // @[ClockDomain.scala:14:9] wire [63:0] nic_vonly_in_bits_data = nic_in_bits_data_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_in_bits_keep = nic_in_bits_keep_0; // @[ClockDomain.scala:14:9] wire nic_vonly_in_bits_last = nic_in_bits_last_0; // @[ClockDomain.scala:14:9] wire nic_vonly_out_valid; // @[NIC.scala:519:21] wire [63:0] nic_vonly_out_bits_data; // @[NIC.scala:519:21] wire [7:0] nic_vonly_out_bits_keep; // @[NIC.scala:519:21] wire nic_vonly_out_bits_last; // @[NIC.scala:519:21] wire [47:0] nic_vonly_macAddr = nic_macAddr_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_rlimit_inc = nic_rlimit_inc_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_rlimit_period = nic_rlimit_period_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_vonly_rlimit_size = nic_rlimit_size_0; // @[ClockDomain.scala:14:9] wire [15:0] nic_vonly_pauser_threshold = nic_pauser_threshold_0; // @[ClockDomain.scala:14:9] wire [15:0] nic_vonly_pauser_quanta = nic_pauser_quanta_0; // @[ClockDomain.scala:14:9] wire auto_icenic_intsink_out_0_0; // @[ClockDomain.scala:14:9] wire auto_icenic_intsink_out_1_0; // @[ClockDomain.scala:14:9] wire [15:0] nic_vonly_pauser_refresh = nic_pauser_refresh_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_icenic_dma_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_icenic_dma_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_dma_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_1_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_icenic_dma_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_dma_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_icenic_dma_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_icenic_dma_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire auto_icenic_dma_out_0_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_icenic_mmio_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_icenic_mmio_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_icenic_mmio_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_icenic_mmio_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_icenic_mmio_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [63:0] nic_out_bits_data_0; // @[ClockDomain.scala:14:9] wire [7:0] nic_out_bits_keep_0; // @[ClockDomain.scala:14:9] wire nic_out_bits_last_0; // @[ClockDomain.scala:14:9] wire nic_out_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire _nic_T_2 = childReset; // @[NIC.scala:525:11] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] assign nic_out_valid_0 = nic_vonly_out_valid; // @[ClockDomain.scala:14:9] assign nic_out_bits_data_0 = nic_vonly_out_bits_data; // @[ClockDomain.scala:14:9] assign nic_out_bits_keep_0 = nic_vonly_out_bits_keep; // @[ClockDomain.scala:14:9] assign nic_out_bits_last_0 = nic_vonly_out_bits_last; // @[ClockDomain.scala:14:9] wire _nic_T = ~nic_vonly_in_valid; // @[NIC.scala:519:21, :525:12] wire _nic_T_3 = ~_nic_T_2; // @[NIC.scala:525:11] IceNIC icenic ( // @[NIC.scala:561:37] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_intsink_out_0 (auto_icenic_intsink_out_0_0), .auto_intsink_out_1 (auto_icenic_intsink_out_1_0), .auto_dma_out_1_a_ready (auto_icenic_dma_out_1_a_ready_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_a_valid (auto_icenic_dma_out_1_a_valid_0), .auto_dma_out_1_a_bits_opcode (auto_icenic_dma_out_1_a_bits_opcode_0), .auto_dma_out_1_a_bits_size (auto_icenic_dma_out_1_a_bits_size_0), .auto_dma_out_1_a_bits_source (auto_icenic_dma_out_1_a_bits_source_0), .auto_dma_out_1_a_bits_address (auto_icenic_dma_out_1_a_bits_address_0), .auto_dma_out_1_a_bits_mask (auto_icenic_dma_out_1_a_bits_mask_0), .auto_dma_out_1_a_bits_data (auto_icenic_dma_out_1_a_bits_data_0), .auto_dma_out_1_d_ready (auto_icenic_dma_out_1_d_ready_0), .auto_dma_out_1_d_valid (auto_icenic_dma_out_1_d_valid_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_opcode (auto_icenic_dma_out_1_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_param (auto_icenic_dma_out_1_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_size (auto_icenic_dma_out_1_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_source (auto_icenic_dma_out_1_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_sink (auto_icenic_dma_out_1_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_denied (auto_icenic_dma_out_1_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_data (auto_icenic_dma_out_1_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_dma_out_1_d_bits_corrupt (auto_icenic_dma_out_1_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_a_ready (auto_icenic_dma_out_0_a_ready_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_a_valid (auto_icenic_dma_out_0_a_valid_0), .auto_dma_out_0_a_bits_size (auto_icenic_dma_out_0_a_bits_size_0), .auto_dma_out_0_a_bits_source (auto_icenic_dma_out_0_a_bits_source_0), .auto_dma_out_0_a_bits_address (auto_icenic_dma_out_0_a_bits_address_0), .auto_dma_out_0_a_bits_mask (auto_icenic_dma_out_0_a_bits_mask_0), .auto_dma_out_0_d_valid (auto_icenic_dma_out_0_d_valid_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_opcode (auto_icenic_dma_out_0_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_param (auto_icenic_dma_out_0_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_size (auto_icenic_dma_out_0_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_source (auto_icenic_dma_out_0_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_sink (auto_icenic_dma_out_0_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_denied (auto_icenic_dma_out_0_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_data (auto_icenic_dma_out_0_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_dma_out_0_d_bits_corrupt (auto_icenic_dma_out_0_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_ready (auto_icenic_mmio_in_a_ready_0), .auto_mmio_in_a_valid (auto_icenic_mmio_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_opcode (auto_icenic_mmio_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_param (auto_icenic_mmio_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_size (auto_icenic_mmio_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_source (auto_icenic_mmio_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_address (auto_icenic_mmio_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_mask (auto_icenic_mmio_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_data (auto_icenic_mmio_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_a_bits_corrupt (auto_icenic_mmio_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_d_ready (auto_icenic_mmio_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_mmio_in_d_valid (auto_icenic_mmio_in_d_valid_0), .auto_mmio_in_d_bits_opcode (auto_icenic_mmio_in_d_bits_opcode_0), .auto_mmio_in_d_bits_size (auto_icenic_mmio_in_d_bits_size_0), .auto_mmio_in_d_bits_source (auto_icenic_mmio_in_d_bits_source_0), .auto_mmio_in_d_bits_data (auto_icenic_mmio_in_d_bits_data_0), .io_ext_in_valid (nic_vonly_in_valid), // @[NIC.scala:519:21] .io_ext_in_bits_data (nic_vonly_in_bits_data), // @[NIC.scala:519:21] .io_ext_in_bits_keep (nic_vonly_in_bits_keep), // @[NIC.scala:519:21] .io_ext_in_bits_last (nic_vonly_in_bits_last), // @[NIC.scala:519:21] .io_ext_out_valid (nic_vonly_out_valid), .io_ext_out_bits_data (nic_vonly_out_bits_data), .io_ext_out_bits_keep (nic_vonly_out_bits_keep), .io_ext_out_bits_last (nic_vonly_out_bits_last), .io_ext_macAddr (nic_vonly_macAddr), // @[NIC.scala:519:21] .io_ext_rlimit_inc (nic_vonly_rlimit_inc), // @[NIC.scala:519:21] .io_ext_rlimit_period (nic_vonly_rlimit_period), // @[NIC.scala:519:21] .io_ext_rlimit_size (nic_vonly_rlimit_size), // @[NIC.scala:519:21] .io_ext_pauser_threshold (nic_vonly_pauser_threshold), // @[NIC.scala:519:21] .io_ext_pauser_quanta (nic_vonly_pauser_quanta), // @[NIC.scala:519:21] .io_ext_pauser_refresh (nic_vonly_pauser_refresh) // @[NIC.scala:519:21] ); // @[NIC.scala:561:37] assign auto_icenic_intsink_out_0 = auto_icenic_intsink_out_0_0; // @[ClockDomain.scala:14:9] assign auto_icenic_intsink_out_1 = auto_icenic_intsink_out_1_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_valid = auto_icenic_dma_out_1_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_opcode = auto_icenic_dma_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_size = auto_icenic_dma_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_source = auto_icenic_dma_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_address = auto_icenic_dma_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_mask = auto_icenic_dma_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_a_bits_data = auto_icenic_dma_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_1_d_ready = auto_icenic_dma_out_1_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_valid = auto_icenic_dma_out_0_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_size = auto_icenic_dma_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_source = auto_icenic_dma_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_address = auto_icenic_dma_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_icenic_dma_out_0_a_bits_mask = auto_icenic_dma_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_a_ready = auto_icenic_mmio_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_valid = auto_icenic_mmio_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_opcode = auto_icenic_mmio_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_size = auto_icenic_mmio_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_source = auto_icenic_mmio_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_icenic_mmio_in_d_bits_data = auto_icenic_mmio_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign nic_out_valid = nic_out_valid_0; // @[ClockDomain.scala:14:9] assign nic_out_bits_data = nic_out_bits_data_0; // @[ClockDomain.scala:14:9] assign nic_out_bits_keep = nic_out_bits_keep_0; // @[ClockDomain.scala:14:9] assign nic_out_bits_last = nic_out_bits_last_0; // @[ClockDomain.scala:14:9] assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_500 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_244 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_500( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_244 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLUART : input clock : Clock input reset : Reset output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}} inst buffer of TLBuffer_a29d64s12k1z2u connect buffer.clock, clock connect buffer.reset, reset inst intsource of IntSyncCrossingSource_n1x1_60 connect intsource.clock, clock connect intsource.reset, reset wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeOut.rxd invalidate ioNodeOut.txd wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_115 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn connect intsource.auto.in[0], intnodeOut[0] connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect intXingIn, intsource.auto.out connect auto.io_out, ioNodeOut connect controlXingIn, auto.control_xing_in connect auto.int_xing_out, intXingOut inst txm of UARTTx connect txm.clock, clock connect txm.reset, reset inst txq of Queue8_UInt8 connect txq.clock, clock connect txq.reset, reset inst rxm of UARTRx connect rxm.clock, clock connect rxm.reset, reset inst rxq of Queue8_UInt8_1 connect rxq.clock, clock connect rxq.reset, reset regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4) regreset txen : UInt<1>, clock, reset, UInt<1>(0h0) regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0) regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0) regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset parity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errie : UInt<1>, clock, reset, UInt<1>(0h0) regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0) regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1) connect txm.io.en, txen connect txm.io.in, txq.io.deq connect txm.io.div, div connect txm.io.nstop, nstop connect ioNodeOut.txd, txm.io.out connect rxm.io.en, rxen connect rxm.io.in, ioNodeOut.rxd connect rxq.io.enq.valid, rxm.io.out.valid connect rxq.io.enq.bits, rxm.io.out.bits connect rxm.io.div, div node _tx_busy_T = orr(txq.io.count) node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T) node tx_busy = and(_tx_busy_T_1, txen) wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>} connect _ie_WIRE.txwm, UInt<1>(0h0) connect _ie_WIRE.rxwm, UInt<1>(0h0) regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE wire ip : { rxwm : UInt<1>, txwm : UInt<1>} node _ip_txwm_T = lt(txq.io.count, txwm) connect ip.txwm, _ip_txwm_T node _ip_rxwm_T = gt(rxq.io.count, rxwm) connect ip.rxwm, _ip_rxwm_T node _intnodeOut_0_T = and(ip.txwm, ie.txwm) node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm) node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1) connect intnodeOut[0], _intnodeOut_0_T_2 wire quash : UInt<1> node _T = eq(txq.io.enq.ready, UInt<1>(0h0)) node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0)) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[16] wire out_wivalid : UInt<1>[16] wire out_roready : UInt<1>[16] wire out_woready : UInt<1>[16] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 7, 0) node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0)) node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T) connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1 connect txq.io.enq.bits, _out_T_8 node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0)) node _out_T_16 = bits(_out_T_15, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 30, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 30, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 30, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 30, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 30, 8) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<8>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<31>(0h0)) node _out_T_25 = bits(_out_T_24, 30, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 31) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 31) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 31) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 31) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 31, 31) node _out_quash_T = bits(_out_T_26, 0, 0) node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T) connect quash, _out_quash_T_1 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0)) node out_prepend_1 = cat(_T, _out_prepend_T_1) node _out_T_33 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_34 = bits(_out_T_33, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 39, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 39, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 39, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 39, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxq.io.deq.ready, out_f_roready_3 node _out_T_35 = bits(out_front.bits.data, 39, 32) node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0)) node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2) node _out_T_42 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_43 = bits(_out_T_42, 39, 0) node _out_rimask_T_4 = bits(out_frontMask, 62, 40) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 62, 40) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 62, 40) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 62, 40) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_44 = bits(out_front.bits.data, 62, 40) node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_51 = or(out_prepend_3, UInt<63>(0h0)) node _out_T_52 = bits(_out_T_51, 62, 0) node _out_rimask_T_5 = bits(out_frontMask, 63, 63) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 63, 63) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 63, 63) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 63, 63) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_53 = bits(out_front.bits.data, 63, 63) node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0)) node out_prepend_4 = cat(_T_1, _out_prepend_T_4) node _out_T_60 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_61 = bits(_out_T_60, 63, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_62 = bits(out_front.bits.data, 0, 0) when out_f_woready_6 : connect txen, _out_T_62 node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_69 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_71 = or(txen, UInt<1>(0h0)) node _out_T_72 = bits(_out_T_71, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 1, 1) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 1, 1) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 1, 1) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 1, 1) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_73 = bits(out_front.bits.data, 1, 1) when out_f_woready_7 : connect nstop, _out_T_73 node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_80 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0)) node out_prepend_5 = cat(nstop, _out_prepend_T_5) node _out_T_82 = or(out_prepend_5, UInt<2>(0h0)) node _out_T_83 = bits(_out_T_82, 1, 0) node _out_rimask_T_8 = bits(out_frontMask, 19, 16) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 19, 16) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 19, 16) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 19, 16) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_84 = bits(out_front.bits.data, 19, 16) when out_f_woready_8 : connect txwm, _out_T_84 node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0)) node out_prepend_6 = cat(txwm, _out_prepend_T_6) node _out_T_93 = or(out_prepend_6, UInt<20>(0h0)) node _out_T_94 = bits(_out_T_93, 19, 0) node _out_rimask_T_9 = bits(out_frontMask, 32, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 32, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 32, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 32, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 32, 32) when out_f_woready_9 : connect rxen, _out_T_95 node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0)) node out_prepend_7 = cat(rxen, _out_prepend_T_7) node _out_T_104 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_105 = bits(_out_T_104, 32, 0) node _out_rimask_T_10 = bits(out_frontMask, 51, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 51, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 51, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 51, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_106 = bits(out_front.bits.data, 51, 48) when out_f_woready_10 : connect rxwm, _out_T_106 node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_113 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_114 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0)) node out_prepend_8 = cat(rxwm, _out_prepend_T_8) node _out_T_115 = or(out_prepend_8, UInt<52>(0h0)) node _out_T_116 = bits(_out_T_115, 51, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_117 = bits(out_front.bits.data, 0, 0) when out_f_woready_11 : connect ie.txwm, _out_T_117 node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_126 = or(ie.txwm, UInt<1>(0h0)) node _out_T_127 = bits(_out_T_126, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_128 = bits(out_front.bits.data, 1, 1) when out_f_woready_12 : connect ie.rxwm, _out_T_128 node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_135 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_136 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0)) node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9) node _out_T_137 = or(out_prepend_9, UInt<2>(0h0)) node _out_T_138 = bits(_out_T_137, 1, 0) node _out_rimask_T_13 = bits(out_frontMask, 32, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 32, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 32, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 32, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_139 = bits(out_front.bits.data, 32, 32) node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_144 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_145 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0)) node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10) node _out_T_146 = or(out_prepend_10, UInt<33>(0h0)) node _out_T_147 = bits(_out_T_146, 32, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 33) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 33) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 33) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 33) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_148 = bits(out_front.bits.data, 33, 33) node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_153 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_154 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0)) node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11) node _out_T_155 = or(out_prepend_11, UInt<34>(0h0)) node _out_T_156 = bits(_out_T_155, 33, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 0) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 0) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 0) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 0) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_157 = bits(out_front.bits.data, 15, 0) when out_f_woready_15 : connect div, _out_T_157 node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_164 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_165 = eq(out_womask_15, UInt<1>(0h0)) node _out_T_166 = or(div, UInt<16>(0h0)) node _out_T_167 = bits(_out_T_166, 15, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_7 connect out_rivalid[9], _out_rifireMux_T_7 connect out_rivalid[8], _out_rifireMux_T_7 connect out_rivalid[7], _out_rifireMux_T_7 connect out_rivalid[6], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_11 connect out_rivalid[13], _out_rifireMux_T_11 connect out_rivalid[12], _out_rifireMux_T_11 connect out_rivalid[11], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_8 connect out_wivalid[9], _out_wifireMux_T_8 connect out_wivalid[8], _out_wifireMux_T_8 connect out_wivalid[7], _out_wifireMux_T_8 connect out_wivalid[6], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_12 connect out_wivalid[13], _out_wifireMux_T_12 connect out_wivalid[12], _out_wifireMux_T_12 connect out_wivalid[11], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_7 connect out_roready[9], _out_rofireMux_T_7 connect out_roready[8], _out_rofireMux_T_7 connect out_roready[7], _out_rofireMux_T_7 connect out_roready[6], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_11 connect out_roready[13], _out_rofireMux_T_11 connect out_roready[12], _out_rofireMux_T_11 connect out_roready[11], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_8 connect out_woready[9], _out_wofireMux_T_8 connect out_woready[8], _out_wofireMux_T_8 connect out_woready[7], _out_wofireMux_T_8 connect out_woready[6], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_12 connect out_woready[13], _out_wofireMux_T_12 connect out_woready[12], _out_wofireMux_T_12 connect out_woready[11], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_61 connect _out_out_bits_data_WIRE_1[1], _out_T_116 connect _out_out_bits_data_WIRE_1[2], _out_T_156 connect _out_out_bits_data_WIRE_1[3], _out_T_167 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)

module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_woready_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] wire out_backSel_0; // @[RegisterRouter.scala:87:24] wire quash; // @[RegisterRouter.scala:87:24] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] reg [15:0] div; // @[UART.scala:135:20] reg txen; // @[UART.scala:141:21] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire ip_txwm = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] wire ip_rxwm = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] wire in_bits_read = auto_control_xing_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_7 = auto_control_xing_in_a_bits_address[11:5] == 7'h0; // @[RegisterRouter.scala:75:19, :87:24] assign quash = out_woready_2 & auto_control_xing_in_a_bits_mask[3] & auto_control_xing_in_a_bits_data[31]; // @[RegisterRouter.scala:87:24] assign out_backSel_0 = auto_control_xing_in_a_bits_address[4:3] == 2'h0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = auto_control_xing_in_a_valid & auto_control_xing_in_d_ready; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_2 = _out_wofireMux_T_2 & out_backSel_0 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_9 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h1 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_12 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h2 & _out_T_7; // @[RegisterRouter.scala:87:24] wire [3:0][63:0] _GEN = {{{48'h0, div}}, {{30'h0, ip_rxwm, ip_txwm, 30'h0, ie_rxwm, ie_txwm}}, {{12'h0, rxwm, 15'h0, rxen, 12'h0, txwm, 14'h0, nstop, txen}}, {{~_rxq_io_deq_valid, 23'h0, _rxq_io_deq_bits, ~_txq_io_enq_ready, 31'h0}}}; // @[MuxLiteral.scala:49:{10,48}] wire [2:0] controlXingIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:127:25, :141:21] rxen <= 1'h0; // @[UART.scala:127:25, :142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:127:25, :151:22] ie_rxwm <= 1'h0; // @[UART.scala:127:25, :186:19] ie_txwm <= 1'h0; // @[UART.scala:127:25, :186:19] end else begin // @[UART.scala:127:25] if (_out_wofireMux_T_2 & (&(auto_control_xing_in_a_bits_address[4:3])) & _out_T_7 & (&{{8{auto_control_xing_in_a_bits_mask[1]}}, {8{auto_control_xing_in_a_bits_mask[0]}}})) // @[RegisterRouter.scala:87:24] div <= auto_control_xing_in_a_bits_data[15:0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] txen <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[4]) // @[RegisterRouter.scala:87:24] rxen <= auto_control_xing_in_a_bits_data[32]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[2]) // @[RegisterRouter.scala:87:24] txwm <= auto_control_xing_in_a_bits_data[19:16]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[6]) // @[RegisterRouter.scala:87:24] rxwm <= auto_control_xing_in_a_bits_data[51:48]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] nstop <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_rxwm <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_txwm <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module CLINT : input clock : Clock input reset : Reset output auto : { int_out : UInt<1>[2], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip rtcTick : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_49 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeOut : UInt<1>[2] invalidate intnodeOut[0] invalidate intnodeOut[1] connect nodeIn, auto.in connect auto.int_out, intnodeOut regreset time : UInt<64>, clock, reset, UInt<64>(0h0) when io.rtcTick : node _time_T = add(time, UInt<1>(0h1)) node _time_T_1 = tail(_time_T, 1) connect time, _time_T_1 reg timecmp_0 : UInt<64>, clock regreset ipi_0 : UInt<1>, clock, reset, UInt<1>(0h0) node _intnodeOut_0_T = bits(ipi_0, 0, 0) connect intnodeOut[0], _intnodeOut_0_T node _intnodeOut_1_T = geq(time, timecmp_0) connect intnodeOut[1], _intnodeOut_1_T node pad = or(timecmp_0, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node timecmp_0_lo_lo = cat(newBytes[1], newBytes[0]) node timecmp_0_lo_hi = cat(newBytes[3], newBytes[2]) node timecmp_0_lo = cat(timecmp_0_lo_hi, timecmp_0_lo_lo) node timecmp_0_hi_lo = cat(newBytes[5], newBytes[4]) node timecmp_0_hi_hi = cat(newBytes[7], newBytes[6]) node timecmp_0_hi = cat(timecmp_0_hi_hi, timecmp_0_hi_lo) node _timecmp_0_T = cat(timecmp_0_hi, timecmp_0_lo) connect timecmp_0, _timecmp_0_T node pad_1 = or(time, UInt<64>(0h0)) node _oldBytes_T_8 = bits(pad_1, 7, 0) node _oldBytes_T_9 = bits(pad_1, 15, 8) node _oldBytes_T_10 = bits(pad_1, 23, 16) node _oldBytes_T_11 = bits(pad_1, 31, 24) node _oldBytes_T_12 = bits(pad_1, 39, 32) node _oldBytes_T_13 = bits(pad_1, 47, 40) node _oldBytes_T_14 = bits(pad_1, 55, 48) node _oldBytes_T_15 = bits(pad_1, 63, 56) wire oldBytes_1 : UInt<8>[8] connect oldBytes_1[0], _oldBytes_T_8 connect oldBytes_1[1], _oldBytes_T_9 connect oldBytes_1[2], _oldBytes_T_10 connect oldBytes_1[3], _oldBytes_T_11 connect oldBytes_1[4], _oldBytes_T_12 connect oldBytes_1[5], _oldBytes_T_13 connect oldBytes_1[6], _oldBytes_T_14 connect oldBytes_1[7], _oldBytes_T_15 wire newBytes_1 : UInt<8>[8] connect newBytes_1, oldBytes_1 wire _valids_WIRE_1 : UInt<1>[8] connect _valids_WIRE_1[0], UInt<1>(0h0) connect _valids_WIRE_1[1], UInt<1>(0h0) connect _valids_WIRE_1[2], UInt<1>(0h0) connect _valids_WIRE_1[3], UInt<1>(0h0) connect _valids_WIRE_1[4], UInt<1>(0h0) connect _valids_WIRE_1[5], UInt<1>(0h0) connect _valids_WIRE_1[6], UInt<1>(0h0) connect _valids_WIRE_1[7], UInt<1>(0h0) wire valids_1 : UInt<1>[8] connect valids_1, _valids_WIRE_1 node _T_7 = or(valids_1[0], valids_1[1]) node _T_8 = or(_T_7, valids_1[2]) node _T_9 = or(_T_8, valids_1[3]) node _T_10 = or(_T_9, valids_1[4]) node _T_11 = or(_T_10, valids_1[5]) node _T_12 = or(_T_11, valids_1[6]) node _T_13 = or(_T_12, valids_1[7]) when _T_13 : node time_lo_lo = cat(newBytes_1[1], newBytes_1[0]) node time_lo_hi = cat(newBytes_1[3], newBytes_1[2]) node time_lo = cat(time_lo_hi, time_lo_lo) node time_hi_lo = cat(newBytes_1[5], newBytes_1[4]) node time_hi_hi = cat(newBytes_1[7], newBytes_1[6]) node time_hi = cat(time_hi_hi, time_hi_lo) node _time_T_2 = cat(time_hi, time_lo) connect time, _time_T_2 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<13>(0h1800)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<13>(0h0)) node _out_T_1 = eq(out_bindex, UInt<13>(0h0)) node _out_T_2 = eq(out_findex, UInt<13>(0h7ff)) node _out_T_3 = eq(out_bindex, UInt<13>(0h7ff)) node _out_T_4 = eq(out_findex, UInt<13>(0h0)) node _out_T_5 = eq(out_bindex, UInt<13>(0h0)) wire out_rivalid : UInt<1>[18] wire out_wivalid : UInt<1>[18] wire out_roready : UInt<1>[18] wire out_woready : UInt<1>[18] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_front.bits.data, 0, 0) when out_f_woready : connect ipi_0, _out_T_6 node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(ipi_0, UInt<1>(0h0)) node _out_T_16 = bits(_out_T_15, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 31, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 31, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 31, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 31, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 31, 1) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<1>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<32>(0h0)) node _out_T_25 = bits(_out_T_24, 31, 0) node _out_rimask_T_2 = bits(out_frontMask, 7, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 7, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 7, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 7, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 7, 0) connect valids_1[0], out_f_woready_2 when out_f_woready_2 : connect newBytes_1[0], _out_T_26 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_35 = or(oldBytes_1[0], UInt<8>(0h0)) node _out_T_36 = bits(_out_T_35, 7, 0) node _out_rimask_T_3 = bits(out_frontMask, 15, 8) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 15, 8) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 15, 8) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 15, 8) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_37 = bits(out_front.bits.data, 15, 8) connect valids_1[1], out_f_woready_3 when out_f_woready_3 : connect newBytes_1[1], _out_T_37 node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_40 = and(out_f_wivalid_3, UInt<1>(0h1)) node _out_T_41 = and(UInt<1>(0h1), out_f_woready_3) node _out_T_42 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_43 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_44 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_45 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_36, UInt<8>(0h0)) node out_prepend_1 = cat(oldBytes_1[1], _out_prepend_T_1) node _out_T_46 = or(out_prepend_1, UInt<16>(0h0)) node _out_T_47 = bits(_out_T_46, 15, 0) node _out_rimask_T_4 = bits(out_frontMask, 23, 16) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 23, 16) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 23, 16) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 23, 16) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_48 = bits(out_front.bits.data, 23, 16) connect valids_1[2], out_f_woready_4 when out_f_woready_4 : connect newBytes_1[2], _out_T_48 node _out_T_49 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_50 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_51 = and(out_f_wivalid_4, UInt<1>(0h1)) node _out_T_52 = and(UInt<1>(0h1), out_f_woready_4) node _out_T_53 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_54 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_55 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_56 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_47, UInt<16>(0h0)) node out_prepend_2 = cat(oldBytes_1[2], _out_prepend_T_2) node _out_T_57 = or(out_prepend_2, UInt<24>(0h0)) node _out_T_58 = bits(_out_T_57, 23, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 24) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 24) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 24) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 24) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_59 = bits(out_front.bits.data, 31, 24) connect valids_1[3], out_f_woready_5 when out_f_woready_5 : connect newBytes_1[3], _out_T_59 node _out_T_60 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_61 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_62 = and(out_f_wivalid_5, UInt<1>(0h1)) node _out_T_63 = and(UInt<1>(0h1), out_f_woready_5) node _out_T_64 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_65 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_66 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_67 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_58, UInt<24>(0h0)) node out_prepend_3 = cat(oldBytes_1[3], _out_prepend_T_3) node _out_T_68 = or(out_prepend_3, UInt<32>(0h0)) node _out_T_69 = bits(_out_T_68, 31, 0) node _out_rimask_T_6 = bits(out_frontMask, 39, 32) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 39, 32) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 39, 32) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 39, 32) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_70 = bits(out_front.bits.data, 39, 32) connect valids_1[4], out_f_woready_6 when out_f_woready_6 : connect newBytes_1[4], _out_T_70 node _out_T_71 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_72 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_73 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_74 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_75 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_76 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_77 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_78 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_69, UInt<32>(0h0)) node out_prepend_4 = cat(oldBytes_1[4], _out_prepend_T_4) node _out_T_79 = or(out_prepend_4, UInt<40>(0h0)) node _out_T_80 = bits(_out_T_79, 39, 0) node _out_rimask_T_7 = bits(out_frontMask, 47, 40) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 47, 40) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 47, 40) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 47, 40) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_81 = bits(out_front.bits.data, 47, 40) connect valids_1[5], out_f_woready_7 when out_f_woready_7 : connect newBytes_1[5], _out_T_81 node _out_T_82 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_83 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_84 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_85 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_86 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_87 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_88 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_89 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_80, UInt<40>(0h0)) node out_prepend_5 = cat(oldBytes_1[5], _out_prepend_T_5) node _out_T_90 = or(out_prepend_5, UInt<48>(0h0)) node _out_T_91 = bits(_out_T_90, 47, 0) node _out_rimask_T_8 = bits(out_frontMask, 55, 48) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 55, 48) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 55, 48) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 55, 48) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_92 = bits(out_front.bits.data, 55, 48) connect valids_1[6], out_f_woready_8 when out_f_woready_8 : connect newBytes_1[6], _out_T_92 node _out_T_93 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_94 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_95 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_96 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_97 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_98 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_99 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_100 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_91, UInt<48>(0h0)) node out_prepend_6 = cat(oldBytes_1[6], _out_prepend_T_6) node _out_T_101 = or(out_prepend_6, UInt<56>(0h0)) node _out_T_102 = bits(_out_T_101, 55, 0) node _out_rimask_T_9 = bits(out_frontMask, 63, 56) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 63, 56) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 63, 56) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 63, 56) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_103 = bits(out_front.bits.data, 63, 56) connect valids_1[7], out_f_woready_9 when out_f_woready_9 : connect newBytes_1[7], _out_T_103 node _out_T_104 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_105 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_106 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_107 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_108 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_109 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_110 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_111 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_102, UInt<56>(0h0)) node out_prepend_7 = cat(oldBytes_1[7], _out_prepend_T_7) node _out_T_112 = or(out_prepend_7, UInt<64>(0h0)) node _out_T_113 = bits(_out_T_112, 63, 0) node _out_rimask_T_10 = bits(out_frontMask, 7, 0) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 7, 0) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 7, 0) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 7, 0) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_114 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready_10 when out_f_woready_10 : connect newBytes[0], _out_T_114 node _out_T_115 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_116 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_117 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_118 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_119 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_120 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_121 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_122 = eq(out_womask_10, UInt<1>(0h0)) node _out_T_123 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_124 = bits(_out_T_123, 7, 0) node _out_rimask_T_11 = bits(out_frontMask, 15, 8) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 15, 8) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 15, 8) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 15, 8) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_125 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_11 when out_f_woready_11 : connect newBytes[1], _out_T_125 node _out_T_126 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_127 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_128 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_129 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_130 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_131 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_132 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_133 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_124, UInt<8>(0h0)) node out_prepend_8 = cat(oldBytes[1], _out_prepend_T_8) node _out_T_134 = or(out_prepend_8, UInt<16>(0h0)) node _out_T_135 = bits(_out_T_134, 15, 0) node _out_rimask_T_12 = bits(out_frontMask, 23, 16) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 23, 16) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 23, 16) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 23, 16) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_136 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_12 when out_f_woready_12 : connect newBytes[2], _out_T_136 node _out_T_137 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_138 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_139 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_140 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_141 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_142 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_143 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_144 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_135, UInt<16>(0h0)) node out_prepend_9 = cat(oldBytes[2], _out_prepend_T_9) node _out_T_145 = or(out_prepend_9, UInt<24>(0h0)) node _out_T_146 = bits(_out_T_145, 23, 0) node _out_rimask_T_13 = bits(out_frontMask, 31, 24) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 31, 24) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 31, 24) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 31, 24) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_147 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_13 when out_f_woready_13 : connect newBytes[3], _out_T_147 node _out_T_148 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_149 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_150 = and(out_f_wivalid_13, UInt<1>(0h1)) node _out_T_151 = and(UInt<1>(0h1), out_f_woready_13) node _out_T_152 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_153 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_154 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_155 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_146, UInt<24>(0h0)) node out_prepend_10 = cat(oldBytes[3], _out_prepend_T_10) node _out_T_156 = or(out_prepend_10, UInt<32>(0h0)) node _out_T_157 = bits(_out_T_156, 31, 0) node _out_rimask_T_14 = bits(out_frontMask, 39, 32) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 39, 32) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 39, 32) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 39, 32) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_158 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_14 when out_f_woready_14 : connect newBytes[4], _out_T_158 node _out_T_159 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_160 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_161 = and(out_f_wivalid_14, UInt<1>(0h1)) node _out_T_162 = and(UInt<1>(0h1), out_f_woready_14) node _out_T_163 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_164 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_165 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_166 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_157, UInt<32>(0h0)) node out_prepend_11 = cat(oldBytes[4], _out_prepend_T_11) node _out_T_167 = or(out_prepend_11, UInt<40>(0h0)) node _out_T_168 = bits(_out_T_167, 39, 0) node _out_rimask_T_15 = bits(out_frontMask, 47, 40) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 47, 40) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 47, 40) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 47, 40) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_169 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_15 when out_f_woready_15 : connect newBytes[5], _out_T_169 node _out_T_170 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_171 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_172 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_173 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_174 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_175 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_176 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_177 = eq(out_womask_15, UInt<1>(0h0)) node _out_prepend_T_12 = or(_out_T_168, UInt<40>(0h0)) node out_prepend_12 = cat(oldBytes[5], _out_prepend_T_12) node _out_T_178 = or(out_prepend_12, UInt<48>(0h0)) node _out_T_179 = bits(_out_T_178, 47, 0) node _out_rimask_T_16 = bits(out_frontMask, 55, 48) node out_rimask_16 = orr(_out_rimask_T_16) node _out_wimask_T_16 = bits(out_frontMask, 55, 48) node out_wimask_16 = andr(_out_wimask_T_16) node _out_romask_T_16 = bits(out_backMask, 55, 48) node out_romask_16 = orr(_out_romask_T_16) node _out_womask_T_16 = bits(out_backMask, 55, 48) node out_womask_16 = andr(_out_womask_T_16) node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) node out_f_roready_16 = and(out_roready[16], out_romask_16) node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) node out_f_woready_16 = and(out_woready[16], out_womask_16) node _out_T_180 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_16 when out_f_woready_16 : connect newBytes[6], _out_T_180 node _out_T_181 = and(out_f_rivalid_16, UInt<1>(0h1)) node _out_T_182 = and(UInt<1>(0h1), out_f_roready_16) node _out_T_183 = and(out_f_wivalid_16, UInt<1>(0h1)) node _out_T_184 = and(UInt<1>(0h1), out_f_woready_16) node _out_T_185 = eq(out_rimask_16, UInt<1>(0h0)) node _out_T_186 = eq(out_wimask_16, UInt<1>(0h0)) node _out_T_187 = eq(out_romask_16, UInt<1>(0h0)) node _out_T_188 = eq(out_womask_16, UInt<1>(0h0)) node _out_prepend_T_13 = or(_out_T_179, UInt<48>(0h0)) node out_prepend_13 = cat(oldBytes[6], _out_prepend_T_13) node _out_T_189 = or(out_prepend_13, UInt<56>(0h0)) node _out_T_190 = bits(_out_T_189, 55, 0) node _out_rimask_T_17 = bits(out_frontMask, 63, 56) node out_rimask_17 = orr(_out_rimask_T_17) node _out_wimask_T_17 = bits(out_frontMask, 63, 56) node out_wimask_17 = andr(_out_wimask_T_17) node _out_romask_T_17 = bits(out_backMask, 63, 56) node out_romask_17 = orr(_out_romask_T_17) node _out_womask_T_17 = bits(out_backMask, 63, 56) node out_womask_17 = andr(_out_womask_T_17) node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) node out_f_roready_17 = and(out_roready[17], out_romask_17) node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) node out_f_woready_17 = and(out_woready[17], out_womask_17) node _out_T_191 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_17 when out_f_woready_17 : connect newBytes[7], _out_T_191 node _out_T_192 = and(out_f_rivalid_17, UInt<1>(0h1)) node _out_T_193 = and(UInt<1>(0h1), out_f_roready_17) node _out_T_194 = and(out_f_wivalid_17, UInt<1>(0h1)) node _out_T_195 = and(UInt<1>(0h1), out_f_woready_17) node _out_T_196 = eq(out_rimask_17, UInt<1>(0h0)) node _out_T_197 = eq(out_wimask_17, UInt<1>(0h0)) node _out_T_198 = eq(out_romask_17, UInt<1>(0h0)) node _out_T_199 = eq(out_womask_17, UInt<1>(0h0)) node _out_prepend_T_14 = or(_out_T_190, UInt<56>(0h0)) node out_prepend_14 = cat(oldBytes[7], _out_prepend_T_14) node _out_T_200 = or(out_prepend_14, UInt<64>(0h0)) node _out_T_201 = bits(_out_T_200, 63, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node out_iindex = cat(_out_iindex_T_12, _out_iindex_T_11) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_front.bits.index, 12, 12) node out_oindex = cat(_out_oindex_T_12, _out_oindex_T_11) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[17], _out_rifireMux_T_7 connect out_rivalid[16], _out_rifireMux_T_7 connect out_rivalid[15], _out_rifireMux_T_7 connect out_rivalid[14], _out_rifireMux_T_7 connect out_rivalid[13], _out_rifireMux_T_7 connect out_rivalid[12], _out_rifireMux_T_7 connect out_rivalid[11], _out_rifireMux_T_7 connect out_rivalid[10], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[9], _out_rifireMux_T_11 connect out_rivalid[8], _out_rifireMux_T_11 connect out_rivalid[7], _out_rifireMux_T_11 connect out_rivalid[6], _out_rifireMux_T_11 connect out_rivalid[5], _out_rifireMux_T_11 connect out_rivalid[4], _out_rifireMux_T_11 connect out_rivalid[3], _out_rifireMux_T_11 connect out_rivalid[2], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[17], _out_wifireMux_T_8 connect out_wivalid[16], _out_wifireMux_T_8 connect out_wivalid[15], _out_wifireMux_T_8 connect out_wivalid[14], _out_wifireMux_T_8 connect out_wivalid[13], _out_wifireMux_T_8 connect out_wivalid[12], _out_wifireMux_T_8 connect out_wivalid[11], _out_wifireMux_T_8 connect out_wivalid[10], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[9], _out_wifireMux_T_12 connect out_wivalid[8], _out_wifireMux_T_12 connect out_wivalid[7], _out_wifireMux_T_12 connect out_wivalid[6], _out_wifireMux_T_12 connect out_wivalid[5], _out_wifireMux_T_12 connect out_wivalid[4], _out_wifireMux_T_12 connect out_wivalid[3], _out_wifireMux_T_12 connect out_wivalid[2], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[17], _out_rofireMux_T_7 connect out_roready[16], _out_rofireMux_T_7 connect out_roready[15], _out_rofireMux_T_7 connect out_roready[14], _out_rofireMux_T_7 connect out_roready[13], _out_rofireMux_T_7 connect out_roready[12], _out_rofireMux_T_7 connect out_roready[11], _out_rofireMux_T_7 connect out_roready[10], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[9], _out_rofireMux_T_11 connect out_roready[8], _out_rofireMux_T_11 connect out_roready[7], _out_rofireMux_T_11 connect out_roready[6], _out_rofireMux_T_11 connect out_roready[5], _out_rofireMux_T_11 connect out_roready[4], _out_rofireMux_T_11 connect out_roready[3], _out_rofireMux_T_11 connect out_roready[2], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[17], _out_wofireMux_T_8 connect out_woready[16], _out_wofireMux_T_8 connect out_woready[15], _out_wofireMux_T_8 connect out_woready[14], _out_wofireMux_T_8 connect out_woready[13], _out_wofireMux_T_8 connect out_woready[12], _out_wofireMux_T_8 connect out_woready[11], _out_wofireMux_T_8 connect out_woready[10], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[9], _out_wofireMux_T_12 connect out_woready[8], _out_wofireMux_T_12 connect out_woready[7], _out_wofireMux_T_12 connect out_woready[6], _out_wofireMux_T_12 connect out_woready[5], _out_wofireMux_T_12 connect out_woready[4], _out_wofireMux_T_12 connect out_woready[3], _out_wofireMux_T_12 connect out_woready[2], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], UInt<1>(0h1) node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_25 connect _out_out_bits_data_WIRE_1[1], _out_T_201 connect _out_out_bits_data_WIRE_1[2], _out_T_113 connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0) node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)

module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [11:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_49 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_4 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 9, 6) node req_tag = shr(req.addr, 10) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_4 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock reg refill_ctr : UInt<3>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) invalidate io.meta_write.bits.data.tag invalidate io.meta_write.bits.data.coh.state invalidate io.meta_write.bits.tag invalidate io.meta_write.bits.way_en invalidate io.meta_write.bits.idx connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) invalidate io.mem_acquire.bits.corrupt invalidate io.mem_acquire.bits.data invalidate io.mem_acquire.bits.mask invalidate io.mem_acquire.bits.address invalidate io.mem_acquire.bits.source invalidate io.mem_acquire.bits.size invalidate io.mem_acquire.bits.param invalidate io.mem_acquire.bits.opcode connect io.refill.valid, UInt<1>(0h0) invalidate io.refill.bits.data invalidate io.refill.bits.wmask invalidate io.refill.bits.addr invalidate io.refill.bits.way_en connect io.replay.valid, UInt<1>(0h0) invalidate io.replay.bits.sdq_id invalidate io.replay.bits.way_en invalidate io.replay.bits.old_meta.tag invalidate io.replay.bits.old_meta.coh.state invalidate io.replay.bits.tag_match invalidate io.replay.bits.is_hella invalidate io.replay.bits.data invalidate io.replay.bits.addr invalidate io.replay.bits.uop.debug_tsrc invalidate io.replay.bits.uop.debug_fsrc invalidate io.replay.bits.uop.bp_xcpt_if invalidate io.replay.bits.uop.bp_debug_if invalidate io.replay.bits.uop.xcpt_ma_if invalidate io.replay.bits.uop.xcpt_ae_if invalidate io.replay.bits.uop.xcpt_pf_if invalidate io.replay.bits.uop.fp_single invalidate io.replay.bits.uop.fp_val invalidate io.replay.bits.uop.frs3_en invalidate io.replay.bits.uop.lrs2_rtype invalidate io.replay.bits.uop.lrs1_rtype invalidate io.replay.bits.uop.dst_rtype invalidate io.replay.bits.uop.ldst_val invalidate io.replay.bits.uop.lrs3 invalidate io.replay.bits.uop.lrs2 invalidate io.replay.bits.uop.lrs1 invalidate io.replay.bits.uop.ldst invalidate io.replay.bits.uop.ldst_is_rs1 invalidate io.replay.bits.uop.flush_on_commit invalidate io.replay.bits.uop.is_unique invalidate io.replay.bits.uop.is_sys_pc2epc invalidate io.replay.bits.uop.uses_stq invalidate io.replay.bits.uop.uses_ldq invalidate io.replay.bits.uop.is_amo invalidate io.replay.bits.uop.is_fencei invalidate io.replay.bits.uop.is_fence invalidate io.replay.bits.uop.mem_signed invalidate io.replay.bits.uop.mem_size invalidate io.replay.bits.uop.mem_cmd invalidate io.replay.bits.uop.bypassable invalidate io.replay.bits.uop.exc_cause invalidate io.replay.bits.uop.exception invalidate io.replay.bits.uop.stale_pdst invalidate io.replay.bits.uop.ppred_busy invalidate io.replay.bits.uop.prs3_busy invalidate io.replay.bits.uop.prs2_busy invalidate io.replay.bits.uop.prs1_busy invalidate io.replay.bits.uop.ppred invalidate io.replay.bits.uop.prs3 invalidate io.replay.bits.uop.prs2 invalidate io.replay.bits.uop.prs1 invalidate io.replay.bits.uop.pdst invalidate io.replay.bits.uop.rxq_idx invalidate io.replay.bits.uop.stq_idx invalidate io.replay.bits.uop.ldq_idx invalidate io.replay.bits.uop.rob_idx invalidate io.replay.bits.uop.csr_addr invalidate io.replay.bits.uop.imm_packed invalidate io.replay.bits.uop.taken invalidate io.replay.bits.uop.pc_lob invalidate io.replay.bits.uop.edge_inst invalidate io.replay.bits.uop.ftq_idx invalidate io.replay.bits.uop.br_tag invalidate io.replay.bits.uop.br_mask invalidate io.replay.bits.uop.is_sfb invalidate io.replay.bits.uop.is_jal invalidate io.replay.bits.uop.is_jalr invalidate io.replay.bits.uop.is_br invalidate io.replay.bits.uop.iw_p2_poisoned invalidate io.replay.bits.uop.iw_p1_poisoned invalidate io.replay.bits.uop.iw_state invalidate io.replay.bits.uop.ctrl.is_std invalidate io.replay.bits.uop.ctrl.is_sta invalidate io.replay.bits.uop.ctrl.is_load invalidate io.replay.bits.uop.ctrl.csr_cmd invalidate io.replay.bits.uop.ctrl.fcn_dw invalidate io.replay.bits.uop.ctrl.op_fcn invalidate io.replay.bits.uop.ctrl.imm_sel invalidate io.replay.bits.uop.ctrl.op2_sel invalidate io.replay.bits.uop.ctrl.op1_sel invalidate io.replay.bits.uop.ctrl.br_type invalidate io.replay.bits.uop.fu_code invalidate io.replay.bits.uop.iq_type invalidate io.replay.bits.uop.debug_pc invalidate io.replay.bits.uop.is_rvc invalidate io.replay.bits.uop.debug_inst invalidate io.replay.bits.uop.inst invalidate io.replay.bits.uop.uopc connect io.wb_req.valid, UInt<1>(0h0) invalidate io.wb_req.bits.voluntary invalidate io.wb_req.bits.way_en invalidate io.wb_req.bits.param invalidate io.wb_req.bits.source invalidate io.wb_req.bits.idx invalidate io.wb_req.bits.tag connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.is_hella invalidate io.resp.bits.data invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) invalidate io.meta_read.bits.tag invalidate io.meta_read.bits.way_en invalidate io.meta_read.bits.idx connect io.mem_finish.valid, UInt<1>(0h0) invalidate io.mem_finish.bits.sink connect io.lb_write.valid, UInt<1>(0h0) invalidate io.lb_write.bits.data invalidate io.lb_write.bits.offset invalidate io.lb_write.bits.id connect io.lb_read.valid, UInt<1>(0h0) invalidate io.lb_read.bits.offset invalidate io.lb_read.bits.id connect io.mem_grant.ready, UInt<1>(0h0) node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5) node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7) node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9) node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.mem_grant.ready, io.lb_write.ready connect io.lb_write.valid, io.mem_grant.valid connect io.lb_write.bits.id, io.id node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<3>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready) node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1 node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load) connect io.lb_read.valid, _io_lb_read_valid_T connect io.lb_read.bits.id, io.id node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3) connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid) node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T) node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load) connect io.resp.valid, _io_resp_valid_T_2 connect io.resp.bits.uop, rpq.io.deq.bits.uop node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.valid, UInt<1>(0h1) connect io.lb_read.bits.id, io.id connect io.lb_read.bits.offset, refill_ctr node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid) connect io.refill.valid, _io_refill_valid_T node _io_refill_bits_addr_T = shl(refill_ctr, 3) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<1>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<3>(0h7)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid connect io.mem_finish.bits, grantack.bits node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1

module BoomMSHR_4( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [2:0] io_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h4; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h4; // @[mshrs.scala:36:7] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h4; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26] wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = |state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = |state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [27:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_229 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_229( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_24 = shr(io.in.a.bits.source, 3) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h10000))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h10000000))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h10000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h10000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_102 = shr(io.in.a.bits.source, 3) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h10000))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h10000000))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h10000000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_184 = shr(io.in.a.bits.source, 3) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h10000000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_237 = shr(io.in.a.bits.source, 3) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h10000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h10000000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_284 = shr(io.in.a.bits.source, 3) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_333 = shr(io.in.a.bits.source, 3) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h10000000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_377 = shr(io.in.a.bits.source, 3) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h10000))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h10000000))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_421 = shr(io.in.a.bits.source, 3) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h10000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h10000000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 3) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_602 = shr(io.in.b.bits.source, 3) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h10000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h10000000))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h10000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h10000000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h10000000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h10000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h10000000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h10000))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h10000000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 3) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_906 = shr(io.in.c.bits.source, 3) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_966 = shr(io.in.c.bits.source, 3) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h10000))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h10000000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h10000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h10000000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1039 = shr(io.in.c.bits.source, 3) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h10000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h10000000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h10000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h10000000))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes : UInt<20>, clock, reset, UInt<20>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<5> connect a_set, UInt<5>(0h0) wire a_set_wo_ready : UInt<5> connect a_set_wo_ready, UInt<5>(0h0) wire a_opcodes_set : UInt<20> connect a_opcodes_set, UInt<20>(0h0) wire a_sizes_set : UInt<20> connect a_sizes_set, UInt<20>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<5> connect d_clr, UInt<5>(0h0) wire d_clr_wo_ready : UInt<5> connect d_clr_wo_ready, UInt<5>(0h0) wire d_opcodes_clr : UInt<20> connect d_opcodes_clr, UInt<20>(0h0) wire d_sizes_clr : UInt<20> connect d_sizes_clr, UInt<20>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_90 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes_1 : UInt<20>, clock, reset, UInt<20>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<5> connect c_set, UInt<5>(0h0) wire c_set_wo_ready : UInt<5> connect c_set_wo_ready, UInt<5>(0h0) wire c_opcodes_set : UInt<20> connect c_opcodes_set, UInt<20>(0h0) wire c_sizes_set : UInt<20> connect c_sizes_set, UInt<20>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<5> connect d_clr_1, UInt<5>(0h0) wire d_clr_wo_ready_1 : UInt<5> connect d_clr_wo_ready_1, UInt<5>(0h0) wire d_opcodes_clr_1 : UInt<20> connect d_opcodes_clr_1, UInt<20>(0h0) wire d_sizes_clr_1 : UInt<20> connect d_sizes_clr_1, UInt<20>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_91 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [19:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [7:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_Debug : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_28 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a12d64s9k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<9>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<9>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLFragmenter_Debug( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [8:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [11:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [8:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [12:0] _find_T_2 = 13'h0; // @[Parameters.scala:137:46] wire [12:0] _find_T_3 = 13'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [8:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [11:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [12:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [12:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [8:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [8:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [12:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[12:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [11:0] _find_T; // @[Parameters.scala:137:31] wire [12:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[11:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [9:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_127 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_127( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s7k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s7k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s7k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s7k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_8 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset

module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [6:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [6:0] in_xbar__addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar__requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar__requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] in_xbar_requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56] wire [6:0] in_xbar__beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar__beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar__portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] in_xbar__portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] in_xbar_portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] in_xbar__portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] in_xbar__portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] in_xbar_portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire in_ready; // @[RegisterRouter.scala:73:18] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34] wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52] wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35] bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_pbus_out_i1_o2_a29d64s7k1z3u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s7k1z3u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] TLBuffer_a29d64s7k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (bus_xingOut_a_ready), .auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (bus_xingOut_d_valid), .auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode), .auto_in_d_bits_param (bus_xingOut_d_bits_param), .auto_in_d_bits_size (bus_xingOut_d_bits_size), .auto_in_d_bits_source (bus_xingOut_d_bits_source), .auto_in_d_bits_sink (bus_xingOut_d_bits_sink), .auto_in_d_bits_denied (bus_xingOut_d_bits_denied), .auto_in_d_bits_data (bus_xingOut_d_bits_data), .auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt), .auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_out_a_valid (in_xbar_auto_anon_in_a_valid), .auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param), .auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size), .auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source), .auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (in_xbar_auto_anon_in_d_ready), .auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9] .auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9] .auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_a_valid (nodeIn_a_valid), .auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param), .auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size), .auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source), .auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address), .auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask), .auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data), .auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_fragmenter_anon_out_d_ready (nodeIn_d_ready), .auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0), .auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0), .auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0), .auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0), .auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0), .auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0), .auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0), .auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0), .auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0), .auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0), .auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLMonitor_8 monitor ( // @[Nodes.scala:27:25] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_100 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_100( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_111 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_111( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] next_uop_ppred = 5'h0; // @[issue-slot.scala:103:21] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21] wire _p3_T = 1'h1; // @[issue-slot.scala:171:11] wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module NoC : input clock : Clock input reset : Reset output auto : { } output io : { ingress : { flip `22` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `21` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `20` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `19` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}}, egress : { `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}, flip router_clocks : { clock : Clock, reset : Reset}[13]} inst router_sink_domain of TLSplitACDxBENoC_acd_router_0ClockSinkDomain inst router_sink_domain_1 of TLSplitACDxBENoC_acd_router_1ClockSinkDomain inst router_sink_domain_2 of TLSplitACDxBENoC_acd_router_2ClockSinkDomain inst router_sink_domain_3 of TLSplitACDxBENoC_acd_router_3ClockSinkDomain inst router_sink_domain_4 of TLSplitACDxBENoC_acd_router_4ClockSinkDomain inst router_sink_domain_5 of TLSplitACDxBENoC_acd_router_5ClockSinkDomain inst router_sink_domain_6 of TLSplitACDxBENoC_acd_router_6ClockSinkDomain inst router_sink_domain_7 of TLSplitACDxBENoC_acd_router_7ClockSinkDomain inst router_sink_domain_8 of TLSplitACDxBENoC_acd_router_8ClockSinkDomain inst router_sink_domain_9 of TLSplitACDxBENoC_acd_router_9ClockSinkDomain inst router_sink_domain_10 of TLSplitACDxBENoC_acd_router_10ClockSinkDomain inst router_sink_domain_11 of TLSplitACDxBENoC_acd_router_11ClockSinkDomain inst router_sink_domain_12 of TLSplitACDxBENoC_acd_router_12ClockSinkDomain wire clockSourceNodesOut : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut.reset invalidate clockSourceNodesOut.clock wire clockSourceNodesOut_1 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_1.reset invalidate clockSourceNodesOut_1.clock wire clockSourceNodesOut_2 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_2.reset invalidate clockSourceNodesOut_2.clock wire clockSourceNodesOut_3 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_3.reset invalidate clockSourceNodesOut_3.clock wire clockSourceNodesOut_4 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_4.reset invalidate clockSourceNodesOut_4.clock wire clockSourceNodesOut_5 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_5.reset invalidate clockSourceNodesOut_5.clock wire clockSourceNodesOut_6 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_6.reset invalidate clockSourceNodesOut_6.clock wire clockSourceNodesOut_7 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_7.reset invalidate clockSourceNodesOut_7.clock wire clockSourceNodesOut_8 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_8.reset invalidate clockSourceNodesOut_8.clock wire clockSourceNodesOut_9 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_9.reset invalidate clockSourceNodesOut_9.clock wire clockSourceNodesOut_10 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_10.reset invalidate clockSourceNodesOut_10.clock wire clockSourceNodesOut_11 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_11.reset invalidate clockSourceNodesOut_11.clock wire clockSourceNodesOut_12 : { clock : Clock, reset : Reset} invalidate clockSourceNodesOut_12.reset invalidate clockSourceNodesOut_12.clock wire ingressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut.flit.bits.egress_id invalidate ingressNodesOut.flit.bits.payload invalidate ingressNodesOut.flit.bits.tail invalidate ingressNodesOut.flit.bits.head invalidate ingressNodesOut.flit.valid invalidate ingressNodesOut.flit.ready wire ingressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_1.flit.bits.egress_id invalidate ingressNodesOut_1.flit.bits.payload invalidate ingressNodesOut_1.flit.bits.tail invalidate ingressNodesOut_1.flit.bits.head invalidate ingressNodesOut_1.flit.valid invalidate ingressNodesOut_1.flit.ready wire ingressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_2.flit.bits.egress_id invalidate ingressNodesOut_2.flit.bits.payload invalidate ingressNodesOut_2.flit.bits.tail invalidate ingressNodesOut_2.flit.bits.head invalidate ingressNodesOut_2.flit.valid invalidate ingressNodesOut_2.flit.ready wire ingressNodesOut_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_3.flit.bits.egress_id invalidate ingressNodesOut_3.flit.bits.payload invalidate ingressNodesOut_3.flit.bits.tail invalidate ingressNodesOut_3.flit.bits.head invalidate ingressNodesOut_3.flit.valid invalidate ingressNodesOut_3.flit.ready wire ingressNodesOut_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_4.flit.bits.egress_id invalidate ingressNodesOut_4.flit.bits.payload invalidate ingressNodesOut_4.flit.bits.tail invalidate ingressNodesOut_4.flit.bits.head invalidate ingressNodesOut_4.flit.valid invalidate ingressNodesOut_4.flit.ready wire ingressNodesOut_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_5.flit.bits.egress_id invalidate ingressNodesOut_5.flit.bits.payload invalidate ingressNodesOut_5.flit.bits.tail invalidate ingressNodesOut_5.flit.bits.head invalidate ingressNodesOut_5.flit.valid invalidate ingressNodesOut_5.flit.ready wire ingressNodesOut_6 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_6.flit.bits.egress_id invalidate ingressNodesOut_6.flit.bits.payload invalidate ingressNodesOut_6.flit.bits.tail invalidate ingressNodesOut_6.flit.bits.head invalidate ingressNodesOut_6.flit.valid invalidate ingressNodesOut_6.flit.ready wire ingressNodesOut_7 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_7.flit.bits.egress_id invalidate ingressNodesOut_7.flit.bits.payload invalidate ingressNodesOut_7.flit.bits.tail invalidate ingressNodesOut_7.flit.bits.head invalidate ingressNodesOut_7.flit.valid invalidate ingressNodesOut_7.flit.ready wire ingressNodesOut_8 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_8.flit.bits.egress_id invalidate ingressNodesOut_8.flit.bits.payload invalidate ingressNodesOut_8.flit.bits.tail invalidate ingressNodesOut_8.flit.bits.head invalidate ingressNodesOut_8.flit.valid invalidate ingressNodesOut_8.flit.ready wire ingressNodesOut_9 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_9.flit.bits.egress_id invalidate ingressNodesOut_9.flit.bits.payload invalidate ingressNodesOut_9.flit.bits.tail invalidate ingressNodesOut_9.flit.bits.head invalidate ingressNodesOut_9.flit.valid invalidate ingressNodesOut_9.flit.ready wire ingressNodesOut_10 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_10.flit.bits.egress_id invalidate ingressNodesOut_10.flit.bits.payload invalidate ingressNodesOut_10.flit.bits.tail invalidate ingressNodesOut_10.flit.bits.head invalidate ingressNodesOut_10.flit.valid invalidate ingressNodesOut_10.flit.ready wire ingressNodesOut_11 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_11.flit.bits.egress_id invalidate ingressNodesOut_11.flit.bits.payload invalidate ingressNodesOut_11.flit.bits.tail invalidate ingressNodesOut_11.flit.bits.head invalidate ingressNodesOut_11.flit.valid invalidate ingressNodesOut_11.flit.ready wire ingressNodesOut_12 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_12.flit.bits.egress_id invalidate ingressNodesOut_12.flit.bits.payload invalidate ingressNodesOut_12.flit.bits.tail invalidate ingressNodesOut_12.flit.bits.head invalidate ingressNodesOut_12.flit.valid invalidate ingressNodesOut_12.flit.ready wire ingressNodesOut_13 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_13.flit.bits.egress_id invalidate ingressNodesOut_13.flit.bits.payload invalidate ingressNodesOut_13.flit.bits.tail invalidate ingressNodesOut_13.flit.bits.head invalidate ingressNodesOut_13.flit.valid invalidate ingressNodesOut_13.flit.ready wire ingressNodesOut_14 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_14.flit.bits.egress_id invalidate ingressNodesOut_14.flit.bits.payload invalidate ingressNodesOut_14.flit.bits.tail invalidate ingressNodesOut_14.flit.bits.head invalidate ingressNodesOut_14.flit.valid invalidate ingressNodesOut_14.flit.ready wire ingressNodesOut_15 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_15.flit.bits.egress_id invalidate ingressNodesOut_15.flit.bits.payload invalidate ingressNodesOut_15.flit.bits.tail invalidate ingressNodesOut_15.flit.bits.head invalidate ingressNodesOut_15.flit.valid invalidate ingressNodesOut_15.flit.ready wire ingressNodesOut_16 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_16.flit.bits.egress_id invalidate ingressNodesOut_16.flit.bits.payload invalidate ingressNodesOut_16.flit.bits.tail invalidate ingressNodesOut_16.flit.bits.head invalidate ingressNodesOut_16.flit.valid invalidate ingressNodesOut_16.flit.ready wire ingressNodesOut_17 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_17.flit.bits.egress_id invalidate ingressNodesOut_17.flit.bits.payload invalidate ingressNodesOut_17.flit.bits.tail invalidate ingressNodesOut_17.flit.bits.head invalidate ingressNodesOut_17.flit.valid invalidate ingressNodesOut_17.flit.ready wire ingressNodesOut_18 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_18.flit.bits.egress_id invalidate ingressNodesOut_18.flit.bits.payload invalidate ingressNodesOut_18.flit.bits.tail invalidate ingressNodesOut_18.flit.bits.head invalidate ingressNodesOut_18.flit.valid invalidate ingressNodesOut_18.flit.ready wire ingressNodesOut_19 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_19.flit.bits.egress_id invalidate ingressNodesOut_19.flit.bits.payload invalidate ingressNodesOut_19.flit.bits.tail invalidate ingressNodesOut_19.flit.bits.head invalidate ingressNodesOut_19.flit.valid invalidate ingressNodesOut_19.flit.ready wire ingressNodesOut_20 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_20.flit.bits.egress_id invalidate ingressNodesOut_20.flit.bits.payload invalidate ingressNodesOut_20.flit.bits.tail invalidate ingressNodesOut_20.flit.bits.head invalidate ingressNodesOut_20.flit.valid invalidate ingressNodesOut_20.flit.ready wire ingressNodesOut_21 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_21.flit.bits.egress_id invalidate ingressNodesOut_21.flit.bits.payload invalidate ingressNodesOut_21.flit.bits.tail invalidate ingressNodesOut_21.flit.bits.head invalidate ingressNodesOut_21.flit.valid invalidate ingressNodesOut_21.flit.ready wire ingressNodesOut_22 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesOut_22.flit.bits.egress_id invalidate ingressNodesOut_22.flit.bits.payload invalidate ingressNodesOut_22.flit.bits.tail invalidate ingressNodesOut_22.flit.bits.head invalidate ingressNodesOut_22.flit.valid invalidate ingressNodesOut_22.flit.ready wire egressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn.flit.bits.ingress_id invalidate egressNodesIn.flit.bits.payload invalidate egressNodesIn.flit.bits.tail invalidate egressNodesIn.flit.bits.head invalidate egressNodesIn.flit.valid invalidate egressNodesIn.flit.ready wire egressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_1.flit.bits.ingress_id invalidate egressNodesIn_1.flit.bits.payload invalidate egressNodesIn_1.flit.bits.tail invalidate egressNodesIn_1.flit.bits.head invalidate egressNodesIn_1.flit.valid invalidate egressNodesIn_1.flit.ready wire egressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_2.flit.bits.ingress_id invalidate egressNodesIn_2.flit.bits.payload invalidate egressNodesIn_2.flit.bits.tail invalidate egressNodesIn_2.flit.bits.head invalidate egressNodesIn_2.flit.valid invalidate egressNodesIn_2.flit.ready wire egressNodesIn_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_3.flit.bits.ingress_id invalidate egressNodesIn_3.flit.bits.payload invalidate egressNodesIn_3.flit.bits.tail invalidate egressNodesIn_3.flit.bits.head invalidate egressNodesIn_3.flit.valid invalidate egressNodesIn_3.flit.ready wire egressNodesIn_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_4.flit.bits.ingress_id invalidate egressNodesIn_4.flit.bits.payload invalidate egressNodesIn_4.flit.bits.tail invalidate egressNodesIn_4.flit.bits.head invalidate egressNodesIn_4.flit.valid invalidate egressNodesIn_4.flit.ready wire egressNodesIn_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_5.flit.bits.ingress_id invalidate egressNodesIn_5.flit.bits.payload invalidate egressNodesIn_5.flit.bits.tail invalidate egressNodesIn_5.flit.bits.head invalidate egressNodesIn_5.flit.valid invalidate egressNodesIn_5.flit.ready wire egressNodesIn_6 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_6.flit.bits.ingress_id invalidate egressNodesIn_6.flit.bits.payload invalidate egressNodesIn_6.flit.bits.tail invalidate egressNodesIn_6.flit.bits.head invalidate egressNodesIn_6.flit.valid invalidate egressNodesIn_6.flit.ready wire egressNodesIn_7 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_7.flit.bits.ingress_id invalidate egressNodesIn_7.flit.bits.payload invalidate egressNodesIn_7.flit.bits.tail invalidate egressNodesIn_7.flit.bits.head invalidate egressNodesIn_7.flit.valid invalidate egressNodesIn_7.flit.ready wire egressNodesIn_8 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_8.flit.bits.ingress_id invalidate egressNodesIn_8.flit.bits.payload invalidate egressNodesIn_8.flit.bits.tail invalidate egressNodesIn_8.flit.bits.head invalidate egressNodesIn_8.flit.valid invalidate egressNodesIn_8.flit.ready wire egressNodesIn_9 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_9.flit.bits.ingress_id invalidate egressNodesIn_9.flit.bits.payload invalidate egressNodesIn_9.flit.bits.tail invalidate egressNodesIn_9.flit.bits.head invalidate egressNodesIn_9.flit.valid invalidate egressNodesIn_9.flit.ready wire egressNodesIn_10 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_10.flit.bits.ingress_id invalidate egressNodesIn_10.flit.bits.payload invalidate egressNodesIn_10.flit.bits.tail invalidate egressNodesIn_10.flit.bits.head invalidate egressNodesIn_10.flit.valid invalidate egressNodesIn_10.flit.ready wire egressNodesIn_11 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_11.flit.bits.ingress_id invalidate egressNodesIn_11.flit.bits.payload invalidate egressNodesIn_11.flit.bits.tail invalidate egressNodesIn_11.flit.bits.head invalidate egressNodesIn_11.flit.valid invalidate egressNodesIn_11.flit.ready wire egressNodesIn_12 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_12.flit.bits.ingress_id invalidate egressNodesIn_12.flit.bits.payload invalidate egressNodesIn_12.flit.bits.tail invalidate egressNodesIn_12.flit.bits.head invalidate egressNodesIn_12.flit.valid invalidate egressNodesIn_12.flit.ready wire egressNodesIn_13 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_13.flit.bits.ingress_id invalidate egressNodesIn_13.flit.bits.payload invalidate egressNodesIn_13.flit.bits.tail invalidate egressNodesIn_13.flit.bits.head invalidate egressNodesIn_13.flit.valid invalidate egressNodesIn_13.flit.ready wire egressNodesIn_14 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_14.flit.bits.ingress_id invalidate egressNodesIn_14.flit.bits.payload invalidate egressNodesIn_14.flit.bits.tail invalidate egressNodesIn_14.flit.bits.head invalidate egressNodesIn_14.flit.valid invalidate egressNodesIn_14.flit.ready wire egressNodesIn_15 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_15.flit.bits.ingress_id invalidate egressNodesIn_15.flit.bits.payload invalidate egressNodesIn_15.flit.bits.tail invalidate egressNodesIn_15.flit.bits.head invalidate egressNodesIn_15.flit.valid invalidate egressNodesIn_15.flit.ready wire egressNodesIn_16 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_16.flit.bits.ingress_id invalidate egressNodesIn_16.flit.bits.payload invalidate egressNodesIn_16.flit.bits.tail invalidate egressNodesIn_16.flit.bits.head invalidate egressNodesIn_16.flit.valid invalidate egressNodesIn_16.flit.ready wire egressNodesIn_17 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_17.flit.bits.ingress_id invalidate egressNodesIn_17.flit.bits.payload invalidate egressNodesIn_17.flit.bits.tail invalidate egressNodesIn_17.flit.bits.head invalidate egressNodesIn_17.flit.valid invalidate egressNodesIn_17.flit.ready wire egressNodesIn_18 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesIn_18.flit.bits.ingress_id invalidate egressNodesIn_18.flit.bits.payload invalidate egressNodesIn_18.flit.bits.tail invalidate egressNodesIn_18.flit.bits.head invalidate egressNodesIn_18.flit.valid invalidate egressNodesIn_18.flit.ready wire sinkIn : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn.sa_stall[0] invalidate sinkIn.sa_stall[1] invalidate sinkIn.sa_stall[2] invalidate sinkIn.va_stall[0] invalidate sinkIn.va_stall[1] invalidate sinkIn.va_stall[2] wire sinkIn_1 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_1.sa_stall[0] invalidate sinkIn_1.sa_stall[1] invalidate sinkIn_1.sa_stall[2] invalidate sinkIn_1.va_stall[0] invalidate sinkIn_1.va_stall[1] invalidate sinkIn_1.va_stall[2] wire sinkIn_2 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_2.sa_stall[0] invalidate sinkIn_2.sa_stall[1] invalidate sinkIn_2.sa_stall[2] invalidate sinkIn_2.va_stall[0] invalidate sinkIn_2.va_stall[1] invalidate sinkIn_2.va_stall[2] wire sinkIn_3 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_3.sa_stall[0] invalidate sinkIn_3.sa_stall[1] invalidate sinkIn_3.sa_stall[2] invalidate sinkIn_3.va_stall[0] invalidate sinkIn_3.va_stall[1] invalidate sinkIn_3.va_stall[2] wire sinkIn_4 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_4.sa_stall[0] invalidate sinkIn_4.sa_stall[1] invalidate sinkIn_4.sa_stall[2] invalidate sinkIn_4.va_stall[0] invalidate sinkIn_4.va_stall[1] invalidate sinkIn_4.va_stall[2] wire sinkIn_5 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_5.sa_stall[0] invalidate sinkIn_5.sa_stall[1] invalidate sinkIn_5.sa_stall[2] invalidate sinkIn_5.va_stall[0] invalidate sinkIn_5.va_stall[1] invalidate sinkIn_5.va_stall[2] wire sinkIn_6 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_6.sa_stall[0] invalidate sinkIn_6.sa_stall[1] invalidate sinkIn_6.sa_stall[2] invalidate sinkIn_6.va_stall[0] invalidate sinkIn_6.va_stall[1] invalidate sinkIn_6.va_stall[2] wire sinkIn_7 : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate sinkIn_7.sa_stall[0] invalidate sinkIn_7.sa_stall[1] invalidate sinkIn_7.sa_stall[2] invalidate sinkIn_7.va_stall[0] invalidate sinkIn_7.va_stall[1] invalidate sinkIn_7.va_stall[2] wire sinkIn_8 : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate sinkIn_8.sa_stall[0] invalidate sinkIn_8.sa_stall[1] invalidate sinkIn_8.sa_stall[2] invalidate sinkIn_8.sa_stall[3] invalidate sinkIn_8.va_stall[0] invalidate sinkIn_8.va_stall[1] invalidate sinkIn_8.va_stall[2] invalidate sinkIn_8.va_stall[3] wire sinkIn_9 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_9.sa_stall[0] invalidate sinkIn_9.sa_stall[1] invalidate sinkIn_9.va_stall[0] invalidate sinkIn_9.va_stall[1] wire sinkIn_10 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_10.sa_stall[0] invalidate sinkIn_10.sa_stall[1] invalidate sinkIn_10.va_stall[0] invalidate sinkIn_10.va_stall[1] wire sinkIn_11 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_11.sa_stall[0] invalidate sinkIn_11.sa_stall[1] invalidate sinkIn_11.va_stall[0] invalidate sinkIn_11.va_stall[1] wire sinkIn_12 : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate sinkIn_12.sa_stall[0] invalidate sinkIn_12.sa_stall[1] invalidate sinkIn_12.va_stall[0] invalidate sinkIn_12.va_stall[1] connect router_sink_domain.auto.clock_in, clockSourceNodesOut connect router_sink_domain_1.auto.clock_in, clockSourceNodesOut_1 connect router_sink_domain_2.auto.clock_in, clockSourceNodesOut_2 connect router_sink_domain_3.auto.clock_in, clockSourceNodesOut_3 connect router_sink_domain_4.auto.clock_in, clockSourceNodesOut_4 connect router_sink_domain_5.auto.clock_in, clockSourceNodesOut_5 connect router_sink_domain_6.auto.clock_in, clockSourceNodesOut_6 connect router_sink_domain_7.auto.clock_in, clockSourceNodesOut_7 connect router_sink_domain_8.auto.clock_in, clockSourceNodesOut_8 connect router_sink_domain_9.auto.clock_in, clockSourceNodesOut_9 connect router_sink_domain_10.auto.clock_in, clockSourceNodesOut_10 connect router_sink_domain_11.auto.clock_in, clockSourceNodesOut_11 connect router_sink_domain_12.auto.clock_in, clockSourceNodesOut_12 connect router_sink_domain_1.auto.routers_dest_nodes_in, router_sink_domain.auto.routers_source_nodes_out connect egressNodesIn_1.flit.bits, router_sink_domain.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_1.flit.valid, router_sink_domain.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_1.flit.ready connect sinkIn, router_sink_domain.auto.routers_debug_out connect router_sink_domain_2.auto.routers_dest_nodes_in, router_sink_domain_1.auto.routers_source_nodes_out connect egressNodesIn_2.flit.bits, router_sink_domain_1.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_2.flit.valid, router_sink_domain_1.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_1.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_2.flit.ready connect sinkIn_1, router_sink_domain_1.auto.routers_debug_out connect router_sink_domain_3.auto.routers_dest_nodes_in, router_sink_domain_2.auto.routers_source_nodes_out connect egressNodesIn_3.flit.bits, router_sink_domain_2.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_3.flit.valid, router_sink_domain_2.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_2.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_3.flit.ready connect sinkIn_2, router_sink_domain_2.auto.routers_debug_out connect router_sink_domain_4.auto.routers_dest_nodes_in, router_sink_domain_3.auto.routers_source_nodes_out connect egressNodesIn_4.flit.bits, router_sink_domain_3.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_4.flit.valid, router_sink_domain_3.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_3.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_4.flit.ready connect sinkIn_3, router_sink_domain_3.auto.routers_debug_out connect router_sink_domain_5.auto.routers_dest_nodes_in, router_sink_domain_4.auto.routers_source_nodes_out connect egressNodesIn_5.flit.bits, router_sink_domain_4.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_5.flit.valid, router_sink_domain_4.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_4.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_5.flit.ready connect sinkIn_4, router_sink_domain_4.auto.routers_debug_out connect router_sink_domain_6.auto.routers_dest_nodes_in, router_sink_domain_5.auto.routers_source_nodes_out connect egressNodesIn_6.flit.bits, router_sink_domain_5.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_6.flit.valid, router_sink_domain_5.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_5.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_6.flit.ready connect sinkIn_5, router_sink_domain_5.auto.routers_debug_out connect router_sink_domain_7.auto.routers_dest_nodes_in, router_sink_domain_6.auto.routers_source_nodes_out connect egressNodesIn_7.flit.bits, router_sink_domain_6.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_7.flit.valid, router_sink_domain_6.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_6.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_7.flit.ready connect sinkIn_6, router_sink_domain_6.auto.routers_debug_out connect router_sink_domain_8.auto.routers_dest_nodes_in, router_sink_domain_7.auto.routers_source_nodes_out connect egressNodesIn_8.flit.bits, router_sink_domain_7.auto.routers_egress_nodes_out.flit.bits connect egressNodesIn_8.flit.valid, router_sink_domain_7.auto.routers_egress_nodes_out.flit.valid connect router_sink_domain_7.auto.routers_egress_nodes_out.flit.ready, egressNodesIn_8.flit.ready connect sinkIn_7, router_sink_domain_7.auto.routers_debug_out connect router_sink_domain_9.auto.routers_dest_nodes_in, router_sink_domain_8.auto.routers_source_nodes_out connect egressNodesIn.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_8.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn.flit.ready connect egressNodesIn_9.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_9.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_8.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_9.flit.ready connect egressNodesIn_10.flit.bits, router_sink_domain_8.auto.routers_egress_nodes_out_2.flit.bits connect egressNodesIn_10.flit.valid, router_sink_domain_8.auto.routers_egress_nodes_out_2.flit.valid connect router_sink_domain_8.auto.routers_egress_nodes_out_2.flit.ready, egressNodesIn_10.flit.ready connect sinkIn_8, router_sink_domain_8.auto.routers_debug_out connect router_sink_domain_10.auto.routers_dest_nodes_in, router_sink_domain_9.auto.routers_source_nodes_out connect egressNodesIn_11.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_11.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_9.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_11.flit.ready connect egressNodesIn_12.flit.bits, router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_12.flit.valid, router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_9.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_12.flit.ready connect sinkIn_9, router_sink_domain_9.auto.routers_debug_out connect router_sink_domain_11.auto.routers_dest_nodes_in, router_sink_domain_10.auto.routers_source_nodes_out connect egressNodesIn_13.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_13.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_10.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_13.flit.ready connect egressNodesIn_14.flit.bits, router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_14.flit.valid, router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_10.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_14.flit.ready connect sinkIn_10, router_sink_domain_10.auto.routers_debug_out connect router_sink_domain_12.auto.routers_dest_nodes_in, router_sink_domain_11.auto.routers_source_nodes_out connect egressNodesIn_15.flit.bits, router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_15.flit.valid, router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_11.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_15.flit.ready connect egressNodesIn_16.flit.bits, router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_16.flit.valid, router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_11.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_16.flit.ready connect sinkIn_11, router_sink_domain_11.auto.routers_debug_out connect router_sink_domain.auto.routers_dest_nodes_in, router_sink_domain_12.auto.routers_source_nodes_out connect egressNodesIn_17.flit.bits, router_sink_domain_12.auto.routers_egress_nodes_out_0.flit.bits connect egressNodesIn_17.flit.valid, router_sink_domain_12.auto.routers_egress_nodes_out_0.flit.valid connect router_sink_domain_12.auto.routers_egress_nodes_out_0.flit.ready, egressNodesIn_17.flit.ready connect egressNodesIn_18.flit.bits, router_sink_domain_12.auto.routers_egress_nodes_out_1.flit.bits connect egressNodesIn_18.flit.valid, router_sink_domain_12.auto.routers_egress_nodes_out_1.flit.valid connect router_sink_domain_12.auto.routers_egress_nodes_out_1.flit.ready, egressNodesIn_18.flit.ready connect sinkIn_12, router_sink_domain_12.auto.routers_debug_out connect router_sink_domain_8.auto.routers_ingress_nodes_in_0, ingressNodesOut connect router_sink_domain_8.auto.routers_ingress_nodes_in_1, ingressNodesOut_1 connect router_sink_domain.auto.routers_ingress_nodes_in_0, ingressNodesOut_2 connect router_sink_domain.auto.routers_ingress_nodes_in_1, ingressNodesOut_3 connect router_sink_domain_1.auto.routers_ingress_nodes_in_0, ingressNodesOut_4 connect router_sink_domain_1.auto.routers_ingress_nodes_in_1, ingressNodesOut_5 connect router_sink_domain_2.auto.routers_ingress_nodes_in_0, ingressNodesOut_6 connect router_sink_domain_2.auto.routers_ingress_nodes_in_1, ingressNodesOut_7 connect router_sink_domain_3.auto.routers_ingress_nodes_in_0, ingressNodesOut_8 connect router_sink_domain_3.auto.routers_ingress_nodes_in_1, ingressNodesOut_9 connect router_sink_domain_4.auto.routers_ingress_nodes_in_0, ingressNodesOut_10 connect router_sink_domain_4.auto.routers_ingress_nodes_in_1, ingressNodesOut_11 connect router_sink_domain_5.auto.routers_ingress_nodes_in_0, ingressNodesOut_12 connect router_sink_domain_5.auto.routers_ingress_nodes_in_1, ingressNodesOut_13 connect router_sink_domain_6.auto.routers_ingress_nodes_in_0, ingressNodesOut_14 connect router_sink_domain_6.auto.routers_ingress_nodes_in_1, ingressNodesOut_15 connect router_sink_domain_7.auto.routers_ingress_nodes_in_0, ingressNodesOut_16 connect router_sink_domain_7.auto.routers_ingress_nodes_in_1, ingressNodesOut_17 connect router_sink_domain_8.auto.routers_ingress_nodes_in_2, ingressNodesOut_18 connect router_sink_domain_9.auto.routers_ingress_nodes_in, ingressNodesOut_19 connect router_sink_domain_10.auto.routers_ingress_nodes_in, ingressNodesOut_20 connect router_sink_domain_11.auto.routers_ingress_nodes_in, ingressNodesOut_21 connect router_sink_domain_12.auto.routers_ingress_nodes_in, ingressNodesOut_22 connect ingressNodesOut, io.ingress.`0` connect ingressNodesOut_1, io.ingress.`1` connect ingressNodesOut_2, io.ingress.`2` connect ingressNodesOut_3, io.ingress.`3` connect ingressNodesOut_4, io.ingress.`4` connect ingressNodesOut_5, io.ingress.`5` connect ingressNodesOut_6, io.ingress.`6` connect ingressNodesOut_7, io.ingress.`7` connect ingressNodesOut_8, io.ingress.`8` connect ingressNodesOut_9, io.ingress.`9` connect ingressNodesOut_10, io.ingress.`10` connect ingressNodesOut_11, io.ingress.`11` connect ingressNodesOut_12, io.ingress.`12` connect ingressNodesOut_13, io.ingress.`13` connect ingressNodesOut_14, io.ingress.`14` connect ingressNodesOut_15, io.ingress.`15` connect ingressNodesOut_16, io.ingress.`16` connect ingressNodesOut_17, io.ingress.`17` connect ingressNodesOut_18, io.ingress.`18` connect ingressNodesOut_19, io.ingress.`19` connect ingressNodesOut_20, io.ingress.`20` connect ingressNodesOut_21, io.ingress.`21` connect ingressNodesOut_22, io.ingress.`22` connect io.egress.`0`, egressNodesIn connect io.egress.`1`, egressNodesIn_1 connect io.egress.`2`, egressNodesIn_2 connect io.egress.`3`, egressNodesIn_3 connect io.egress.`4`, egressNodesIn_4 connect io.egress.`5`, egressNodesIn_5 connect io.egress.`6`, egressNodesIn_6 connect io.egress.`7`, egressNodesIn_7 connect io.egress.`8`, egressNodesIn_8 connect io.egress.`9`, egressNodesIn_9 connect io.egress.`10`, egressNodesIn_10 connect io.egress.`11`, egressNodesIn_11 connect io.egress.`12`, egressNodesIn_12 connect io.egress.`13`, egressNodesIn_13 connect io.egress.`14`, egressNodesIn_14 connect io.egress.`15`, egressNodesIn_15 connect io.egress.`16`, egressNodesIn_16 connect io.egress.`17`, egressNodesIn_17 connect io.egress.`18`, egressNodesIn_18 connect clockSourceNodesOut, io.router_clocks[0] connect clockSourceNodesOut_1, io.router_clocks[1] connect clockSourceNodesOut_2, io.router_clocks[2] connect clockSourceNodesOut_3, io.router_clocks[3] connect clockSourceNodesOut_4, io.router_clocks[4] connect clockSourceNodesOut_5, io.router_clocks[5] connect clockSourceNodesOut_6, io.router_clocks[6] connect clockSourceNodesOut_7, io.router_clocks[7] connect clockSourceNodesOut_8, io.router_clocks[8] connect clockSourceNodesOut_9, io.router_clocks[9] connect clockSourceNodesOut_10, io.router_clocks[10] connect clockSourceNodesOut_11, io.router_clocks[11] connect clockSourceNodesOut_12, io.router_clocks[12] regreset debug_va_stall_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset debug_sa_stall_ctr : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_any_stall_ctr_T = add(debug_va_stall_ctr, debug_sa_stall_ctr) node debug_any_stall_ctr = tail(_debug_any_stall_ctr_T, 1) node _debug_va_stall_ctr_T = add(sinkIn.va_stall[0], sinkIn.va_stall[1]) node _debug_va_stall_ctr_T_1 = tail(_debug_va_stall_ctr_T, 1) node _debug_va_stall_ctr_T_2 = add(_debug_va_stall_ctr_T_1, sinkIn.va_stall[2]) node _debug_va_stall_ctr_T_3 = tail(_debug_va_stall_ctr_T_2, 1) node _debug_va_stall_ctr_T_4 = add(sinkIn_1.va_stall[0], sinkIn_1.va_stall[1]) node _debug_va_stall_ctr_T_5 = tail(_debug_va_stall_ctr_T_4, 1) node _debug_va_stall_ctr_T_6 = add(_debug_va_stall_ctr_T_5, sinkIn_1.va_stall[2]) node _debug_va_stall_ctr_T_7 = tail(_debug_va_stall_ctr_T_6, 1) node _debug_va_stall_ctr_T_8 = add(sinkIn_2.va_stall[0], sinkIn_2.va_stall[1]) node _debug_va_stall_ctr_T_9 = tail(_debug_va_stall_ctr_T_8, 1) node _debug_va_stall_ctr_T_10 = add(_debug_va_stall_ctr_T_9, sinkIn_2.va_stall[2]) node _debug_va_stall_ctr_T_11 = tail(_debug_va_stall_ctr_T_10, 1) node _debug_va_stall_ctr_T_12 = add(sinkIn_3.va_stall[0], sinkIn_3.va_stall[1]) node _debug_va_stall_ctr_T_13 = tail(_debug_va_stall_ctr_T_12, 1) node _debug_va_stall_ctr_T_14 = add(_debug_va_stall_ctr_T_13, sinkIn_3.va_stall[2]) node _debug_va_stall_ctr_T_15 = tail(_debug_va_stall_ctr_T_14, 1) node _debug_va_stall_ctr_T_16 = add(sinkIn_4.va_stall[0], sinkIn_4.va_stall[1]) node _debug_va_stall_ctr_T_17 = tail(_debug_va_stall_ctr_T_16, 1) node _debug_va_stall_ctr_T_18 = add(_debug_va_stall_ctr_T_17, sinkIn_4.va_stall[2]) node _debug_va_stall_ctr_T_19 = tail(_debug_va_stall_ctr_T_18, 1) node _debug_va_stall_ctr_T_20 = add(sinkIn_5.va_stall[0], sinkIn_5.va_stall[1]) node _debug_va_stall_ctr_T_21 = tail(_debug_va_stall_ctr_T_20, 1) node _debug_va_stall_ctr_T_22 = add(_debug_va_stall_ctr_T_21, sinkIn_5.va_stall[2]) node _debug_va_stall_ctr_T_23 = tail(_debug_va_stall_ctr_T_22, 1) node _debug_va_stall_ctr_T_24 = add(sinkIn_6.va_stall[0], sinkIn_6.va_stall[1]) node _debug_va_stall_ctr_T_25 = tail(_debug_va_stall_ctr_T_24, 1) node _debug_va_stall_ctr_T_26 = add(_debug_va_stall_ctr_T_25, sinkIn_6.va_stall[2]) node _debug_va_stall_ctr_T_27 = tail(_debug_va_stall_ctr_T_26, 1) node _debug_va_stall_ctr_T_28 = add(sinkIn_7.va_stall[0], sinkIn_7.va_stall[1]) node _debug_va_stall_ctr_T_29 = tail(_debug_va_stall_ctr_T_28, 1) node _debug_va_stall_ctr_T_30 = add(_debug_va_stall_ctr_T_29, sinkIn_7.va_stall[2]) node _debug_va_stall_ctr_T_31 = tail(_debug_va_stall_ctr_T_30, 1) node _debug_va_stall_ctr_T_32 = add(sinkIn_8.va_stall[0], sinkIn_8.va_stall[1]) node _debug_va_stall_ctr_T_33 = tail(_debug_va_stall_ctr_T_32, 1) node _debug_va_stall_ctr_T_34 = add(_debug_va_stall_ctr_T_33, sinkIn_8.va_stall[2]) node _debug_va_stall_ctr_T_35 = tail(_debug_va_stall_ctr_T_34, 1) node _debug_va_stall_ctr_T_36 = add(_debug_va_stall_ctr_T_35, sinkIn_8.va_stall[3]) node _debug_va_stall_ctr_T_37 = tail(_debug_va_stall_ctr_T_36, 1) node _debug_va_stall_ctr_T_38 = add(sinkIn_9.va_stall[0], sinkIn_9.va_stall[1]) node _debug_va_stall_ctr_T_39 = tail(_debug_va_stall_ctr_T_38, 1) node _debug_va_stall_ctr_T_40 = add(sinkIn_10.va_stall[0], sinkIn_10.va_stall[1]) node _debug_va_stall_ctr_T_41 = tail(_debug_va_stall_ctr_T_40, 1) node _debug_va_stall_ctr_T_42 = add(sinkIn_11.va_stall[0], sinkIn_11.va_stall[1]) node _debug_va_stall_ctr_T_43 = tail(_debug_va_stall_ctr_T_42, 1) node _debug_va_stall_ctr_T_44 = add(sinkIn_12.va_stall[0], sinkIn_12.va_stall[1]) node _debug_va_stall_ctr_T_45 = tail(_debug_va_stall_ctr_T_44, 1) node _debug_va_stall_ctr_T_46 = add(_debug_va_stall_ctr_T_3, _debug_va_stall_ctr_T_7) node _debug_va_stall_ctr_T_47 = tail(_debug_va_stall_ctr_T_46, 1) node _debug_va_stall_ctr_T_48 = add(_debug_va_stall_ctr_T_47, _debug_va_stall_ctr_T_11) node _debug_va_stall_ctr_T_49 = tail(_debug_va_stall_ctr_T_48, 1) node _debug_va_stall_ctr_T_50 = add(_debug_va_stall_ctr_T_49, _debug_va_stall_ctr_T_15) node _debug_va_stall_ctr_T_51 = tail(_debug_va_stall_ctr_T_50, 1) node _debug_va_stall_ctr_T_52 = add(_debug_va_stall_ctr_T_51, _debug_va_stall_ctr_T_19) node _debug_va_stall_ctr_T_53 = tail(_debug_va_stall_ctr_T_52, 1) node _debug_va_stall_ctr_T_54 = add(_debug_va_stall_ctr_T_53, _debug_va_stall_ctr_T_23) node _debug_va_stall_ctr_T_55 = tail(_debug_va_stall_ctr_T_54, 1) node _debug_va_stall_ctr_T_56 = add(_debug_va_stall_ctr_T_55, _debug_va_stall_ctr_T_27) node _debug_va_stall_ctr_T_57 = tail(_debug_va_stall_ctr_T_56, 1) node _debug_va_stall_ctr_T_58 = add(_debug_va_stall_ctr_T_57, _debug_va_stall_ctr_T_31) node _debug_va_stall_ctr_T_59 = tail(_debug_va_stall_ctr_T_58, 1) node _debug_va_stall_ctr_T_60 = add(_debug_va_stall_ctr_T_59, _debug_va_stall_ctr_T_37) node _debug_va_stall_ctr_T_61 = tail(_debug_va_stall_ctr_T_60, 1) node _debug_va_stall_ctr_T_62 = add(_debug_va_stall_ctr_T_61, _debug_va_stall_ctr_T_39) node _debug_va_stall_ctr_T_63 = tail(_debug_va_stall_ctr_T_62, 1) node _debug_va_stall_ctr_T_64 = add(_debug_va_stall_ctr_T_63, _debug_va_stall_ctr_T_41) node _debug_va_stall_ctr_T_65 = tail(_debug_va_stall_ctr_T_64, 1) node _debug_va_stall_ctr_T_66 = add(_debug_va_stall_ctr_T_65, _debug_va_stall_ctr_T_43) node _debug_va_stall_ctr_T_67 = tail(_debug_va_stall_ctr_T_66, 1) node _debug_va_stall_ctr_T_68 = add(_debug_va_stall_ctr_T_67, _debug_va_stall_ctr_T_45) node _debug_va_stall_ctr_T_69 = tail(_debug_va_stall_ctr_T_68, 1) node _debug_va_stall_ctr_T_70 = add(debug_va_stall_ctr, _debug_va_stall_ctr_T_69) node _debug_va_stall_ctr_T_71 = tail(_debug_va_stall_ctr_T_70, 1) connect debug_va_stall_ctr, _debug_va_stall_ctr_T_71 node _debug_sa_stall_ctr_T = add(sinkIn.sa_stall[0], sinkIn.sa_stall[1]) node _debug_sa_stall_ctr_T_1 = tail(_debug_sa_stall_ctr_T, 1) node _debug_sa_stall_ctr_T_2 = add(_debug_sa_stall_ctr_T_1, sinkIn.sa_stall[2]) node _debug_sa_stall_ctr_T_3 = tail(_debug_sa_stall_ctr_T_2, 1) node _debug_sa_stall_ctr_T_4 = add(sinkIn_1.sa_stall[0], sinkIn_1.sa_stall[1]) node _debug_sa_stall_ctr_T_5 = tail(_debug_sa_stall_ctr_T_4, 1) node _debug_sa_stall_ctr_T_6 = add(_debug_sa_stall_ctr_T_5, sinkIn_1.sa_stall[2]) node _debug_sa_stall_ctr_T_7 = tail(_debug_sa_stall_ctr_T_6, 1) node _debug_sa_stall_ctr_T_8 = add(sinkIn_2.sa_stall[0], sinkIn_2.sa_stall[1]) node _debug_sa_stall_ctr_T_9 = tail(_debug_sa_stall_ctr_T_8, 1) node _debug_sa_stall_ctr_T_10 = add(_debug_sa_stall_ctr_T_9, sinkIn_2.sa_stall[2]) node _debug_sa_stall_ctr_T_11 = tail(_debug_sa_stall_ctr_T_10, 1) node _debug_sa_stall_ctr_T_12 = add(sinkIn_3.sa_stall[0], sinkIn_3.sa_stall[1]) node _debug_sa_stall_ctr_T_13 = tail(_debug_sa_stall_ctr_T_12, 1) node _debug_sa_stall_ctr_T_14 = add(_debug_sa_stall_ctr_T_13, sinkIn_3.sa_stall[2]) node _debug_sa_stall_ctr_T_15 = tail(_debug_sa_stall_ctr_T_14, 1) node _debug_sa_stall_ctr_T_16 = add(sinkIn_4.sa_stall[0], sinkIn_4.sa_stall[1]) node _debug_sa_stall_ctr_T_17 = tail(_debug_sa_stall_ctr_T_16, 1) node _debug_sa_stall_ctr_T_18 = add(_debug_sa_stall_ctr_T_17, sinkIn_4.sa_stall[2]) node _debug_sa_stall_ctr_T_19 = tail(_debug_sa_stall_ctr_T_18, 1) node _debug_sa_stall_ctr_T_20 = add(sinkIn_5.sa_stall[0], sinkIn_5.sa_stall[1]) node _debug_sa_stall_ctr_T_21 = tail(_debug_sa_stall_ctr_T_20, 1) node _debug_sa_stall_ctr_T_22 = add(_debug_sa_stall_ctr_T_21, sinkIn_5.sa_stall[2]) node _debug_sa_stall_ctr_T_23 = tail(_debug_sa_stall_ctr_T_22, 1) node _debug_sa_stall_ctr_T_24 = add(sinkIn_6.sa_stall[0], sinkIn_6.sa_stall[1]) node _debug_sa_stall_ctr_T_25 = tail(_debug_sa_stall_ctr_T_24, 1) node _debug_sa_stall_ctr_T_26 = add(_debug_sa_stall_ctr_T_25, sinkIn_6.sa_stall[2]) node _debug_sa_stall_ctr_T_27 = tail(_debug_sa_stall_ctr_T_26, 1) node _debug_sa_stall_ctr_T_28 = add(sinkIn_7.sa_stall[0], sinkIn_7.sa_stall[1]) node _debug_sa_stall_ctr_T_29 = tail(_debug_sa_stall_ctr_T_28, 1) node _debug_sa_stall_ctr_T_30 = add(_debug_sa_stall_ctr_T_29, sinkIn_7.sa_stall[2]) node _debug_sa_stall_ctr_T_31 = tail(_debug_sa_stall_ctr_T_30, 1) node _debug_sa_stall_ctr_T_32 = add(sinkIn_8.sa_stall[0], sinkIn_8.sa_stall[1]) node _debug_sa_stall_ctr_T_33 = tail(_debug_sa_stall_ctr_T_32, 1) node _debug_sa_stall_ctr_T_34 = add(_debug_sa_stall_ctr_T_33, sinkIn_8.sa_stall[2]) node _debug_sa_stall_ctr_T_35 = tail(_debug_sa_stall_ctr_T_34, 1) node _debug_sa_stall_ctr_T_36 = add(_debug_sa_stall_ctr_T_35, sinkIn_8.sa_stall[3]) node _debug_sa_stall_ctr_T_37 = tail(_debug_sa_stall_ctr_T_36, 1) node _debug_sa_stall_ctr_T_38 = add(sinkIn_9.sa_stall[0], sinkIn_9.sa_stall[1]) node _debug_sa_stall_ctr_T_39 = tail(_debug_sa_stall_ctr_T_38, 1) node _debug_sa_stall_ctr_T_40 = add(sinkIn_10.sa_stall[0], sinkIn_10.sa_stall[1]) node _debug_sa_stall_ctr_T_41 = tail(_debug_sa_stall_ctr_T_40, 1) node _debug_sa_stall_ctr_T_42 = add(sinkIn_11.sa_stall[0], sinkIn_11.sa_stall[1]) node _debug_sa_stall_ctr_T_43 = tail(_debug_sa_stall_ctr_T_42, 1) node _debug_sa_stall_ctr_T_44 = add(sinkIn_12.sa_stall[0], sinkIn_12.sa_stall[1]) node _debug_sa_stall_ctr_T_45 = tail(_debug_sa_stall_ctr_T_44, 1) node _debug_sa_stall_ctr_T_46 = add(_debug_sa_stall_ctr_T_3, _debug_sa_stall_ctr_T_7) node _debug_sa_stall_ctr_T_47 = tail(_debug_sa_stall_ctr_T_46, 1) node _debug_sa_stall_ctr_T_48 = add(_debug_sa_stall_ctr_T_47, _debug_sa_stall_ctr_T_11) node _debug_sa_stall_ctr_T_49 = tail(_debug_sa_stall_ctr_T_48, 1) node _debug_sa_stall_ctr_T_50 = add(_debug_sa_stall_ctr_T_49, _debug_sa_stall_ctr_T_15) node _debug_sa_stall_ctr_T_51 = tail(_debug_sa_stall_ctr_T_50, 1) node _debug_sa_stall_ctr_T_52 = add(_debug_sa_stall_ctr_T_51, _debug_sa_stall_ctr_T_19) node _debug_sa_stall_ctr_T_53 = tail(_debug_sa_stall_ctr_T_52, 1) node _debug_sa_stall_ctr_T_54 = add(_debug_sa_stall_ctr_T_53, _debug_sa_stall_ctr_T_23) node _debug_sa_stall_ctr_T_55 = tail(_debug_sa_stall_ctr_T_54, 1) node _debug_sa_stall_ctr_T_56 = add(_debug_sa_stall_ctr_T_55, _debug_sa_stall_ctr_T_27) node _debug_sa_stall_ctr_T_57 = tail(_debug_sa_stall_ctr_T_56, 1) node _debug_sa_stall_ctr_T_58 = add(_debug_sa_stall_ctr_T_57, _debug_sa_stall_ctr_T_31) node _debug_sa_stall_ctr_T_59 = tail(_debug_sa_stall_ctr_T_58, 1) node _debug_sa_stall_ctr_T_60 = add(_debug_sa_stall_ctr_T_59, _debug_sa_stall_ctr_T_37) node _debug_sa_stall_ctr_T_61 = tail(_debug_sa_stall_ctr_T_60, 1) node _debug_sa_stall_ctr_T_62 = add(_debug_sa_stall_ctr_T_61, _debug_sa_stall_ctr_T_39) node _debug_sa_stall_ctr_T_63 = tail(_debug_sa_stall_ctr_T_62, 1) node _debug_sa_stall_ctr_T_64 = add(_debug_sa_stall_ctr_T_63, _debug_sa_stall_ctr_T_41) node _debug_sa_stall_ctr_T_65 = tail(_debug_sa_stall_ctr_T_64, 1) node _debug_sa_stall_ctr_T_66 = add(_debug_sa_stall_ctr_T_65, _debug_sa_stall_ctr_T_43) node _debug_sa_stall_ctr_T_67 = tail(_debug_sa_stall_ctr_T_66, 1) node _debug_sa_stall_ctr_T_68 = add(_debug_sa_stall_ctr_T_67, _debug_sa_stall_ctr_T_45) node _debug_sa_stall_ctr_T_69 = tail(_debug_sa_stall_ctr_T_68, 1) node _debug_sa_stall_ctr_T_70 = add(debug_sa_stall_ctr, _debug_sa_stall_ctr_T_69) node _debug_sa_stall_ctr_T_71 = tail(_debug_sa_stall_ctr_T_70, 1) connect debug_sa_stall_ctr, _debug_sa_stall_ctr_T_71

module NoC( // @[NoC.scala:141:9] input clock, // @[NoC.scala:141:9] input reset, // @[NoC.scala:141:9] output io_ingress_22_flit_ready, // @[NoC.scala:143:16] input io_ingress_22_flit_valid, // @[NoC.scala:143:16] input io_ingress_22_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_22_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_22_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_22_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_21_flit_ready, // @[NoC.scala:143:16] input io_ingress_21_flit_valid, // @[NoC.scala:143:16] input io_ingress_21_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_21_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_21_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_21_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_20_flit_ready, // @[NoC.scala:143:16] input io_ingress_20_flit_valid, // @[NoC.scala:143:16] input io_ingress_20_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_20_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_20_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_20_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_19_flit_ready, // @[NoC.scala:143:16] input io_ingress_19_flit_valid, // @[NoC.scala:143:16] input io_ingress_19_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_19_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_19_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_19_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_18_flit_ready, // @[NoC.scala:143:16] input io_ingress_18_flit_valid, // @[NoC.scala:143:16] input io_ingress_18_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_18_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_18_flit_bits_payload, // @[NoC.scala:143:16] input [3:0] io_ingress_18_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_17_flit_ready, // @[NoC.scala:143:16] input io_ingress_17_flit_valid, // @[NoC.scala:143:16] input io_ingress_17_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_17_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_17_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_17_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_16_flit_ready, // @[NoC.scala:143:16] input io_ingress_16_flit_valid, // @[NoC.scala:143:16] input io_ingress_16_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_16_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_16_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_16_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_15_flit_ready, // @[NoC.scala:143:16] input io_ingress_15_flit_valid, // @[NoC.scala:143:16] input io_ingress_15_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_15_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_15_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_15_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_14_flit_ready, // @[NoC.scala:143:16] input io_ingress_14_flit_valid, // @[NoC.scala:143:16] input io_ingress_14_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_14_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_14_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_14_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_13_flit_ready, // @[NoC.scala:143:16] input io_ingress_13_flit_valid, // @[NoC.scala:143:16] input io_ingress_13_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_13_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_13_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_13_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_12_flit_ready, // @[NoC.scala:143:16] input io_ingress_12_flit_valid, // @[NoC.scala:143:16] input io_ingress_12_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_12_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_12_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_12_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_11_flit_ready, // @[NoC.scala:143:16] input io_ingress_11_flit_valid, // @[NoC.scala:143:16] input io_ingress_11_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_11_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_11_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_11_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_10_flit_ready, // @[NoC.scala:143:16] input io_ingress_10_flit_valid, // @[NoC.scala:143:16] input io_ingress_10_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_10_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_10_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_10_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_9_flit_ready, // @[NoC.scala:143:16] input io_ingress_9_flit_valid, // @[NoC.scala:143:16] input io_ingress_9_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_9_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_9_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_9_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_8_flit_ready, // @[NoC.scala:143:16] input io_ingress_8_flit_valid, // @[NoC.scala:143:16] input io_ingress_8_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_8_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_8_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_8_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_7_flit_ready, // @[NoC.scala:143:16] input io_ingress_7_flit_valid, // @[NoC.scala:143:16] input io_ingress_7_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_7_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_7_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_7_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_6_flit_ready, // @[NoC.scala:143:16] input io_ingress_6_flit_valid, // @[NoC.scala:143:16] input io_ingress_6_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_6_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_6_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_6_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_5_flit_ready, // @[NoC.scala:143:16] input io_ingress_5_flit_valid, // @[NoC.scala:143:16] input io_ingress_5_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_5_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_5_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_5_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_4_flit_ready, // @[NoC.scala:143:16] input io_ingress_4_flit_valid, // @[NoC.scala:143:16] input io_ingress_4_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_4_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_4_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_4_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_3_flit_ready, // @[NoC.scala:143:16] input io_ingress_3_flit_valid, // @[NoC.scala:143:16] input io_ingress_3_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_3_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_3_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_3_flit_bits_egress_id, // @[NoC.scala:143:16] output io_ingress_2_flit_ready, // @[NoC.scala:143:16] input io_ingress_2_flit_valid, // @[NoC.scala:143:16] input io_ingress_2_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_2_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_2_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_2_flit_bits_egress_id, // @[NoC.scala:143:16] input io_ingress_1_flit_valid, // @[NoC.scala:143:16] output io_ingress_0_flit_ready, // @[NoC.scala:143:16] input io_ingress_0_flit_valid, // @[NoC.scala:143:16] input io_ingress_0_flit_bits_head, // @[NoC.scala:143:16] input io_ingress_0_flit_bits_tail, // @[NoC.scala:143:16] input [72:0] io_ingress_0_flit_bits_payload, // @[NoC.scala:143:16] input [4:0] io_ingress_0_flit_bits_egress_id, // @[NoC.scala:143:16] input io_egress_18_flit_ready, // @[NoC.scala:143:16] output io_egress_18_flit_valid, // @[NoC.scala:143:16] output io_egress_18_flit_bits_head, // @[NoC.scala:143:16] output io_egress_18_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_18_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_17_flit_ready, // @[NoC.scala:143:16] output io_egress_17_flit_valid, // @[NoC.scala:143:16] output io_egress_17_flit_bits_head, // @[NoC.scala:143:16] output io_egress_17_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_17_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_16_flit_ready, // @[NoC.scala:143:16] output io_egress_16_flit_valid, // @[NoC.scala:143:16] output io_egress_16_flit_bits_head, // @[NoC.scala:143:16] output io_egress_16_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_16_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_15_flit_ready, // @[NoC.scala:143:16] output io_egress_15_flit_valid, // @[NoC.scala:143:16] output io_egress_15_flit_bits_head, // @[NoC.scala:143:16] output io_egress_15_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_15_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_14_flit_ready, // @[NoC.scala:143:16] output io_egress_14_flit_valid, // @[NoC.scala:143:16] output io_egress_14_flit_bits_head, // @[NoC.scala:143:16] output io_egress_14_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_14_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_13_flit_ready, // @[NoC.scala:143:16] output io_egress_13_flit_valid, // @[NoC.scala:143:16] output io_egress_13_flit_bits_head, // @[NoC.scala:143:16] output io_egress_13_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_13_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_12_flit_ready, // @[NoC.scala:143:16] output io_egress_12_flit_valid, // @[NoC.scala:143:16] output io_egress_12_flit_bits_head, // @[NoC.scala:143:16] output io_egress_12_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_12_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_11_flit_ready, // @[NoC.scala:143:16] output io_egress_11_flit_valid, // @[NoC.scala:143:16] output io_egress_11_flit_bits_head, // @[NoC.scala:143:16] output io_egress_11_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_11_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_10_flit_ready, // @[NoC.scala:143:16] output io_egress_10_flit_valid, // @[NoC.scala:143:16] output io_egress_10_flit_bits_head, // @[NoC.scala:143:16] output io_egress_10_flit_bits_tail, // @[NoC.scala:143:16] input io_egress_9_flit_ready, // @[NoC.scala:143:16] output io_egress_9_flit_valid, // @[NoC.scala:143:16] output io_egress_9_flit_bits_head, // @[NoC.scala:143:16] output io_egress_9_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_9_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_8_flit_ready, // @[NoC.scala:143:16] output io_egress_8_flit_valid, // @[NoC.scala:143:16] output io_egress_8_flit_bits_head, // @[NoC.scala:143:16] output io_egress_8_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_8_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_7_flit_ready, // @[NoC.scala:143:16] output io_egress_7_flit_valid, // @[NoC.scala:143:16] output io_egress_7_flit_bits_head, // @[NoC.scala:143:16] output io_egress_7_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_7_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_6_flit_ready, // @[NoC.scala:143:16] output io_egress_6_flit_valid, // @[NoC.scala:143:16] output io_egress_6_flit_bits_head, // @[NoC.scala:143:16] output io_egress_6_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_6_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_5_flit_ready, // @[NoC.scala:143:16] output io_egress_5_flit_valid, // @[NoC.scala:143:16] output io_egress_5_flit_bits_head, // @[NoC.scala:143:16] output io_egress_5_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_5_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_4_flit_ready, // @[NoC.scala:143:16] output io_egress_4_flit_valid, // @[NoC.scala:143:16] output io_egress_4_flit_bits_head, // @[NoC.scala:143:16] output io_egress_4_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_4_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_3_flit_ready, // @[NoC.scala:143:16] output io_egress_3_flit_valid, // @[NoC.scala:143:16] output io_egress_3_flit_bits_head, // @[NoC.scala:143:16] output io_egress_3_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_3_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_2_flit_ready, // @[NoC.scala:143:16] output io_egress_2_flit_valid, // @[NoC.scala:143:16] output io_egress_2_flit_bits_head, // @[NoC.scala:143:16] output io_egress_2_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_2_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_1_flit_ready, // @[NoC.scala:143:16] output io_egress_1_flit_valid, // @[NoC.scala:143:16] output io_egress_1_flit_bits_head, // @[NoC.scala:143:16] output io_egress_1_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_1_flit_bits_payload, // @[NoC.scala:143:16] input io_egress_0_flit_ready, // @[NoC.scala:143:16] output io_egress_0_flit_valid, // @[NoC.scala:143:16] output io_egress_0_flit_bits_head, // @[NoC.scala:143:16] output io_egress_0_flit_bits_tail, // @[NoC.scala:143:16] output [72:0] io_egress_0_flit_bits_payload, // @[NoC.scala:143:16] input io_router_clocks_0_clock, // @[NoC.scala:143:16] input io_router_clocks_0_reset, // @[NoC.scala:143:16] input io_router_clocks_1_clock, // @[NoC.scala:143:16] input io_router_clocks_1_reset, // @[NoC.scala:143:16] input io_router_clocks_2_clock, // @[NoC.scala:143:16] input io_router_clocks_2_reset, // @[NoC.scala:143:16] input io_router_clocks_3_clock, // @[NoC.scala:143:16] input io_router_clocks_3_reset, // @[NoC.scala:143:16] input io_router_clocks_4_clock, // @[NoC.scala:143:16] input io_router_clocks_4_reset, // @[NoC.scala:143:16] input io_router_clocks_5_clock, // @[NoC.scala:143:16] input io_router_clocks_5_reset, // @[NoC.scala:143:16] input io_router_clocks_6_clock, // @[NoC.scala:143:16] input io_router_clocks_6_reset, // @[NoC.scala:143:16] input io_router_clocks_7_clock, // @[NoC.scala:143:16] input io_router_clocks_7_reset, // @[NoC.scala:143:16] input io_router_clocks_8_clock, // @[NoC.scala:143:16] input io_router_clocks_8_reset, // @[NoC.scala:143:16] input io_router_clocks_9_clock, // @[NoC.scala:143:16] input io_router_clocks_9_reset, // @[NoC.scala:143:16] input io_router_clocks_10_clock, // @[NoC.scala:143:16] input io_router_clocks_10_reset, // @[NoC.scala:143:16] input io_router_clocks_11_clock, // @[NoC.scala:143:16] input io_router_clocks_11_reset, // @[NoC.scala:143:16] input io_router_clocks_12_clock, // @[NoC.scala:143:16] input io_router_clocks_12_reset // @[NoC.scala:143:16] ); wire [2:0] _router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_12_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_12_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_11_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_11_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_10_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_10_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_9_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_9_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_8_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_8_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_7_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_7_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_6_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_6_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_5_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_5_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_4_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_4_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_2_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_2_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_1_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_1_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [72:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [5:0] _router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] reg [63:0] debug_va_stall_ctr; // @[NoC.scala:163:37] reg [63:0] debug_sa_stall_ctr; // @[NoC.scala:164:37] wire [63:0] debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50] always @(posedge clock) begin // @[NoC.scala:141:9] if (reset) begin // @[NoC.scala:141:9] debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37] debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37] end else begin // @[NoC.scala:141:9] debug_va_stall_ctr <= debug_va_stall_ctr + {61'h0, _router_sink_domain_auto_routers_debug_out_va_stall_0 + _router_sink_domain_auto_routers_debug_out_va_stall_1 + _router_sink_domain_auto_routers_debug_out_va_stall_2 + _router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _router_sink_domain_3_auto_routers_debug_out_va_stall_1 + _router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _router_sink_domain_8_auto_routers_debug_out_va_stall_3 + _router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _router_sink_domain_12_auto_routers_debug_out_va_stall_1}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}] debug_sa_stall_ctr <= debug_sa_stall_ctr + {61'h0, _router_sink_domain_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_12_auto_routers_debug_out_sa_stall_1}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e5_s11_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e5_s11_1( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_290 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_34 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_290( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_34 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_47 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_47 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_47(); // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out = 33'h180000000; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [26:0] io_in_sig = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [9:0] io_in_sExp = 10'hFF; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_sign = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_47 roundAnyRawFNToRecFN (); // @[RoundAnyRawFNToRecFN.scala:310:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_1 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T

module MulAddRecFNToRaw_postMul_e8_s24_1( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ComposedBranchPredictorBank : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid inst loop of LoopBranchPredictorBank connect loop.clock, clock connect loop.reset, reset inst tage of TageBranchPredictorBank connect tage.clock, clock connect tage.reset, reset inst btb of BTBBranchPredictorBank connect btb.clock, clock connect btb.reset, reset inst bim of BIMBranchPredictorBank connect bim.clock, clock connect bim.reset, reset inst ubtb of FAMicroBTBBranchPredictorBank connect ubtb.clock, clock connect ubtb.reset, reset invalidate loop.io.update.bits.meta invalidate loop.io.update.bits.target invalidate loop.io.update.bits.lhist invalidate loop.io.update.bits.ghist invalidate loop.io.update.bits.cfi_is_jalr invalidate loop.io.update.bits.cfi_is_jal invalidate loop.io.update.bits.cfi_is_br invalidate loop.io.update.bits.cfi_mispredicted invalidate loop.io.update.bits.cfi_taken invalidate loop.io.update.bits.cfi_idx.bits invalidate loop.io.update.bits.cfi_idx.valid invalidate loop.io.update.bits.br_mask invalidate loop.io.update.bits.pc invalidate loop.io.update.bits.btb_mispredicts invalidate loop.io.update.bits.is_repair_update invalidate loop.io.update.bits.is_mispredict_update invalidate loop.io.update.valid invalidate loop.io.f3_fire invalidate loop.io.f3_meta invalidate loop.io.resp.f3[0].predicted_pc.bits invalidate loop.io.resp.f3[0].predicted_pc.valid invalidate loop.io.resp.f3[0].is_jal invalidate loop.io.resp.f3[0].is_br invalidate loop.io.resp.f3[0].taken invalidate loop.io.resp.f3[1].predicted_pc.bits invalidate loop.io.resp.f3[1].predicted_pc.valid invalidate loop.io.resp.f3[1].is_jal invalidate loop.io.resp.f3[1].is_br invalidate loop.io.resp.f3[1].taken invalidate loop.io.resp.f3[2].predicted_pc.bits invalidate loop.io.resp.f3[2].predicted_pc.valid invalidate loop.io.resp.f3[2].is_jal invalidate loop.io.resp.f3[2].is_br invalidate loop.io.resp.f3[2].taken invalidate loop.io.resp.f3[3].predicted_pc.bits invalidate loop.io.resp.f3[3].predicted_pc.valid invalidate loop.io.resp.f3[3].is_jal invalidate loop.io.resp.f3[3].is_br invalidate loop.io.resp.f3[3].taken invalidate loop.io.resp.f2[0].predicted_pc.bits invalidate loop.io.resp.f2[0].predicted_pc.valid invalidate loop.io.resp.f2[0].is_jal invalidate loop.io.resp.f2[0].is_br invalidate loop.io.resp.f2[0].taken invalidate loop.io.resp.f2[1].predicted_pc.bits invalidate loop.io.resp.f2[1].predicted_pc.valid invalidate loop.io.resp.f2[1].is_jal invalidate loop.io.resp.f2[1].is_br invalidate loop.io.resp.f2[1].taken invalidate loop.io.resp.f2[2].predicted_pc.bits invalidate loop.io.resp.f2[2].predicted_pc.valid invalidate loop.io.resp.f2[2].is_jal invalidate loop.io.resp.f2[2].is_br invalidate loop.io.resp.f2[2].taken invalidate loop.io.resp.f2[3].predicted_pc.bits invalidate loop.io.resp.f2[3].predicted_pc.valid invalidate loop.io.resp.f2[3].is_jal invalidate loop.io.resp.f2[3].is_br invalidate loop.io.resp.f2[3].taken invalidate loop.io.resp.f1[0].predicted_pc.bits invalidate loop.io.resp.f1[0].predicted_pc.valid invalidate loop.io.resp.f1[0].is_jal invalidate loop.io.resp.f1[0].is_br invalidate loop.io.resp.f1[0].taken invalidate loop.io.resp.f1[1].predicted_pc.bits invalidate loop.io.resp.f1[1].predicted_pc.valid invalidate loop.io.resp.f1[1].is_jal invalidate loop.io.resp.f1[1].is_br invalidate loop.io.resp.f1[1].taken invalidate loop.io.resp.f1[2].predicted_pc.bits invalidate loop.io.resp.f1[2].predicted_pc.valid invalidate loop.io.resp.f1[2].is_jal invalidate loop.io.resp.f1[2].is_br invalidate loop.io.resp.f1[2].taken invalidate loop.io.resp.f1[3].predicted_pc.bits invalidate loop.io.resp.f1[3].predicted_pc.valid invalidate loop.io.resp.f1[3].is_jal invalidate loop.io.resp.f1[3].is_br invalidate loop.io.resp.f1[3].taken invalidate loop.io.resp_in[0].f3[0].predicted_pc.bits invalidate loop.io.resp_in[0].f3[0].predicted_pc.valid invalidate loop.io.resp_in[0].f3[0].is_jal invalidate loop.io.resp_in[0].f3[0].is_br invalidate loop.io.resp_in[0].f3[0].taken invalidate loop.io.resp_in[0].f3[1].predicted_pc.bits invalidate loop.io.resp_in[0].f3[1].predicted_pc.valid invalidate loop.io.resp_in[0].f3[1].is_jal invalidate loop.io.resp_in[0].f3[1].is_br invalidate loop.io.resp_in[0].f3[1].taken invalidate loop.io.resp_in[0].f3[2].predicted_pc.bits invalidate loop.io.resp_in[0].f3[2].predicted_pc.valid invalidate loop.io.resp_in[0].f3[2].is_jal invalidate loop.io.resp_in[0].f3[2].is_br invalidate loop.io.resp_in[0].f3[2].taken invalidate loop.io.resp_in[0].f3[3].predicted_pc.bits invalidate loop.io.resp_in[0].f3[3].predicted_pc.valid invalidate loop.io.resp_in[0].f3[3].is_jal invalidate loop.io.resp_in[0].f3[3].is_br invalidate loop.io.resp_in[0].f3[3].taken invalidate loop.io.resp_in[0].f2[0].predicted_pc.bits invalidate loop.io.resp_in[0].f2[0].predicted_pc.valid invalidate loop.io.resp_in[0].f2[0].is_jal invalidate loop.io.resp_in[0].f2[0].is_br invalidate loop.io.resp_in[0].f2[0].taken invalidate loop.io.resp_in[0].f2[1].predicted_pc.bits invalidate loop.io.resp_in[0].f2[1].predicted_pc.valid invalidate loop.io.resp_in[0].f2[1].is_jal invalidate loop.io.resp_in[0].f2[1].is_br invalidate loop.io.resp_in[0].f2[1].taken invalidate loop.io.resp_in[0].f2[2].predicted_pc.bits invalidate loop.io.resp_in[0].f2[2].predicted_pc.valid invalidate loop.io.resp_in[0].f2[2].is_jal invalidate loop.io.resp_in[0].f2[2].is_br invalidate loop.io.resp_in[0].f2[2].taken invalidate loop.io.resp_in[0].f2[3].predicted_pc.bits invalidate loop.io.resp_in[0].f2[3].predicted_pc.valid invalidate loop.io.resp_in[0].f2[3].is_jal invalidate loop.io.resp_in[0].f2[3].is_br invalidate loop.io.resp_in[0].f2[3].taken invalidate loop.io.resp_in[0].f1[0].predicted_pc.bits invalidate loop.io.resp_in[0].f1[0].predicted_pc.valid invalidate loop.io.resp_in[0].f1[0].is_jal invalidate loop.io.resp_in[0].f1[0].is_br invalidate loop.io.resp_in[0].f1[0].taken invalidate loop.io.resp_in[0].f1[1].predicted_pc.bits invalidate loop.io.resp_in[0].f1[1].predicted_pc.valid invalidate loop.io.resp_in[0].f1[1].is_jal invalidate loop.io.resp_in[0].f1[1].is_br invalidate loop.io.resp_in[0].f1[1].taken invalidate loop.io.resp_in[0].f1[2].predicted_pc.bits invalidate loop.io.resp_in[0].f1[2].predicted_pc.valid invalidate loop.io.resp_in[0].f1[2].is_jal invalidate loop.io.resp_in[0].f1[2].is_br invalidate loop.io.resp_in[0].f1[2].taken invalidate loop.io.resp_in[0].f1[3].predicted_pc.bits invalidate loop.io.resp_in[0].f1[3].predicted_pc.valid invalidate loop.io.resp_in[0].f1[3].is_jal invalidate loop.io.resp_in[0].f1[3].is_br invalidate loop.io.resp_in[0].f1[3].taken invalidate loop.io.f1_lhist invalidate loop.io.f1_ghist invalidate loop.io.f0_mask invalidate loop.io.f0_pc invalidate loop.io.f0_valid invalidate tage.io.update.bits.meta invalidate tage.io.update.bits.target invalidate tage.io.update.bits.lhist invalidate tage.io.update.bits.ghist invalidate tage.io.update.bits.cfi_is_jalr invalidate tage.io.update.bits.cfi_is_jal invalidate tage.io.update.bits.cfi_is_br invalidate tage.io.update.bits.cfi_mispredicted invalidate tage.io.update.bits.cfi_taken invalidate tage.io.update.bits.cfi_idx.bits invalidate tage.io.update.bits.cfi_idx.valid invalidate tage.io.update.bits.br_mask invalidate tage.io.update.bits.pc invalidate tage.io.update.bits.btb_mispredicts invalidate tage.io.update.bits.is_repair_update invalidate tage.io.update.bits.is_mispredict_update invalidate tage.io.update.valid invalidate tage.io.f3_fire invalidate tage.io.f3_meta invalidate tage.io.resp.f3[0].predicted_pc.bits invalidate tage.io.resp.f3[0].predicted_pc.valid invalidate tage.io.resp.f3[0].is_jal invalidate tage.io.resp.f3[0].is_br invalidate tage.io.resp.f3[0].taken invalidate tage.io.resp.f3[1].predicted_pc.bits invalidate tage.io.resp.f3[1].predicted_pc.valid invalidate tage.io.resp.f3[1].is_jal invalidate tage.io.resp.f3[1].is_br invalidate tage.io.resp.f3[1].taken invalidate tage.io.resp.f3[2].predicted_pc.bits invalidate tage.io.resp.f3[2].predicted_pc.valid invalidate tage.io.resp.f3[2].is_jal invalidate tage.io.resp.f3[2].is_br invalidate tage.io.resp.f3[2].taken invalidate tage.io.resp.f3[3].predicted_pc.bits invalidate tage.io.resp.f3[3].predicted_pc.valid invalidate tage.io.resp.f3[3].is_jal invalidate tage.io.resp.f3[3].is_br invalidate tage.io.resp.f3[3].taken invalidate tage.io.resp.f2[0].predicted_pc.bits invalidate tage.io.resp.f2[0].predicted_pc.valid invalidate tage.io.resp.f2[0].is_jal invalidate tage.io.resp.f2[0].is_br invalidate tage.io.resp.f2[0].taken invalidate tage.io.resp.f2[1].predicted_pc.bits invalidate tage.io.resp.f2[1].predicted_pc.valid invalidate tage.io.resp.f2[1].is_jal invalidate tage.io.resp.f2[1].is_br invalidate tage.io.resp.f2[1].taken invalidate tage.io.resp.f2[2].predicted_pc.bits invalidate tage.io.resp.f2[2].predicted_pc.valid invalidate tage.io.resp.f2[2].is_jal invalidate tage.io.resp.f2[2].is_br invalidate tage.io.resp.f2[2].taken invalidate tage.io.resp.f2[3].predicted_pc.bits invalidate tage.io.resp.f2[3].predicted_pc.valid invalidate tage.io.resp.f2[3].is_jal invalidate tage.io.resp.f2[3].is_br invalidate tage.io.resp.f2[3].taken invalidate tage.io.resp.f1[0].predicted_pc.bits invalidate tage.io.resp.f1[0].predicted_pc.valid invalidate tage.io.resp.f1[0].is_jal invalidate tage.io.resp.f1[0].is_br invalidate tage.io.resp.f1[0].taken invalidate tage.io.resp.f1[1].predicted_pc.bits invalidate tage.io.resp.f1[1].predicted_pc.valid invalidate tage.io.resp.f1[1].is_jal invalidate tage.io.resp.f1[1].is_br invalidate tage.io.resp.f1[1].taken invalidate tage.io.resp.f1[2].predicted_pc.bits invalidate tage.io.resp.f1[2].predicted_pc.valid invalidate tage.io.resp.f1[2].is_jal invalidate tage.io.resp.f1[2].is_br invalidate tage.io.resp.f1[2].taken invalidate tage.io.resp.f1[3].predicted_pc.bits invalidate tage.io.resp.f1[3].predicted_pc.valid invalidate tage.io.resp.f1[3].is_jal invalidate tage.io.resp.f1[3].is_br invalidate tage.io.resp.f1[3].taken invalidate tage.io.resp_in[0].f3[0].predicted_pc.bits invalidate tage.io.resp_in[0].f3[0].predicted_pc.valid invalidate tage.io.resp_in[0].f3[0].is_jal invalidate tage.io.resp_in[0].f3[0].is_br invalidate tage.io.resp_in[0].f3[0].taken invalidate tage.io.resp_in[0].f3[1].predicted_pc.bits invalidate tage.io.resp_in[0].f3[1].predicted_pc.valid invalidate tage.io.resp_in[0].f3[1].is_jal invalidate tage.io.resp_in[0].f3[1].is_br invalidate tage.io.resp_in[0].f3[1].taken invalidate tage.io.resp_in[0].f3[2].predicted_pc.bits invalidate tage.io.resp_in[0].f3[2].predicted_pc.valid invalidate tage.io.resp_in[0].f3[2].is_jal invalidate tage.io.resp_in[0].f3[2].is_br invalidate tage.io.resp_in[0].f3[2].taken invalidate tage.io.resp_in[0].f3[3].predicted_pc.bits invalidate tage.io.resp_in[0].f3[3].predicted_pc.valid invalidate tage.io.resp_in[0].f3[3].is_jal invalidate tage.io.resp_in[0].f3[3].is_br invalidate tage.io.resp_in[0].f3[3].taken invalidate tage.io.resp_in[0].f2[0].predicted_pc.bits invalidate tage.io.resp_in[0].f2[0].predicted_pc.valid invalidate tage.io.resp_in[0].f2[0].is_jal invalidate tage.io.resp_in[0].f2[0].is_br invalidate tage.io.resp_in[0].f2[0].taken invalidate tage.io.resp_in[0].f2[1].predicted_pc.bits invalidate tage.io.resp_in[0].f2[1].predicted_pc.valid invalidate tage.io.resp_in[0].f2[1].is_jal invalidate tage.io.resp_in[0].f2[1].is_br invalidate tage.io.resp_in[0].f2[1].taken invalidate tage.io.resp_in[0].f2[2].predicted_pc.bits invalidate tage.io.resp_in[0].f2[2].predicted_pc.valid invalidate tage.io.resp_in[0].f2[2].is_jal invalidate tage.io.resp_in[0].f2[2].is_br invalidate tage.io.resp_in[0].f2[2].taken invalidate tage.io.resp_in[0].f2[3].predicted_pc.bits invalidate tage.io.resp_in[0].f2[3].predicted_pc.valid invalidate tage.io.resp_in[0].f2[3].is_jal invalidate tage.io.resp_in[0].f2[3].is_br invalidate tage.io.resp_in[0].f2[3].taken invalidate tage.io.resp_in[0].f1[0].predicted_pc.bits invalidate tage.io.resp_in[0].f1[0].predicted_pc.valid invalidate tage.io.resp_in[0].f1[0].is_jal invalidate tage.io.resp_in[0].f1[0].is_br invalidate tage.io.resp_in[0].f1[0].taken invalidate tage.io.resp_in[0].f1[1].predicted_pc.bits invalidate tage.io.resp_in[0].f1[1].predicted_pc.valid invalidate tage.io.resp_in[0].f1[1].is_jal invalidate tage.io.resp_in[0].f1[1].is_br invalidate tage.io.resp_in[0].f1[1].taken invalidate tage.io.resp_in[0].f1[2].predicted_pc.bits invalidate tage.io.resp_in[0].f1[2].predicted_pc.valid invalidate tage.io.resp_in[0].f1[2].is_jal invalidate tage.io.resp_in[0].f1[2].is_br invalidate tage.io.resp_in[0].f1[2].taken invalidate tage.io.resp_in[0].f1[3].predicted_pc.bits invalidate tage.io.resp_in[0].f1[3].predicted_pc.valid invalidate tage.io.resp_in[0].f1[3].is_jal invalidate tage.io.resp_in[0].f1[3].is_br invalidate tage.io.resp_in[0].f1[3].taken invalidate tage.io.f1_lhist invalidate tage.io.f1_ghist invalidate tage.io.f0_mask invalidate tage.io.f0_pc invalidate tage.io.f0_valid invalidate btb.io.update.bits.meta invalidate btb.io.update.bits.target invalidate btb.io.update.bits.lhist invalidate btb.io.update.bits.ghist invalidate btb.io.update.bits.cfi_is_jalr invalidate btb.io.update.bits.cfi_is_jal invalidate btb.io.update.bits.cfi_is_br invalidate btb.io.update.bits.cfi_mispredicted invalidate btb.io.update.bits.cfi_taken invalidate btb.io.update.bits.cfi_idx.bits invalidate btb.io.update.bits.cfi_idx.valid invalidate btb.io.update.bits.br_mask invalidate btb.io.update.bits.pc invalidate btb.io.update.bits.btb_mispredicts invalidate btb.io.update.bits.is_repair_update invalidate btb.io.update.bits.is_mispredict_update invalidate btb.io.update.valid invalidate btb.io.f3_fire invalidate btb.io.f3_meta invalidate btb.io.resp.f3[0].predicted_pc.bits invalidate btb.io.resp.f3[0].predicted_pc.valid invalidate btb.io.resp.f3[0].is_jal invalidate btb.io.resp.f3[0].is_br invalidate btb.io.resp.f3[0].taken invalidate btb.io.resp.f3[1].predicted_pc.bits invalidate btb.io.resp.f3[1].predicted_pc.valid invalidate btb.io.resp.f3[1].is_jal invalidate btb.io.resp.f3[1].is_br invalidate btb.io.resp.f3[1].taken invalidate btb.io.resp.f3[2].predicted_pc.bits invalidate btb.io.resp.f3[2].predicted_pc.valid invalidate btb.io.resp.f3[2].is_jal invalidate btb.io.resp.f3[2].is_br invalidate btb.io.resp.f3[2].taken invalidate btb.io.resp.f3[3].predicted_pc.bits invalidate btb.io.resp.f3[3].predicted_pc.valid invalidate btb.io.resp.f3[3].is_jal invalidate btb.io.resp.f3[3].is_br invalidate btb.io.resp.f3[3].taken invalidate btb.io.resp.f2[0].predicted_pc.bits invalidate btb.io.resp.f2[0].predicted_pc.valid invalidate btb.io.resp.f2[0].is_jal invalidate btb.io.resp.f2[0].is_br invalidate btb.io.resp.f2[0].taken invalidate btb.io.resp.f2[1].predicted_pc.bits invalidate btb.io.resp.f2[1].predicted_pc.valid invalidate btb.io.resp.f2[1].is_jal invalidate btb.io.resp.f2[1].is_br invalidate btb.io.resp.f2[1].taken invalidate btb.io.resp.f2[2].predicted_pc.bits invalidate btb.io.resp.f2[2].predicted_pc.valid invalidate btb.io.resp.f2[2].is_jal invalidate btb.io.resp.f2[2].is_br invalidate btb.io.resp.f2[2].taken invalidate btb.io.resp.f2[3].predicted_pc.bits invalidate btb.io.resp.f2[3].predicted_pc.valid invalidate btb.io.resp.f2[3].is_jal invalidate btb.io.resp.f2[3].is_br invalidate btb.io.resp.f2[3].taken invalidate btb.io.resp.f1[0].predicted_pc.bits invalidate btb.io.resp.f1[0].predicted_pc.valid invalidate btb.io.resp.f1[0].is_jal invalidate btb.io.resp.f1[0].is_br invalidate btb.io.resp.f1[0].taken invalidate btb.io.resp.f1[1].predicted_pc.bits invalidate btb.io.resp.f1[1].predicted_pc.valid invalidate btb.io.resp.f1[1].is_jal invalidate btb.io.resp.f1[1].is_br invalidate btb.io.resp.f1[1].taken invalidate btb.io.resp.f1[2].predicted_pc.bits invalidate btb.io.resp.f1[2].predicted_pc.valid invalidate btb.io.resp.f1[2].is_jal invalidate btb.io.resp.f1[2].is_br invalidate btb.io.resp.f1[2].taken invalidate btb.io.resp.f1[3].predicted_pc.bits invalidate btb.io.resp.f1[3].predicted_pc.valid invalidate btb.io.resp.f1[3].is_jal invalidate btb.io.resp.f1[3].is_br invalidate btb.io.resp.f1[3].taken invalidate btb.io.resp_in[0].f3[0].predicted_pc.bits invalidate btb.io.resp_in[0].f3[0].predicted_pc.valid invalidate btb.io.resp_in[0].f3[0].is_jal invalidate btb.io.resp_in[0].f3[0].is_br invalidate btb.io.resp_in[0].f3[0].taken invalidate btb.io.resp_in[0].f3[1].predicted_pc.bits invalidate btb.io.resp_in[0].f3[1].predicted_pc.valid invalidate btb.io.resp_in[0].f3[1].is_jal invalidate btb.io.resp_in[0].f3[1].is_br invalidate btb.io.resp_in[0].f3[1].taken invalidate btb.io.resp_in[0].f3[2].predicted_pc.bits invalidate btb.io.resp_in[0].f3[2].predicted_pc.valid invalidate btb.io.resp_in[0].f3[2].is_jal invalidate btb.io.resp_in[0].f3[2].is_br invalidate btb.io.resp_in[0].f3[2].taken invalidate btb.io.resp_in[0].f3[3].predicted_pc.bits invalidate btb.io.resp_in[0].f3[3].predicted_pc.valid invalidate btb.io.resp_in[0].f3[3].is_jal invalidate btb.io.resp_in[0].f3[3].is_br invalidate btb.io.resp_in[0].f3[3].taken invalidate btb.io.resp_in[0].f2[0].predicted_pc.bits invalidate btb.io.resp_in[0].f2[0].predicted_pc.valid invalidate btb.io.resp_in[0].f2[0].is_jal invalidate btb.io.resp_in[0].f2[0].is_br invalidate btb.io.resp_in[0].f2[0].taken invalidate btb.io.resp_in[0].f2[1].predicted_pc.bits invalidate btb.io.resp_in[0].f2[1].predicted_pc.valid invalidate btb.io.resp_in[0].f2[1].is_jal invalidate btb.io.resp_in[0].f2[1].is_br invalidate btb.io.resp_in[0].f2[1].taken invalidate btb.io.resp_in[0].f2[2].predicted_pc.bits invalidate btb.io.resp_in[0].f2[2].predicted_pc.valid invalidate btb.io.resp_in[0].f2[2].is_jal invalidate btb.io.resp_in[0].f2[2].is_br invalidate btb.io.resp_in[0].f2[2].taken invalidate btb.io.resp_in[0].f2[3].predicted_pc.bits invalidate btb.io.resp_in[0].f2[3].predicted_pc.valid invalidate btb.io.resp_in[0].f2[3].is_jal invalidate btb.io.resp_in[0].f2[3].is_br invalidate btb.io.resp_in[0].f2[3].taken invalidate btb.io.resp_in[0].f1[0].predicted_pc.bits invalidate btb.io.resp_in[0].f1[0].predicted_pc.valid invalidate btb.io.resp_in[0].f1[0].is_jal invalidate btb.io.resp_in[0].f1[0].is_br invalidate btb.io.resp_in[0].f1[0].taken invalidate btb.io.resp_in[0].f1[1].predicted_pc.bits invalidate btb.io.resp_in[0].f1[1].predicted_pc.valid invalidate btb.io.resp_in[0].f1[1].is_jal invalidate btb.io.resp_in[0].f1[1].is_br invalidate btb.io.resp_in[0].f1[1].taken invalidate btb.io.resp_in[0].f1[2].predicted_pc.bits invalidate btb.io.resp_in[0].f1[2].predicted_pc.valid invalidate btb.io.resp_in[0].f1[2].is_jal invalidate btb.io.resp_in[0].f1[2].is_br invalidate btb.io.resp_in[0].f1[2].taken invalidate btb.io.resp_in[0].f1[3].predicted_pc.bits invalidate btb.io.resp_in[0].f1[3].predicted_pc.valid invalidate btb.io.resp_in[0].f1[3].is_jal invalidate btb.io.resp_in[0].f1[3].is_br invalidate btb.io.resp_in[0].f1[3].taken invalidate btb.io.f1_lhist invalidate btb.io.f1_ghist invalidate btb.io.f0_mask invalidate btb.io.f0_pc invalidate btb.io.f0_valid invalidate ubtb.io.update.bits.meta invalidate ubtb.io.update.bits.target invalidate ubtb.io.update.bits.lhist invalidate ubtb.io.update.bits.ghist invalidate ubtb.io.update.bits.cfi_is_jalr invalidate ubtb.io.update.bits.cfi_is_jal invalidate ubtb.io.update.bits.cfi_is_br invalidate ubtb.io.update.bits.cfi_mispredicted invalidate ubtb.io.update.bits.cfi_taken invalidate ubtb.io.update.bits.cfi_idx.bits invalidate ubtb.io.update.bits.cfi_idx.valid invalidate ubtb.io.update.bits.br_mask invalidate ubtb.io.update.bits.pc invalidate ubtb.io.update.bits.btb_mispredicts invalidate ubtb.io.update.bits.is_repair_update invalidate ubtb.io.update.bits.is_mispredict_update invalidate ubtb.io.update.valid invalidate ubtb.io.f3_fire invalidate ubtb.io.f3_meta invalidate ubtb.io.resp.f3[0].predicted_pc.bits invalidate ubtb.io.resp.f3[0].predicted_pc.valid invalidate ubtb.io.resp.f3[0].is_jal invalidate ubtb.io.resp.f3[0].is_br invalidate ubtb.io.resp.f3[0].taken invalidate ubtb.io.resp.f3[1].predicted_pc.bits invalidate ubtb.io.resp.f3[1].predicted_pc.valid invalidate ubtb.io.resp.f3[1].is_jal invalidate ubtb.io.resp.f3[1].is_br invalidate ubtb.io.resp.f3[1].taken invalidate ubtb.io.resp.f3[2].predicted_pc.bits invalidate ubtb.io.resp.f3[2].predicted_pc.valid invalidate ubtb.io.resp.f3[2].is_jal invalidate ubtb.io.resp.f3[2].is_br invalidate ubtb.io.resp.f3[2].taken invalidate ubtb.io.resp.f3[3].predicted_pc.bits invalidate ubtb.io.resp.f3[3].predicted_pc.valid invalidate ubtb.io.resp.f3[3].is_jal invalidate ubtb.io.resp.f3[3].is_br invalidate ubtb.io.resp.f3[3].taken invalidate ubtb.io.resp.f2[0].predicted_pc.bits invalidate ubtb.io.resp.f2[0].predicted_pc.valid invalidate ubtb.io.resp.f2[0].is_jal invalidate ubtb.io.resp.f2[0].is_br invalidate ubtb.io.resp.f2[0].taken invalidate ubtb.io.resp.f2[1].predicted_pc.bits invalidate ubtb.io.resp.f2[1].predicted_pc.valid invalidate ubtb.io.resp.f2[1].is_jal invalidate ubtb.io.resp.f2[1].is_br invalidate ubtb.io.resp.f2[1].taken invalidate ubtb.io.resp.f2[2].predicted_pc.bits invalidate ubtb.io.resp.f2[2].predicted_pc.valid invalidate ubtb.io.resp.f2[2].is_jal invalidate ubtb.io.resp.f2[2].is_br invalidate ubtb.io.resp.f2[2].taken invalidate ubtb.io.resp.f2[3].predicted_pc.bits invalidate ubtb.io.resp.f2[3].predicted_pc.valid invalidate ubtb.io.resp.f2[3].is_jal invalidate ubtb.io.resp.f2[3].is_br invalidate ubtb.io.resp.f2[3].taken invalidate ubtb.io.resp.f1[0].predicted_pc.bits invalidate ubtb.io.resp.f1[0].predicted_pc.valid invalidate ubtb.io.resp.f1[0].is_jal invalidate ubtb.io.resp.f1[0].is_br invalidate ubtb.io.resp.f1[0].taken invalidate ubtb.io.resp.f1[1].predicted_pc.bits invalidate ubtb.io.resp.f1[1].predicted_pc.valid invalidate ubtb.io.resp.f1[1].is_jal invalidate ubtb.io.resp.f1[1].is_br invalidate ubtb.io.resp.f1[1].taken invalidate ubtb.io.resp.f1[2].predicted_pc.bits invalidate ubtb.io.resp.f1[2].predicted_pc.valid invalidate ubtb.io.resp.f1[2].is_jal invalidate ubtb.io.resp.f1[2].is_br invalidate ubtb.io.resp.f1[2].taken invalidate ubtb.io.resp.f1[3].predicted_pc.bits invalidate ubtb.io.resp.f1[3].predicted_pc.valid invalidate ubtb.io.resp.f1[3].is_jal invalidate ubtb.io.resp.f1[3].is_br invalidate ubtb.io.resp.f1[3].taken invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[0].is_jal invalidate ubtb.io.resp_in[0].f3[0].is_br invalidate ubtb.io.resp_in[0].f3[0].taken invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[1].is_jal invalidate ubtb.io.resp_in[0].f3[1].is_br invalidate ubtb.io.resp_in[0].f3[1].taken invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[2].is_jal invalidate ubtb.io.resp_in[0].f3[2].is_br invalidate ubtb.io.resp_in[0].f3[2].taken invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.bits invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.valid invalidate ubtb.io.resp_in[0].f3[3].is_jal invalidate ubtb.io.resp_in[0].f3[3].is_br invalidate ubtb.io.resp_in[0].f3[3].taken invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[0].is_jal invalidate ubtb.io.resp_in[0].f2[0].is_br invalidate ubtb.io.resp_in[0].f2[0].taken invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[1].is_jal invalidate ubtb.io.resp_in[0].f2[1].is_br invalidate ubtb.io.resp_in[0].f2[1].taken invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[2].is_jal invalidate ubtb.io.resp_in[0].f2[2].is_br invalidate ubtb.io.resp_in[0].f2[2].taken invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.bits invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.valid invalidate ubtb.io.resp_in[0].f2[3].is_jal invalidate ubtb.io.resp_in[0].f2[3].is_br invalidate ubtb.io.resp_in[0].f2[3].taken invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[0].is_jal invalidate ubtb.io.resp_in[0].f1[0].is_br invalidate ubtb.io.resp_in[0].f1[0].taken invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[1].is_jal invalidate ubtb.io.resp_in[0].f1[1].is_br invalidate ubtb.io.resp_in[0].f1[1].taken invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[2].is_jal invalidate ubtb.io.resp_in[0].f1[2].is_br invalidate ubtb.io.resp_in[0].f1[2].taken invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.bits invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.valid invalidate ubtb.io.resp_in[0].f1[3].is_jal invalidate ubtb.io.resp_in[0].f1[3].is_br invalidate ubtb.io.resp_in[0].f1[3].taken invalidate ubtb.io.f1_lhist invalidate ubtb.io.f1_ghist invalidate ubtb.io.f0_mask invalidate ubtb.io.f0_pc invalidate ubtb.io.f0_valid invalidate bim.io.update.bits.meta invalidate bim.io.update.bits.target invalidate bim.io.update.bits.lhist invalidate bim.io.update.bits.ghist invalidate bim.io.update.bits.cfi_is_jalr invalidate bim.io.update.bits.cfi_is_jal invalidate bim.io.update.bits.cfi_is_br invalidate bim.io.update.bits.cfi_mispredicted invalidate bim.io.update.bits.cfi_taken invalidate bim.io.update.bits.cfi_idx.bits invalidate bim.io.update.bits.cfi_idx.valid invalidate bim.io.update.bits.br_mask invalidate bim.io.update.bits.pc invalidate bim.io.update.bits.btb_mispredicts invalidate bim.io.update.bits.is_repair_update invalidate bim.io.update.bits.is_mispredict_update invalidate bim.io.update.valid invalidate bim.io.f3_fire invalidate bim.io.f3_meta invalidate bim.io.resp.f3[0].predicted_pc.bits invalidate bim.io.resp.f3[0].predicted_pc.valid invalidate bim.io.resp.f3[0].is_jal invalidate bim.io.resp.f3[0].is_br invalidate bim.io.resp.f3[0].taken invalidate bim.io.resp.f3[1].predicted_pc.bits invalidate bim.io.resp.f3[1].predicted_pc.valid invalidate bim.io.resp.f3[1].is_jal invalidate bim.io.resp.f3[1].is_br invalidate bim.io.resp.f3[1].taken invalidate bim.io.resp.f3[2].predicted_pc.bits invalidate bim.io.resp.f3[2].predicted_pc.valid invalidate bim.io.resp.f3[2].is_jal invalidate bim.io.resp.f3[2].is_br invalidate bim.io.resp.f3[2].taken invalidate bim.io.resp.f3[3].predicted_pc.bits invalidate bim.io.resp.f3[3].predicted_pc.valid invalidate bim.io.resp.f3[3].is_jal invalidate bim.io.resp.f3[3].is_br invalidate bim.io.resp.f3[3].taken invalidate bim.io.resp.f2[0].predicted_pc.bits invalidate bim.io.resp.f2[0].predicted_pc.valid invalidate bim.io.resp.f2[0].is_jal invalidate bim.io.resp.f2[0].is_br invalidate bim.io.resp.f2[0].taken invalidate bim.io.resp.f2[1].predicted_pc.bits invalidate bim.io.resp.f2[1].predicted_pc.valid invalidate bim.io.resp.f2[1].is_jal invalidate bim.io.resp.f2[1].is_br invalidate bim.io.resp.f2[1].taken invalidate bim.io.resp.f2[2].predicted_pc.bits invalidate bim.io.resp.f2[2].predicted_pc.valid invalidate bim.io.resp.f2[2].is_jal invalidate bim.io.resp.f2[2].is_br invalidate bim.io.resp.f2[2].taken invalidate bim.io.resp.f2[3].predicted_pc.bits invalidate bim.io.resp.f2[3].predicted_pc.valid invalidate bim.io.resp.f2[3].is_jal invalidate bim.io.resp.f2[3].is_br invalidate bim.io.resp.f2[3].taken invalidate bim.io.resp.f1[0].predicted_pc.bits invalidate bim.io.resp.f1[0].predicted_pc.valid invalidate bim.io.resp.f1[0].is_jal invalidate bim.io.resp.f1[0].is_br invalidate bim.io.resp.f1[0].taken invalidate bim.io.resp.f1[1].predicted_pc.bits invalidate bim.io.resp.f1[1].predicted_pc.valid invalidate bim.io.resp.f1[1].is_jal invalidate bim.io.resp.f1[1].is_br invalidate bim.io.resp.f1[1].taken invalidate bim.io.resp.f1[2].predicted_pc.bits invalidate bim.io.resp.f1[2].predicted_pc.valid invalidate bim.io.resp.f1[2].is_jal invalidate bim.io.resp.f1[2].is_br invalidate bim.io.resp.f1[2].taken invalidate bim.io.resp.f1[3].predicted_pc.bits invalidate bim.io.resp.f1[3].predicted_pc.valid invalidate bim.io.resp.f1[3].is_jal invalidate bim.io.resp.f1[3].is_br invalidate bim.io.resp.f1[3].taken invalidate bim.io.resp_in[0].f3[0].predicted_pc.bits invalidate bim.io.resp_in[0].f3[0].predicted_pc.valid invalidate bim.io.resp_in[0].f3[0].is_jal invalidate bim.io.resp_in[0].f3[0].is_br invalidate bim.io.resp_in[0].f3[0].taken invalidate bim.io.resp_in[0].f3[1].predicted_pc.bits invalidate bim.io.resp_in[0].f3[1].predicted_pc.valid invalidate bim.io.resp_in[0].f3[1].is_jal invalidate bim.io.resp_in[0].f3[1].is_br invalidate bim.io.resp_in[0].f3[1].taken invalidate bim.io.resp_in[0].f3[2].predicted_pc.bits invalidate bim.io.resp_in[0].f3[2].predicted_pc.valid invalidate bim.io.resp_in[0].f3[2].is_jal invalidate bim.io.resp_in[0].f3[2].is_br invalidate bim.io.resp_in[0].f3[2].taken invalidate bim.io.resp_in[0].f3[3].predicted_pc.bits invalidate bim.io.resp_in[0].f3[3].predicted_pc.valid invalidate bim.io.resp_in[0].f3[3].is_jal invalidate bim.io.resp_in[0].f3[3].is_br invalidate bim.io.resp_in[0].f3[3].taken invalidate bim.io.resp_in[0].f2[0].predicted_pc.bits invalidate bim.io.resp_in[0].f2[0].predicted_pc.valid invalidate bim.io.resp_in[0].f2[0].is_jal invalidate bim.io.resp_in[0].f2[0].is_br invalidate bim.io.resp_in[0].f2[0].taken invalidate bim.io.resp_in[0].f2[1].predicted_pc.bits invalidate bim.io.resp_in[0].f2[1].predicted_pc.valid invalidate bim.io.resp_in[0].f2[1].is_jal invalidate bim.io.resp_in[0].f2[1].is_br invalidate bim.io.resp_in[0].f2[1].taken invalidate bim.io.resp_in[0].f2[2].predicted_pc.bits invalidate bim.io.resp_in[0].f2[2].predicted_pc.valid invalidate bim.io.resp_in[0].f2[2].is_jal invalidate bim.io.resp_in[0].f2[2].is_br invalidate bim.io.resp_in[0].f2[2].taken invalidate bim.io.resp_in[0].f2[3].predicted_pc.bits invalidate bim.io.resp_in[0].f2[3].predicted_pc.valid invalidate bim.io.resp_in[0].f2[3].is_jal invalidate bim.io.resp_in[0].f2[3].is_br invalidate bim.io.resp_in[0].f2[3].taken invalidate bim.io.resp_in[0].f1[0].predicted_pc.bits invalidate bim.io.resp_in[0].f1[0].predicted_pc.valid invalidate bim.io.resp_in[0].f1[0].is_jal invalidate bim.io.resp_in[0].f1[0].is_br invalidate bim.io.resp_in[0].f1[0].taken invalidate bim.io.resp_in[0].f1[1].predicted_pc.bits invalidate bim.io.resp_in[0].f1[1].predicted_pc.valid invalidate bim.io.resp_in[0].f1[1].is_jal invalidate bim.io.resp_in[0].f1[1].is_br invalidate bim.io.resp_in[0].f1[1].taken invalidate bim.io.resp_in[0].f1[2].predicted_pc.bits invalidate bim.io.resp_in[0].f1[2].predicted_pc.valid invalidate bim.io.resp_in[0].f1[2].is_jal invalidate bim.io.resp_in[0].f1[2].is_br invalidate bim.io.resp_in[0].f1[2].taken invalidate bim.io.resp_in[0].f1[3].predicted_pc.bits invalidate bim.io.resp_in[0].f1[3].predicted_pc.valid invalidate bim.io.resp_in[0].f1[3].is_jal invalidate bim.io.resp_in[0].f1[3].is_br invalidate bim.io.resp_in[0].f1[3].taken invalidate bim.io.f1_lhist invalidate bim.io.f1_ghist invalidate bim.io.f0_mask invalidate bim.io.f0_pc invalidate bim.io.f0_valid connect ubtb.io.resp_in[0].f3[0].predicted_pc.bits, io.resp_in[0].f3[0].predicted_pc.bits connect ubtb.io.resp_in[0].f3[0].predicted_pc.valid, io.resp_in[0].f3[0].predicted_pc.valid connect ubtb.io.resp_in[0].f3[0].is_jal, io.resp_in[0].f3[0].is_jal connect ubtb.io.resp_in[0].f3[0].is_br, io.resp_in[0].f3[0].is_br connect ubtb.io.resp_in[0].f3[0].taken, io.resp_in[0].f3[0].taken connect ubtb.io.resp_in[0].f3[1].predicted_pc.bits, io.resp_in[0].f3[1].predicted_pc.bits connect ubtb.io.resp_in[0].f3[1].predicted_pc.valid, io.resp_in[0].f3[1].predicted_pc.valid connect ubtb.io.resp_in[0].f3[1].is_jal, io.resp_in[0].f3[1].is_jal connect ubtb.io.resp_in[0].f3[1].is_br, io.resp_in[0].f3[1].is_br connect ubtb.io.resp_in[0].f3[1].taken, io.resp_in[0].f3[1].taken connect ubtb.io.resp_in[0].f3[2].predicted_pc.bits, io.resp_in[0].f3[2].predicted_pc.bits connect ubtb.io.resp_in[0].f3[2].predicted_pc.valid, io.resp_in[0].f3[2].predicted_pc.valid connect ubtb.io.resp_in[0].f3[2].is_jal, io.resp_in[0].f3[2].is_jal connect ubtb.io.resp_in[0].f3[2].is_br, io.resp_in[0].f3[2].is_br connect ubtb.io.resp_in[0].f3[2].taken, io.resp_in[0].f3[2].taken connect ubtb.io.resp_in[0].f3[3].predicted_pc.bits, io.resp_in[0].f3[3].predicted_pc.bits connect ubtb.io.resp_in[0].f3[3].predicted_pc.valid, io.resp_in[0].f3[3].predicted_pc.valid connect ubtb.io.resp_in[0].f3[3].is_jal, io.resp_in[0].f3[3].is_jal connect ubtb.io.resp_in[0].f3[3].is_br, io.resp_in[0].f3[3].is_br connect ubtb.io.resp_in[0].f3[3].taken, io.resp_in[0].f3[3].taken connect ubtb.io.resp_in[0].f2[0].predicted_pc.bits, io.resp_in[0].f2[0].predicted_pc.bits connect ubtb.io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].predicted_pc.valid connect ubtb.io.resp_in[0].f2[0].is_jal, io.resp_in[0].f2[0].is_jal connect ubtb.io.resp_in[0].f2[0].is_br, io.resp_in[0].f2[0].is_br connect ubtb.io.resp_in[0].f2[0].taken, io.resp_in[0].f2[0].taken connect ubtb.io.resp_in[0].f2[1].predicted_pc.bits, io.resp_in[0].f2[1].predicted_pc.bits connect ubtb.io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].predicted_pc.valid connect ubtb.io.resp_in[0].f2[1].is_jal, io.resp_in[0].f2[1].is_jal connect ubtb.io.resp_in[0].f2[1].is_br, io.resp_in[0].f2[1].is_br connect ubtb.io.resp_in[0].f2[1].taken, io.resp_in[0].f2[1].taken connect ubtb.io.resp_in[0].f2[2].predicted_pc.bits, io.resp_in[0].f2[2].predicted_pc.bits connect ubtb.io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].predicted_pc.valid connect ubtb.io.resp_in[0].f2[2].is_jal, io.resp_in[0].f2[2].is_jal connect ubtb.io.resp_in[0].f2[2].is_br, io.resp_in[0].f2[2].is_br connect ubtb.io.resp_in[0].f2[2].taken, io.resp_in[0].f2[2].taken connect ubtb.io.resp_in[0].f2[3].predicted_pc.bits, io.resp_in[0].f2[3].predicted_pc.bits connect ubtb.io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].predicted_pc.valid connect ubtb.io.resp_in[0].f2[3].is_jal, io.resp_in[0].f2[3].is_jal connect ubtb.io.resp_in[0].f2[3].is_br, io.resp_in[0].f2[3].is_br connect ubtb.io.resp_in[0].f2[3].taken, io.resp_in[0].f2[3].taken connect ubtb.io.resp_in[0].f1[0].predicted_pc.bits, io.resp_in[0].f1[0].predicted_pc.bits connect ubtb.io.resp_in[0].f1[0].predicted_pc.valid, io.resp_in[0].f1[0].predicted_pc.valid connect ubtb.io.resp_in[0].f1[0].is_jal, io.resp_in[0].f1[0].is_jal connect ubtb.io.resp_in[0].f1[0].is_br, io.resp_in[0].f1[0].is_br connect ubtb.io.resp_in[0].f1[0].taken, io.resp_in[0].f1[0].taken connect ubtb.io.resp_in[0].f1[1].predicted_pc.bits, io.resp_in[0].f1[1].predicted_pc.bits connect ubtb.io.resp_in[0].f1[1].predicted_pc.valid, io.resp_in[0].f1[1].predicted_pc.valid connect ubtb.io.resp_in[0].f1[1].is_jal, io.resp_in[0].f1[1].is_jal connect ubtb.io.resp_in[0].f1[1].is_br, io.resp_in[0].f1[1].is_br connect ubtb.io.resp_in[0].f1[1].taken, io.resp_in[0].f1[1].taken connect ubtb.io.resp_in[0].f1[2].predicted_pc.bits, io.resp_in[0].f1[2].predicted_pc.bits connect ubtb.io.resp_in[0].f1[2].predicted_pc.valid, io.resp_in[0].f1[2].predicted_pc.valid connect ubtb.io.resp_in[0].f1[2].is_jal, io.resp_in[0].f1[2].is_jal connect ubtb.io.resp_in[0].f1[2].is_br, io.resp_in[0].f1[2].is_br connect ubtb.io.resp_in[0].f1[2].taken, io.resp_in[0].f1[2].taken connect ubtb.io.resp_in[0].f1[3].predicted_pc.bits, io.resp_in[0].f1[3].predicted_pc.bits connect ubtb.io.resp_in[0].f1[3].predicted_pc.valid, io.resp_in[0].f1[3].predicted_pc.valid connect ubtb.io.resp_in[0].f1[3].is_jal, io.resp_in[0].f1[3].is_jal connect ubtb.io.resp_in[0].f1[3].is_br, io.resp_in[0].f1[3].is_br connect ubtb.io.resp_in[0].f1[3].taken, io.resp_in[0].f1[3].taken connect bim.io.resp_in[0].f3[0].predicted_pc.bits, ubtb.io.resp.f3[0].predicted_pc.bits connect bim.io.resp_in[0].f3[0].predicted_pc.valid, ubtb.io.resp.f3[0].predicted_pc.valid connect bim.io.resp_in[0].f3[0].is_jal, ubtb.io.resp.f3[0].is_jal connect bim.io.resp_in[0].f3[0].is_br, ubtb.io.resp.f3[0].is_br connect bim.io.resp_in[0].f3[0].taken, ubtb.io.resp.f3[0].taken connect bim.io.resp_in[0].f3[1].predicted_pc.bits, ubtb.io.resp.f3[1].predicted_pc.bits connect bim.io.resp_in[0].f3[1].predicted_pc.valid, ubtb.io.resp.f3[1].predicted_pc.valid connect bim.io.resp_in[0].f3[1].is_jal, ubtb.io.resp.f3[1].is_jal connect bim.io.resp_in[0].f3[1].is_br, ubtb.io.resp.f3[1].is_br connect bim.io.resp_in[0].f3[1].taken, ubtb.io.resp.f3[1].taken connect bim.io.resp_in[0].f3[2].predicted_pc.bits, ubtb.io.resp.f3[2].predicted_pc.bits connect bim.io.resp_in[0].f3[2].predicted_pc.valid, ubtb.io.resp.f3[2].predicted_pc.valid connect bim.io.resp_in[0].f3[2].is_jal, ubtb.io.resp.f3[2].is_jal connect bim.io.resp_in[0].f3[2].is_br, ubtb.io.resp.f3[2].is_br connect bim.io.resp_in[0].f3[2].taken, ubtb.io.resp.f3[2].taken connect bim.io.resp_in[0].f3[3].predicted_pc.bits, ubtb.io.resp.f3[3].predicted_pc.bits connect bim.io.resp_in[0].f3[3].predicted_pc.valid, ubtb.io.resp.f3[3].predicted_pc.valid connect bim.io.resp_in[0].f3[3].is_jal, ubtb.io.resp.f3[3].is_jal connect bim.io.resp_in[0].f3[3].is_br, ubtb.io.resp.f3[3].is_br connect bim.io.resp_in[0].f3[3].taken, ubtb.io.resp.f3[3].taken connect bim.io.resp_in[0].f2[0].predicted_pc.bits, ubtb.io.resp.f2[0].predicted_pc.bits connect bim.io.resp_in[0].f2[0].predicted_pc.valid, ubtb.io.resp.f2[0].predicted_pc.valid connect bim.io.resp_in[0].f2[0].is_jal, ubtb.io.resp.f2[0].is_jal connect bim.io.resp_in[0].f2[0].is_br, ubtb.io.resp.f2[0].is_br connect bim.io.resp_in[0].f2[0].taken, ubtb.io.resp.f2[0].taken connect bim.io.resp_in[0].f2[1].predicted_pc.bits, ubtb.io.resp.f2[1].predicted_pc.bits connect bim.io.resp_in[0].f2[1].predicted_pc.valid, ubtb.io.resp.f2[1].predicted_pc.valid connect bim.io.resp_in[0].f2[1].is_jal, ubtb.io.resp.f2[1].is_jal connect bim.io.resp_in[0].f2[1].is_br, ubtb.io.resp.f2[1].is_br connect bim.io.resp_in[0].f2[1].taken, ubtb.io.resp.f2[1].taken connect bim.io.resp_in[0].f2[2].predicted_pc.bits, ubtb.io.resp.f2[2].predicted_pc.bits connect bim.io.resp_in[0].f2[2].predicted_pc.valid, ubtb.io.resp.f2[2].predicted_pc.valid connect bim.io.resp_in[0].f2[2].is_jal, ubtb.io.resp.f2[2].is_jal connect bim.io.resp_in[0].f2[2].is_br, ubtb.io.resp.f2[2].is_br connect bim.io.resp_in[0].f2[2].taken, ubtb.io.resp.f2[2].taken connect bim.io.resp_in[0].f2[3].predicted_pc.bits, ubtb.io.resp.f2[3].predicted_pc.bits connect bim.io.resp_in[0].f2[3].predicted_pc.valid, ubtb.io.resp.f2[3].predicted_pc.valid connect bim.io.resp_in[0].f2[3].is_jal, ubtb.io.resp.f2[3].is_jal connect bim.io.resp_in[0].f2[3].is_br, ubtb.io.resp.f2[3].is_br connect bim.io.resp_in[0].f2[3].taken, ubtb.io.resp.f2[3].taken connect bim.io.resp_in[0].f1[0].predicted_pc.bits, ubtb.io.resp.f1[0].predicted_pc.bits connect bim.io.resp_in[0].f1[0].predicted_pc.valid, ubtb.io.resp.f1[0].predicted_pc.valid connect bim.io.resp_in[0].f1[0].is_jal, ubtb.io.resp.f1[0].is_jal connect bim.io.resp_in[0].f1[0].is_br, ubtb.io.resp.f1[0].is_br connect bim.io.resp_in[0].f1[0].taken, ubtb.io.resp.f1[0].taken connect bim.io.resp_in[0].f1[1].predicted_pc.bits, ubtb.io.resp.f1[1].predicted_pc.bits connect bim.io.resp_in[0].f1[1].predicted_pc.valid, ubtb.io.resp.f1[1].predicted_pc.valid connect bim.io.resp_in[0].f1[1].is_jal, ubtb.io.resp.f1[1].is_jal connect bim.io.resp_in[0].f1[1].is_br, ubtb.io.resp.f1[1].is_br connect bim.io.resp_in[0].f1[1].taken, ubtb.io.resp.f1[1].taken connect bim.io.resp_in[0].f1[2].predicted_pc.bits, ubtb.io.resp.f1[2].predicted_pc.bits connect bim.io.resp_in[0].f1[2].predicted_pc.valid, ubtb.io.resp.f1[2].predicted_pc.valid connect bim.io.resp_in[0].f1[2].is_jal, ubtb.io.resp.f1[2].is_jal connect bim.io.resp_in[0].f1[2].is_br, ubtb.io.resp.f1[2].is_br connect bim.io.resp_in[0].f1[2].taken, ubtb.io.resp.f1[2].taken connect bim.io.resp_in[0].f1[3].predicted_pc.bits, ubtb.io.resp.f1[3].predicted_pc.bits connect bim.io.resp_in[0].f1[3].predicted_pc.valid, ubtb.io.resp.f1[3].predicted_pc.valid connect bim.io.resp_in[0].f1[3].is_jal, ubtb.io.resp.f1[3].is_jal connect bim.io.resp_in[0].f1[3].is_br, ubtb.io.resp.f1[3].is_br connect bim.io.resp_in[0].f1[3].taken, ubtb.io.resp.f1[3].taken connect btb.io.resp_in[0].f3[0].predicted_pc.bits, bim.io.resp.f3[0].predicted_pc.bits connect btb.io.resp_in[0].f3[0].predicted_pc.valid, bim.io.resp.f3[0].predicted_pc.valid connect btb.io.resp_in[0].f3[0].is_jal, bim.io.resp.f3[0].is_jal connect btb.io.resp_in[0].f3[0].is_br, bim.io.resp.f3[0].is_br connect btb.io.resp_in[0].f3[0].taken, bim.io.resp.f3[0].taken connect btb.io.resp_in[0].f3[1].predicted_pc.bits, bim.io.resp.f3[1].predicted_pc.bits connect btb.io.resp_in[0].f3[1].predicted_pc.valid, bim.io.resp.f3[1].predicted_pc.valid connect btb.io.resp_in[0].f3[1].is_jal, bim.io.resp.f3[1].is_jal connect btb.io.resp_in[0].f3[1].is_br, bim.io.resp.f3[1].is_br connect btb.io.resp_in[0].f3[1].taken, bim.io.resp.f3[1].taken connect btb.io.resp_in[0].f3[2].predicted_pc.bits, bim.io.resp.f3[2].predicted_pc.bits connect btb.io.resp_in[0].f3[2].predicted_pc.valid, bim.io.resp.f3[2].predicted_pc.valid connect btb.io.resp_in[0].f3[2].is_jal, bim.io.resp.f3[2].is_jal connect btb.io.resp_in[0].f3[2].is_br, bim.io.resp.f3[2].is_br connect btb.io.resp_in[0].f3[2].taken, bim.io.resp.f3[2].taken connect btb.io.resp_in[0].f3[3].predicted_pc.bits, bim.io.resp.f3[3].predicted_pc.bits connect btb.io.resp_in[0].f3[3].predicted_pc.valid, bim.io.resp.f3[3].predicted_pc.valid connect btb.io.resp_in[0].f3[3].is_jal, bim.io.resp.f3[3].is_jal connect btb.io.resp_in[0].f3[3].is_br, bim.io.resp.f3[3].is_br connect btb.io.resp_in[0].f3[3].taken, bim.io.resp.f3[3].taken connect btb.io.resp_in[0].f2[0].predicted_pc.bits, bim.io.resp.f2[0].predicted_pc.bits connect btb.io.resp_in[0].f2[0].predicted_pc.valid, bim.io.resp.f2[0].predicted_pc.valid connect btb.io.resp_in[0].f2[0].is_jal, bim.io.resp.f2[0].is_jal connect btb.io.resp_in[0].f2[0].is_br, bim.io.resp.f2[0].is_br connect btb.io.resp_in[0].f2[0].taken, bim.io.resp.f2[0].taken connect btb.io.resp_in[0].f2[1].predicted_pc.bits, bim.io.resp.f2[1].predicted_pc.bits connect btb.io.resp_in[0].f2[1].predicted_pc.valid, bim.io.resp.f2[1].predicted_pc.valid connect btb.io.resp_in[0].f2[1].is_jal, bim.io.resp.f2[1].is_jal connect btb.io.resp_in[0].f2[1].is_br, bim.io.resp.f2[1].is_br connect btb.io.resp_in[0].f2[1].taken, bim.io.resp.f2[1].taken connect btb.io.resp_in[0].f2[2].predicted_pc.bits, bim.io.resp.f2[2].predicted_pc.bits connect btb.io.resp_in[0].f2[2].predicted_pc.valid, bim.io.resp.f2[2].predicted_pc.valid connect btb.io.resp_in[0].f2[2].is_jal, bim.io.resp.f2[2].is_jal connect btb.io.resp_in[0].f2[2].is_br, bim.io.resp.f2[2].is_br connect btb.io.resp_in[0].f2[2].taken, bim.io.resp.f2[2].taken connect btb.io.resp_in[0].f2[3].predicted_pc.bits, bim.io.resp.f2[3].predicted_pc.bits connect btb.io.resp_in[0].f2[3].predicted_pc.valid, bim.io.resp.f2[3].predicted_pc.valid connect btb.io.resp_in[0].f2[3].is_jal, bim.io.resp.f2[3].is_jal connect btb.io.resp_in[0].f2[3].is_br, bim.io.resp.f2[3].is_br connect btb.io.resp_in[0].f2[3].taken, bim.io.resp.f2[3].taken connect btb.io.resp_in[0].f1[0].predicted_pc.bits, bim.io.resp.f1[0].predicted_pc.bits connect btb.io.resp_in[0].f1[0].predicted_pc.valid, bim.io.resp.f1[0].predicted_pc.valid connect btb.io.resp_in[0].f1[0].is_jal, bim.io.resp.f1[0].is_jal connect btb.io.resp_in[0].f1[0].is_br, bim.io.resp.f1[0].is_br connect btb.io.resp_in[0].f1[0].taken, bim.io.resp.f1[0].taken connect btb.io.resp_in[0].f1[1].predicted_pc.bits, bim.io.resp.f1[1].predicted_pc.bits connect btb.io.resp_in[0].f1[1].predicted_pc.valid, bim.io.resp.f1[1].predicted_pc.valid connect btb.io.resp_in[0].f1[1].is_jal, bim.io.resp.f1[1].is_jal connect btb.io.resp_in[0].f1[1].is_br, bim.io.resp.f1[1].is_br connect btb.io.resp_in[0].f1[1].taken, bim.io.resp.f1[1].taken connect btb.io.resp_in[0].f1[2].predicted_pc.bits, bim.io.resp.f1[2].predicted_pc.bits connect btb.io.resp_in[0].f1[2].predicted_pc.valid, bim.io.resp.f1[2].predicted_pc.valid connect btb.io.resp_in[0].f1[2].is_jal, bim.io.resp.f1[2].is_jal connect btb.io.resp_in[0].f1[2].is_br, bim.io.resp.f1[2].is_br connect btb.io.resp_in[0].f1[2].taken, bim.io.resp.f1[2].taken connect btb.io.resp_in[0].f1[3].predicted_pc.bits, bim.io.resp.f1[3].predicted_pc.bits connect btb.io.resp_in[0].f1[3].predicted_pc.valid, bim.io.resp.f1[3].predicted_pc.valid connect btb.io.resp_in[0].f1[3].is_jal, bim.io.resp.f1[3].is_jal connect btb.io.resp_in[0].f1[3].is_br, bim.io.resp.f1[3].is_br connect btb.io.resp_in[0].f1[3].taken, bim.io.resp.f1[3].taken connect tage.io.resp_in[0].f3[0].predicted_pc.bits, btb.io.resp.f3[0].predicted_pc.bits connect tage.io.resp_in[0].f3[0].predicted_pc.valid, btb.io.resp.f3[0].predicted_pc.valid connect tage.io.resp_in[0].f3[0].is_jal, btb.io.resp.f3[0].is_jal connect tage.io.resp_in[0].f3[0].is_br, btb.io.resp.f3[0].is_br connect tage.io.resp_in[0].f3[0].taken, btb.io.resp.f3[0].taken connect tage.io.resp_in[0].f3[1].predicted_pc.bits, btb.io.resp.f3[1].predicted_pc.bits connect tage.io.resp_in[0].f3[1].predicted_pc.valid, btb.io.resp.f3[1].predicted_pc.valid connect tage.io.resp_in[0].f3[1].is_jal, btb.io.resp.f3[1].is_jal connect tage.io.resp_in[0].f3[1].is_br, btb.io.resp.f3[1].is_br connect tage.io.resp_in[0].f3[1].taken, btb.io.resp.f3[1].taken connect tage.io.resp_in[0].f3[2].predicted_pc.bits, btb.io.resp.f3[2].predicted_pc.bits connect tage.io.resp_in[0].f3[2].predicted_pc.valid, btb.io.resp.f3[2].predicted_pc.valid connect tage.io.resp_in[0].f3[2].is_jal, btb.io.resp.f3[2].is_jal connect tage.io.resp_in[0].f3[2].is_br, btb.io.resp.f3[2].is_br connect tage.io.resp_in[0].f3[2].taken, btb.io.resp.f3[2].taken connect tage.io.resp_in[0].f3[3].predicted_pc.bits, btb.io.resp.f3[3].predicted_pc.bits connect tage.io.resp_in[0].f3[3].predicted_pc.valid, btb.io.resp.f3[3].predicted_pc.valid connect tage.io.resp_in[0].f3[3].is_jal, btb.io.resp.f3[3].is_jal connect tage.io.resp_in[0].f3[3].is_br, btb.io.resp.f3[3].is_br connect tage.io.resp_in[0].f3[3].taken, btb.io.resp.f3[3].taken connect tage.io.resp_in[0].f2[0].predicted_pc.bits, btb.io.resp.f2[0].predicted_pc.bits connect tage.io.resp_in[0].f2[0].predicted_pc.valid, btb.io.resp.f2[0].predicted_pc.valid connect tage.io.resp_in[0].f2[0].is_jal, btb.io.resp.f2[0].is_jal connect tage.io.resp_in[0].f2[0].is_br, btb.io.resp.f2[0].is_br connect tage.io.resp_in[0].f2[0].taken, btb.io.resp.f2[0].taken connect tage.io.resp_in[0].f2[1].predicted_pc.bits, btb.io.resp.f2[1].predicted_pc.bits connect tage.io.resp_in[0].f2[1].predicted_pc.valid, btb.io.resp.f2[1].predicted_pc.valid connect tage.io.resp_in[0].f2[1].is_jal, btb.io.resp.f2[1].is_jal connect tage.io.resp_in[0].f2[1].is_br, btb.io.resp.f2[1].is_br connect tage.io.resp_in[0].f2[1].taken, btb.io.resp.f2[1].taken connect tage.io.resp_in[0].f2[2].predicted_pc.bits, btb.io.resp.f2[2].predicted_pc.bits connect tage.io.resp_in[0].f2[2].predicted_pc.valid, btb.io.resp.f2[2].predicted_pc.valid connect tage.io.resp_in[0].f2[2].is_jal, btb.io.resp.f2[2].is_jal connect tage.io.resp_in[0].f2[2].is_br, btb.io.resp.f2[2].is_br connect tage.io.resp_in[0].f2[2].taken, btb.io.resp.f2[2].taken connect tage.io.resp_in[0].f2[3].predicted_pc.bits, btb.io.resp.f2[3].predicted_pc.bits connect tage.io.resp_in[0].f2[3].predicted_pc.valid, btb.io.resp.f2[3].predicted_pc.valid connect tage.io.resp_in[0].f2[3].is_jal, btb.io.resp.f2[3].is_jal connect tage.io.resp_in[0].f2[3].is_br, btb.io.resp.f2[3].is_br connect tage.io.resp_in[0].f2[3].taken, btb.io.resp.f2[3].taken connect tage.io.resp_in[0].f1[0].predicted_pc.bits, btb.io.resp.f1[0].predicted_pc.bits connect tage.io.resp_in[0].f1[0].predicted_pc.valid, btb.io.resp.f1[0].predicted_pc.valid connect tage.io.resp_in[0].f1[0].is_jal, btb.io.resp.f1[0].is_jal connect tage.io.resp_in[0].f1[0].is_br, btb.io.resp.f1[0].is_br connect tage.io.resp_in[0].f1[0].taken, btb.io.resp.f1[0].taken connect tage.io.resp_in[0].f1[1].predicted_pc.bits, btb.io.resp.f1[1].predicted_pc.bits connect tage.io.resp_in[0].f1[1].predicted_pc.valid, btb.io.resp.f1[1].predicted_pc.valid connect tage.io.resp_in[0].f1[1].is_jal, btb.io.resp.f1[1].is_jal connect tage.io.resp_in[0].f1[1].is_br, btb.io.resp.f1[1].is_br connect tage.io.resp_in[0].f1[1].taken, btb.io.resp.f1[1].taken connect tage.io.resp_in[0].f1[2].predicted_pc.bits, btb.io.resp.f1[2].predicted_pc.bits connect tage.io.resp_in[0].f1[2].predicted_pc.valid, btb.io.resp.f1[2].predicted_pc.valid connect tage.io.resp_in[0].f1[2].is_jal, btb.io.resp.f1[2].is_jal connect tage.io.resp_in[0].f1[2].is_br, btb.io.resp.f1[2].is_br connect tage.io.resp_in[0].f1[2].taken, btb.io.resp.f1[2].taken connect tage.io.resp_in[0].f1[3].predicted_pc.bits, btb.io.resp.f1[3].predicted_pc.bits connect tage.io.resp_in[0].f1[3].predicted_pc.valid, btb.io.resp.f1[3].predicted_pc.valid connect tage.io.resp_in[0].f1[3].is_jal, btb.io.resp.f1[3].is_jal connect tage.io.resp_in[0].f1[3].is_br, btb.io.resp.f1[3].is_br connect tage.io.resp_in[0].f1[3].taken, btb.io.resp.f1[3].taken connect loop.io.resp_in[0].f3[0].predicted_pc.bits, tage.io.resp.f3[0].predicted_pc.bits connect loop.io.resp_in[0].f3[0].predicted_pc.valid, tage.io.resp.f3[0].predicted_pc.valid connect loop.io.resp_in[0].f3[0].is_jal, tage.io.resp.f3[0].is_jal connect loop.io.resp_in[0].f3[0].is_br, tage.io.resp.f3[0].is_br connect loop.io.resp_in[0].f3[0].taken, tage.io.resp.f3[0].taken connect loop.io.resp_in[0].f3[1].predicted_pc.bits, tage.io.resp.f3[1].predicted_pc.bits connect loop.io.resp_in[0].f3[1].predicted_pc.valid, tage.io.resp.f3[1].predicted_pc.valid connect loop.io.resp_in[0].f3[1].is_jal, tage.io.resp.f3[1].is_jal connect loop.io.resp_in[0].f3[1].is_br, tage.io.resp.f3[1].is_br connect loop.io.resp_in[0].f3[1].taken, tage.io.resp.f3[1].taken connect loop.io.resp_in[0].f3[2].predicted_pc.bits, tage.io.resp.f3[2].predicted_pc.bits connect loop.io.resp_in[0].f3[2].predicted_pc.valid, tage.io.resp.f3[2].predicted_pc.valid connect loop.io.resp_in[0].f3[2].is_jal, tage.io.resp.f3[2].is_jal connect loop.io.resp_in[0].f3[2].is_br, tage.io.resp.f3[2].is_br connect loop.io.resp_in[0].f3[2].taken, tage.io.resp.f3[2].taken connect loop.io.resp_in[0].f3[3].predicted_pc.bits, tage.io.resp.f3[3].predicted_pc.bits connect loop.io.resp_in[0].f3[3].predicted_pc.valid, tage.io.resp.f3[3].predicted_pc.valid connect loop.io.resp_in[0].f3[3].is_jal, tage.io.resp.f3[3].is_jal connect loop.io.resp_in[0].f3[3].is_br, tage.io.resp.f3[3].is_br connect loop.io.resp_in[0].f3[3].taken, tage.io.resp.f3[3].taken connect loop.io.resp_in[0].f2[0].predicted_pc.bits, tage.io.resp.f2[0].predicted_pc.bits connect loop.io.resp_in[0].f2[0].predicted_pc.valid, tage.io.resp.f2[0].predicted_pc.valid connect loop.io.resp_in[0].f2[0].is_jal, tage.io.resp.f2[0].is_jal connect loop.io.resp_in[0].f2[0].is_br, tage.io.resp.f2[0].is_br connect loop.io.resp_in[0].f2[0].taken, tage.io.resp.f2[0].taken connect loop.io.resp_in[0].f2[1].predicted_pc.bits, tage.io.resp.f2[1].predicted_pc.bits connect loop.io.resp_in[0].f2[1].predicted_pc.valid, tage.io.resp.f2[1].predicted_pc.valid connect loop.io.resp_in[0].f2[1].is_jal, tage.io.resp.f2[1].is_jal connect loop.io.resp_in[0].f2[1].is_br, tage.io.resp.f2[1].is_br connect loop.io.resp_in[0].f2[1].taken, tage.io.resp.f2[1].taken connect loop.io.resp_in[0].f2[2].predicted_pc.bits, tage.io.resp.f2[2].predicted_pc.bits connect loop.io.resp_in[0].f2[2].predicted_pc.valid, tage.io.resp.f2[2].predicted_pc.valid connect loop.io.resp_in[0].f2[2].is_jal, tage.io.resp.f2[2].is_jal connect loop.io.resp_in[0].f2[2].is_br, tage.io.resp.f2[2].is_br connect loop.io.resp_in[0].f2[2].taken, tage.io.resp.f2[2].taken connect loop.io.resp_in[0].f2[3].predicted_pc.bits, tage.io.resp.f2[3].predicted_pc.bits connect loop.io.resp_in[0].f2[3].predicted_pc.valid, tage.io.resp.f2[3].predicted_pc.valid connect loop.io.resp_in[0].f2[3].is_jal, tage.io.resp.f2[3].is_jal connect loop.io.resp_in[0].f2[3].is_br, tage.io.resp.f2[3].is_br connect loop.io.resp_in[0].f2[3].taken, tage.io.resp.f2[3].taken connect loop.io.resp_in[0].f1[0].predicted_pc.bits, tage.io.resp.f1[0].predicted_pc.bits connect loop.io.resp_in[0].f1[0].predicted_pc.valid, tage.io.resp.f1[0].predicted_pc.valid connect loop.io.resp_in[0].f1[0].is_jal, tage.io.resp.f1[0].is_jal connect loop.io.resp_in[0].f1[0].is_br, tage.io.resp.f1[0].is_br connect loop.io.resp_in[0].f1[0].taken, tage.io.resp.f1[0].taken connect loop.io.resp_in[0].f1[1].predicted_pc.bits, tage.io.resp.f1[1].predicted_pc.bits connect loop.io.resp_in[0].f1[1].predicted_pc.valid, tage.io.resp.f1[1].predicted_pc.valid connect loop.io.resp_in[0].f1[1].is_jal, tage.io.resp.f1[1].is_jal connect loop.io.resp_in[0].f1[1].is_br, tage.io.resp.f1[1].is_br connect loop.io.resp_in[0].f1[1].taken, tage.io.resp.f1[1].taken connect loop.io.resp_in[0].f1[2].predicted_pc.bits, tage.io.resp.f1[2].predicted_pc.bits connect loop.io.resp_in[0].f1[2].predicted_pc.valid, tage.io.resp.f1[2].predicted_pc.valid connect loop.io.resp_in[0].f1[2].is_jal, tage.io.resp.f1[2].is_jal connect loop.io.resp_in[0].f1[2].is_br, tage.io.resp.f1[2].is_br connect loop.io.resp_in[0].f1[2].taken, tage.io.resp.f1[2].taken connect loop.io.resp_in[0].f1[3].predicted_pc.bits, tage.io.resp.f1[3].predicted_pc.bits connect loop.io.resp_in[0].f1[3].predicted_pc.valid, tage.io.resp.f1[3].predicted_pc.valid connect loop.io.resp_in[0].f1[3].is_jal, tage.io.resp.f1[3].is_jal connect loop.io.resp_in[0].f1[3].is_br, tage.io.resp.f1[3].is_br connect loop.io.resp_in[0].f1[3].taken, tage.io.resp.f1[3].taken connect io.resp, loop.io.resp connect loop.io.f0_valid, io.f0_valid connect loop.io.f0_pc, io.f0_pc connect loop.io.f0_mask, io.f0_mask connect loop.io.f1_ghist, io.f1_ghist connect loop.io.f1_lhist, io.f1_lhist connect loop.io.f3_fire, io.f3_fire node _T = shl(UInt<1>(0h0), 40) node _T_1 = bits(loop.io.f3_meta, 39, 0) node _T_2 = or(_T, _T_1) connect tage.io.f0_valid, io.f0_valid connect tage.io.f0_pc, io.f0_pc connect tage.io.f0_mask, io.f0_mask connect tage.io.f1_ghist, io.f1_ghist connect tage.io.f1_lhist, io.f1_lhist connect tage.io.f3_fire, io.f3_fire node _T_3 = shl(_T_2, 56) node _T_4 = bits(tage.io.f3_meta, 55, 0) node _T_5 = or(_T_3, _T_4) connect btb.io.f0_valid, io.f0_valid connect btb.io.f0_pc, io.f0_pc connect btb.io.f0_mask, io.f0_mask connect btb.io.f1_ghist, io.f1_ghist connect btb.io.f1_lhist, io.f1_lhist connect btb.io.f3_fire, io.f3_fire node _T_6 = shl(_T_5, 1) node _T_7 = bits(btb.io.f3_meta, 0, 0) node _T_8 = or(_T_6, _T_7) connect ubtb.io.f0_valid, io.f0_valid connect ubtb.io.f0_pc, io.f0_pc connect ubtb.io.f0_mask, io.f0_mask connect ubtb.io.f1_ghist, io.f1_ghist connect ubtb.io.f1_lhist, io.f1_lhist connect ubtb.io.f3_fire, io.f3_fire node _T_9 = shl(_T_8, 8) node _T_10 = bits(ubtb.io.f3_meta, 7, 0) node _T_11 = or(_T_9, _T_10) connect bim.io.f0_valid, io.f0_valid connect bim.io.f0_pc, io.f0_pc connect bim.io.f0_mask, io.f0_mask connect bim.io.f1_ghist, io.f1_ghist connect bim.io.f1_lhist, io.f1_lhist connect bim.io.f3_fire, io.f3_fire node _T_12 = shl(_T_11, 8) node _T_13 = bits(bim.io.f3_meta, 7, 0) node _T_14 = or(_T_12, _T_13) connect io.f3_meta, _T_14 connect bim.io.update.bits.meta, io.update.bits.meta connect bim.io.update.bits.target, io.update.bits.target connect bim.io.update.bits.lhist, io.update.bits.lhist connect bim.io.update.bits.ghist, io.update.bits.ghist connect bim.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect bim.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect bim.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect bim.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect bim.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect bim.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect bim.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect bim.io.update.bits.br_mask, io.update.bits.br_mask connect bim.io.update.bits.pc, io.update.bits.pc connect bim.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect bim.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect bim.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect bim.io.update.valid, io.update.valid connect bim.io.update.bits.meta, io.update.bits.meta node _T_15 = shr(io.update.bits.meta, 8) connect ubtb.io.update.bits.meta, io.update.bits.meta connect ubtb.io.update.bits.target, io.update.bits.target connect ubtb.io.update.bits.lhist, io.update.bits.lhist connect ubtb.io.update.bits.ghist, io.update.bits.ghist connect ubtb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect ubtb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect ubtb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect ubtb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect ubtb.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect ubtb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect ubtb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect ubtb.io.update.bits.br_mask, io.update.bits.br_mask connect ubtb.io.update.bits.pc, io.update.bits.pc connect ubtb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect ubtb.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect ubtb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect ubtb.io.update.valid, io.update.valid connect ubtb.io.update.bits.meta, _T_15 node _T_16 = shr(_T_15, 8) connect btb.io.update.bits.meta, io.update.bits.meta connect btb.io.update.bits.target, io.update.bits.target connect btb.io.update.bits.lhist, io.update.bits.lhist connect btb.io.update.bits.ghist, io.update.bits.ghist connect btb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect btb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect btb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect btb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect btb.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect btb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect btb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect btb.io.update.bits.br_mask, io.update.bits.br_mask connect btb.io.update.bits.pc, io.update.bits.pc connect btb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect btb.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect btb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect btb.io.update.valid, io.update.valid connect btb.io.update.bits.meta, _T_16 node _T_17 = shr(_T_16, 1) connect tage.io.update.bits.meta, io.update.bits.meta connect tage.io.update.bits.target, io.update.bits.target connect tage.io.update.bits.lhist, io.update.bits.lhist connect tage.io.update.bits.ghist, io.update.bits.ghist connect tage.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect tage.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect tage.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect tage.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect tage.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect tage.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect tage.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect tage.io.update.bits.br_mask, io.update.bits.br_mask connect tage.io.update.bits.pc, io.update.bits.pc connect tage.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect tage.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect tage.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect tage.io.update.valid, io.update.valid connect tage.io.update.bits.meta, _T_17 node _T_18 = shr(_T_17, 56) connect loop.io.update.bits.meta, io.update.bits.meta connect loop.io.update.bits.target, io.update.bits.target connect loop.io.update.bits.lhist, io.update.bits.lhist connect loop.io.update.bits.ghist, io.update.bits.ghist connect loop.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect loop.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect loop.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect loop.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect loop.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect loop.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect loop.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect loop.io.update.bits.br_mask, io.update.bits.br_mask connect loop.io.update.bits.pc, io.update.bits.pc connect loop.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect loop.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect loop.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect loop.io.update.valid, io.update.valid connect loop.io.update.bits.meta, _T_18 node _T_19 = shr(_T_18, 40)

module ComposedBranchPredictorBank( // @[composer.scala:14:7] input clock, // @[composer.scala:14:7] input reset, // @[composer.scala:14:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26] wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26] wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26] wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26] wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25] wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25] wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25] wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25] wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25] wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25] wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25] wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25] wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26] wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26] wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26] wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26] wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26] wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7] wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7] wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14] wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_0_taken_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_1_taken_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_2_taken_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f1_3_taken_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_0_taken_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_1_taken_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_2_taken_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f2_3_taken_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_0_taken_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_1_taken_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_2_taken_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] wire io_resp_f3_3_taken_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7] wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] wire [119:0] io_f3_meta_0; // @[composer.scala:14:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [36:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14] always @(posedge clock) begin // @[composer.scala:14:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] always @(posedge) LoopBranchPredictorBank loop ( // @[config-mixins.scala:445:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26] .io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26] .io_resp_f1_0_taken (io_resp_f1_0_taken_0), .io_resp_f1_0_is_br (io_resp_f1_0_is_br_0), .io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0), .io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0), .io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0), .io_resp_f1_1_taken (io_resp_f1_1_taken_0), .io_resp_f1_1_is_br (io_resp_f1_1_is_br_0), .io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0), .io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0), .io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0), .io_resp_f1_2_taken (io_resp_f1_2_taken_0), .io_resp_f1_2_is_br (io_resp_f1_2_is_br_0), .io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0), .io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0), .io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0), .io_resp_f1_3_taken (io_resp_f1_3_taken_0), .io_resp_f1_3_is_br (io_resp_f1_3_is_br_0), .io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0), .io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0), .io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0), .io_resp_f2_0_taken (io_resp_f2_0_taken_0), .io_resp_f2_0_is_br (io_resp_f2_0_is_br_0), .io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0), .io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0), .io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0), .io_resp_f2_1_taken (io_resp_f2_1_taken_0), .io_resp_f2_1_is_br (io_resp_f2_1_is_br_0), .io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0), .io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0), .io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0), .io_resp_f2_2_taken (io_resp_f2_2_taken_0), .io_resp_f2_2_is_br (io_resp_f2_2_is_br_0), .io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0), .io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0), .io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0), .io_resp_f2_3_taken (io_resp_f2_3_taken_0), .io_resp_f2_3_is_br (io_resp_f2_3_is_br_0), .io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0), .io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0), .io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0), .io_resp_f3_0_taken (io_resp_f3_0_taken_0), .io_resp_f3_0_is_br (io_resp_f3_0_is_br_0), .io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0), .io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0), .io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0), .io_resp_f3_1_taken (io_resp_f3_1_taken_0), .io_resp_f3_1_is_br (io_resp_f3_1_is_br_0), .io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0), .io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0), .io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0), .io_resp_f3_2_taken (io_resp_f3_2_taken_0), .io_resp_f3_2_is_br (io_resp_f3_2_is_br_0), .io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0), .io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0), .io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0), .io_resp_f3_3_taken (io_resp_f3_3_taken_0), .io_resp_f3_3_is_br (io_resp_f3_3_is_br_0), .io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0), .io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0), .io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0), .io_f3_meta (_loop_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:445:26] TageBranchPredictorBank tage ( // @[config-mixins.scala:446:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25] .io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25] .io_resp_f1_0_taken (_tage_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_tage_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_tage_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_tage_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_tage_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_tage_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_tage_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_tage_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_tage_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_tage_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_tage_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_tage_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_tage_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:446:26] BTBBranchPredictorBank btb ( // @[config-mixins.scala:447:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25] .io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25] .io_resp_f1_0_taken (_btb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_btb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_btb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_btb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_btb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_btb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_btb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_btb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_btb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_btb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_btb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_btb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_btb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31] ); // @[config-mixins.scala:447:25] BIMBranchPredictorBank bim ( // @[config-mixins.scala:448:25] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26] .io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26] .io_resp_f1_0_taken (_bim_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_bim_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_bim_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_bim_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_bim_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_bim_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_bim_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_bim_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_bim_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_bim_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_bim_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_bim_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_bim_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7] ); // @[config-mixins.scala:448:25] FAMicroBTBBranchPredictorBank ubtb ( // @[config-mixins.scala:449:26] .clock (clock), .reset (reset), .io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7] .io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7] .io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7] .io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7] .io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken), .io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), .io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), .io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), .io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), .io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken), .io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), .io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), .io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), .io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), .io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken), .io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), .io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), .io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), .io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), .io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken), .io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), .io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), .io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), .io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), .io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken), .io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), .io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), .io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), .io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), .io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken), .io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), .io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), .io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), .io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), .io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken), .io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), .io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), .io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), .io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), .io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken), .io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), .io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), .io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), .io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), .io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken), .io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), .io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), .io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), .io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), .io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken), .io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), .io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), .io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), .io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), .io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken), .io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), .io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), .io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), .io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), .io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken), .io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), .io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), .io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), .io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), .io_f3_meta (_ubtb_io_f3_meta), .io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7] .io_update_valid (io_update_valid_0), // @[composer.scala:14:7] .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7] .io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7] .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7] .io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7] .io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7] .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7] .io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7] .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7] .io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7] .io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7] .io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7] .io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7] .io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31] ); // @[config-mixins.scala:449:26] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7] assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_PutBufferAEntry_q40_e40_1 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}}}, valid : UInt<40>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}} regreset valid : UInt<40>, clock, reset, UInt<40>(0h0) cmem head : UInt<6> [40] cmem tail : UInt<6> [40] regreset used : UInt<40>, clock, reset, UInt<40>(0h0) cmem next : UInt<6> [40] cmem data : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>} [40] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = shl(_freeOH_T_15, 32) node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0) node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17) node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0) node _freeOH_T_20 = shl(_freeOH_T_19, 1) node _freeOH_T_21 = not(_freeOH_T_20) node _freeOH_T_22 = not(used) node freeOH = and(_freeOH_T_21, _freeOH_T_22) node freeIdx_hi = bits(freeOH, 40, 32) node freeIdx_lo = bits(freeOH, 31, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16) node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8) node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4) node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2) node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0) node _freeIdx_T_8 = orr(freeIdx_hi_4) node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4) node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1) node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10) node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11) node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12) node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13) node freeIdx = cat(_freeIdx_T, _freeIdx_T_14) wire valid_set : UInt<40> connect valid_set, UInt<40>(0h0) wire valid_clr : UInt<40> connect valid_clr, UInt<40>(0h0) wire used_set : UInt<40> connect used_set, UInt<40>(0h0) wire used_clr : UInt<40> connect used_clr, UInt<40>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 39, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH write mport MPORT = data[freeIdx], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_1 = eq(io.pop.valid, UInt<1>(0h0)) node _T_2 = dshr(io.valid, io.pop.bits) node _T_3 = bits(_T_2, 0, 0) node _T_4 = or(_T_1, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 5, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 39, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_8 = eq(pop_head, MPORT_4) when _T_8 : node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 39, 0) connect valid_clr, _valid_clr_T_1 node _T_9 = and(io.push.ready, io.push.valid) node _T_10 = and(_T_9, push_valid) node _T_11 = eq(push_tail, pop_head) node _T_12 = and(_T_10, _T_11) read mport MPORT_5 = next[pop_head], clock node _T_13 = mux(_T_12, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_13 node _T_14 = eq(io.pop.valid, UInt<1>(0h0)) node _T_15 = or(UInt<1>(0h1), _T_14) node _T_16 = or(_T_15, pop_valid) when _T_16 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2

module ListBuffer_PutBufferAEntry_q40_e40_1( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input [127:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14] input [15:0] io_push_bits_data_mask, // @[ListBuffer.scala:39:14] input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14] output [39:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output [127:0] io_data_data, // @[ListBuffer.scala:39:14] output [15:0] io_data_mask, // @[ListBuffer.scala:39:14] output io_data_corrupt // @[ListBuffer.scala:39:14] ); wire [144:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire [127:0] io_push_bits_data_data_0 = io_push_bits_data_data; // @[ListBuffer.scala:36:7] wire [15:0] io_push_bits_data_mask_0 = io_push_bits_data_mask; // @[ListBuffer.scala:36:7] wire io_push_bits_data_corrupt_0 = io_push_bits_data_corrupt; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire [127:0] io_data_data_0; // @[ListBuffer.scala:36:7] wire [15:0] io_data_mask_0; // @[ListBuffer.scala:36:7] wire io_data_corrupt_0; // @[ListBuffer.scala:36:7] wire [39:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [39:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [39:0] used; // @[ListBuffer.scala:50:22] assign io_data_data_0 = _data_ext_R0_data[127:0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_mask_0 = _data_ext_R0_data[143:128]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_corrupt_0 = _data_ext_R0_data[144]; // @[ListBuffer.scala:36:7, :52:18] wire [39:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}] wire [39:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire [39:0] valid_set; // @[ListBuffer.scala:57:30] wire [39:0] valid_clr; // @[ListBuffer.scala:58:30] wire [39:0] used_set; // @[ListBuffer.scala:59:30] wire [39:0] used_clr; // @[ListBuffer.scala:60:30] wire [39:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _valid_set_T_1 = _valid_set_T[39:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 40'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[39:0] : 40'h0; // @[Decoupled.scala:51:35] wire [39:0] _GEN = {34'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [39:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]

Generate the Verilog code corresponding to this FIRRTL code module PE_360 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_104 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_360( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_104 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule